An InAs / AlSb heterojunction type radio frequency field effect transistor device and a preparation method thereof

Abstract

The application relates to an InAs / AlSb heterojunction type radio frequency field effect transistor device and a preparation method thereof. The device comprises a GaAs substrate, an AlGaSb buffer layer, a p-type GaSb interlayer, a lower barrier layer, an InAs channel layer, an upper barrier layer, an InAlAs hole blocking layer, an InAs cap layer, a source electrode, a drain electrode and a gate electrode. The GaAs substrate, the AlGaSb buffer layer, the p-type GaSb interlayer, the lower barrier layer, the InAs channel layer, the upper barrier layer and the InAlAs hole blocking layer are stacked in sequence. The source electrode and the drain electrode are both located on the InAs cap layer and are spaced apart by a certain distance. The InAs cap layer is provided with a gate slot, the gate slot is located between the source electrode and the drain electrode and on the InAlAs hole blocking layer, and the gate electrode is located in the gate slot. In the radio frequency field effect transistor device, the p-type GaSb interlayer is inserted between the AlGaSb buffer layer and the lower barrier layer, the p-type GaSb interlayer can eliminate some holes caused by the collision ionization effect, inhibit the movement of the holes in the direction of the substrate, thereby improving the direct current characteristics of the device and improving the performance of the device.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an InAs / AlSb heterojunction type radio frequency field-effect transistor device and its fabrication method. Background Technology

[0002] Antimony-based compound semiconductors refer to binary, ternary, and multi-component antimony-based materials formed from group III elements (In, Al, Ga) and group V elements (Sb, As, etc.). They possess considerable band structure and diverse band gap structures, with the conduction band level between InAs and AlSb reaching as high as 1.35 eV. The diverse band gap structures allow for the adjustment of band structure between materials by modifying the composition of the multi-component antimony-based compound semiconductor, resulting in flexible Sb-based semiconductor material structures. Sb-based semiconductor materials are currently widely used in microelectronics and optoelectronic devices and integrated circuits, active array space radar, satellite communications, ultra-high-speed and ultra-low-power integrated circuits for portable mobile devices, gas detectors, chemical detection, and other fields. Compared to other group III-V compound semiconductor materials, InSb and InAs materials have smaller effective carrier mass, smaller band gap, and higher electron mobility and drift velocity, enabling devices to simultaneously achieve high current gain cutoff frequencies. T And low source-side parasitic resistance Rs.

[0003] In InAs / AlSb HEMTs, charge carriers in the channel readily collide with lattice atoms under high electric fields, generating excess electron-hole pairs, i.e., collisional ionization. Some holes cross the upper barrier and flow out from the gate, forming hole-gate leakage current. The remaining holes accumulate in the buffer layer near the gate-drain side due to the influence of the buffer layer and the valence band energy barrier of the channel, increasing the electron density at the gate and leading to an increase in channel leakage current. Furthermore, the collisional ionization effect of the device is frequency-dependent, exhibiting a very pronounced effect below 10 GHz, significantly impacting the device's RF performance and severely degrading noise performance. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides an InAs / AlSb heterojunction-based radio frequency field-effect transistor device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides an InAs / AlSb heterojunction-based radio frequency field-effect transistor device, comprising a GaAs substrate, an AlGaSb buffer layer, a p-type GaSb insertion layer, a lower barrier layer, an InAs channel layer, an upper barrier layer, an InAlAs hole blocking layer, an InAs cap layer, a source, a drain, and a gate.

[0006] The GaAs substrate, AlGaSb buffer layer, p-type GaSb insertion layer, lower barrier layer, InAs channel layer, upper barrier layer, InAlAs hole blocking layer, and InAs cap layer are stacked sequentially.

[0007] The source and the drain are both located on the InAs cap layer, and there is a certain distance between the source and the drain;

[0008] A gate trench is provided in the InAs cap layer, the gate trench is located between the source and the drain and on the InAlAs hole blocking layer, and the gate is located in the gate trench.

[0009] In one embodiment of the present invention, the lower barrier layer includes a first AlSb lower barrier sublayer, an InAs lower barrier insertion layer and a second AlSb lower barrier sublayer stacked sequentially, and the first AlSb lower barrier sublayer is located on the p-type GaSb insertion layer.

[0010] In one embodiment of the present invention, the upper barrier layer includes a first AlSb upper barrier sublayer, an InAs upper barrier insertion layer and a second AlSb upper barrier sublayer stacked sequentially, and the first AlSb upper barrier sublayer is located on the InAs channel layer.

[0011] In one embodiment of the present invention, the material of the AlGaSb buffer layer includes Al 0.7 Ga 0.3 Sb, with a thickness of 600~800nm;

[0012] The doping element of the p-type GaSb insertion layer includes Si, and the thickness is 10~30nm.

[0013] The thickness of the first AlSb lower barrier sublayer is 40~50nm, the thickness of the InAs lower barrier insertion layer is 4~6nm, and the thickness of the second AlSb lower barrier sublayer is 8~12nm.

[0014] The thickness of the InAs channel layer is 10~20nm;

[0015] The thickness of the barrier sublayer on the first AlSb is 4~6 nm;

[0016] The barrier insertion layer on the InAs is a 2-5 molecular layer δ-doped InAs, with Si as the doping element and a doping concentration of 1×10⁻⁶. 19 ~1.2×10 19 cm -3 ;

[0017] The thickness of the barrier sublayer on the second AlSb is 4~6 nm;

[0018] The thickness of the InAlAs hole-blocking layer is 4~6nm;

[0019] The InAs cap layer is doped with Si, and the doping concentration is 2 × 10⁻⁶. 19 ~2.2×10 19 cm -3 The thickness is 4~6nm.

[0020] In one embodiment of the invention, a back gate is also included, wherein,

[0021] The GaAs substrate and the AlGaSb buffer layer have a back hole located on the back side of the p-type GaSb insertion layer, and the back gate covers the surface of the back hole and the back side of the GaAs substrate.

[0022] In one embodiment of the present invention, a GaAs material layer is further included, the GaAs material layer being located between the GaAs substrate and the AlGaSb buffer layer.

[0023] Another embodiment of the present invention provides a method for fabricating an InAs / AlSb heterojunction radio frequency field-effect transistor device, comprising the steps of:

[0024] S1. Grow an AlGaSb buffer layer on a GaAs substrate;

[0025] S2. Grow a p-type GaSb insertion layer on the AlGaSb buffer layer;

[0026] S3. Grow a lower barrier layer on the p-type GaSb insertion layer;

[0027] S4. Grow an InAs channel layer on the lower barrier layer;

[0028] S5. A barrier layer is grown on the InAs channel layer;

[0029] S6. An InAlAs hole blocking layer is grown on the upper barrier layer.

[0030] S7. Grow an InAs cap layer on the InAlAs hole blocking layer;

[0031] S8. A source and a drain are fabricated on the InAs cap layer, such that the source and the drain are separated by a certain distance.

[0032] S9. Etch the InAs cap layer to form a gate trench located on the InAlAs hole blocking layer and between the source and the drain, and fabricate a gate in the gate trench.

[0033] In one embodiment of the present invention, step S3 includes:

[0034] S31. A first AlSb lower barrier sublayer is grown on the p-type GaSb insertion layer.

[0035] S32. Grow an InAs lower barrier insertion layer on the first AlSb lower barrier sublayer;

[0036] S33. A second AlSb lower barrier sublayer is grown on the InAs lower barrier insertion layer to form the lower barrier layer.

[0037] In one embodiment of the present invention, step S5 includes:

[0038] S51. A first AlSb upper barrier sublayer is grown on the InAs channel layer.

[0039] S52. Grow an InAs barrier insertion layer on the first AlSb barrier sublayer;

[0040] S53. A second AlSb upper barrier sublayer is grown on the InAs upper barrier insertion layer to form the upper barrier layer.

[0041] In one embodiment of the present invention, step S9 is followed by:

[0042] S10. Etch the GaAs substrate and the AlGaSb buffer layer to form a back hole on the back side of the p-type GaSb insertion layer, and deposit a back gate on the surface of the back hole and the back side of the GaAs substrate.

[0043] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0044] 1. In the radio frequency field-effect transistor device of the present invention, a p-type GaSb insertion layer is inserted between the AlGaSb buffer layer and the lower barrier layer. The p-type GaSb insertion layer can eliminate some holes caused by impact ionization effect and suppress the movement of holes towards the substrate, thereby improving the DC characteristics of the device and improving the performance of the device.

[0045] 2. In the radio frequency field effect transistor device of the present invention, an InAs lower barrier insertion layer is inserted between the first AlSb lower barrier sublayer and the second AlSb lower barrier sublayer as a sub-channel layer. The sub-channel layer absorbs surrounding electrons, thereby increasing the total electron concentration in the InAs channel layer and the sub-channel layer, thereby suppressing the impact ionization effect and improving the performance of the device.

[0046] 3. In the radio frequency field effect transistor device of the present invention, an InAs upper barrier insertion layer is inserted between the first AlSb upper barrier sublayer and the second AlSb upper barrier sublayer. The δ-doped InAs insertion layer enables electrons in the InAs channel layer to jump into the InAs lower barrier insertion layer through the quantum well effect before they have the energy required for collisional ionization, thereby avoiding collisional ionization in the conductive main channel and improving the performance of the device.

[0047] 4. In the radio frequency field-effect transistor device of the present invention, a back gate structure is provided on the back side of the device. The back gate structure can eliminate the holes tunneling towards the substrate generated by the collision ionization effect, and together with the p-type GaSb insertion layer, suppress the influence of the collision ionization effect on the device performance and improve the device performance. Attached Figure Description

[0048] Figure 1 A schematic diagram of a radio frequency field-effect transistor device based on an InAs / AlSb heterojunction is provided for an embodiment of the present invention;

[0049] Figure 2 A schematic flowchart illustrating a method for fabricating an InAs / AlSb heterojunction radio frequency field-effect transistor device according to an embodiment of the present invention;

[0050] Figures 3a-3f This is a schematic diagram illustrating the fabrication process of an InAs / AlSb heterojunction-based radio frequency field-effect transistor device provided in an embodiment of the present invention. Detailed Implementation

[0051] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0052] Example 1

[0053] Please see Figure 1 , Figure 1 This is a schematic diagram of a radio frequency field-effect transistor device based on an InAs / AlSb heterojunction, provided as an embodiment of the present invention.

[0054] The radio frequency field-effect transistor device includes: a GaAs substrate 1, an AlGaSb buffer layer 2, a p-type GaSb insertion layer 3, a lower barrier layer 4, an InAs channel layer 5, an upper barrier layer 6, an InAlAs hole blocking layer 7, an InAs cap layer 8, a source 9, a drain 10, and a gate 11. The GaAs substrate 1, AlGaSb buffer layer 2, p-type GaSb insertion layer 3, lower barrier layer 4, InAs channel layer 5, upper barrier layer 6, InAlAs hole blocking layer 7, and InAs cap layer 8 are stacked sequentially. The source 9 and drain 10 are both located on the InAs cap layer 8, and are separated by a certain distance. A gate trench 110 is disposed in the InAs cap layer 8, located between the source 9 and drain 10 and on the InAlAs hole blocking layer 7, and the gate 11 is located in the gate trench 110.

[0055] Specifically, the GaAs substrate 1 can be 2 inches in size. The material of the AlGaSb buffer layer 2 includes Al 0.7 Ga 0.3 The doping element of the p-type GaSb insertion layer 3 includes Si. The material of the lower barrier layer 4 includes AlSb. The material of the upper barrier layer 6 includes AlSb; the doping element of the InAs cap layer 8 includes Si, with a doping concentration of 2 × 10⁻⁶. 19 ~2.2×10 19 cm -3 The source electrode 9 and drain electrode 10 are made of alloy materials or non-alloy materials; when the source electrode 9 and drain electrode 10 are alloy materials, the alloy materials include one or more of Ni and Au; when the source electrode 9 and drain electrode 10 are non-alloy materials, the non-alloy materials include one or more of Pd, Pt, and Au. The gate electrode 11 is made of one or more of Ti, Pt, and Au.

[0056] Specifically, the gate slot 110 can be a trapezoidal gate slot. The trapezoidal gate slot can prevent the gate from being directly connected to the source and drain, and at the same time reduce the distance between the gate and the channel, thereby increasing the gate control capability.

[0057] In this embodiment, an AlGaSb buffer layer 2 is disposed between the GaAs substrate 1 and the p-type GaSb insertion layer 3, which can release the lattice mismatch stress between the substrate and the p-type GaSb insertion layer. The p-type GaSb insertion layer, inserted between the AlGaSb buffer layer and the lower barrier layer, can eliminate some holes caused by impact ionization, suppress the movement of holes towards the substrate, thereby improving the DC characteristics of the device and enhancing its performance.

[0058] In one specific embodiment, the lower barrier layer 4 includes a first AlSb lower barrier sublayer 41, an InAs lower barrier insertion layer 42, and a second AlSb lower barrier sublayer 43 stacked sequentially, and the first AlSb lower barrier sublayer 41 is located on the p-type GaSb insertion layer 3.

[0059] In this embodiment, an InAs lower barrier insertion layer is inserted between the first AlSb lower barrier sublayer and the second AlSb lower barrier sublayer as a sub-channel layer. The sub-channel layer absorbs surrounding electrons, which increases the total electron concentration in the InAs channel layer and the sub-channel layer, thereby suppressing the impact ionization effect and improving the performance of the device.

[0060] In one specific embodiment, the upper barrier layer 6 includes a first AlSb upper barrier sublayer 61, an InAs upper barrier insertion layer 62, and a second AlSb upper barrier sublayer 63 stacked sequentially, and the first AlSb upper barrier sublayer 61 is located on the InAs channel layer 5.

[0061] Specifically, the barrier insertion layer 62 on InAs is δ-doped InAs, with Si as the doping element and a doping concentration of 1×10⁻⁶. 19 ~1.2×10 19 cm -3 .

[0062] In this embodiment, an InAs upper barrier insertion layer is inserted between the first AlSb upper barrier sublayer and the second AlSb upper barrier sublayer. The δ-doped InAs insertion layer enables electrons in the InAs channel layer to jump into the InAs lower barrier insertion layer through the quantum well effect before they have the energy required for collisional ionization, thus avoiding collisional ionization in the conductive main channel and improving the performance of the device.

[0063] In one specific embodiment, the radio frequency field-effect transistor device further includes a back gate 12, wherein a back hole 120 is provided in the GaAs substrate 1 and the AlGaSb buffer layer 2, located on the back side of the p-type GaSb insertion layer 3, and the back gate 12 covers the surface of the back hole 120 and the back side of the GaAs substrate 1.

[0064] Specifically, the material of the back grid 12 includes one or more of Cr and Au.

[0065] In this embodiment, a back gate structure is provided on the back side of the device. The back gate structure can eliminate the holes tunneling towards the substrate caused by the impact ionization effect. Together with the p-type GaSb insertion layer, it suppresses the impact ionization effect on the device performance and improves the device performance.

[0066] In one specific embodiment, a GaAs material layer 101 is further disposed between the GaAs substrate 1 and the AlGaSb buffer layer 2. The GaAs material layer 101 can prevent impurities and defects in the substrate, thereby obtaining a more complete crystal structure.

[0067] In the above embodiments, the p-type GaSb insertion layer 3, the InAs lower barrier insertion layer 42, the InAs upper barrier insertion layer 62, and the back gate 12 structure can all suppress the impact of collisional ionization on device performance. In other words, based on the traditional InAs / AlSb heterojunction high electron mobility transistor, the collisional ionization effect can be suppressed by adding one or more of the p-type GaSb insertion layer 3, the InAs lower barrier insertion layer 42, the InAs upper barrier insertion layer 62, and the back gate 12 structure. When different structures are used to suppress the collisional ionization effect, the thickness of each material layer in the device changes accordingly.

[0068] In a preferred embodiment, the InAs / AlSb heterojunction-based radio frequency field-effect transistor device includes a GaAs substrate 1, a GaAs material layer 101, an AlGaSb buffer layer 2, a p-type GaSb insertion layer 3, a first AlSb lower barrier sublayer 41, an InAs lower barrier insertion layer 42, a second AlSb lower barrier sublayer 43, an InAs channel layer 5, a first AlSb upper barrier sublayer 61, an InAs upper barrier insertion layer 62, a second AlSb upper barrier sublayer 63, an InAlAs hole blocking layer 7, an InAs cap layer 8, a source 9, a drain 10, a gate 11, and a back gate 12, as shown below. Figure 1 As shown.

[0069] The structure comprises a GaAs substrate 1, a GaAs material layer 101, an AlGaSb buffer layer 2, a p-type GaSb insertion layer 3, a first AlSb lower barrier sublayer 41, an InAs lower barrier insertion layer 42, a second AlSb lower barrier sublayer 43, an InAs channel layer 5, a first AlSb upper barrier sublayer 61, an InAs upper barrier insertion layer 62, a second AlSb upper barrier sublayer 63, an InAlAs hole blocking layer 7, and an InAs cap layer 8, which are stacked sequentially. The source 9 and drain 10 are both located on the InAs cap layer 8, and there is a certain distance between the source 9 and the drain 10. A gate trench 110 is provided in the InAs cap layer 8, which is located between the source 9 and the drain 10 and on the InAlAs hole blocking layer 7. The gate 11 is located in the gate trench 110. A back hole 120 is provided in the GaAs substrate 1 and the AlGaSb buffer layer 2, located on the back side of the p-type GaSb insertion layer 3. The back gate 12 covers the surface of the back hole 120 and the back side of the GaAs substrate 1.

[0070] Specifically, the thickness of the GaAs material layer 101 is 100~300nm; the material of the AlGaSb buffer layer 2 includes Al0.7 Ga 0.3 The first AlSb lower barrier sublayer 41 has a thickness of 600-800 nm; the p-type GaSb insertion layer 3 is doped with Si and has a thickness of 10-30 nm; the first AlSb lower barrier sublayer 41 has a thickness of 40-50 nm; the InAs lower barrier sublayer 42 has a thickness of 4-6 nm; the second AlSb lower barrier sublayer 43 has a thickness of 8-12 nm; the InAs channel layer 5 has a thickness of 10-20 nm; the first AlSb upper barrier sublayer 61 has a thickness of 4-6 nm; the InAs upper barrier sublayer 62 is 2-5 molecular layers of δ-doped InAs, with Si as the doping element and a doping concentration of 1×10⁻⁵. 19 ~1.2×10 19 cm -3 The thickness of the second AlSb barrier sublayer 63 is 6~10 nm; the thickness of the InAlAs hole blocking layer 7 is 4~6 nm; the InAs cap layer 8 is doped with Si, and the doping concentration is 2×10⁻⁶. 19 ~2.2×10 19 cm -3 The thickness is 4~6nm.

[0071] This preferred embodiment adds an InAs lower barrier insertion layer as a secondary channel, an upper barrier δ-doped InAs insertion layer, a p-type GaSb insertion layer, and a back gate structure to the traditional InAs / AlSb heterojunction high electron mobility transistor. This achieves the following functions: the insertion of the secondary channel in the lower barrier layer absorbs surrounding electrons, increasing the total electron concentration in both the main and secondary channels to suppress collisional ionization; the introduction of the δ-doped InAs insertion layer in the upper barrier layer allows electrons in the main channel to jump into the InAs secondary channel via a quantum well effect before they have the energy required for collisional ionization, preventing collisional ionization in the conductive main channel; the insertion of the p-type GaSb layer eliminates some holes caused by collisional ionization, suppressing hole movement towards the substrate and thus improving the device's DC characteristics; simultaneously, the grown back gate structure also eliminates holes tunneling towards the substrate caused by collisional ionization, collectively suppressing the impact of collisional ionization on device performance and improving device performance. In summary, this preferred device significantly enhances the suppression of collisional ionization effects, and can effectively improve performance in terms of noise, transition frequency, and leakage current while ensuring the concentration of two-dimensional electron gas in the device.

[0072] Example 2

[0073] Based on Example 1, please refer to Figure 2 and Figures 3a-3f , Figure 2 This is a schematic flowchart illustrating a method for fabricating an InAs / AlSb heterojunction radio frequency field-effect transistor device according to an embodiment of the present invention. Figures 3a-3fThis is a schematic diagram illustrating a fabrication method for an InAs / AlSb heterojunction radio frequency field-effect transistor device according to an embodiment of the present invention. The fabrication method includes the following steps:

[0074] S1. Grow an AlGaSb buffer layer 2 on GaAs substrate 1. (See below) Figure 3a .

[0075] First, a 2-inch GaAs semi-insulating material was selected as the GaAs substrate 1; the GaAs substrate 1 was placed in the vacuum chamber of the MBE device at an angle of 0~1°, and the vacuum level was maintained at 10. -10 ~10 -11 torr, then adjust the vacuum level to 10. -7 ~10 -8 Next, the GaAs substrate is heated to 570-590°C in an As atmosphere for deoxidation treatment, and a GaAs material layer of 100-300 nm is grown to form a GaAs material layer 101. The GaAs material layer 101 can prevent impurities and defects in the substrate, thereby obtaining a more complete crystal structure.

[0076] Then, 600-800 nm Al was grown on the substrate surface using molecular beam epitaxy (MBE). 0.7 Ga 0.3 Sb forms an AlGaSb buffer layer 2 to release the lattice mismatch stress between the GaAs material 101 and the p-type GaSb insertion layer 3.

[0077] S2. Grow a p-type GaSb insertion layer 3 on the AlGaSb buffer layer 2. (See below) Figure 3a .

[0078] Specifically, by adjusting the temperature to 450~500℃ and maintaining a V / III beam ratio of 4:1, a 10~30nm p-type GaSb insertion layer is grown on the AlGaSb buffer layer 2. This insertion layer can effectively suppress the impact ionization effect.

[0079] S3. A lower barrier layer 4 is grown on the p-type GaSb insertion layer 3.

[0080] In one specific embodiment, an AlSb material is directly grown on the p-type GaSb insertion layer 3 to form an AlSb lower barrier layer 4.

[0081] In another embodiment, please refer to Figure 3a If the lower barrier layer 4 includes a first AlSb lower barrier sublayer 41, an InAs lower barrier insertion layer 42, and a second AlSb lower barrier sublayer 43, then step S3 includes:

[0082] S31. A first AlSb lower barrier sublayer 41 is grown on the p-type GaSb insertion layer 3.

[0083] Specifically, the temperature is adjusted to 550~560℃, and a V / III beam ratio of 5:1 is maintained to grow 40~50nm of AlSb material on the p-type GaSb insertion layer 3 to form the first AlSb lower barrier sublayer 41.

[0084] S32. An InAs lower barrier insertion layer 42 is grown on the first AlSb lower barrier sublayer 41.

[0085] Specifically, by maintaining a V / III beam ratio of 10:1, 4-6 nm of InAs material is grown on the first AlSb lower barrier sublayer 41 to form an InAs lower barrier insertion layer 42, which serves as the secondary channel of the device. The first AlSb lower barrier insertion layer 41 can also effectively suppress the impact ionization effect.

[0086] S33. A second AlSb lower barrier sublayer 43 is grown on the InAs lower barrier insertion layer 42 to form the lower barrier layer 4.

[0087] Specifically, by maintaining a V / III beam ratio of 5:1, 8-12 nm of AlSb is grown on the buffer layer to form the second AlSb lower barrier sublayer 43, thus completing the growth of the lower barrier layer 4.

[0088] S4. Grow InAs channel layer 5 on the lower barrier layer 4. (See below) Figure 3a .

[0089] Specifically, on the surface of the lower barrier layer 4, 10~20nm of InAs is generated as the main channel of the device by maintaining a V / III beam ratio of 10:1, thus forming the InAs channel layer 5.

[0090] S5. A barrier layer 6 is grown on the InAs channel layer 5.

[0091] In one specific embodiment, an AlSb material layer is directly grown on the InAs channel layer 5 to form the upper barrier layer 6.

[0092] In another embodiment, please refer to Figure 3a If the upper barrier layer 6 includes a first AlSb upper barrier sublayer 61, an InAs upper barrier insertion layer 62, and a second AlSb upper barrier sublayer 63, then step S5 includes:

[0093] S51. A first AlSb upper barrier sublayer 61 is grown on the InAs channel layer 5.

[0094] Specifically, maintaining a V / III beam ratio of 5:1, 4-6 nm of AlSb is grown on the InAs channel layer 5 to form the first AlSb barrier sublayer 61.

[0095] S52. An InAs barrier insertion layer 62 is grown on the first AlSb barrier sublayer 61.

[0096] Specifically, maintaining a V / III beam ratio of 10:1, an InAs insertion layer of 2-5 molecular layers is grown on the first AlSb barrier sublayer 61, and a concentration of 1×10⁻⁶ is achieved. 19 ~1.2×10 19 cm -3 The Si doping, with the insertion layer acting as a δ-doped InAs spacer, can increase the two-dimensional electron gas concentration and suppress collisional ionization effects.

[0097] S53. A second AlSb upper barrier sublayer 63 is grown on the InAs upper barrier insertion layer 62 to form the upper barrier layer 6.

[0098] Specifically, maintaining a V / III beam ratio of 5:1, AlSb is grown for another 6-10 nm to form the second AlSb upper barrier sublayer 63, thus completing the fabrication of the upper barrier layer 6.

[0099] S6. Grow an InAlAs hole-blocking layer 7 on the upper barrier layer 6. (See above) Figure 3a .

[0100] Specifically, maintaining a V / III group beam ratio of 10:1 and an Al:In beam ratio of 1:3, 4-6 nm InAlAs material is generated on the surface of the upper barrier layer 6 to form an InAlAs hole blocking layer 7.

[0101] S7. Grow an InAs cap layer 8 on the InAlAs hole-blocking layer 7. (See below) Figure 3a .

[0102] Specifically, a 4-6 nm thick Si doping concentration of 2 × 10⁻⁶ nm is epitaxially grown on the surface of the InAlAs hole-blocking layer 7. 19 ~2.2×10 19 cm -3 The highly doped InAs material forms an InAs cap layer 8.

[0103] Next, the temperature was adjusted to 380~420℃ in the As atmosphere, and then the As source was turned off; when the sample reached room temperature, the growth of the InAs / AlSb HEMT epitaxial material was completed.

[0104] S8. Fabricate source 9 and drain 10 on the InAs cap layer 8, such that source 9 and drain 10 are spaced a certain distance apart. Please refer to [link to documentation]. Figure 3b .

[0105] Specifically, both source 9 and drain 10 are ohmic contacts, and both involve photolithography, exposure, development, electron beam evaporation to deposit metal, lift-off, and annealing. The materials for source 9 and drain 10 include alloy materials or non-alloy materials. Alloy materials include one or more of Ni and Au, and non-alloy materials include one or more of Pd, Pt, and Au.

[0106] The method for preparing the source electrode 9 and drain electrode 10 by metal method includes: first, cleaning the InAs / AlSb HEMT epitaxial material prepared above with BOE and deionized water, and drying it with nitrogen gas; then, placing the epitaxial material into an electron beam evaporation chamber, and evacuating the chamber to a vacuum of 2×10⁻⁶. -7 ~3×10 -7 The torr method involves depositing Ni / Au / Ni / Au source and drain electrodes with thicknesses of 10~20nm / 100~120nm / 50~60nm / 100~120nm respectively on the epitaxial material. Afterwards, the sample is annealed at a temperature below 300°C, and the metal is peeled off by ultrasound in acetone to ensure that the metal edges are completely intact and form ohmic contacts as source 9 and drain 10, with a certain distance between source 9 and drain 10.

[0107] The method for preparing the source electrode 9 and drain electrode 10 using the non-alloy method includes: cleaning the InAs / AlSb HEMT epitaxial material prepared above with BOE and deionized water, and drying it with nitrogen gas; then, placing the epitaxial material into an electron beam evaporation chamber and evacuating the chamber to a vacuum of 2×10⁻⁶. -7 Torr, a 10-12 nm Pd metal layer is deposited on the epitaxial material. After cooling for 30-45 minutes, a 30-40 nm Pt layer is deposited as the second layer. Finally, an 80-100 nm Au layer is deposited directly on top. Afterward, the sample is annealed at 240-260 °C, and the metal is peeled off by ultrasound in acetone to ensure that the metal edge is completely ohmic contact to serve as the source 9 and drain 10, with a certain distance between the source 9 and drain 10.

[0108] After forming source 9 and drain 10, electrical isolation is achieved by mesa etching of the device. Please refer to [link to documentation]. Figure 3c .

[0109] Specifically, electrical isolation typically employs a wet isolation method. The specific method is as follows: First, an etching solution is prepared by mixing H3PO4, H2O2, and deionized water in a ratio of 5:3:100. Then, the prepared device is etched at 22°C at a etching rate of approximately 50-60 nm / min, etching 100-120 nm into the p-type GaSb insertion layer 3. This process removes the InAs cap layer 8, InAlAs hole blocking layer 7, upper barrier layer 6, InAs channel layer 5, lower barrier layer 4, and a portion of the p-type GaSb insertion layer 3, forming a mesa isolation layer.

[0110] S9. Etch the InAs cap layer 8 to form a gate trench 110 located on the InAlAs hole blocking layer 7 and between the source 9 and the drain 10, and fabricate the gate 11 in the gate trench 110.

[0111] In this embodiment, the fabrication of the gate 11 includes photolithography, exposure, development, electron beam evaporation deposition of metal, and stripping. Specifically, the steps include:

[0112] First, etch the gate groove 110, please refer to... Figure 3d .

[0113] Specifically, first, mix 1-1.2 grams of solid C6H8O7·H2O with 1-1.2 ml of deionized water, stir and let stand for one day until fully dissolved to form citric acid liquid. Then, mix the citric acid liquid with 30% H2O2 in a 1:1 ratio and stir thoroughly to form an etching solution for the gate trench. Next, use the etching solution to sequentially etch the oxide layer on the surface of the InAs cap layer 8 and the InAs cap layer 8 until the InAlAs hole blocking layer 7 is formed, creating the gate trench 110. The gate trench 110 can be trapezoidal in shape. A trapezoidal gate trench avoids direct connection between the gate and the source / drain, while also reducing the distance from the gate to the channel, thus increasing gate control capability.

[0114] Then, the gate 11 is fabricated in the gate trench 110, see [link to documentation]. Figure 3e The gate is an 11-bit front-side gate, and its material includes one or more of Ti, Pt, and Au.

[0115] Specifically, the oxide layer on the surface of the InAlAs hole blocking layer 7 at the bottom of the gate trench 110 is acid-treated, and then Ti / Pt / Au metals with thicknesses of 20~30nm / 20~30nm / 150~200nm are sequentially deposited by electron beam evaporation to form the gate 11.

[0116] S10. Etch the GaAs substrate 1 and the AlGaSb buffer layer 2 to form a back hole 120 on the back side of the p-type GaSb insertion layer 3, and deposit a back gate 12 on the surface of the back hole 120 and the back side of the GaAs substrate 1. Please refer to [link to relevant documentation]. Figure 3f .

[0117] In this embodiment, the back gate 12 is fabricated using photolithography, exposure, development, back hole etching, lift-off, and metal deposition processes. Specifically, firstly, GaAs substrate 1 and AlGaSb buffer layer 2 are etched on the back side of the device, extending to the back side of p-type GaSb insertion layer 3, forming a back hole 120; the shape of the back hole 120 can be trapezoidal. Then, Cr / Au metals with thicknesses of 10~20nm and 100~120nm are sequentially deposited on the back side of the device, forming the back gate 12 located on the surface of the back hole 120 and the back side of the GaAs substrate 1.

[0118] The device prepared by the method in this embodiment significantly enhances the suppression of collisional ionization effects and can effectively improve performance such as noise, transition frequency, and leakage current while ensuring the concentration of two-dimensional electron gas in the device.

[0119] Example 3

[0120] Based on Example 2, please combine Figure 2 and Figures 3a-3f This embodiment provides a method for fabricating an InAs / AlSb heterojunction RF field-effect transistor device. The specific dimensions of this InAs / AlSb heterojunction RF field-effect transistor device are as follows: GaAs substrate 1 is 2 inches in size; GaAs material layer 101 has a thickness of 200 nm; AlGaSb buffer layer 2 has a thickness of 700 nm; p-type GaSb insertion layer 3 has a thickness of 20 nm; the first AlSb lower barrier sublayer 41 has a thickness of 40 nm; the InAs lower barrier insertion layer 42 has a thickness of 5 nm; the second AlSb lower barrier sublayer 43 has a thickness of 10 nm; the InAs channel layer 5 has a thickness of 15 nm; the first AlSb upper barrier sublayer 61 has a thickness of 5 nm; and the InAs upper barrier insertion layer 62 has a Si doping concentration of 10%. 19 cm -3 The InAlAs consists of 2-5 molecular layers, with the second AlSb barrier sublayer 63 having a thickness of 8 nm, the InAlAs hole blocking layer 7 having a thickness of 6 nm, the InAs cap layer 8 having a thickness of 6 nm, and the Si doping concentration being 2 × 10⁻⁶. 19 cm -3 The source 9 and drain 10 are both made of Ni / Au / Ni / Au with a thickness of 10nm / 100nm / 50nm / 100nm, the gate 11 is made of Ti / Pt / Au metal with a thickness of 20nm / 20nm / 200nm, and the back gate 12 is made of Cr / Au metal with a thickness of 10nm / 100nm.

[0121] The fabrication method of this InAs / AlSb heterojunction-based radio frequency field-effect transistor device specifically includes the following steps:

[0122] S1. Grow an AlGaSb buffer layer 2 on GaAs substrate 1. (See below) Figure 3a .

[0123] First, a 2-inch GaAs semi-insulating material was selected as the GaAs substrate 1; the GaAs substrate 1 was placed in the vacuum chamber of the MBE device at a 0.5° offset angle, and the vacuum level was maintained at 10. -11 torr, then adjust the vacuum level to 10. -8 torr; Next, the GaAs substrate is heated to 580°C in an As atmosphere for deoxidation treatment, and a 200nm GaAs material is grown to form a GaAs material layer 101.

[0124] Then, 700 nm Al was grown on the substrate surface via MBE. 0.7 Ga 0.3 Sb forms an AlGaSb buffer layer 2 to release the lattice mismatch stress between the GaAs material 101 and the p-type GaSb insertion layer 3.

[0125] S2. Grow a p-type GaSb insertion layer 3 on the AlGaSb buffer layer 2. (See below) Figure 3a .

[0126] Specifically, the temperature was adjusted to 480℃, and a V / III beam ratio of 4:1 was maintained to grow a 20nm p-type GaSb insertion layer 3 on the AlGaSb buffer layer 2. This insertion layer can effectively suppress the impact ionization effect.

[0127] S3. A lower barrier layer 4 is grown on the p-type GaSb insertion layer 3.

[0128] For details, please see Figure 3a If the lower barrier layer 4 includes a first AlSb lower barrier sublayer 41, an InAs lower barrier insertion layer 42, and a second AlSb lower barrier sublayer 43, then step S3 includes:

[0129] S31. A first AlSb lower barrier sublayer 41 is grown on the p-type GaSb insertion layer 3.

[0130] Specifically, the temperature is adjusted to 550℃, and a V / III beam ratio of 5:1 is maintained to grow 40nm of AlSb material on the p-type GaSb insertion layer 3 to form the first AlSb lower barrier sublayer 41.

[0131] S32. An InAs lower barrier insertion layer 42 is grown on the first AlSb lower barrier sublayer 41.

[0132] Specifically, by maintaining a V / III beam ratio of 10:1, a 5nm InAs material is grown on the first AlSb lower barrier sublayer 41 to form an InAs lower barrier insertion layer 42, which serves as the secondary channel of the device. The first AlSb lower barrier insertion layer 41 can also effectively suppress the impact ionization effect.

[0133] S33. A second AlSb lower barrier sublayer 43 is grown on the InAs lower barrier insertion layer 42 to form the lower barrier layer 4.

[0134] Specifically, by maintaining a V / III beam ratio of 5:1, 10 nm of AlSb is grown on the buffer layer to form the second AlSb lower barrier sublayer 43, thus completing the growth of the lower barrier layer 4.

[0135] S4. Grow InAs channel layer 5 on the lower barrier layer 4. (See below) Figure 3a .

[0136] Specifically, on the surface of the lower barrier layer 4, 15nm of InAs is generated as the main channel of the device by maintaining a V / III beam ratio of 10:1, thus forming the InAs channel layer 5.

[0137] S5. A barrier layer 6 is grown on the InAs channel layer 5.

[0138] For details, please see Figure 3a If the upper barrier layer 6 includes a first AlSb upper barrier sublayer 61, an InAs upper barrier insertion layer 62, and a second AlSb upper barrier sublayer 63, then step S5 includes:

[0139] S51. A first AlSb upper barrier sublayer 61 is grown on the InAs channel layer 5.

[0140] Specifically, 5 nm of AlSb is grown on the InAs channel layer 5 while maintaining a V / III beam ratio of 5:1 to form the first AlSb barrier sublayer 61.

[0141] S52. An InAs barrier insertion layer 62 is grown on the first AlSb barrier sublayer 61.

[0142] Specifically, maintaining a V / III beam ratio of 10:1, an InAs insertion layer of 2-5 molecular layers is grown on the first AlSb barrier sublayer 61, and a concentration of 10 is achieved. 19 cm -3 The Si doping, with the insertion layer acting as a δ-doped InAs spacer, can increase the two-dimensional electron gas concentration and suppress collisional ionization effects.

[0143] S53. A second AlSb upper barrier sublayer 63 is grown on the InAs upper barrier insertion layer 62 to form the upper barrier layer 6.

[0144] Specifically, maintaining a V / III beam ratio of 5:1, we continue to grow 8 nm of AlSb to form the second AlSb upper barrier sublayer 63, thus completing the fabrication of the upper barrier layer 6.

[0145] S6. Grow an InAlAs hole-blocking layer 7 on the upper barrier layer 6. (See above) Figure 3a .

[0146] Specifically, maintaining a V / III group beam ratio of 10:1 and an Al:In beam ratio of 1:3, a 6nm InAlAs material is generated on the surface of the upper barrier layer 6 to form an InAlAs hole blocking layer 7.

[0147] S7. Grow an InAs cap layer 8 on the InAlAs hole-blocking layer 7. (See below) Figure 3a .

[0148] Specifically, a 6 nm thick Si doping concentration of 2 × 10⁻⁶ was epitaxially grown on the surface of the InAlAs hole blocking layer 7. 19 cm -3 The highly doped InAs material forms an InAs cap layer 8.

[0149] Next, the temperature was adjusted to 400℃ in the As atmosphere, and then the As source was turned off; when the sample returned to room temperature, the growth of the InAs / AlSb HEMT epitaxial material was completed.

[0150] S8. Fabricate source 9 and drain 10 on the InAs cap layer 8, such that source 9 and drain 10 are spaced a certain distance apart. Please refer to [link to documentation]. Figure 3b .

[0151] Specifically, both the source electrode 9 and the drain electrode 10 are ohmic contacts, and both involve photolithography, exposure, development, electron beam evaporation to deposit metal, lift-off, and annealing steps. In this embodiment, the source electrode 9 and the drain electrode 10 are made of alloy materials, including one or more of Ni and Au.

[0152] The method for preparing the source electrode 9 and drain electrode 10 by metal method includes: first, cleaning the InAs / AlSb HEMT epitaxial material prepared above with BOE 10:1 and deionized water, and then drying it with nitrogen gas; then, placing the epitaxial material into an electron beam evaporation chamber and evacuating the chamber to a vacuum of 2×10⁻⁶. -7 The torr method deposits Ni / Au / Ni / Au source and drain electrodes with thicknesses of 10nm / 100nm / 50nm / 100nm on the epitaxial material. Then, the electrodes are annealed at a temperature below 300°C, and the metal is peeled off by ultrasonication in acetone to ensure that the metal edges are completely intact and form ohmic contacts as source 9 and drain 10, with a certain distance between source 9 and drain 10.

[0153] After forming source 9 and drain 10, electrical isolation is achieved by mesa etching of the device. Please refer to [link to documentation]. Figure 3c .

[0154] Specifically, electrical isolation typically employs a wet isolation method. The method involves first preparing an etching solution using H3PO4, H2O2, and deionized water in a ratio of 5:3:100. Then, the prepared device is etched at 22°C at a rate of approximately 60 nm / min, etching 100-120 nm into the p-type GaSb insertion layer 3. This process removes the InAs cap layer 8, InAlAs hole blocking layer 7, upper barrier layer 6, InAs channel layer 5, lower barrier layer 4, and a portion of the p-type GaSb insertion layer 3, forming a mesa isolation layer.

[0155] S9. Etch the InAs cap layer 8 to form a gate trench 110 located on the InAlAs hole blocking layer 7 and between the source 9 and the drain 10, and fabricate the gate 11 in the gate trench 110.

[0156] In this embodiment, the fabrication of the gate 11 includes photolithography, exposure, development, electron beam evaporation deposition of metal, and stripping. Specifically, the steps include:

[0157] First, etch the gate groove 110, please refer to... Figure 3d .

[0158] Specifically, first, 1 gram of solid C6H8O7·H2O and 1 ml of deionized water are mixed and stirred for one day to fully dissolve, forming a citric acid liquid. Then, at 22°C, the citric acid liquid and 30% H2O2 are mixed in a 1:1 ratio and stirred thoroughly to form an etching solution for the gate trench. Next, the etching solution is used to sequentially etch the oxide layer on the surface of the InAs cap layer 8 and the InAs cap layer 8 itself, etching down to the InAlAs hole-blocking layer 7 to form the gate trench 110. The gate trench 110 can be trapezoidal in shape. A trapezoidal gate trench avoids direct connection between the gate and the source / drain, while also reducing the distance between the gate and the channel, thus increasing gate control capability.

[0159] Then, the gate 11 is fabricated in the gate trench 110, see [link to documentation]. Figure 3e The gate is an 11-bit front-side gate, and its material is a Ti / Pt / Au metal system.

[0160] Specifically, the oxide layer on the surface of the InAlAs hole blocking layer 7 at the bottom of the gate trench 110 is acid-treated, and then Ti / Pt / Au metals with thicknesses of 20nm / 20nm / 200nm are sequentially deposited by electron beam evaporation to form the gate 11.

[0161] S10. Etch the GaAs substrate 1 and the AlGaSb buffer layer 2 to form a back hole 120 on the back side of the p-type GaSb insertion layer 3, and deposit a back gate 12 on the surface of the back hole 120 and the back side of the GaAs substrate 1. Please refer to [link to relevant documentation]. Figure 3f .

[0162] In this embodiment, the back gate 12 is fabricated using photolithography, exposure, development, back hole etching, lift-off, and metal deposition processes. Specifically, firstly, GaAs substrate 1 and AlGaSb buffer layer 2 are etched on the back side of the device, extending to the back side of p-type GaSb insertion layer 3, forming a back hole 120; the shape of the back hole 120 can be trapezoidal. Then, Cr / Au metals with thicknesses of 10nm and 100nm are sequentially deposited on the back side of the device to form the back gate 12 located on the surface of the back hole 120 and the back side of the GaAs substrate 1.

[0163] The device prepared by the method in this embodiment significantly enhances the suppression of collisional ionization effects and can effectively improve performance such as noise, transition frequency, and leakage current while ensuring the concentration of two-dimensional electron gas in the device.

[0164] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A radio frequency field-effect transistor device based on an InAs / AlSb heterojunction, characterized in that, The structure includes a GaAs substrate (1), an AlGaSb buffer layer (2), a p-type GaSb insertion layer (3), a lower barrier layer (4), an InAs channel layer (5), an upper barrier layer (6), an InAlAs hole blocking layer (7), an InAs cap layer (8), a source (9), a drain (10), and a gate (11). The GaAs substrate (1), AlGaSb buffer layer (2), p-type GaSb insertion layer (3), lower barrier layer (4), InAs channel layer (5), upper barrier layer (6), InAlAs hole blocking layer (7), and InAs cap layer (8) are stacked sequentially; the lower barrier layer (4) includes a first AlSb lower barrier sublayer (41), an InAs lower barrier insertion layer (42), and a second AlSb lower barrier sublayer (43) stacked sequentially, and the first AlSb lower barrier sublayer... (41) Located on the p-type GaSb insertion layer (3); the upper barrier layer (6) includes a first AlSb upper barrier sublayer (61), an InAs upper barrier insertion layer (62), and a second AlSb upper barrier sublayer (63) stacked sequentially, and the first AlSb upper barrier sublayer (61) is located on the InAs channel layer (5); the InAs upper barrier insertion layer (62) is 2 to 5 molecular layers of δ-doped InAs, the doping element includes Si, and the doping concentration is 1×10 19 ~1.2×10 19 cm -3 ; The source (9) and the drain (10) are both located on the InAs cap layer (8), and the source (9) and the drain (10) are separated by a certain distance; A gate trench (110) is provided in the InAs cap layer (8). The gate trench (110) is located between the source (9) and the drain (10) and on the InAlAs hole blocking layer (7). The gate (11) is located in the gate trench (110).

2. The InAs / AlSb heterojunction-based radio frequency field-effect transistor device according to claim 1, characterized in that, The material of the AlGaSb buffer layer (2) includes Al 0.7 Ga 0.3 Sb, with a thickness of 600~800nm; The doping element of the p-type GaSb insertion layer (3) includes Si, and the thickness is 10~30nm; The thickness of the first AlSb lower barrier sublayer (41) is 40~50nm, the thickness of the InAs lower barrier insertion layer (42) is 4~6nm, and the thickness of the second AlSb lower barrier sublayer (43) is 8~12nm. The thickness of the InAs channel layer (5) is 10~20nm; The thickness of the first AlSb barrier sublayer (61) is 4~6 nm; The thickness of the second AlSb barrier sublayer (63) is 4~6 nm; The thickness of the InAlAs hole blocking layer (7) is 4~6nm; The InAs cap layer (8) is doped with Si at a concentration of 2 × 10⁻⁶. 19 ~2.2×10 19 cm -3 The thickness is 4~6nm.

3. The InAs / AlSb heterojunction-based radio frequency field-effect transistor device according to claim 1, characterized in that, It also includes the back grille (12), in which, The GaAs substrate (1) and the AlGaSb buffer layer (2) are provided with a back hole (120) located on the back side of the p-type GaSb insertion layer (3), and the back gate (12) covers the surface of the back hole (120) and the back side of the GaAs substrate (1).

4. The InAs / AlSb heterojunction-based radio frequency field-effect transistor device according to claim 1, characterized in that, It also includes a GaAs material layer (101) located between the GaAs substrate (1) and the AlGaSb buffer layer (2).

5. A method for fabricating a radio frequency field-effect transistor device based on an InAs / AlSb heterojunction, characterized in that, Including the following steps: S1. An AlGaSb buffer layer (2) is grown on a GaAs substrate (1); S2. Grow a p-type GaSb insertion layer (3) on the AlGaSb buffer layer (2); S3. Growing a lower barrier layer (4) on the p-type GaSb insertion layer (3); including: growing a first AlSb lower barrier sublayer (41) on the p-type GaSb insertion layer (3); growing an InAs lower barrier insertion layer (42) on the first AlSb lower barrier sublayer (41); growing a second AlSb lower barrier sublayer (43) on the InAs lower barrier insertion layer (42) to form the lower barrier layer (4); S4. An InAs channel layer (5) is grown on the lower barrier layer (4); S5. Growing an upper barrier layer (6) on the InAs channel layer (5); including: growing a first AlSb upper barrier sublayer (61) on the InAs channel layer (5); growing an InAs upper barrier insertion layer (62) on the first AlSb upper barrier sublayer (61); growing a second AlSb upper barrier sublayer (63) on the InAs upper barrier insertion layer (62) to form the upper barrier layer (6); the InAs upper barrier insertion layer (62) is 2 to 5 molecular layers of δ-doped InAs, the doping element includes Si, and the doping concentration is 1×10 19 ~1.2×10 19 cm -3 ; S6. An InAlAs hole blocking layer (7) is grown on the upper barrier layer (6); S7. An InAs cap layer (8) is grown on the InAlAs hole blocking layer (7); S8. A source (9) and a drain (10) are fabricated on the InAs cap layer (8) such that the source (9) and the drain (10) are separated by a certain distance. S9. The InAs cap layer (8) is etched to form a gate trench (110) located on the InAlAs hole blocking layer (7) and between the source (9) and the drain (10), and a gate (11) is fabricated in the gate trench (110).

6. The fabrication method of the InAs / AlSb heterojunction-based radio frequency field-effect transistor device according to claim 5, characterized in that, Step S9 is followed by: S10. The GaAs substrate (1) and the AlGaSb buffer layer (2) are etched to form a back hole (120) on the back side of the p-type GaSb insertion layer (3), and a back gate (12) is deposited on the surface of the back hole (120) and the back side of the GaAs substrate (1).

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