An amplifier that reduces system imbalance

Abstract

The application discloses an amplifier capable of reducing system imbalance, which is based on a five-tube amplifier circuit with a current mirror as a load, and a clamping circuit composed of a fourth NMOS tube Mn4 and a fifth NMOS tube Mn5 is added to the amplifier circuit, the clamping function of the Mn4 and Mn5 can make the drain-source voltage of a first NMOS tube Mn1 and a second NMOS tube Mn2 of a differential pair of NMOS tubes in the amplifier remain equal within the normal working range of the amplifier, when the output voltage Vout changes, the drain-source voltage of the Mn1 and Mn2 can follow the change and remain equal, so that the system imbalance of the Mn1 and Mn2 is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to amplifier technology, in particular to an amplifier for reducing system imbalance, by adding a clamping circuit composed of a fourth NMOS transistor Mn4 and a fifth NMOS transistor Mn5 to a five-transistor amplifier circuit loaded by a current mirror, the clamping effect of Mn4 and Mn5 can make the drain-source voltage of the first NMOS transistor Mn1 and the second NMOS transistor Mn2 of the NMOS differential pair in the amplifier remain equal within the normal working range of the amplifier, when the output voltage Vout changes, the drain-source voltage of Mn1 and Mn2 changes and can remain equal, thereby reducing the system imbalance of Mn1 and Mn2. BACKGROUND

[0002] When the output voltage of the five-transistor amplifier loaded by a current mirror changes, the Vds (drain-source voltage) of the negative input MOS changes with the output, and the Vds of the positive input MOS hardly changes. In this way, the system imbalance of the input differential pair will be relatively large, and will also change with the change of the output voltage. For example Figure 2 , Figure 2 is a schematic diagram of a five-transistor amplifier circuit in the prior art. Figure 2 The first PMOS transistor Mp1 and the second PMOS transistor Mp2 including gate interconnection are included, the source of Mp1 and the source of Mp2 are respectively connected to the power supply voltage terminal VDD, the drain of Mp2 is respectively connected to the output voltage terminal Vout and the drain of the second NMOS transistor Mn2, the gate of Mn2 is connected to the negative input voltage terminal Vin-, the gate-drain interconnection of Mp1 is connected to the drain of the first NMOS transistor Mn1, the gate of Mn1 is connected to the positive input voltage terminal Vin+, the source of Mn1 and the source of Mn2 are both connected to the drain of the third NMOS transistor Mn3, the gate of Mn3 is connected to the first bias voltage terminal Vbn, and the source of Mn3 is grounded. As shown in Figure 2 the conventional five-transistor amplifier circuit, in which Mn1 and Mn2 constitute an NMOS differential pair, Mp1 and Mp2 constitute a PMOS current mirror load, and Mn3 serves as a tail current of the differential pair. When the input common-mode voltage is determined, since Mp1 is diode-connected, the drain voltage of Mp1 hardly changes within the normal working range of the amplifier, so that the drain-source voltage Vds of Mn1 remains unchanged, but the drain of Mp2 and the drain of Mn2 serve as the output terminal of the amplifier, and the drain-source voltage Vds of Mn2 changes with the change of the output voltage. This results in a relatively large system imbalance of the input differential pair Mn1 and Mn2, and the system imbalance changes with the change of the output voltage. SUMMARY

[0003] The present application provides an amplifier for reducing system imbalance, which is based on a five-tube amplifier circuit with a current mirror as a load, and a clamping circuit composed of a fourth NMOS tube Mn4 and a fifth NMOS tube Mn5 is added to the amplifier circuit, the clamping effect of Mn4 and Mn5 can make the drain-source voltage of the first NMOS tube Mn1 and the second NMOS tube Mn2 of the NMOS differential pair in the amplifier remain equal within the normal working range of the amplifier, when the output voltage Vout changes, the drain-source voltage of Mn1 and Mn2 can also change and remain equal, thereby reducing the system imbalance of Mn1 and Mn2.

[0004] The technical solution of the present application is as follows:

[0005] An amplifier for reducing system imbalance, characterized in that a clamping circuit is arranged between a current mirror load and an NMOS differential pair, the clamping effect of the clamping circuit can make the drain-source voltage of the first NMOS tube Mn1 and the second NMOS tube Mn2 of the NMOS differential pair remain equal within the normal working range of the amplifier, when the output voltage Vout changes, the drain-source voltage of Mn1 and Mn2 can also change and remain equal, thereby reducing the system imbalance of Mn1 and Mn2.

[0006] The clamping circuit comprises a fourth NMOS tube Mn4 and a fifth NMOS tube Mn5 which are interconnected at the gate, the source of Mn5 is connected to the output voltage terminal Vout and the drain of Mn2 respectively, the sources of Mn2 and Mn1 are interconnected and connected to a tail current source MOS tube which is grounded, the source of Mn4 is connected to the drain of Mn1, the gate of Mn1 is connected to a positive input voltage terminal Vin+, the gate of Mn2 is connected to a negative input voltage terminal Vin-, the gate and the drain of Mn5 are interconnected, the drain of Mn4 and the drain of Mn5 are connected to a power supply voltage terminal VDD through the current mirror respectively.

[0007] The tail current source MOS tube is a third NMOS tube Mn3, the drain of Mn3 is connected to the source of Mn1, the source of Mn3 is grounded, and the gate of Mn3 is connected to a first bias voltage terminal Vbn.

[0008] The current mirror comprises a first PMOS tube Mp1 and a second PMOS tube Mp2 which are interconnected at the gate, the source of Mp1 and the source of Mp2 are connected to the power supply voltage terminal VDD respectively, the gate and the drain of Mp1 are connected to the drain of Mn4 after being interconnected, and the drain of Mp2 is connected to the drain of Mn5.

[0009] An amplitude recovery circuit is further included, the amplitude recovery circuit comprises a third PMOS tube Mp3, the drain of Mp3 is connected to the source of Mn5, the source of Mp3 is connected to the drain of Mn5, and the gate of Mp3 is connected to a second bias voltage terminal Vbp.

[0010] The transient response acceleration circuit comprises a fourth PMOS tube Mp4, a source of the Mp4 is connected with a power voltage terminal VDD, a drain of the Mp4 is connected with an output voltage terminal Vout, and a gate of the Mp4 is connected with a gate of the Mp2.

[0011] The technical effect of the application is as follows: the amplifier for reducing system imbalance is improved on the basis of the traditional circuit, a clamping circuit is added to make the Vds of the input differential pair approximately equal, an amplitude recovery circuit is added to reach the amplitude level of the traditional circuit, and a transient response acceleration circuit is added to accelerate the transient response of the circuit.

[0012] The application has the advantages of simple circuit structure, ingenious design, and small system imbalance of the input differential pair. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a schematic diagram of the amplifier circuit for reducing system imbalance according to the application.

[0014] Figure 2 is a schematic diagram of a five-tube amplifier circuit in the prior art.

[0015] Figure 3 is a schematic diagram of the amplifier circuit for reducing system imbalance by adding a clamping circuit to the five-tube amplifier circuit.

[0016] Figure 4 is a schematic diagram of the amplifier circuit for reducing system imbalance by adding an amplitude recovery circuit to the five-tube amplifier circuit. Figure 3

[0017] The reference signs are listed as follows: VDD-power voltage terminal; Mn1-Mn5-first NMOS tube to fifth NMOS tube; Mp1-Mp4-first PMOS tube to fourth PMOS tube; Vin+-positive input voltage terminal; Vin--negative input voltage terminal; Vout-output voltage terminal; Vbn-first bias voltage terminal; Vbp-second bias voltage terminal. DETAILED DESCRIPTION

[0018] The application will be described below in conjunction with the drawings. Figures 1-4

[0019] Figure 1 is a schematic diagram of the amplifier circuit for reducing system imbalance according to the application. Figure 2 is a schematic diagram of a five-tube amplifier circuit in the prior art. Figure 3 is a schematic diagram of the amplifier circuit for reducing system imbalance by adding a clamping circuit to the five-tube amplifier circuit. Figure 4 is a schematic diagram of the amplifier circuit for reducing system imbalance by adding an amplitude recovery circuit to the five-tube amplifier circuit. Figure 3 is a schematic diagram of the amplifier circuit for reducing system imbalance by adding an amplitude recovery circuit to the five-tube amplifier circuit.​​Figures 1 to 4 As shown in the figure, an amplifier for reducing system imbalance, comprising a clamping circuit arranged between a current mirror load and an NMOS differential pair, the clamping function of the clamping circuit makes the drain-source voltage of the first NMOS transistor Mn1 and the second NMOS transistor Mn2 of the NMOS differential pair remain equal within the normal working range of the amplifier, when the output voltage Vout changes, the drain-source voltage of Mn1 and Mn2 changes and remains equal, thereby reducing the system imbalance of Mn1 and Mn2.

[0020] The clamping circuit comprises a fourth NMOS transistor Mn4 and a fifth NMOS transistor Mn5 interconnected at the gate, the source of Mn5 is connected to the output voltage terminal Vout and the drain of Mn2 respectively, the sources of Mn2 and Mn1 are interconnected and grounded through a tail current source MOS transistor, the source of Mn4 is connected to the drain of Mn1, the gate of Mn1 is connected to the positive input voltage terminal Vin+, the gate of Mn2 is connected to the negative input voltage terminal Vin-, Mn5 is interconnected at the gate and the drain, the drain of Mn4 and the drain of Mn5 are connected to the power supply voltage terminal VDD through the current mirror respectively. The tail current source MOS transistor is a third NMOS transistor Mn3, the drain of Mn3 is connected to the source of Mn1, the source of Mn3 is grounded, and the gate of Mn3 is connected to the first bias voltage terminal Vbn. The current mirror comprises a first PMOS transistor Mp1 and a second PMOS transistor Mp2 interconnected at the gate, the sources of Mp1 and Mp2 are connected to the power supply voltage terminal VDD respectively, Mp1 is interconnected at the gate and the drain and is connected to the drain of Mn4, and the drain of Mp2 is connected to the drain of Mn5. An amplitude recovery circuit is included, the amplitude recovery circuit comprises a third PMOS transistor Mp3, the drain of Mp3 is connected to the source of Mn5, the source of Mp3 is connected to the drain of Mn5, and the gate of Mp3 is connected to the second bias voltage terminal Vbp. A transient response acceleration circuit is included, the transient response acceleration circuit comprises a fourth PMOS transistor Mp4, the source of Mp4 is connected to the power supply voltage terminal VDD, the drain of Mp4 is connected to the output voltage terminal Vout, and the gate of Mp4 is connected to the gate of Mp2.

[0021] The five-transistor amplifier with current mirror as load is the most commonly used amplifier, when the output voltage changes, the Vds of the negative input MOS changes with the output, and the Vds of the positive input MOS hardly changes. In this way, the system imbalance of the input differential pair will be relatively large, and will also change with the change of the output voltage. Therefore, the present application proposes an improved circuit, based on the traditional circuit, a clamping circuit is added to make the Vds of the input differential pair approximately equal, thereby reducing the system imbalance of the input differential pair. The clamping circuit will limit the output swing, therefore, an amplitude recovery circuit is added to make the output swing of the circuit consistent with that of the traditional circuit.

[0022] Figure 3 As shown in the figure, the design is based on Figure 2Improved amplifier circuit, on the basis of traditional circuit such as Figure 2 Mn4, Mn5 constitute a clamping circuit. Due to the clamping effect of Mn4, Mn5, the drain-source voltage of input differential pair Mn1, Mn2 is kept equal in the normal working range of the amplifier. When the output voltage changes, the drain-source voltage of Mn1, Mn2 changes simultaneously and can remain equal. This can reduce the system imbalance of Mn1, Mn2.

[0023] Figure 4 As shown in Figure 3 , on the basis of adding swing recovery circuit. Due to the addition of clamping circuit, the maximum output of the amplifier is Vdd-Vgs-Vdsat (power voltage-gate-source voltage-drain end saturation voltage), and the maximum output of the traditional circuit is Vdd-Vdsat. This design restores the output swing to the level of the traditional amplifier by adding Mp3. When the output voltage is higher than Vdd-Vgs-Vdsat, Mn5 is closed, Mp3 is opened, and the current of Mp2 flows to the output through Mp3. At this time, the maximum output of the amplifier can also approach Vdd-Vdsat.

[0024] For the circuit in Figure 4 , when the output voltage is slightly greater than Vdd-Vgs-Vdsat, the circuit will go through a process of Mn5 closing and Mp3 opening, which is not conducive to the transient response of the circuit. On this basis, Mp4 is added to speed up the transient response of the circuit, as shown in Figure 1 .

[0025] The contents not described in detail in the specification of the present invention belong to the prior art known to those skilled in the art. It is indicated here that the above description is helpful for those skilled in the art to understand the present invention, but does not limit the protection scope of the present invention. Any equivalent replacement, modification, improvement and / or deletion of the above description without departing from the essential content of the present invention falls within the protection scope of the present invention.

Claims

1. An amplifier for reducing system offset, characterized in that, The system includes a clamping circuit positioned between the current mirror load and the NMOS differential pair. The clamping effect of the clamping circuit ensures that the drain-source voltages of the first NMOS transistor Mn1 and the second NMOS transistor Mn2 of the NMOS differential pair remain equal within the normal operating range of the amplifier. When the output voltage Vout changes, the drain-source voltages of Mn1 and Mn2 change accordingly and remain equal, thereby reducing the system offset of Mn1 and Mn2. The clamping circuit includes a fourth NMOS transistor Mn4 and a fifth NMOS transistor Mn5 with interconnected gates. The source of Mn5 is connected to the output voltage terminal Vout and the drain of Mn2, respectively. The sources of Mn2 and Mn1 are interconnected and grounded through a tail current source MOS transistor. The source of Mn4 is connected to the drain of Mn1. The gate of Mn1 is connected to the positive input voltage terminal Vin+. The gate of Mn2 is connected to the negative input voltage terminal Vin-. The gate and drain of Mn5 are interconnected. The drains of Mn4 and Mn5 are connected to the power supply voltage terminal VDD through the current mirror, respectively.

2. The amplifier for reducing system offset according to claim 1, characterized in that, The tail current source MOS transistor is the third NMOS transistor Mn3. The drain of Mn3 is connected to the source of Mn1, the source of Mn3 is grounded, and the gate of Mn3 is connected to the first bias voltage terminal Vbn.

3. The amplifier for reducing system offset according to claim 1, characterized in that, The current mirror includes a first PMOS transistor Mp1 and a second PMOS transistor Mp2 with gate interconnection. The source of Mp1 and the source of Mp2 are respectively connected to the power supply voltage terminal VDD. The gate-drain interconnection of Mp1 is connected to the drain of Mn4, and the drain of Mp2 is connected to the drain of Mn5.

4. The amplifier for reducing system offset according to claim 1, characterized in that, The circuit includes a swing recovery circuit, which includes a third PMOS transistor Mp3. The drain of Mp3 is connected to the source of Mn5, the source of Mp3 is connected to the drain of Mn5, and the gate of Mp3 is connected to the second bias voltage terminal Vbp.

5. The amplifier for reducing system offset according to claim 1, characterized in that, It includes a transient response acceleration circuit, which includes a fourth PMOS transistor Mp4. The source of Mp4 is connected to the power supply voltage terminal VDD, the drain of Mp4 is connected to the output voltage terminal Vout, and the gate of Mp4 is connected to the gate of Mp2.

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