A multi-phase clock generation circuit

Abstract

The present application discloses a multi-phase clock generation circuit, comprising: a first frequency divider, which receives a first clock signal and divides the first clock signal to generate a second clock signal with multiple phases; a second frequency divider, which is connected to the first frequency divider and divides the clock signal of a certain phase in the second clock signal; a plurality of first latch circuits connected in sequence, wherein the second frequency divider outputs the divided clock signal to the first first latch circuit, and each first latch circuit delays the clock signal output by the previous first latch circuit and outputs it to the next first latch circuit; and a plurality of first logic circuits, which respectively receive the output of the first frequency divider and one of the first latch circuits, and generate a third clock signal after performing a logical operation. The frequencies of the first clock signal, the second clock signal, and the third clock signal decrease in sequence, and the number of phases increases in sequence. The present application does not require a clock synchronization reset circuit, which can reduce power consumption and clock jitter.

Description

Technical Field

[0001] The present invention generally relates to the technical field of integrated circuits, and in particular to a multi-phase clock generation circuit. Background Art

[0002] With the development of communication technology, the amount of data generated per unit time is increasing, and the required communication speed is also getting faster and faster. Therefore, high-speed analog-to-digital converters are becoming more and more important. For 32GS / S or 64GS / S sampling rates, clock-interleaved analog-to-digital converters are a more conventional architecture. For clock interleaving circuits, complex clock generation circuits are required to create the interleaving of multiple phase clocks. For clock generation circuits, functionally speaking, the relative order of phases must be met. In addition, low power consumption and low clock jitter are both necessary performances. However, for many traditional clock generation methods that use dividers to generate multiple phases, there is a necessary module, the clock synchronization reset module, to ensure that the clock is synchronized from the source, without any glitches, and the phase relationship is completely determined. For reference, Figure 1 The clock generation circuit using clock synchronous reset and frequency divider shown in . Figure 2 The following diagrams illustrate correct and incorrect eight-phase timing sequences for traditional multi-phase clock generation using frequency dividers. Due to space limitations, the eight-phase diagrams illustrate the potential differences in phase order caused by the lack of a correct clock reset initial state. Furthermore, all subsequent frequency dividers must be reset to specific states to ensure the correct timing of each divider, significantly increasing the complexity of the design. Another issue with clock synchronization reset is the additional power consumption and clock jitter, both of which require optimization. Furthermore, as analog-to-digital converters become faster, clock synchronization will become impossible, or multiple input clocks will be generated using other circuits, making clock synchronization impossible. Summary of the Invention

[0003] The object of the present invention is to provide a multi-phase clock generation circuit that does not require a clock synchronization reset circuit and can reduce power consumption and clock jitter.

[0004] The present application discloses a multi-phase clock generation circuit, comprising:

[0005] a first frequency divider, receiving a first clock signal and dividing the first clock signal to generate a second clock signal having multiple phases;

[0006] a second frequency divider, connected to the first frequency divider and dividing the frequency of a clock signal of a certain phase in the second clock signal;

[0007] A plurality of first latch circuits are connected in sequence, wherein the second frequency divider outputs a divided clock signal to the first of the first latch circuits, and starting from the first first latch circuit, second clock signals of each phase after the first phase are sequentially sent to each first latch circuit, and the second clock signals of each phase are cyclically sent to the corresponding first latch circuits from the beginning to the end, and each first latch circuit delays the clock signal output by the previous first latch circuit and outputs it to the next first latch circuit;

[0008] a plurality of first logic circuits, respectively receiving the output of the first frequency divider and one of the first latch circuits, and generating a third clock signal after performing a logic operation;

[0009] The frequencies of the first clock signal, the second clock signal and the third clock signal decrease in sequence, and the numbers of phases increase in sequence.

[0010] In a preferred example, the first frequency divider is a 1 / 2 frequency divider.

[0011] In a preferred example, the second frequency divider is a 1 / 4 frequency divider.

[0012] In a preferred example, the first clock signal is a 32 GHz clock signal with phases of 0° and 180°, the second clock signal is a 16 GHz clock signal with phases of 0°, 90°, 180° and 270°, and the third clock signal is a 4 GHz clock signal with 16 phases.

[0013] In a preferred example, the plurality of first logic circuits are NAND gate logic.

[0014] In a preferred embodiment, the multi-phase clock generation circuit further includes:

[0015] a signal acquisition unit, configured to acquire a clock signal of a certain phase in the third clock signal or a clock signal output by one of the plurality of latch circuits, wherein the phase of the clock signal acquired by the signal acquisition unit is the same as the phase of the clock signal acquired by the second frequency divider;

[0016] a third frequency divider, configured to divide the frequency of the signal output by the signal acquisition unit;

[0017] A plurality of second latch circuits connected in sequence, wherein the third frequency divider outputs a divided clock signal to the first of the first latch circuits, and starting from the first second latch circuit, the third clock signals of each phase after the first phase are sequentially sent to each second latch circuit, and the third clock signals of each phase are cyclically sent to the corresponding second latch circuits from the first to the last, and each second latch circuit delays the clock signal output by the previous second latch circuit and outputs it to the next second latch circuit;

[0018] Several second logic circuits respectively receive the output of the signal acquisition unit and one of the second latch circuits, perform logic operations and generate a fourth clock signal. The frequency of the fourth clock signal is lower than that of the third clock signal, and the number of phases is greater than that of the third clock signal.

[0019] In a preferred example, the third frequency divider is a 1 / 4 frequency divider.

[0020] In a preferred example, the plurality of second logic circuits are NAND gate logic.

[0021] In a preferred example, the fourth clock signal is a 1 GHz clock signal with 64 phases.

[0022] In a preferred example, the duty cycle of the second clock signal is 50%, the duty cycle of the third clock signal is 12.5%, and the duty cycle of the fourth clock signal is 12.5%.

[0023] Compared with the prior art, the multi-phase clock generation circuit of the present invention has the following beneficial effects:

[0024] In this invention, multi-phase implementation is achieved using high-speed clock latch delays, eliminating the need for clock synchronization reset circuits. Phase sequencing is guaranteed with any asynchronous reset. Both the first and second stages of the step sampling employ similar implementations. The second stage of the step sampling uses the first stage's clock as input, ensuring the order and timing relationship between the first and second stage sampling circuits, thereby achieving clock jitter reduction while minimizing power consumption.

[0025] This specification records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above invention content of this specification, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Non-limiting and non-exhaustive embodiments of the present application are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified.

[0027] Figure 1 A schematic diagram of a multi-phase clock generation circuit in the prior art is shown.

[0028] Figure 2 FIG. 4 shows a timing diagram for generating an 8-phase clock in the prior art.

[0029] Figure 3 A schematic diagram of a multi-phase clock generation circuit in an embodiment of the present application is shown.

[0030] Figure 4 A timing diagram for generating a 16-phase clock in an embodiment of the present application is shown.

[0031] Figure 5 A schematic diagram of a third clock signal and a fourth clock signal with a phase of 0° in an embodiment of the present application is shown.

[0032] Description of reference numerals:

[0033] 101 - first frequency divider, 102 - second frequency divider, 103 - first latch circuit, 104 - first logic circuit, 105 - signal acquisition unit, 106 - third frequency divider, 107 - second latch circuit, 108 - second logic circuit DETAILED DESCRIPTION

[0034] Various aspects and examples of the present application will now be described. The following description provides specific details for a thorough understanding and implementation of the description of these examples. However, it will be understood by those skilled in the art that the present application can be practiced without many of these details.

[0035] Additionally, some well-known structures or functions may not be shown or described in detail to maintain clarity and avoid unnecessarily obscuring the relevant description.

[0036] The terms used in the description given below are intended to be interpreted in their broadest reasonable manner, even when used in conjunction with the detailed description of certain specific examples of the present application. Certain terms may even be emphasized below, however, any term intended to be interpreted in any restricted manner will be clearly and specifically defined in this detailed description section.

[0037] Explanation of some terms:

[0038] A frequency divider is an electronic circuit that generates an output signal with an integer fraction of the input signal frequency. For any N-fold frequency divider, with the input signal unchanged, the output signal can have a phase of 2pi / N. This phenomenon is inherent to the frequency divider and is independent of the specific circuitry of the frequency divider. It is known as the multi-valued phase of the frequency divider output.

[0039] A latch circuit is a pulse-level-sensitive memory cell circuit that changes state in response to a specific input pulse level. Latching temporarily stores a signal to maintain a specific level. The primary function of a latch is to provide buffering, followed by resolving asynchronous issues between high-speed controllers and slower peripherals, further resolving driver issues, and finally, enabling an I / O port to function as both an input and output port. Latches utilize level control to control data input and come in two types: latches without and latches with enable controls.

[0040] Logic circuit: A circuit that transmits and processes discrete signals, uses binary as the principle, and implements logical operations and manipulations of digital signals.

[0041] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0042] In one embodiment of the present application, a multi-phase clock generation circuit is provided. Figure 3 A schematic diagram of a multi-phase clock generation circuit in one embodiment is shown. The circuit includes: a first frequency divider 101 , a second frequency divider 102 , a plurality of first latch circuits 103 , and a plurality of first logic circuits 104 . Figure 3In the example of achieving a predetermined phase relationship of 16 clocks, it should be understood that the present application is not limited to generating a clock with 16 phases. For example, 64 phases, 32 phases, 8 phases, etc. can also be generated, and the present invention is not limited thereto. The first frequency divider 101, the second frequency divider 102, the plurality of first latch circuits 103, and the plurality of first logic circuits 104 can generate a first-stage sampling clock.

[0043] A first frequency divider 101 receives a first clock signal and divides the first clock signal to generate a second clock signal with multiple phases. A second frequency divider 102 is connected to the first frequency divider 101 and divides the clock signal of a phase within the second clock signal. Several first latch circuits 103 are connected in sequence. The second frequency divider 102 outputs the divided clock signal to the first of the first latch circuits. Starting from the first first latch circuit, the second clock signal of each phase after the first phase is sent to each first latch circuit in sequence. The second clock signal of each phase is sent to the corresponding first latch circuits in a cyclic manner from the first to the last. Each first latch circuit delays the clock signal output by the previous first latch circuit and outputs it to the next first latch circuit. Several first logic circuits receive the output of the first frequency divider and one of the first latch circuits, perform logical operations, and generate a third clock signal after performing a logical operation. In one embodiment, the frequencies of the first clock signal, the second clock signal, and the third clock signal decrease in sequence, and the number of phases increases in sequence.

[0044] In one embodiment, the first frequency divider 101 is a 1 / 2 frequency divider. The first clock signal passes through the first frequency divider 101 to generate a second clock signal having a frequency half that of the first clock signal. For example, the first clock signal has a frequency of 32 GHz, and the second clock signal has a frequency of 16 GHz. Furthermore, the second clock signal can have multiple phases and an adjustable duty cycle. It should be understood that the first frequency divider is not limited to a 1 / 2 frequency divider; for example, it can also be a 1 / 4 frequency divider.

[0045] In one embodiment, the second frequency divider 102 is a 1 / 4 frequency divider. The second clock signal is passed through the second frequency divider 102 to generate a third clock signal having a frequency of 1 / 4 of the second clock signal. For example, the frequency of the second clock signal is 16 GHz and the frequency of the third clock signal is 4 GHz. In addition, the third clock signal can have multiple phases and an adjustable duty cycle. It should be understood that the second frequency divider is not limited to a 1 / 4 frequency divider. For example, it can also be a 1 / 2 frequency divider. It should be noted that the second frequency divider 101 takes the clock signal of phase 0 in the second clock signal. It should be understood that clock signals of other phases can also be used for frequency division, and the present invention is not limited to this.

[0046] In one embodiment, the first clock signal is a 32 GHz clock signal with phases of 0° and 180°, the second clock signal is a 16 GHz clock signal with phases of 0°, 90°, 180°, and 270°, and the third clock signal is a 4 GHz clock signal with 16 phases.

[0047] In one embodiment, the plurality of first logic circuits 104 are NAND gate logic.

[0048] In other embodiments, the multi-phase clock generation circuit further includes: a signal acquisition unit 105, a third frequency divider 106, a plurality of second latch circuits 107, and a plurality of second logic circuits 108. The signal acquisition unit 105, the third frequency divider 106, the plurality of second latch circuits 107, and the plurality of second logic circuits 108 are used to generate a second-stage sampling clock.

[0049] The signal acquisition unit 105 is configured to acquire a clock signal of a certain phase within the third clock signal or a clock signal output by one of the plurality of latch circuits, wherein the phase of the clock signal acquired by the signal acquisition unit is the same as the phase of the clock signal acquired by the second frequency divider. A third frequency divider 106 is configured to frequency-divide the signal output by the signal acquisition unit. A plurality of second latch circuits 107 are connected in sequence, wherein the third frequency divider outputs the divided clock signal to the first of the first latch circuits. Starting with the first second latch circuit, the third clock signal of each subsequent phase is sequentially transmitted to each second latch circuit, and the third clock signal of each subsequent phase is cyclically transmitted to the corresponding second latch circuits from the first to the last. Each second latch circuit delays the clock signal output by the previous second latch circuit and outputs it to the next second latch circuit. A plurality of second logic circuits receive the outputs of the signal acquisition unit and one of the second latch circuits, perform logical operations, and generate a fourth clock signal after performing a logical operation. The fourth clock signal has a lower frequency than the third clock signal and a greater number of phases than the third clock signal.

[0050] In one embodiment, the third frequency divider is a 1 / 4 frequency divider.

[0051] In one embodiment, the plurality of second logic circuits are NAND gate logics.

[0052] In one embodiment, the fourth clock signal is a 1 GHz clock signal with 64 phases.

[0053] In one embodiment, the duty cycle of the second clock signal is 50%, the duty cycle of the third clock signal is 12.5%, and the duty cycle of the fourth clock signal is 12.5%.

[0054] In order to better understand the technical solution of this specification, a specific example is used below for illustration. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0055] Combine Figure 3 and Figure 4 As shown, the example of generating a 4GHz clock signal with 16 phases from a 32GHz clock signal is used for explanation. The clock generation circuit in this embodiment includes 16 latch circuits 103 and 16 NAND gate logic circuits 104. The phases of the 32GHz clock signal include 0° and 180°. After passing through the first frequency divider 101, a 16GHz clock signal with 4 phases is generated, with phases of 0°, 90°, and 180° respectively.

[0056] and 270°, the duty cycle is 50%, such as Figure 4 CK4T <0> ,CK4T <1> ,CK4T <2> ,CK4T <3> The clock signal with a phase of 0° is output to the second frequency divider 102, and the second frequency divider 102 outputs a clock signal CK16T with a divided frequency of 4 GHz and a duty cycle of 25%. <0> , clock signal CK16T <0> Output to the first latch circuit 103, the first latch circuit and the clock signal CK4T with a 90° phase <1> Output to the second latch circuit, the second latch circuit and the clock signal CK4T with 180° phase <2> Output to the third latch circuit, the third latch circuit and the clock signal CK4T with a 270° phase <3> Output to the fourth latch circuit, the fourth latch circuit and the 0° phase clock signal CK4T <0> Output to the fifth latch circuit, ..., and so on, until the sixteenth latch circuit. The first latch circuit outputs CK16T <0> , the second latch circuit outputs CK16T <1> , the third latch circuit outputs CK16T <2> , ..., and so on, the sixteenth latch circuit outputs CK16T <15> After passing through each latch circuit, 16 clock signals CK16T with 16 phases delayed in sequence are generated. <0> to CK16T <15> . And, CK16T <0> to CK16T <15> The corresponding output is sent to each NAND gate logic circuit, and after logical operation, a 16-phase clock signal with a frequency of 4 GHz and a duty cycle of 12.5% ​​is generated. At the same time, the second clock signal CK4T of the four phases <0> ,CK4T <1> ,CK4T <2> ,CK4T <3> Output to each NAND gate logic circuit respectively, and then connect to CK16T <0> to CK16T <15> A third clock circuit that generates 16 phases.

[0057] refer to Figure 4 As shown, Figure 4The timing diagram for the 16 phases of the first-level sampling is generated, specifically, CK4T <0> With CK16T <10> The first phase clock signal is generated through the NAND gate logic, CK4T <1> With CK16T <11> The second phase clock signal is generated through the NAND gate logic, CK4T <2> With CK16T <12> The third phase clock signal is generated through the NAND gate logic, CK4T <3> With CK16T <13> The fourth phase clock signal is generated through the NAND gate logic, CK4T <0> With CK16T <14> The fifth phase clock signal is generated through the NAND gate logic, CK4T <1> With CK16T <15> The sixth phase clock signal is generated through the NAND gate logic, CK4T <2> With CK16T <0> The seventh phase clock signal is generated through the NAND gate logic, CK4T <3> With CK16T <1> The eighth phase clock signal is generated through the NAND gate logic, CK4T <0> With CK16T <2> The ninth phase clock signal is generated through the NAND gate logic, CK4T <1> With CK16T <3> The tenth phase clock signal is generated through the NAND gate logic, CK4T <2> With CK16T <4> The eleventh phase clock signal is generated through the NAND gate logic, CK4T <3> With CK16T <5> The twelfth phase clock signal is generated through the NAND gate logic, CK4T <0> With CK16T <6> The thirteenth phase clock signal is generated through the NAND gate logic, CK4T <1> With CK16T <7> The fourteenth phase clock signal is generated through the NAND gate logic, CK4T <2> With CK16T <8> The fifteenth phase clock signal is generated through the NAND gate logic, CK4T <3> With CK16T <9> The sixteenth phase clock signal is generated through the NAND gate logic.

[0058] Continue to refer Figure 3 As shown, the clock generation circuit also includes a signal acquisition unit 105, a third frequency divider 106, a plurality of second latch circuits 107, and a plurality of second logic circuits 108. The second logic circuit can also be a NAND gate logic circuit. The signal acquisition unit 105 is connected to the first latch circuit and is used to obtain the clock signal output by any one of the first latch circuits. In this embodiment, the signal acquisition unit 105 is connected to the first latch circuit, obtains the clock signal with a phase of 0° among the 16 phases and outputs it to the third frequency divider 106. The clock generation circuit includes 64 second latch circuits 107 and 64 NAND gate logic circuits 108, which are used to generate 64-phase clock signals, which can be used as the second-stage sampling clock. It should be understood that the signal acquisition unit 105 can also be connected to the output of the first logic circuit.

[0059] The third frequency divider 106 is a 1 / 4 frequency divider. It generates a 1 GHz, 25% duty cycle clock signal and outputs it to the first second latch circuit 107. The phases are 0°, 22.5°, 45°, 67.5°, 90°, 112.5°, 135°, 157.5°, 180°, 202.5°, 225°, 247.5°, 270°, 292.5°, 315°, and 337.5°, respectively. Starting from the first second latch circuit 107, the third clock signal of each phase after phase 0° is sequentially transmitted to each second latch circuit. The third clock signal of each phase is then cyclically transmitted to the corresponding second latch circuits from the beginning to the end. For example, a clock signal with a phase of 22.5° is transmitted to the second second latch circuit, a clock signal with a phase of 45° is transmitted to the third second latch circuit, and so on. The connection method is similar to that of the first latch circuit and will not be described in detail here. Each second latch circuit delays the clock signal output by the previous second latch circuit and outputs it to the next second latch circuit, and finally outputs 64 clock signals to 64 NAND gate logic circuits respectively.

[0060] The NAND gate logic circuit receives one of the phases of 0°, 22.5°, 45°, 67.5°, 90°, 112.5°, 135°, 157.5°, 180°, 202.5°, 225°, 247.5°, 270°, 292.5°, 315°, and 337.5°, and generates a fourth clock signal after performing a logic operation with the output of one of the second latch circuits, thereby generating a fourth clock signal with 64 phases, a frequency of 1 GHz, and a duty cycle of 12.5%. The phase of the third clock signal and the fourth clock signal is 0°, which is a signal reference. Figure 5 The process of the NAND gate logic circuit 108 is similar to that of the NAND gate logic circuit 104, and will not be described in detail here.

[0061] In this invention, multi-phase implementation is achieved using high-speed clock latch delays, eliminating the need for clock synchronization reset circuits. Phase sequencing is guaranteed with any asynchronous reset. Both the first and second stages of the step sampling employ similar implementations. The second stage of the step sampling uses the first stage's clock as input, ensuring the order and timing relationship between the first and second stage sampling circuits, thereby achieving clock jitter reduction while minimizing power consumption.

[0062] It should be noted that in this patent application, relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element specified by the phrase "comprising a" does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element. In this patent application, reference to performing an action in accordance with an element means performing the action in accordance with at least that element, including two situations: performing the action in accordance with that element alone, and performing the action in accordance with that element and other elements. Expressions such as "plurality," "multiple times," and "many" include "two," "twice," "two kinds," and "more than two," "more than two times," and "more than two kinds."

[0063] All documents mentioned in this specification are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above description is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

[0064] In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. Additionally, the processes depicted in the accompanying drawings do not necessarily require the particular order shown or sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A multi-phase clock generation circuit, characterized in that: include: a first frequency divider, receiving a first clock signal and dividing the first clock signal to generate a second clock signal having multiple phases; a second frequency divider, connected to the first frequency divider and dividing the frequency of a clock signal of a certain phase in the second clock signal; A plurality of first latch circuits are connected in sequence, wherein the second frequency divider outputs a divided clock signal to the first of the first latch circuits, and starting from the first first latch circuit, second clock signals of each phase after the first phase are sequentially sent to each first latch circuit, and the second clock signals of each phase are cyclically sent to the corresponding first latch circuits from the beginning to the end, and each first latch circuit delays the clock signal output by the previous first latch circuit and outputs it to the next first latch circuit; a plurality of first logic circuits, respectively receiving the output of the first frequency divider and one of the first latch circuits, performing a NAND logic operation on the output and generating a third clock signal; The frequencies of the first clock signal, the second clock signal and the third clock signal decrease in sequence, and the numbers of phases increase in sequence.

2. The multi-phase clock generation circuit according to claim 1, wherein: The first frequency divider is a 1 / 2 frequency divider.

3. The multi-phase clock generation circuit according to claim 1, wherein: The second frequency divider is a 1 / 4 frequency divider.

4. The multi-phase clock generation circuit according to claim 1, wherein: The first clock signal is a 32 GHz clock signal with phases of 0° and 180°, the second clock signal is a 16 GHz clock signal with phases of 0°, 90°, 180°, and 270°, and the third clock signal is a 4 GHz clock signal with 16 phases.

5. The multi-phase clock generation circuit according to claim 1, wherein: The plurality of first logic circuits are NAND gate logic.

6. The multi-phase clock generation circuit according to claim 1, wherein: The multi-phase clock generation circuit further includes: a signal acquisition unit, configured to acquire a clock signal of a certain phase in the third clock signal or a clock signal output by a first latch circuit among the plurality of first latch circuits, wherein the phase of the clock signal acquired by the signal acquisition unit is the same as the phase of the clock signal acquired by the second frequency divider; a third frequency divider, configured to divide the frequency of the signal output by the signal acquisition unit; A plurality of second latch circuits connected in sequence, wherein the third frequency divider outputs a divided clock signal to the first of the second latch circuits, and starting from the first second latch circuit, the third clock signals of each phase after the first phase are sequentially sent to each second latch circuit, and the third clock signals of each phase are cyclically sent to the corresponding second latch circuits from the first to the last, and each second latch circuit delays the clock signal output by the previous second latch circuit and outputs it to the next second latch circuit; Several second logic circuits respectively receive the output of the signal acquisition unit and one of the second latch circuits, perform logic operations and generate a fourth clock signal. The frequency of the fourth clock signal is lower than that of the third clock signal, and the number of phases is greater than that of the third clock signal.

7. The multi-phase clock generation circuit according to claim 6, wherein: The third frequency divider is a 1 / 4 frequency divider.

8. The multi-phase clock generation circuit according to claim 6, wherein: The plurality of second logic circuits are NAND gate logic.

9. The multi-phase clock generation circuit according to claim 6, wherein: The fourth clock signal is a 1 GHz clock signal having 64 phases.

10. The multi-phase clock generation circuit according to claim 6, wherein: The duty cycle of the second clock signal is 50%, the duty cycle of the third clock signal is 12.5%, and the duty cycle of the fourth clock signal is 12.5%.

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