Semiconductor device

Abstract

A semiconductor device includes a semiconductor chip having a main surface, a high-potential region formed in a surface layer portion of the main surface, a low-potential region formed in the surface layer portion of the main surface at intervals from the high-potential region, a drift region of a first conductivity type formed in a region between the high-potential region and the low-potential region in the surface layer portion of the main surface, and a reduced-surface-electric-field region of the first conductivity type partially formed in a surface layer portion of the drift region so that a portion of a region that becomes a current path in the drift region is exposed from the main surface, the reduced-surface-electric-field region having an impurity concentration exceeding that of the drift region.

Description

Technical Field

[0001] This application corresponds to Japanese Patent Application No. 2020-023747, filed with the Japan Patent Office on February 14, 2020, the entire disclosure of which is incorporated herein by reference.

[0002] This invention relates to a semiconductor device. Background Technology

[0003] Patent Document 1 discloses a semiconductor device comprising a semiconductor layer, a first electrode, a second electrode, and a lateral element. The first electrode is formed on the surface of the semiconductor layer. The second electrode is formed at intervals from the first electrode on the surface of the semiconductor layer. The lateral element is formed in the surface portion of the semiconductor layer in the region between the first electrode and the second electrode, and is electrically connected to both the first electrode and the second electrode.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: U.S. Patent Application Publication No. 2013 / 075877 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] One embodiment of the present invention provides a semiconductor device capable of reducing on-resistance while suppressing voltage drop.

[0009] Methods for solving problems

[0010] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor chip having a main surface; a high-potential region formed on a surface portion of the main surface; a low-potential region formed at intervals from the high-potential region on the surface portion of the main surface; a drift region of a first conductivity type formed on the surface portion of the main surface in a region between the high-potential region and the low-potential region; and a reduced surface electric field region of the first conductivity type partially formed on the surface portion of the drift region such that a portion of a region in the drift region that becomes a current path is exposed from the main surface, the reduced surface electric field region having an impurity concentration exceeding that of the drift region.

[0011] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor chip having a main surface; a high-potential region and a low-potential region formed at intervals on a surface portion of the main surface; a drift region of a first conductivity type formed on the surface portion of the main surface in a region between the high-potential region and the low-potential region; a reduced surface electric field region of the first conductivity type formed on the surface portion of the drift region as a line extending in an opposing direction to the high-potential region and the low-potential region, such that a portion of a region in the drift region that becomes a current path is exposed from the main surface, the reduced surface electric field region having an impurity concentration exceeding that of the drift region; a field insulating film covering the drift region and the reduced surface electric field region; and a field electrode formed on the field insulating film and wound in a linear manner intersecting the reduced surface electric field region in a top view.

[0012] The above or other objects, features and effects of the present invention will become clear from the following description of the embodiments with reference to the accompanying drawings. Attached Figure Description

[0013] Figure 1 This is a top view of the semiconductor chip of the semiconductor device according to the first embodiment of the present invention.

[0014] Figure 2 yes Figure 1 An enlarged view of region II shown.

[0015] Figure 3 yes Figure 2 An enlarged view of region III shown.

[0016] Figure 4 yes Figure 2 The partial cutaway perspective view of region III shown.

[0017] Figure 5 It is along Figure 3 The cross-sectional view of the VV line shown.

[0018] Figure 6 This is an enlarged view showing the main part of the region where the surface electric field is reduced.

[0019] Figure 7 It is a measured curve used to illustrate the on-resistance.

[0020] Figure 8 It is a measured curve used to illustrate the breakdown voltage.

[0021] Figure 9 It is a measured graph used to illustrate the gate threshold voltage.

[0022] Figure 10 Is with Figure 5The corresponding figure is a cross-sectional view used to illustrate the semiconductor device according to the second embodiment of the present invention.

[0023] Figure 11 Is with Figure 5 The corresponding figure is a cross-sectional view used to illustrate the semiconductor device according to the third embodiment of the present invention.

[0024] Figure 12 Is with Figure 4 The corresponding figure is a three-dimensional sectional view used to illustrate the reduced surface electric field region of the first modified example.

[0025] Figure 13 Is with Figure 4 The corresponding figure is a perspective sectional view used to illustrate the reduced surface electric field region of the second modified example.

[0026] Figure 14 Is with Figure 4 The corresponding figure is a three-dimensional sectional view used to illustrate the reduced surface electric field region of the third modified example.

[0027] Figure 15 Is with Figure 4 The corresponding figure is a three-dimensional sectional view used to illustrate the reduced surface electric field region of the fourth modified example. Detailed Implementation

[0028] Figure 1 This is a top view showing the semiconductor chip 2 of the semiconductor device 1 according to the first embodiment of the present invention. Figure 2 yes Figure 1 An enlarged view of region II shown. Figure 3 yes Figure 2 An enlarged view of region III shown. Figure 4 yes Figure 2 The partial cutaway perspective view of region III shown. Figure 5 It is along Figure 3 The cross-sectional view of the VV line shown. Figure 6 This is an enlarged view of the main part of the region 20 where the surface electric field is reduced.

[0029] Reference Figures 1-6 The semiconductor device 1 includes a silicon semiconductor chip 2 in the shape of a cuboid. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed into quadrilateral shapes in a top view (hereinafter referred to as the "top view") viewed from their normal direction Z.

[0030] The first to fourth sides 5A to 5D include: a first side 5A, a second side 5B, a third side 5C, and a fourth side 5D. The first side 5A and the second side 5B extend in a first direction X and are opposite each other in a second direction Y, which is orthogonal to the first direction X. The third side 5C and the fourth side 5D extend in the second direction Y and are opposite each other in the first direction X. In this embodiment, the semiconductor chip 2 has a stacked structure comprising a p-type semiconductor substrate 6 and an n-type epitaxial layer 7 formed on the semiconductor substrate 6.

[0031] The semiconductor substrate 6 forms a portion of the second main surface 4 and the first to fourth side surfaces 5A to 5D. The semiconductor substrate 6 may have a size of 1.0 × 10⁻⁶. 13 cm -3 Above and 1.0×10 15 cm -3 The following are p-type impurity concentrations. The thickness of the semiconductor substrate 6 can be 100 μm or more and 500 μm or less. The epitaxial layer 7 forms a portion of the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0032] Epitaxial layer 7 can have an n-type impurity concentration exceeding that of semiconductor substrate 6. The n-type impurity concentration of epitaxial layer 7 can be 1.0 × 10⁻⁶. 14 cm -3 Above and 1.0×10 16 cm -3 The n-type impurity concentration of epitaxial layer 7 is preferably 1.0 × 10⁻⁶. 15 cm -3 Above and 5.0×10 15 cm -3 The thickness of epitaxial layer 7 can be greater than 5 μm and less than 20 μm.

[0033] The semiconductor device 1 includes a plurality of device regions 8 divided by a first main surface 3. The number and arrangement of the plurality of device regions 8 are arbitrary. Each of the plurality of device regions 8 includes a functional device formed using the first main surface 3 and / or the surface portion of the first main surface 3. The functional device may include at least one of a semiconductor switching device, a semiconductor rectifier device, and a passive device. The functional device may also include a circuit network formed by combining at least two of a semiconductor switching device, a semiconductor rectifier device, and a passive device.

[0034] Semiconductor switching devices may include at least one of MISFET (Metal Insulator Semiconductor Field-Effect Transistor), BJT (Bipolar Junction Transistor), IGBT (Insulated Gate Bipolar Junction Transistor), and JFET (Junction Field-Effect Transistor). Semiconductor rectifier devices may include at least one of pn junction diode, pin junction diode, Zener diode, Schottky barrier diode, and fast recovery diode. Passive devices may include at least one of resistor, capacitor, and inductor.

[0035] Multiple device regions 8 include LDMIS region 9 (refer to) Figure 1 Region II), this LDMIS region 9 is formed with an LDMISFET (Lateral Double Diffused MISFET), which is an example of a MISFET. The construction of LDMIS region 9 will be explained in detail below.

[0036] Reference Figures 2-5 Semiconductor device 1 includes an n-type impurity region 10 formed in the surface portion of a first main surface 3 within an LDMIS region 9. In this embodiment, the impurity region 10 is formed using a portion of an epitaxial layer 7. Therefore, the impurity region 10 has an n-type impurity concentration equal to that of the epitaxial layer 7. In this embodiment, the impurity region 10 is formed in an elongated oval shape in a top view. The impurity region 10 may also be formed in a circular, elliptical, or polygonal shape (e.g., a quadrilateral shape).

[0037] Semiconductor device 1 includes a high-potential region 11, a low-potential region 12, and a drift region 13 formed in the surface portion of a first main surface 3 in an LDMIS region 9. The high-potential region 11 is formed in the central portion of an impurity region 10. The low-potential region 12 is formed at intervals from the high-potential region 11 in the surface portion of the first main surface 3 and is connected to the impurity region 10. The drift region 13 is formed in the impurity region 10 in the region between the high-potential region 11 and the low-potential region 12.

[0038] Specifically, the high-potential region 11 includes an n-type well region 14 formed on the surface of the impurity region 10. The well region 14 has an n-type impurity concentration exceeding that of the impurity region 10. The n-type impurity concentration of the well region 14 can be 1.0 × 10⁻⁶. 15 cm -3 Above and 1.0×1018 cm -3 In this embodiment, the trap region 14 is formed in a top view as an elongated oval shape extending along the impurity region 10. The trap region 14 may also be formed as a circle, an ellipse, or a polygon (e.g., a quadrilateral shape).

[0039] The high-potential region 11 includes an n-type drain region 15 formed on the surface of the well region 14. The drain region 15 has an n-type impurity concentration exceeding that of the well region 14. The n-type impurity concentration of the drain region 15 can be 1.0 × 10⁻⁶. 18 cm -3 Above and 1.0×10 21 cm -3 Below. Drain regions 15 are formed at intervals from the periphery of the well region 14 within the well region 14. In this embodiment, the drain regions 15 are formed in a top view as an elongated oval shape extending along the well region 14. The drain regions 15 may also be formed in a circular, elliptical, or polygonal shape (e.g., a quadrilateral shape).

[0040] Specifically, the low potential region 12 includes a p-type body region 16 adjacent to the impurity region 10 and formed on the surface portion of the first main surface 3. The body region 16 may have a size of 1.0 × 10⁻⁶. 15 cm -3 Above and 1.0×10 18 cm -3 The following is the p-type impurity concentration. The body region 16 has a bottom connected to the semiconductor substrate 6, fixing the semiconductor substrate 6 at the same potential. The body region 16 is formed as a strip extending along the impurity region 10. Specifically, the body region 16 is formed as an annular shape (in this embodiment, an elongated annular shape) surrounding the impurity region 10, dividing the impurity region 10 into a predetermined shape (in this embodiment, an elongated oval shape).

[0041] In the top view, the body region 16 includes: a first straight portion 16A, a second straight portion 16B, a first curved portion 16C, and a second curved portion 16D. The first straight portion 16A is formed in the second direction Y on one side of the impurity region 10 and extends in the first direction X. The second straight portion 16B is formed in the second direction Y on the other side of the impurity region 10, opposite to the first straight portion 16A, and extends parallel to the first straight portion 16A. In the first direction X, the lengths of the first straight portion 16A and the second straight portion 16B are preferably less than or equal to the length of the drain region 15.

[0042] The first curved portion 16C is formed as a strip extending in an arc shape between one end of the first straight portion 16A and one end of the second straight portion 16B. The second curved portion 16D is opposite to the first curved portion 16C across the impurity region 10, and is formed as a strip extending in an arc shape between the other end of the first straight portion 16A and the other end of the second straight portion 16B.

[0043] The low potential region 12 includes n-type source regions 17 formed at intervals from the impurity region 10 on the surface portion of the body region 16. The source regions 17 are formed on the inner edge side (impurity region 10 side) of the body region 16 and define the channel region 18 of the LDMISFET between the source regions 17 and the impurity region 10 (drift region 13). The source regions 17 have an n-type impurity concentration exceeding that of the well region 14. The n-type impurity concentration of the source regions 17 can be 1.0 × 10⁻⁶. 18 cm -3 Above and 1.0×10 21 cm -3 The n-type impurity concentration in the source region 17 is preferably equal to the n-type impurity concentration in the drain region 15.

[0044] In this embodiment, the source electrode region 17 is formed as an ended strip in a portion of the body region 16 in a top view. Specifically, the source electrode region 17 is formed at intervals from the first curved portion 16C and the second curved portion 16D in the first straight portion 16A and the second straight portion 16B, respectively. That is, the source electrode region 17 is not formed in the first curved portion 16C and the second curved portion 16D of the body region 16. In the top view, the source electrode region 17 is formed as an ended strip extending along the first straight portion 16A and the second straight portion 16B.

[0045] The source region 17 is opposite the drain region 15 in the second direction Y, and a current path extending in the second direction Y is formed between the drift region 13 and the drain region 15. In the first direction X, the length of the source region 17 is preferably less than or equal to the length of the drain region 15. Of course, the source region 17 can also be formed as a ring surrounding the impurity region 10 (specifically, an elongated ring). That is, the source region 17 can also be formed in the first curved portion 16C and the second curved portion 16D of the body region 16.

[0046] The low-potential region 12 includes a p-type contact region 19 formed in the surface portion of the body region 16 in a region different from the source region 17. The contact region 19 is formed on the outer edge of the body region 16 (the side opposite to the impurity region 10), and is opposite to the channel region 18 across the source region 17. The contact region 19 has a p-type impurity concentration exceeding that of the body region 16. The p-type impurity concentration of the contact region 19 can be 1.0 × 10⁻⁶. 18 cm -3 Above and 1.0×10 21 cm -3 the following.

[0047] In this configuration, the contact area 19 is formed as an ended strip in a portion of the body region 16 in the top view. Specifically, the contact area 19 is formed at intervals from the first curved portion 16C and the second curved portion 16D of the body region 16 in the first straight portion 16A and the second straight portion 16B, respectively. That is, the contact area 19 is not formed in the first curved portion 16C and the second curved portion 16D of the body region 16. In the top view, the contact area 19 is formed as an ended strip extending along the first straight portion 16A and the second straight portion 16B.

[0048] The contact region 19 is opposite the drain region 15 in the second direction Y. In the first direction X, the length of the contact region 19 is preferably less than or equal to the length of the drain region 15. Of course, the contact region 19 may also be formed as an annular shape (specifically an elongated annular shape) surrounding the impurity region 10. That is, the contact region 19 may also be formed in the first curved portion 16C and the second curved portion 16D of the body region 16.

[0049] Drift region 13 is formed as a portion of impurity region 10. Drift region 13 forms a current path connecting high potential region 11 and low potential region 12. Specifically, drift region 13 is defined in impurity region 10 between drain region 15 (well region 14) and source region 17 (body region 16). Thus, drift region 13 forms a current path connecting drain region 15 and source region 17.

[0050] The drift region 13 is formed in a ring shape (in this embodiment, an elongated ring shape) surrounding the drain region 15. In this embodiment, the drift region 13 has a straight portion defined by the first straight portion 16A (second straight portion 16B) of the body region 16, and a curved portion defined by the first curved portion 16C (second curved portion 16D) of the body region 16. The distance between the drift regions 13 can be 50 μm or more and 200 μm or less. Preferably, the drift regions 13 are formed at a certain distance along the ring shape (in this embodiment, an elongated ring shape).

[0051] Reference Figures 4-6 Semiconductor device 1 includes an n-type reduced surface electric field region 20 locally formed on the surface portion of drift region 13, such that a portion of drift region 13 is exposed from a first main surface 3. The reduced surface electric field region 20 has an n-type impurity concentration exceeding that of drift region 13. The n-type impurity concentration of the reduced surface electric field region 20 may be 1.0 × 10⁻⁶. 15 cm -3 Above 5.0×10 16 cm -3 the following.

[0052] The upper limit for reducing the surface electric field region 20 is preferably 20 times the concentration of n-type impurities in the drift region 13. The reduction in the n-type impurity concentration of the surface electric field region 20 is preferably greater than 2.25 × 10⁻⁶. 15 cm -3 And it is 3.25×10 16 cm -3 The concentration of n-type impurities in the surface electric field region 20 is preferably 1.25 × 10⁻⁶. 15 cm -3 Above and 2.5×10 16 cm -3 The concentration of n-type impurities in the surface electric field region 20 is preferably lower than that in the well region 14.

[0053] In this configuration, a plurality of surface electric field reduction regions 20 are formed at intervals on the surface portion of the drift region 13. These regions are formed at intervals from the bottom of the drift region 13 toward the first main surface 3. Specifically, the plurality of surface electric field reduction regions 20 are formed shallower than the well region 14 and deeper than the drain region 15. The plurality of surface electric field reduction regions 20 are positioned opposite the semiconductor substrate 6, separated by a portion of the drift region 13.

[0054] In the top view, multiple surface electric field reduction regions 20 extend linearly in the opposite direction of the high potential region 11 and the low potential region 12, and are spaced apart in the orthogonal direction of the opposite direction to form a stripe pattern. As a result, in the top view, the multiple surface electric field reduction regions 20 cause a portion of the drift region 13 to be exposed from the first main surface 3 in a stripe pattern.

[0055] Multiple surface electric field reduction regions 20 are formed in the surface portion of the drift region 13 in the region between the drain region 15 and the body region 16. Specifically, the surface electric field reduction regions 20 are formed in the region between the well region 14 and the body region 16. In this embodiment, the surface electric field reduction region 20 has one end connected to the well region 14 and another end connected to the body region 16. Thus, the surface electric field reduction regions 20 form a current path that extends continuously in the region between the well region 14 and the body region 16.

[0056] Multiple surface electric field reduction regions 20 are formed at intervals from the curved portion of the drift region 13 on the straight portion of the drift region 13. That is, multiple surface electric field reduction regions 20 are not formed in the region between the first curved portion 16C (second curved portion 16D) of the drain region 15 and the body region 16. Multiple surface electric field reduction regions 20 are formed in the region between the first straight portion 16A (second straight portion 16B) of the drain region 15 and the body region 16.

[0057] Preferably, the surface electric field reduction regions 20 are locally formed on the surface portion of the drift region 13, such that a portion of the region in the drift region 13 that becomes a current path is exposed from the first main surface 3. That is, preferably, the plurality of surface electric field reduction regions 20 are formed only in the region between the drain region 15 and the source region 17 in the surface portion of the drift region 13. Thus, the surface electric field reduction regions 20 are formed in a current path that extends continuously in the region between the drain region 15 and the source region 17. When the source region 17 (contact region 19) is formed as an annulus surrounding the impurity region 10, the plurality of surface electric field reduction regions 20 can be formed on the curved portion of the drift region 13.

[0058] Semiconductor device 1 includes a plurality of drift line regions 13A (drift exposed regions) that are respectively divided in the surface portion of a drift region 13 between a plurality of adjacent reduced surface electric field regions 20. The plurality of drift line regions 13A are formed by a portion of the drift region 13. In a top view, the plurality of drift line regions 13A extend linearly in opposite directions to the high potential region 11 and the low potential region 12, and are alternately formed with the plurality of reduced surface electric field regions 20 in orthogonal directions to the opposite directions.

[0059] The n-type impurity concentration in the drift line region 13A is lower than that in the surface electric field reduction region 20. Therefore, the current density flowing through the drift line region 13A is lower than the current density flowing through the surface electric field reduction region 20. On the other hand, the depletion layer extending from the drift line region 13A is larger than the depletion layer extending from the surface electric field reduction region 20. Therefore, in the LDMIS region 9, the breakdown voltage is suppressed by the drift line region 13A, and the on-resistance Ron is reduced by the surface electric field reduction region 20.

[0060] Reference Figure 6 Each of the plurality of surface electric field reduction regions 20 has a first width W1. The first width W1 is the width in a direction orthogonal to the direction in which the surface electric field reduction region 20 extends. Each of the plurality of drift line regions 13A has a second width W2. The second width W2 is the width in a direction orthogonal to the direction in which the drift line region 13A extends.

[0061] The ratio W1 / W2 of the first width W1 of the reduced surface electric field region 20 to the second width W2 of the drift line region 13A can be 0.5 or more and 2.0 or less (0.5 ≤ W1 / W2 ≤ 2.0). Preferably, the ratio W1 / W2 is 1.0 or less (0.5 ≤ W1 / W2 ≤ 1.0). More preferably, the ratio W1 / W2 is less than 1.0 (0.5 ≤ W1 / W2 < 1.0). That is, it is preferable to form a reduced surface electric field region 20 with a width narrower than that of the drift line region 13A.

[0062] The first width W1 can be 1 μm or more and 5 μm or less. The second width W2 can be 1 μm or more and 5 μm or less. The first width W1 and the second width W2 are preferably 3 μm or less. The total value of the first width W1 and the second width W2, W1+W2, is preferably 3 μm or more and 6 μm or less.

[0063] In the opposing region between the drain region 15 and the source region 17, a plurality of surface electric field reduction regions 20 are formed at a first proprietary ratio R1. The first proprietary ratio R1 is the proportion of the plurality of surface electric field reduction regions 20 in the opposing region when the opposing region is set to "1". In the opposing region, a plurality of drift line regions 13A are formed at a second proprietary ratio R2. The second proprietary ratio R2 is the proportion of the plurality of drift line regions 13A in the opposing region when the opposing region is set to "1".

[0064] The second proprietary ratio R2 can be more than 0.5 times the first proprietary ratio R1 and less than 2.0 times the first proprietary ratio R1 (0.5×R1≤R2≤2×R1). The second proprietary ratio R2 is preferably more than the first proprietary ratio R1 (R1≤R2≤2×R1). The second proprietary ratio R2 is further preferably greater than the first proprietary ratio R1 (R1<R2≤2×R1).

[0065] Semiconductor device 1 includes a field insulating film 21 formed on a first main surface 3 in an LDMIS region 9 to cover a drift region 13 and a plurality of surface electric field reduction regions 20. The field insulating film 21 comprises silicon oxide. In this embodiment, the field insulating film 21 is composed of a LOCOS film formed by selective oxidation of the first main surface 3. The field insulating film 21 may have a thickness of 0.1 μm or more and 2 μm or less.

[0066] Specifically, the field insulating film 21, in a top view, is formed as an annular shape (in this embodiment, an elongated annular shape) covering the region between the drain region 15 and the body region 16. The field insulating film 21 includes an inner edge 22 and an outer edge 23. Figure 2 and Figure 3 In the diagram, the outer edge 23 of the field insulating film 21 is indicated by a dashed line. The inner edge 22 of the field insulating film 21 covers the well region 14, exposing the drain region 15.

[0067] The outer edge 23 of the field insulating film 21 is formed at intervals from the inner edge of the body region 16 toward the high potential region 11, exposing the body region 16, the source region 17, and the contact region 19. The outer edge 23 of the field insulating film 21 exposes a portion of the drift region 13 and a portion of the reduced surface electric field region 20 between itself and the inner edge of the body region 16.

[0068] Semiconductor device 1 includes an outer field insulating film 24 formed on a first main surface 3 to cover the area outside the LDMIS region 9. The outer field insulating film 24 has the same thickness as the field insulating film 21 and contains the same material as the field insulating film 21. That is, in this embodiment, the outer field insulating film 24 is made of a LOCOS film. The outer field insulating film 24 covers the outer edge of the body region 16, exposing the body region 16, the source region 17, and the contact region 19.

[0069] Reference Figure 4 as well as Figure 5 The semiconductor device 1 includes a field electrode 31 wound in a linear fashion on a field insulating film 21. In this embodiment, the field electrode 31 comprises conductive polysilicon. In this embodiment, the field electrode 31 is composed of a field resistive film electrically connected to a high-potential region 11 and a low-potential region 12. Specifically, the field electrode 31 is electrically connected to a drain region 15 and a body region 16 (source region 17 and contact region 19). The field electrode 31 forms a voltage drop from the high-potential region 11 toward the low-potential region 12, suppressing deviations in the electric field distribution in the drift region 13.

[0070] In the top view, the field electrode 31 extends in a linear form, intersecting multiple reduced surface electric field regions 20, and traverses these regions multiple times. Specifically, the field electrode 31 includes a straight-line extending portion and a curved-line extending portion. The field electrode 31 traverses the multiple reduced surface electric field regions 20 multiple times in its straight-line extending portion. That is, when a straight line connecting the high-potential region 11 and the low-potential region 12 is defined in the top view, the field electrode 31 traverses this straight line multiple times. In its curved-line extending portion, the field electrode 31 is positioned opposite the drift region 13 through the field insulating film 21.

[0071] Specifically, the field electrode 31 surrounds the high-potential region 11 multiple times in the top view. More specifically, the field electrode 31 is formed in a spiral shape in the top view, the spiral having an inner end 32 on the drain region 15 side, an outer end 33 on the body region 16 side, and a spiral portion 34 extending between the inner end 32 and the outer end 33. The arrangement of the inner end 32 and the outer end 33 is arbitrary.

[0072] In this configuration, the inner end portion 32 is formed at a position opposite to the drain region 15 in the second direction Y. The inner end portion 32 may be opposite to the well region 14 through the field insulating film 21. In this configuration, the outer end portion 33 is formed at a position opposite to the source region 17 in the second direction Y. The outer end portion 33 may be opposite to the drift line region 13A and the reduced surface electric field region 20 through the field insulating film 21.

[0073] In the top view, the spiral portion 34 is wound outward from the inner end 32 toward the outer end 33 in a manner that surrounds the drain region 15, forming an elongated spiral shape. The spiral portion 34 is opposed to the drift line region 13A and the reduced surface electric field region 20 through the field insulating film 21.

[0074] The field electrode 31 has a structure that generates a voltage drop in a helical direction from the inner end 32 to the outer end 33. That is, the field electrode 31 forms a potential gradient that gradually decreases from the high potential region 11 to the low potential region 12 in a direction orthogonal to the helical direction through a potential corresponding to the voltage drop. This electrical property of the field electrode 31 is used to suppress deviations in the electric field distribution in the drift region 13.

[0075] Reference Figure 6 The field electrode 31 has a linewidth W3. The linewidth W3 is defined by the width of a direction orthogonal to the extension direction (i.e., the helical direction) of the field electrode 31. The linewidth W3 can be 1 μm or more and 5 μm or less. Preferably, the linewidth W3 is 3 μm or less. The linewidth W3 can also be a first width W1 or more (W1 ≤ W3) for the surface electric field reduction region 20. The linewidth W3 can also be a second width W2 or more (W2 ≤ W3) for the drift line region 13A.

[0076] The resistance of the field electrode 31 can be 10 MΩ or more and 100 MΩ or less. The spacing between the field electrodes 31 can be 1 μm or more and 10 μm or less. Preferably, the spacing between the field electrodes 31 is 2 μm or more. The spacing between the field electrodes 31 is defined by the distance between adjacent portions (i.e., the winding spacing of the helical portion 34). The number of windings of the field electrodes 31 can be 5 or more and 20 or less. The linewidth W3, resistance, spacing, and number of windings of the field electrodes 31 are arbitrary and can be adjusted according to the electric field to be mitigated.

[0077] Semiconductor device 1 includes an inner field electrode 36 formed on a field insulating film 21 in a region between a field electrode 31 and a high-potential region 11 (drain region 15). In this embodiment, the inner field electrode 36 is formed in the region surrounded by the field electrode 31 and is fixed at the same potential as the high-potential region 11 (drain region 15). The inner field electrode 36 has the same thickness as the field electrode 31 and comprises the same material as the field electrode 31 (i.e., conductive polycrystalline silicon).

[0078] The inner field electrode 36 is formed as a ring (specifically an elongated ring) surrounding the drain region 15, spaced apart from the drain region 15 and the field electrode 31. The inner field electrode 36 can be positioned opposite the well region 14 through the field insulating film 21. Preferably, in a top view, the inner field electrode 36 is formed spaced apart from the plurality of reduced surface electric field regions 20 toward the drain region 15.

[0079] The inner field electrode 36 includes an inner edge portion 37 and an outer edge portion 38. The inner edge portion 37 of the inner field electrode 36 surrounds the drain region 15 at intervals from the drain region 15. Preferably, the inner edge portion 37 of the inner field electrode 36 is formed at approximately a certain interval from the drain region 15.

[0080] The outer edge 38 of the inner field electrode 36 is formed at intervals from the field electrode 31. Preferably, the outer edge 38 of the inner field electrode 36 is formed at approximately a certain interval from the field electrode 31. The distance between the inner field electrode 36 and the field electrode 31 is preferably equal to the spacing between the field electrodes 31.

[0081] In this configuration, the inner field electrode 36 is formed with a non-uniform width along the circumferential direction. Specifically, the inner field electrode 36 has a field extension 39 at its outer edge 38. The field extension 39 extends toward the field electrode 31 such that it is opposed to the front end of the inner end 32 in the helical direction of the field electrode 31. The field extension 39 maintains a substantially fixed distance between the inner field electrode 36 and the field electrode 31, suppressing electric field deviation caused by the inner end 32 of the field electrode 31.

[0082] In this configuration, the inner field electrode 36 is connected to the inner end 32 of the field electrode 31 and fixed at the same potential as the inner end 32. Specifically, the field extension 39 is connected to the inner end 32. As long as the inner field electrode 36 and the inner end 32 can be fixed at the same potential, the inner field electrode 36 does not necessarily need to be connected to the inner end 32. Furthermore, the presence or absence of the inner field electrode 36 is arbitrary and can be removed as needed.

[0083] The linewidth of the inner field electrode 36 can be 1 μm or more and 15 μm or less. The inner field electrode 36 is preferably formed to be wider than the field electrode 31. The linewidth of the inner field electrode 36 is preferably 1.5 times or more and 5 times or less than the linewidth W3 of the field electrode 31. Of course, the inner field electrode 36 can also be formed with a linewidth W3 or less.

[0084] Reference Figure 4 as well as Figure 5 The semiconductor device 1 includes a gate insulating film 40 covering a channel region 18 on a first main surface 3. In this embodiment, the gate insulating film 40 is made of silicon oxide. In a top view, the gate insulating film 40 is formed as a strip extending along a field insulating film 21, exposing the body region 16, the source region 17, and the contact region 19.

[0085] In this embodiment, the gate insulating film 40 is formed in a ring shape (specifically, an elongated ring shape) surrounding the field insulating film 21 in a top view. The gate insulating film 40 has a thickness less than that of the field insulating film 21 and is connected to the field insulating film 21 (outer edge 23). Thus, the gate insulating film 40 covers the portion exposed between the inner edge of the body region 16 and the outer edge 23 of the field insulating film 21 in the drift region 13 (drift line region 13A) and the reduced surface electric field region 20. The thickness of the gate insulating film 40 can be 10 nm or more and 200 nm or less.

[0086] Semiconductor device 1 includes a gate electrode 41 formed on a gate insulating film 40. The gate electrode 41 has the same thickness as the field electrode 31 and comprises the same material as the field electrode 31 (i.e., conductive polysilicon). The gate electrode 41 is opposed to the channel region 18 across the gate insulating film 40. In this embodiment, the gate electrode 41 is also opposed to the drift region 13 (drift line region 13A) and the reduced surface electric field region 20 across the gate insulating film 40. In a top view, the gate electrode 41 is formed as a strip extending along the field insulating film 21. In this embodiment, the gate electrode 41 is formed as an annulus (specifically, an elongated annulus) surrounding the field insulating film 21 in a top view.

[0087] The gate electrode 41 has a cover portion 42 extending from the gate insulating film 40 to the field insulating film 21. The cover portion 42 is formed as an annular shape (specifically an elongated annular shape) surrounding the field electrode 31 at intervals from the field electrode 31. The cover portion 42 is positioned opposite the drift region 13 and the reduced surface electric field region 20 through the field insulating film 21.

[0088] The gate electrode 41 includes an inner edge portion 43 and an outer edge portion 44. The inner edge portion 43 of the gate electrode 41 is formed by a cover portion 42, which, in the top view, traverses the drift line region 13A and the reduced surface electric field region 20. The inner edge portion 43 of the gate electrode 41 is preferably formed at approximately a certain interval from the field electrode 31. The distance between the gate electrode 41 and the field electrode 31 is preferably equal to the spacing of the field electrodes 31. The outer edge portion 44 of the gate electrode 41, in the top view, is formed in the region overlapping with the body region 16. The outer edge portion 44 of the gate electrode 41 is preferably formed at approximately a certain interval from the outer edge portion 23 of the field insulating film 21.

[0089] In this configuration, the gate electrode 41 is formed with a non-uniform width along the circumferential direction. In this configuration, the gate electrode 41 has a gate protrusion 45 at its inner edge 43. The gate protrusion 45 extends toward the field electrode 31 in a manner opposite to the front end of the outer end 33 in the helical direction of the field electrode 31. The gate protrusion 45 maintains a substantially fixed distance between the gate electrode 41 and the field electrode 31, suppressing electric field deviation caused by the outer end 33 of the field electrode 31.

[0090] Reference Figure 4 The semiconductor device 1 includes an insulating layer 71 stacked on a first main surface 3 and covering an LDMIS region 9. The insulating layer 71 is composed of a multilayer wiring structure 74, which has a stacked structure consisting of alternating layers of interlayer insulating layers 72 and multiple wiring layers 73. An interlayer insulating layer 72 is an insulating layer located between two adjacent wiring layers 73 in the vertical direction. The lowest interlayer insulating layer 72 is the insulating layer located between the semiconductor chip 2 and the initial wiring layer 73.

[0091] exist Figure 4 The text indicates the alternating layers of the first and second interlayer insulating layers 72A-72B and the first and second wiring layers 73A-73B in the multilayer wiring structure 74. The number of interlayer insulating layers 72 and wiring layers 73 is arbitrary and not limited to a specific value. The multilayer wiring structure 74 can have a multilayer structure consisting of three or more layers of interlayer insulating layers 72 and three or more layers of wiring layers 73 stacked alternately.

[0092] Each interlayer insulating layer 72 comprises at least one of a SiO2 film and a SiN film. Each interlayer insulating layer 72 may have a single-layer structure composed of a SiO2 film or a SiN film. Each interlayer insulating layer 72 may have a stacked structure consisting of one or more SiO2 films and / or one or more SiN films stacked in any order. Each wiring layer 73 may comprise at least one of an Al film, a Cu film, an AlSiCu alloy film, an AlSi alloy film, and an AlCu alloy film.

[0093] A plurality of first wiring layers 73A are formed on the first interlayer insulating layer 72A. The plurality of first wiring layers 73A are electrically connected to corresponding connection objects via one or more first via electrodes 75 penetrating the first interlayer insulating layer 72A. The first via electrodes 75 may be tungsten plug electrodes. Specifically, the plurality of first wiring layers 73A include: a first drain wiring 76, a first source wiring 77, a first gate wiring 78, an inner field wiring 79, and an outer field wiring 80.

[0094] The first drain wiring 76 is electrically connected to the drain region 15 via one or more first via electrodes 75. The first source wiring 77 is electrically connected to the source region 17 (body region 16 and contact region 19) via one or more first via electrodes 75. The first gate wiring 78 is electrically connected to the gate electrode 41 via one or more first via electrodes 75.

[0095] The inner field wiring 79 is electrically connected to the inner end 32 of the field electrode 31 via one or more first via electrodes 75. The inner field wiring 79 may also be electrically connected to the inner field electrode 36 via one or more first via electrodes 75. The inner field wiring 79 may also be integrally formed with the first drain wiring 76. The outer field wiring 80 is electrically connected to the outer end 33 of the field electrode 31 via one or more first via electrodes 75. The outer field wiring 80 may also be integrally formed with the first source wiring 77.

[0096] A plurality of second wiring layers 73B are formed on the second interlayer insulating layer 72B. The plurality of second wiring layers 73B are electrically connected to corresponding connection objects via one or more second via electrodes 81 penetrating the second interlayer insulating layer 72B. The second via electrodes 81 may be tungsten plug electrodes. Specifically, the plurality of second wiring layers 73B include: a second drain wiring 82, a second source wiring 83, and a second gate wiring (not shown).

[0097] The second drain wiring 82 is electrically connected to the first drain wiring 76 and the inner field wiring 79 via a plurality of second via electrodes 81. In a top view, the second drain wiring 82 covers the drain region 15 and the inner field wiring 79. Preferably, the second drain wiring 82 covers the entire area of ​​the drain region 15 and the entire area of ​​the inner field wiring 79 in a top view. Preferably, the second drain wiring 82 extends in a top view to a position opposite to the inner field electrode 36. The second drain wiring 82 also preferably extends in a top view to a position opposite to the portion forming the innermost periphery in the field electrode 31.

[0098] The second source wiring 83 is electrically connected to the first source wiring 77 and the outer field wiring 80 via a plurality of second via electrodes 81. In a top view, the second source wiring 83 is formed as a ring extending along the body region 16. Preferably, the second source wiring 83 covers the gate electrode 41 and the outer field wiring 80 in a top view.

[0099] The second drain wiring 82 is preferably located over the entire area of ​​the cover region 16, the entire area of ​​the gate electrode 41, and the entire area of ​​the outer field wiring 80 in the top view. The second source wiring 83 is also preferably led out in the top view to a position opposite to the portion forming the outermost periphery in the field electrode 31.

[0100] The following is for reference Figures 7-9 The electrical characteristics of semiconductor device 1 will be described. Here, the on-resistance Ron, breakdown voltage VB, and gate threshold voltage Vth are investigated as electrical characteristics of semiconductor device 1. The breakdown voltage VB is the withstand voltage of semiconductor device 1. A first device, a second device, a third device, and a fourth device were prepared for investigating the electrical characteristics of semiconductor device 1.

[0101] The first device is a semiconductor device 1 having a structure in which the ratio W1 / W2 of the first width W1 of the reduced surface electric field region 20 to the second width W2 of the drift line region 13A is set to "0.5". The second device is a semiconductor device 1 having a ratio W1 / W2 set to "1.0". The third device is a semiconductor device 1 having a ratio W1 / W2 set to "2.0". Here, the first width W1 and the second width W2 are adjusted to be in the range of 1 μm or more and 3 μm or less, respectively. In addition, the sum of the first width W1 and the second width W2, W1+W2, is adjusted to be in the range of 3 μm or more and 6 μm or less, respectively.

[0102] The fourth device is a comparative example semiconductor device. In the comparative example semiconductor device, a surface electric field reduction region 20 is formed in the entire region of the drift region 13 that becomes a current path, and no drift line region 13A is formed. That is, in the comparative example semiconductor device, the surface electric field reduction region 20 is formed in the entire region of the surface portion of the drift region 13 between the drain region 15 and the source region 17.

[0103] Furthermore, in each of the first to fourth devices, the n-type impurity concentration in the surface electric field reduction region 20 is adjusted to 1.25 × 10⁻⁶. 16 cm -3 2.5×10 16 cm -3 and 3.25×10 16 cm -3 Their electrical characteristics were investigated separately. The n-type impurity concentration in drift region 13 (drift line region 13A) was 2.25 × 10⁻⁶. 15 cm -3 .

[0104] Figure 7 This is a measured graph used to illustrate the on-resistance Ron. The vertical axis represents the on-resistance Ron [Ω]. The horizontal axis represents the n-type impurity concentration in drift region 13 (drift line region 13A) (=2.25×10). 15 cm -3 The concentration of n-type impurities in the surface electric field region 20 was reduced based on the baseline [cm]. -3 ].

[0105] Figure 7The first to fourth line segments LA1 to LA4 are shown. Line LA1, consisting of four quadrilateral points, illustrates the on-resistance Ron of the first device (W1 / W2 = 0.5). Line LA2, consisting of four triangular points, illustrates the on-resistance Ron of the second device (W1 / W2 = 1.0). Line LA3, consisting of four circular points, illustrates the on-resistance Ron of the second device (W1 / W2 = 2.0). Line LA4, consisting of four black circular points, illustrates the on-resistance Ron of the fourth device (comparative example).

[0106] Referring to the first to fourth segment lines LA1 to LA4, the on-resistance Ron decreases as the surface electric field reduction region 20 is formed, and further decreases as the n-type impurity concentration in the surface electric field reduction region 20 increases. Furthermore, the reduction rate of on-resistance Ron as the n-type impurity concentration increases in the order of the first to fourth devices. That is, the reduction rate of on-resistance Ron increases with the increase of the ratio W1 / W2, reaching its maximum when the surface electric field reduction region 20 is formed over the entire area of ​​the opposing region between the drain region 15 and the source region 17.

[0107] Therefore, it is preferable to set the n-type impurity concentration of the reduced surface electric field region 20 to a relatively high value. Furthermore, it is preferable to set the ratio W1 / W2 to a relatively large value. That is, in terms of reducing the on-resistance Ron, it is preferable to form a reduced surface electric field region 20 with a relatively high concentration and a relatively wide width, under conditions where the n-type impurity concentration exceeds that of the drift region 13.

[0108] Figure 8 This is a measured graph used to illustrate the breakdown voltage VB. The vertical axis represents the breakdown voltage VB [V]. The horizontal axis represents the n-type impurity concentration in drift region 13 (drift line region 13A) (=2.25×10). 15 cm -3 The concentration of n-type impurities in the surface electric field region 20 was reduced based on the baseline [cm]. -3 ].

[0109] Figure 8 The first to fourth line segments LB1 to LB4 are shown. The first line segment LB1, composed of four quadrilateral points, shows the breakdown voltage VB characteristic of the first device (W1 / W2 = 0.5). The second line segment LB2, composed of four triangular points, shows the breakdown voltage VB characteristic of the second device (W1 / W2 = 1.0). The third line segment LB3, composed of four circular points, shows the breakdown voltage VB characteristic of the second device (W1 / W2 = 2.0). The fourth line segment LB4, composed of four black circular points, shows the breakdown voltage VB characteristic of the fourth device (comparative example).

[0110] Referring to the first to fourth line segments LB1 to LB4, it can be seen that the breakdown voltage VB tends to decrease as the surface electric field reduction region 20 is formed. Furthermore, the breakdown voltage VB decreases with increasing n-type impurity concentration in the surface electric field reduction region 20. The percentage decrease in breakdown voltage VB with increasing n-type impurity concentration increases in the order of the first to fourth devices. That is, the percentage decrease in breakdown voltage VB increases with increasing ratio W1 / W2, reaching its maximum when the surface electric field reduction region 20 is formed over the entire opposing region between the drain region 15 and the source region 17.

[0111] In particular, the breakdown voltage VB is significantly reduced in the fourth device. Regarding this, the breakdown voltage VB of the first to third devices is higher than that of the fourth device at any n-type impurity concentration. Therefore, the surface electric field reduction region 20 is preferably formed locally on the surface portion of the drift region 13, such that a portion of the region in the drift region 13 that becomes a current path is exposed from the first main surface 3. Furthermore, the surface electric field reduction region 20 is preferably formed in the entire region of the drift region 13 that becomes a current path.

[0112] Furthermore, the concentration of n-type impurities in the reduced surface electric field region 20 is preferably set to a relatively low value. Additionally, the ratio W1 / W2 is preferably set to a relatively small value. That is, in terms of increasing the breakdown voltage VB, it is preferable to form a reduced surface electric field region 20 with a relatively low concentration and a relatively narrow width, under conditions where the n-type impurity concentration exceeds that of the drift region 13.

[0113] Reference Figure 7 as well as Figure 8 The on-resistance Ron and the breakdown voltage VB have an inverse relationship with respect to reducing the n-type impurity concentration in the surface electric field region 20. Specifically, increasing the n-type impurity concentration in the surface electric field region 20 reduces the on-resistance Ron, but decreases the breakdown voltage VB. Conversely, decreasing the n-type impurity concentration in the surface electric field region 20 increases the on-resistance Ron, but increases the breakdown voltage VB. The n-type impurity concentration in the surface electric field region 20 can be set to any value within a range exceeding the n-type impurity concentration in the drift region 13 (drift line region 13A), but needs to be adjusted based on the on-resistance Ron and the breakdown voltage VB.

[0114] Similarly, the on-resistance Ron and the breakdown voltage VB have inverse relationships with respect to the ratio W1 / W2. Specifically, increasing the ratio W1 / W2 reduces the on-resistance Ron, but decreases the breakdown voltage VB. Conversely, decreasing the ratio W1 / W2 increases the on-resistance Ron, but increases the breakdown voltage VB. The ratio W1 / W2 can be set to any value, but needs to be adjusted based on the on-resistance Ron and the breakdown voltage VB.

[0115] Drift line region 13A has the property of increasing the breakdown voltage VB and increasing the on-resistance Ron. On the other hand, surface electric field reduction region 20 has the property of reducing the on-resistance Ron and decreasing the breakdown voltage VB. Therefore, by making the n-type impurity concentration of surface electric field reduction region 20 close to the n-type impurity concentration of drift region 13 (drift line region 13A), it is possible to reduce the on-resistance Ron while suppressing the decrease in breakdown voltage VB.

[0116] Based on the results from the first to third devices, it is preferable to adjust the n-type impurity concentration in the surface electric field region 20 to exceed 2.25 × 10⁻⁶. 15 cm -3 And 3.25×10 16 cm -3 Furthermore, the ratio of W1 / W2 is preferably adjusted to 0.5 or higher and 2.0 or lower. This allows for the reduction of on-resistance Ron while suppressing the decrease in breakdown voltage VB.

[0117] according to Figure 8 The curve can also be understood; when the concentration of n-type impurities in the reduced surface electric field region 20 exceeds 2.5 × 10⁻⁶, the situation becomes clearer. 16 cm -3 At this time, the breakdown voltage VB of the first to third devices decreases sharply. Therefore, it is particularly preferable to adjust the n-type impurity concentration in the surface electric field region 20 to 1.25 × 10⁻⁶. 15 cm -3 Above and 2.5×10 16 cm -3 Therefore, the decrease in breakdown voltage VB can be appropriately suppressed.

[0118] Furthermore, the larger the ratio of W1 / W2, the greater the reduction in breakdown voltage VB. Therefore, the ratio of W1 / W2 is preferably 0.5 or higher and less than 2.0. The ratio of W1 / W2 is particularly preferably 0.5 or higher and less than 1.0. This allows for the appropriate reduction in on-resistance Ron while appropriately suppressing the decrease in breakdown voltage VB.

[0119] Figure 9This is a measured graph used to illustrate the gate threshold voltage Vth. The vertical axis shows the gate threshold voltage Vth [V]. The horizontal axis shows the n-type impurity concentration (2.25 × 10⁻⁶) in drift region 13 (drift line region 13A). 15 cm -3 The concentration of n-type impurities in the surface electric field region 20 was reduced based on the baseline [cm]. -3 ].

[0120] Figure 9 The first to fourth segmented lines LC1 to LC4 are shown. The first segmented line LC1 consists of four quadrilateral points and illustrates the gate threshold voltage Vth characteristic of the first device (W1 / W2 = 0.5). The second segmented line LC2 consists of four triangular points and illustrates the gate threshold voltage Vth characteristic of the second device (W1 / W2 = 1.0). The third segmented line LC3 consists of four circular points and illustrates the gate threshold voltage Vth characteristic of the second device (W1 / W2 = 2.0). The fourth segmented line LC4 consists of four black circular points and illustrates the gate threshold voltage Vth characteristic of the fourth device (comparative example).

[0121] Referring to the first to fourth segment lines LC1 to LC4, the gate threshold voltage Vth of the first to fourth devices remains approximately constant regardless of the reduction in the n-type impurity concentration and the ratio W1 / W2 in the surface electric field region 20. Therefore, according to the first to third devices, it is possible to reduce the on-resistance Ron while suppressing the variation of the gate threshold voltage Vth and the reduction of the breakdown voltage VB.

[0122] The semiconductor device 1 includes: a semiconductor chip 2, a high-potential region 11, a low-potential region 12, an n-type drift region 13, and an n-type reduced surface electric field region 20. The high-potential region 11 is formed on the surface layer of the first main surface 3 of the semiconductor chip 2. The low-potential region 12 is formed at intervals from the high-potential region 11 on the surface layer of the first main surface 3. The drift region 13 is formed in the surface layer of the first main surface 3 in the region between the high-potential region 11 and the low-potential region 12.

[0123] The reduced surface electric field region 20 is locally formed on the surface of the drift region 13, such that a portion of the drift region 13 is exposed from the first main surface 3. Specifically, the reduced surface electric field region 20 is formed such that a portion of the region in the drift region 13 that becomes a current path is exposed from the first main surface 3. The reduced surface electric field region 20 has an n-type impurity concentration exceeding that of the drift region 13.

[0124] The current density flowing through the reduced surface electric field region 20 exceeds the current density flowing through the drift region 13. On the other hand, the depletion layer extending from the drift region 13 is larger than the depletion layer extending from the reduced surface electric field region 20. As a result, the decrease in breakdown voltage VB (withstand voltage) can be suppressed by the drift region 13, and the on-resistance Ron can be reduced by the reduced surface electric field region 20.

[0125] Preferably, a plurality of reduced surface electric field regions 20 are formed at intervals on the surface portion of the drift region 13. With this configuration, the on-resistance Ron can be reduced by the plurality of reduced surface electric field regions 20. The reduced surface electric field regions 20 preferably extend linearly in the opposite direction of the high potential region 11 and the low potential region 12. With this configuration, the on-resistance Ron can be reduced in the linear current path connecting the high potential region 11 and the low potential region 12.

[0126] Particularly preferred is that the plurality of reduced surface electric field regions 20 are formed in a stripe-like pattern extending in the aforementioned opposing directions, so that a portion of the drift region 13 is exposed from the first main surface 3 in a stripe-like pattern. In this case, a plurality of drift line regions 13A extending in a stripe-like pattern in the aforementioned opposing directions are defined between the plurality of adjacent reduced surface electric field regions 20. The plurality of drift line regions 13A and the plurality of reduced surface electric field regions 20 are formed alternately. According to this configuration, regions that suppress breakdown voltage drop and regions that reduce on-resistance Ron are formed alternately on the surface portion of the drift region 13. Therefore, breakdown voltage drop can be appropriately suppressed, and on-resistance Ron can be appropriately reduced.

[0127] The semiconductor device 1 further includes an n-type impurity region 10 formed on the surface portion of the first main surface 3. The high potential region 11 includes an n-type drain region 15 formed on the surface portion of the impurity region 10. The low potential region 12 includes a p-type body region 16 formed on the surface portion of the first main surface 3 adjacent to the impurity region 10, and an n-type source region 17 formed on the surface portion of the body region 16 at intervals from the impurity region 10.

[0128] Drift region 13 is formed in impurity region 10 in the area between drain region 15 and source region 17. Surface electric field reduction region 20 is formed on the surface of drift region 13 in the area between drain region 15 and source region 17. According to this configuration, the on-resistance Ron can be reduced in the current path connecting drain region 15 and source region 17.

[0129] The reduced surface electric field region 20 is preferably formed only in the region between the drain region 15 and the source region 17 within the drift region 13. According to this configuration, the relatively low-resistance reduced surface electric field region 20 is not formed outside the region between the drain region 15 and the source region 17. Therefore, unwanted current flow outside the region between the drain region 15 and the source region 17 can be appropriately suppressed.

[0130] The high-potential region 11 may include an n-type well region 14 formed on the surface portion of the impurity region 10, and a drain region 15 formed on the surface portion of the well region 14 at intervals from its periphery. In this case, the surface electric field reduction region 20 may be formed on the surface portion of the drift region 13 in the region between the well region 14 and the source region 17. According to this configuration, unwanted current flow outside the region sandwiched between the well region 14 and the source region 17 can be appropriately suppressed. In this case, the surface electric field reduction region 20 is preferably connected to either or both (preferably both) of the well region 14 and the body region 16.

[0131] The semiconductor device 1 further includes a field insulating film 21 and a field electrode 31. The field insulating film 21 covers the drift region 13 and the reduced surface electric field region 20 on the first main surface 3. The field electrode 31 is wound linearly on the field insulating film 21 and traverses the reduced surface electric field region 20 in a top view. According to this configuration, the electric field concentration in the drift region 13 and the reduced surface electric field region 20 can be suppressed by the field electrode 31. Therefore, the withstand voltage can be improved.

[0132] In this case, the field electrode 31 preferably traverses the reduced surface electric field region 20 multiple times in the top view. The field electrode 31 further preferably surrounds the high potential region 11 multiple times. According to these configurations, the drift region 13 and the electric field concentration in the surface electric field region 20 can be appropriately suppressed.

[0133] The field electrode 31 is preferably composed of a field resistance film electrically connected to the high potential region 11 and the low potential region 12. With this configuration, the electric field can be appropriately distributed in the drift region 13 by utilizing the voltage drop in the field electrode 31. Therefore, the drift region 13 can be appropriately suppressed, and the electric field concentration in the surface electric field region 20 can be reduced.

[0134] Figure 10 Is with Figure 5 The corresponding figure is a cross-sectional view used to describe the semiconductor device 91 according to the second embodiment of the present invention. Hereinafter, the same reference numerals will be used for the configuration corresponding to the configuration described for the semiconductor device 1, and descriptions will be omitted.

[0135] The high-potential region 11 of the semiconductor device 91 includes a p-type collector region 92 instead of the drain region 15. Therefore, according to the semiconductor device 91, an IGBT can be provided instead of an LDMISFET. In this case, the "source" of the LDMISFET is replaced by the "emitter" of the IGBT. Furthermore, the "drain" of the LDMISFET is replaced by the "collector" of the IGBT. Even when an IGBT is used instead of an LDMISFET, the same effect as described for the semiconductor device 1 can be obtained.

[0136] Figure 11 Is with Figure 5 The corresponding figure is a cross-sectional view used to describe the semiconductor device 101 according to the third embodiment of the present invention. Hereinafter, the same reference numerals will be used for the configuration corresponding to the configuration described for the semiconductor device 1, and descriptions will be omitted.

[0137] The high-potential region 11 of the semiconductor device 101 includes an n-type cathode well region 102 instead of the well region 14, and an n-type cathode region 103 instead of the drain region 15. Additionally, the low-potential region 12 of the semiconductor device 101 includes a p-type anode well region 104 instead of the body region 16, and a p-type anode region 105 instead of the source region 17 and the contact region 19. The drift region 13 of the semiconductor device 101 is formed in the region between the cathode well region 102 (cathode region 103) and the anode well region 104 (anode region 105).

[0138] Semiconductor device 101 does not have a gate insulating film 40 and a gate electrode 41. Cathode well region 102 and cathode region 103 are formed in the same manner as well region 14 and drain region 15 in the first embodiment. Anode well region 104 is formed in the same manner as body region 16 in the first embodiment.

[0139] Anode region 105 is formed on the surface of anode sink region 104. Anode region 105 has a p-type impurity concentration exceeding that of anode sink region 104. The p-type impurity concentration of anode region 105 can be 1.0 × 10⁻⁶. 18 cm -3 Above and 1.0×10 21 cm -3 the following.

[0140] In this embodiment, the anode region 105 is formed at intervals from the first curved portion 16C and the second curved portion 16D of the anode sink region 104 in the first straight portion 16A and the second straight portion 16B (also referred to). Figure 2 That is, the anode region 105 is not formed in the first curved portion 16C and the second curved portion 16D of the anode sink region 104. In the top view, the anode region 105 is formed as an ended strip extending along the first straight portion 16A and the second straight portion 16B.

[0141] Thus, the anode region 105 is formed in the drift region 13, opposite the cathode region 103 in the second direction Y, and forms a current path along the second direction Y between the anode region 105 and the cathode region 103. In the first direction X, the length of the anode region 105 is preferably less than the length of the cathode region 103. Of course, the anode region 105 can also be formed as an annulus surrounding the impurity region 10 (specifically, an elongated annulus). That is, the anode region 105 can also be formed in the first curved portion 16C and the second curved portion 16D of the anode trap region 104.

[0142] The semiconductor device 101 includes a surface electric field reduction region 20 formed on the surface portion of the drift region 13. The surface electric field reduction region 20 of the semiconductor device 101 is formed in the same manner as the surface electric field reduction region 20 in the first embodiment. That is, in this embodiment, a plurality of surface electric field reduction regions 20 are formed at intervals on the surface portion of the drift region 13.

[0143] Multiple surface electric field reduction regions 20 are formed at intervals from the bottom of the drift region 13 toward the first main surface 3. Specifically, the multiple surface electric field reduction regions 20 are formed shallower than the cathode sink region 102 and deeper than the cathode region 103. The multiple surface electric field reduction regions 20 are opposed to the semiconductor substrate 6 across a portion of the drift region 13.

[0144] In the top view, multiple reduced surface electric field regions 20 extend linearly in the opposite direction of the high potential region 11 and the low potential region 12, and are formed in a stripe-like pattern at intervals in the orthogonal direction of the opposite direction. As a result, in the top view, a portion of the drift region 13 is exposed from the first main surface 3 in a stripe-like pattern by the multiple reduced surface electric field regions 20.

[0145] Multiple surface electric field reduction regions 20 are formed on the surface portion of the drift region 13 in the region between the cathode region 103 and the anode well region 104. Specifically, multiple surface electric field reduction regions 20 are formed in the region between the cathode well region 102 and the anode well region 104. In this embodiment, the surface electric field reduction region 20 has one end connected to the cathode well region 102 and another end connected to the anode well region 104. Thus, the surface electric field reduction region 20 forms a current path that extends continuously in the region between the cathode well region 102 and the anode well region 104.

[0146] Multiple surface electric field reduction regions 20 are formed at intervals along the straight sections of the drift region 13, starting from the curved sections. That is, the multiple surface electric field reduction regions 20 are not formed in the region between the first curved section 16C (second curved section 16D) of the cathode region 103 and the anode sink region 104. The multiple surface electric field reduction regions 20 are formed in the region between the first straight section 16A (second straight section 16B) of the cathode region 103 and the anode sink region 104.

[0147] Multiple surface electric field reduction regions 20 are formed only in the region between the cathode region 103 and the anode region 105 on the surface of the drift region 13. Thus, the surface electric field reduction regions 20 are formed along a continuously extending current path in the region between the cathode region 103 and the anode region 105. If the anode region 105 is formed as a ring surrounding the impurity region 10, the multiple surface electric field reduction regions 20 may also be formed in the curved portion of the drift region 13. Other structures of the multiple surface electric field reduction regions 20 are the same as in the first embodiment, therefore, detailed descriptions are omitted.

[0148] The semiconductor device 101 includes multiple drift line regions 13A (drift exposed regions) that are respectively divided in the surface portion of the drift region 13 between multiple adjacent reduced surface electric field regions 20. The structure of the multiple drift line regions 13A is the same as in the first embodiment, therefore, a detailed description is omitted.

[0149] The first wiring layer 73A of the semiconductor device 101 includes a first cathode wiring 106 and a first anode wiring 107 in place of the first drain wiring 76, the first source wiring 77 and the first gate wiring 78. The first cathode wiring 106 and the first anode wiring 107 are formed in the same manner as the first drain wiring 76 and the first source wiring 77 in the first embodiment.

[0150] The second wiring layer 73B of the semiconductor device 101 includes a second cathode wiring 108 and a second anode wiring 109 in place of the second drain wiring 82, the second source wiring 83 and the second gate wiring (not shown). The second cathode wiring 108 and the second anode wiring 109 are formed in the same manner as the second drain wiring 82 and the second source wiring 83 in the first embodiment.

[0151] As described above, according to semiconductor device 101, a diode can be provided to replace LDMISFET. Even when a diode is used instead of LDMISFET, the same effect as that described for semiconductor device 1 can be obtained. The diode of semiconductor device 101 can be used as a freewheeling diode connected in reverse parallel with semiconductor switching devices such as MISFET (e.g., LDMISFET of the first embodiment) and IGBT (e.g., IGBT of the second embodiment).

[0152] The embodiments of the present invention can be implemented in other ways.

[0153] In the embodiments described above, an example of forming a field electrode 31 composed of a field resistance film was described. However, a field electrode 31 in an electrically suspended state may also be formed. In this case, multiple field electrodes 31 can be formed that concentrically surround the high potential region 11. In this case, the inner field electrode 36 can be removed.

[0154] In the third embodiment described above, the diode can be formed on the same semiconductor chip 2 (first main surface 3) as the LDMISFET in the first embodiment. In this case, the LDMISFET of the first embodiment is formed in one device region 8 (LDMIS region 9), and the diode of the third embodiment is formed in the other device regions 8. Furthermore, in this case, the diode can be connected in reverse parallel with the LDMISFET as a freewheeling diode.

[0155] In the third embodiment, the diode can be formed on the same semiconductor chip 2 (first main surface 3) as the IGBT in the second embodiment. In this case, the IGBT of the second embodiment is formed in one device region 8, and the diode of the third embodiment is formed in other device regions 8. Furthermore, in this case, the diode can be connected in reverse parallel with the IGBT as a freewheeling diode.

[0156] In the above embodiments, the resistive field electrode 31 can be used as a current monitor to detect the current flowing between the high potential region 11 and the low potential region 12. For example, the current flowing between the high potential region 11 and the low potential region 12 can be detected based on the voltage drop across the field electrode 31 and the current flowing through the field electrode 31. With this configuration, the electric field can be appropriately distributed through the field electrode 31, and the convenience of the semiconductor devices 1, 91, and 101 can be improved through the current monitoring function.

[0157] In the above embodiments, various semiconductor regions with inverted conductivity types can be employed. That is, the p-type portion can be n-type, and the n-type portion can be p-type.

[0158] In the above embodiments, examples of forming multiple surface electric field-reducing regions 20 extending in a stripe pattern have been described. However, it is also possible to form... Figures 12-15 The reduced surface electric field region 20 is shown.

[0159] Figure 12 Is with Figure 4 The corresponding figure is a perspective sectional view used to illustrate the reduced surface electric field region 20 of the first modified example. Hereinafter, the same reference numerals will be used for the configuration corresponding to the configuration described for semiconductor device 1, and descriptions will be omitted.

[0160] The reduced surface electric field region 20 of the first embodiment is formed in a top view as a grid with multiple crosses. Specifically, the reduced surface electric field region 20 includes multiple first regions 111 and multiple second regions 112. The multiple first regions 111 extend in a stripe-like pattern in the opposite direction (second direction Y) of the high potential region 11 and the low potential region 12. The multiple second regions 112 extend in a stripe-like pattern in the orthogonal direction (first direction X) of the opposite direction, and intersect the multiple first regions 111 in a cross shape.

[0161] In the surface portion of the drift region 13, a plurality of segmented regions 113 are formed by reducing the surface electric field region 20. The plurality of segmented regions 113 correspond to the structure in the first embodiment where the drift line region 13A is divided into multiple parts by a plurality of second regions 112.

[0162] In the top view, multiple segmented regions 113 are arranged in a matrix, spaced apart along the first direction X and the second direction Y. In this example, the multiple segmented regions 113 are each formed as a strip extending along the second direction Y in the top view. The planar shape of the multiple segmented regions 113 is arbitrary and can also be formed as a quadrilateral, a circle, an ellipse, or an oblong shape.

[0163] In the case of forming the reduced surface electric field region 20 of the first modification, the same effect as that described for the semiconductor device 1 can be obtained. The reduced surface electric field region 20 of the first modification can also be applied to the second to third embodiments described above.

[0164] Figure 13 Is with Figure 4 The corresponding figure is a perspective sectional view used to illustrate the reduced surface electric field region 20 in the second modified example. Hereinafter, the same reference numerals will be used for the configuration corresponding to the configuration described for semiconductor device 1, and descriptions will be omitted.

[0165] The reduced surface electric field region 20 of the second embodiment is formed in a top view as a grid with multiple T-shapes. Specifically, the reduced surface electric field region 20 includes multiple first regions 111 and multiple second regions 112. The multiple first regions 111 extend in a stripe-like pattern in the opposite direction (second direction Y) of the high potential region 11 and the low potential region 12. The multiple second regions 112 are formed at intervals in the region between adjacent multiple first regions 111 in the opposite direction, and the adjacent multiple first regions 111 are respectively connected in a T-shape.

[0166] In the surface portion of the drift region 13, a plurality of segmented regions 113 are defined by reducing the surface electric field region 20, forming a portion of the drift region 13. The plurality of segmented regions 113 correspond to the structure in the first embodiment where the drift line region 13A is divided into multiple parts by a plurality of second regions 112.

[0167] In the top view, multiple segmented regions 113 are arranged in an alternating pattern, spaced apart along the first direction X and the second direction Y. In this example, the multiple segmented regions 113 are each formed as a strip extending along the second direction Y in the top view. The planar shape of the multiple segmented regions 113 is arbitrary and can also be formed as a quadrilateral, a circle, an ellipse, or an oblong shape.

[0168] Therefore, even when the reduced surface electric field region 20 of the second modification is formed, the same effect as that described for the semiconductor device 1 can be obtained. The reduced surface electric field region 20 of the second modification can also be applied to the second to third embodiments.

[0169] Figure 14 Is with Figure 4The corresponding figure is a perspective sectional view used to explain the reduced surface electric field region 20 in the third modified example. Hereinafter, the same reference numerals will be used for the configuration corresponding to the configuration described for semiconductor device 1, and descriptions will be omitted.

[0170] In the third variation, the plurality of surface electric field reduction regions 20 are formed in a matrix shape, spaced apart in the opposite direction (second direction Y) and the orthogonal direction (first direction X) of the high potential region 11 and the low potential region 12, in the top view. In this example, the plurality of surface electric field reduction regions 20 are each formed as strips extending in the second direction Y in the top view. The planar shape of the plurality of surface electric field reduction regions 20 is arbitrary and can also be formed as a quadrilateral shape, a circle, an ellipse, or an oblong shape.

[0171] On the surface of the drift region 13, a drift line region 13A, comprising a portion of the drift region 13, is defined by multiple reduced surface electric field regions 20. The drift line region 13A is divided into a grid pattern with multiple crosses. That is, the drift line region 13A includes multiple first line regions 114 and multiple second line regions 115 forming crosses. The multiple first line regions 114 extend in a striped pattern in the opposing direction (second direction Y). The multiple second line regions 115 extend in a striped pattern in the orthogonal direction (first direction X) and intersect the multiple first line regions 114 in a cross pattern.

[0172] As described above, even with the formation of the reduced surface electric field region 20 in the third modification, the same effect as that described for the semiconductor device 1 can be obtained. However, in the third modification, the plurality of reduced surface electric field regions 20 are formed spaced apart from each other by a portion of the drift region 13. Therefore, the structure of the semiconductor device 1 is preferred in terms of reducing the on-resistance Ron. The reduced surface electric field region 20 of the third modification can also be applied to the second and third embodiments.

[0173] Figure 15 Is with Figure 4 The corresponding figure is a perspective sectional view used to explain the reduced surface electric field region 20 of the fourth modified example. Hereinafter, the same reference numerals will be used for the configuration corresponding to the configuration described for semiconductor device 1, and descriptions will be omitted.

[0174] In the fourth variation, the plurality of surface electric field reduction regions 20 are formed in an alternating pattern at intervals in the opposite direction (second direction Y) of the high potential region 11 and the low potential region 12 and in the orthogonal direction (first direction X) of the opposite direction, as shown in the top view. In this example, the plurality of surface electric field reduction regions 20 are each formed as a strip extending in the second direction Y in the top view. The planar shape of the plurality of surface electric field reduction regions 20 is arbitrary and can also be formed as a quadrilateral shape, a circle, an ellipse, or an oblong shape.

[0175] On the surface of the drift region 13, a drift line region 13A, comprising a portion of the drift region 13, is defined by multiple reduced surface electric field regions 20. The drift line region 13A is divided into a grid pattern with multiple T-shapes. That is, the drift line region 13A includes multiple first line regions 114 and multiple second line regions 115 forming T-shapes. The multiple first line regions 114 extend in a stripe-like pattern in the opposite direction (second direction Y). The multiple second line regions 115 are formed at intervals in the region between adjacent multiple first line regions 114 in the opposite direction, connecting adjacent multiple first line regions 114 in a T-shape.

[0176] Even with the fourth modified surface electric field reduction region 20, the same effect as described for the semiconductor device 1 can be achieved. However, in the fourth modified example, the plurality of surface electric field reduction regions 20 are formed spaced apart from each other by a portion of the drift region 13. Therefore, the structure of the semiconductor device 1 is preferred in terms of reducing the on-resistance Ron. The surface electric field reduction region 20 of the fourth modified example can also be applied to the second and third embodiments.

[0177] The aforementioned semiconductor devices 1, 91, and 101 can be assembled, for example, into power modules used in inverter circuits that drive electric motors, which serve as power sources for automobiles (including electric vehicles), trams, industrial robots, air conditioning units, air compressors, fans, vacuum cleaners, dryers, refrigerators, and the like. Furthermore, the aforementioned semiconductor devices 1, 91, and 101 can also be assembled into power modules used in inverter circuits for solar cells, wind turbines, and other power generation devices. Additionally, the aforementioned semiconductor devices 1, 91, and 101 can also be assembled into circuit modules used in analog control power supplies, digital control power supplies, and the like.

[0178] The following are examples of features extracted from this specification and accompanying drawings. [A1] to [A19] and [B1] to [B20] below provide semiconductor devices capable of suppressing voltage drop while reducing on-resistance. Hereinafter, the alphanumeric characters in parentheses indicate corresponding constituent elements in the above embodiments, but do not imply that the scope of each item is limited to the embodiments.

[0179] [A1] A semiconductor device (1, 91, 101) includes: a semiconductor chip (2) having a main surface (3); a high potential region (11) formed on a surface portion of the main surface (3); a low potential region (12) formed at intervals from the high potential region (11) on the surface portion of the main surface (3); a drift region (13) of a first conductivity type formed on the surface portion of the main surface (3) in a region between the high potential region (11) and the low potential region (12); and a reduced surface electric field region (20) of a first conductivity type locally formed on the surface portion of the drift region (13) such that a portion of a region in the drift region (13) that becomes a current path is exposed from the main surface (3), the reduced surface electric field region (20) having an impurity concentration exceeding that of the drift region (13). According to the semiconductor device (1, 91, 101), it is possible to reduce the on-resistance (Ron) while suppressing the decrease in withstand voltage (VB).

[0180] [A2] In the semiconductor device (1, 91, 101) according to A1, the reduced surface electric field region (20) is formed as a line extending in the opposite direction of the high potential region (11) and the low potential region (12).

[0181] [A3] The semiconductor device (1, 91, 101) according to A1 or A2, wherein a plurality of the reduced surface electric field regions (20) are formed at intervals on the surface portion of the drift region (13).

[0182] [A4] In the semiconductor device (1, 91, 101) according to A3, a plurality of said reduced surface electric field regions (20) are formed as stripes extending in opposite directions of the high potential region (11) and the low potential region (12), and a portion of the drift region (13) is exposed from the main surface (3) in a striped manner.

[0183] [A5] The semiconductor device (1, 91, 101) according to any one of A1 to A4, wherein the semiconductor device further comprises: a field insulating film (21) covering the drift region (13) and the reduced surface electric field region (20) on the main surface (3); and a field electrode (31) being linearly wound on the field insulating film (21) and traversing the reduced surface electric field region (20) in a top view.

[0184] [A6] The semiconductor device (1, 91, 101) according to A5, wherein the field electrode (31) crosses the reduced surface electric field region (20) multiple times in the top view.

[0185] [A7] The semiconductor device (1, 91, 101) according to A5 or A6, wherein the field electrode (31) surrounds the high potential region (11) multiple times.

[0186] [A8] The semiconductor device (1, 91, 101) according to any one of A5 to A7, wherein the field electrode (31) is composed of a field resistive film electrically connected to the high potential region (11) and the low potential region (12).

[0187] [A9] The semiconductor device (1) according to any one of A1 to A8, wherein the high potential region (11) includes: a drain region (15) of a first conductivity type formed on the surface portion of the main surface (3), the low potential region (12) includes: a body region (16) of a second conductivity type formed on the surface portion of the main surface (3), and a source region (17) of a first conductivity type formed on the surface portion of the body region (16), the drift region (13) is formed on the surface portion of the main surface (3) in the region between the drain region (15) and the body region (16), and the reduced surface electric field region (20) is formed on the surface portion of the drift region (13) in the region between the drain region (15) and the source region (17).

[0188] [A10] The semiconductor device (1) according to A9, wherein the reduced surface electric field region (20) is connected to the body region (16).

[0189] [A11] The semiconductor device (1) according to A9 or A10, wherein the high potential region (11) includes: a first conductivity type well region (14) formed on the surface portion of the main surface (3) and the drain region (15) formed on the surface portion of the well region (14), and the reduced surface electric field region (20) is formed on the surface portion of the drift region (13) in the region between the well region (14) and the source region (17).

[0190] [A12] The semiconductor device (1) according to A11, wherein the reduced surface electric field region (20) is connected to the well region (14).

[0191] [A13] The semiconductor device (1) according to any one of A9 to A12, wherein the reduced surface electric field region (20) is formed only in the drift region (13) in the region sandwiched between the source region (17) and the drift region (13).

[0192] [A14] The semiconductor device (1) according to any one of A9 to A13, wherein the body region (16) surrounds the drain region (15), and the source region (17) is formed in an end-shaped manner on the surface portion of the body region (16).

[0193] [A15] The semiconductor device (1) according to any one of A9 to A14, wherein the semiconductor device further comprises: a channel region (18) formed on the surface portion of the body region (16) between the drift region (13) and the source region (17); a gate insulating film (40) covering the channel region (18) on the main surface (3); and a gate electrode (41) formed on the gate insulating film (40).

[0194] [A16] The semiconductor device (1, 91, 101) according to A15, wherein the gate insulating film (40) covers the drift region (13) and the reduced surface electric field region (20).

[0195] [A17] A semiconductor device (1, 91, 101) includes: a semiconductor chip (2) having a main surface (3); a high-potential region (11) and a low-potential region (12) formed at intervals on a surface portion of the main surface (3); a drift region (13) of a first conductivity type formed on the surface portion of the main surface (3) in a region between the high-potential region (11) and the low-potential region (12); and a surface electric field reduction region (20) of a first conductivity type formed on the surface portion of the drift region (13) in the high-potential region (11). And a linear extension in the opposite direction of the low potential region (12), such that part of the region that becomes a current path in the drift region (13) is exposed from the main surface (3), the reduced surface electric field region (20) has an impurity concentration exceeding that of the drift region (13); a field insulating film (21) covering the drift region (13) and the reduced surface electric field region (20); and a field electrode (31) formed on the field insulating film (21) and wound linearly in a manner intersecting the reduced surface electric field region (20) in a top view.

[0196] [A18] In the semiconductor device (1, 91, 101) according to A17, the field electrode (31) is composed of a field resistive film electrically connected to the high potential region (11) and the low potential region (12).

[0197] [A19] The semiconductor device (1, 91, 101) according to A17 or A18, wherein the field electrode (31) is orthogonal to the reduced surface electric field region (20) in a top view.

[0198] [B1] A semiconductor device (101) includes: a semiconductor chip (2) having a main surface (3); a cathode region (103) of a first conductivity type formed on a surface portion of the main surface (3); an anode region (105) of a second conductivity type formed at intervals from the cathode region (103) on the surface portion of the main surface (3); a drift region (13) of a first conductivity type formed on the surface portion of the main surface (3) in a region between the cathode region (103) and the anode region (105); and a reduced surface electric field region (20) of a first conductivity type partially formed on the surface portion of the drift region (13) such that a portion of the region in the drift region (13) that becomes a current path is exposed from the main surface (3), the reduced surface electric field region (20) having an impurity concentration exceeding that of the drift region (13). According to the semiconductor device (101), it is possible to reduce the on-resistance (Ron) while suppressing the decrease of the withstand voltage (VB).

[0199] [B2] The semiconductor device (101) according to B1, wherein a high potential is applied to the cathode region (103) and a low potential is applied to the anode region (105).

[0200] [B3] The semiconductor device (101) according to B1 or B2, wherein the drift region (13) has a lower impurity concentration than the cathode region (103).

[0201] [B4] The semiconductor device (101) according to any one of B1 to B3, wherein the reduced surface electric field region (20) is formed as a line extending in the opposite direction of the cathode region (103) and the anode region (105).

[0202] [B5] The semiconductor device (101) according to any one of B1 to B4, wherein a plurality of said reduced surface electric field regions (20) are formed at intervals on the surface portion of the drift region (13).

[0203] [B6] According to the semiconductor device (101) of B5, a plurality of the reduced surface electric field regions (20) are formed as stripes extending in opposite directions of the cathode region (103) and the anode region (105), and a portion of the drift region (13) is exposed from the main surface (3) in a striped manner.

[0204] [B7] The semiconductor device (101) according to B6, wherein the plurality of said reduced surface electric field regions (20) are divided on the main surface (3) into a plurality of drift exposure regions (13A) extending in a stripe pattern in the opposite direction.

[0205] [B8] The semiconductor device (101) according to any one of B1 to B7, wherein the semiconductor device further comprises: a field insulating film (21) covering the drift region (13) and the reduced surface electric field region (20) on the main surface (3); and a field electrode (31) being linearly wound on the field insulating film (21) and traversing the reduced surface electric field region (20) in a top view.

[0206] [B9] The semiconductor device (101) according to B8, wherein the field electrode (31) crosses the reduced surface electric field region (20) multiple times in a top view.

[0207] [B10] The semiconductor device (101) according to B8 or B9, wherein the field electrode (31) surrounds the cathode region (103) multiple times.

[0208] [B11] The semiconductor device (101) according to any one of B8 to B10, wherein the field electrode (31) is composed of a field resistance film electrically connected to the cathode region (103) and the anode region (105).

[0209] [B12] The semiconductor device (101) according to any one of B1 to B11, wherein the reduced surface electric field region (20) is formed only in the drift region (13) in the region sandwiched between the cathode region (103) and the anode region (105).

[0210] [B13] The semiconductor device (101) according to any one of B1 to B12, wherein the semiconductor device further comprises: an impurity region (11) of a first conductivity type formed on the surface portion of the main surface (3); a cathode well region (102) of a first conductivity type formed on the surface portion of the impurity region (11); and an anode well region (104) of a second conductivity type formed adjacent to the impurity region (11) on the surface portion of the main surface (3), the cathode region (103) formed on the surface portion of the cathode well region (102), the anode region (105) formed on the surface portion of the anode well region (104), the drift region (13) formed in the region between the cathode well region (102) and the anode well region (104), and the reduced surface electric field region (20) formed on the surface portion of the drift region (13) in the region between the cathode well region (102) and the anode well region (104).

[0211] [B14] The semiconductor device (101) according to B13, wherein the cathode region (103) has an impurity concentration exceeding that of the cathode well region (102), and the anode region (105) has an impurity concentration exceeding that of the anode well region (104).

[0212] [B15] The semiconductor device (101) according to B13 or B14, wherein the reduced surface electric field region (20) is connected to the cathode well region (102).

[0213] [B16] The semiconductor device (101) according to any one of B13 to B15, wherein the reduced surface electric field region (20) is connected to the anode well region (104).

[0214] [B17] The semiconductor device (101) according to any one of B13 to B16, wherein the anode well region (104) surrounds the impurity region (11), and the anode region (105) is formed as an ended strip extending along the impurity region (11).

[0215] [B18] A semiconductor device (101) includes: a semiconductor chip (2) having a main surface (3); a cathode region (103) of a first conductivity type and an anode region (105) of a second conductivity type, which are spaced apart from each other on a surface portion of the main surface (3); a drift region (13) of the first conductivity type, which is formed on the surface portion of the main surface (3) in a region between the cathode region (103) and the anode region (105); and a surface electric field reduction region (20) of the first conductivity type, which is formed on the surface portion of the drift region (13) in a manner that reduces the surface electric field. The cathode region (103) and the anode region (105) extend in opposite directions in a linear fashion, such that a portion of the drift region (13) is exposed from the main surface (3), the reduced surface electric field region (20) has an impurity concentration exceeding that of the drift region (13); a field insulating film (21) covers the drift region (13) and the reduced surface electric field region (20); and a field electrode (31) is formed on the field insulating film (21) and is linearly wound in a manner that intersects with the reduced surface electric field region (20) in a top view.

[0216] [B19] The semiconductor device (101) according to B18, wherein the field electrode (31) is composed of a field resistive film electrically connected to the cathode region (103) and the anode region (105).

[0217] [B20] The semiconductor device (101) according to B18 or B19, wherein the field electrode (31) is orthogonal to the reduced surface electric field region (20) in a top view.

[0218] The embodiments of the present invention have been described in detail, but these are merely specific examples used to clarify the technical content of the present invention. The present invention should not be construed as being limited to these specific examples, and the scope of the present invention is defined by the appended claims.

[0219] Symbol Explanation

[0220] 1. Semiconductor device

[0221] 2 Semiconductor chips

[0222] 3 First Main Face

[0223] 11 High Potential Region

[0224] 12 Low Potential Region

[0225] 13 Drift Zone

[0226] 14 Tunnel Area

[0227] 15 Drain region

[0228] 16 body areas

[0229] 17 Source Region

[0230] 18. Ditch area

[0231] 20 Reduce the surface electric field area

[0232] 21 Field Insulating Film

[0233] 31 field electrodes

[0234] 40 Gate insulating film

[0235] 41 Gate electrode

[0236] 91 Semiconductor Devices

[0237] 101 Semiconductor device.

Claims

1. A semiconductor device, characterized in that, Include: Semiconductor chips have a main surface; A high-potential region is formed on the surface of the main surface; Low potential regions are formed at intervals from the high potential regions on the surface portion of the main surface; A drift region of the first conductivity type is formed in the area between the high potential region and the low potential region on the surface of the main surface; as well as A first conductivity type of reduced surface electric field region is locally formed on the surface portion of the drift region such that a portion of the region in the drift region that becomes a current path is exposed from the main surface. The reduced surface electric field region has an impurity concentration exceeding that of the drift region. The reduced surface electric field region is formed as a line extending in the opposite direction of the high potential region and the low potential region.

2. The semiconductor device according to claim 1, characterized in that, Multiple reduced surface electric field regions are formed at intervals on the surface of the drift region.

3. The semiconductor device according to claim 2, characterized in that, The plurality of said reduced surface electric field regions are formed as stripes extending in the opposite direction of the high potential region and the low potential region, and a portion of the drift region is exposed from the main surface in a striped pattern.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A field-insulating film covering the drift region and the reduced surface electric field region on the main surface; and The field electrode is wound in a linear fashion over the field insulating film and traverses the reduced surface electric field region in the top view.

5. The semiconductor device according to claim 4, characterized in that, The field electrode crosses the reduced surface electric field region multiple times in the top view.

6. The semiconductor device according to claim 4, characterized in that, The field electrode surrounds the high potential region multiple times.

7. The semiconductor device according to claim 4, characterized in that, The field electrode is composed of a field resistance film electrically connected to the high potential region and the low potential region.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The high-potential region includes a first conductivity type drain region formed on the surface portion of the main surface. The low-potential region includes: a second conductivity type body region formed on the surface portion of the main surface, and a first conductivity type source region formed on the surface portion of the body region. The drift region is formed on the surface of the main surface in the area between the drain region and the body region. The reduced surface electric field region is formed on the surface of the drift region in the area between the drain region and the source region.

9. The semiconductor device according to claim 8, characterized in that, The reduced surface electric field region is connected to the bulk region.

10. The semiconductor device according to claim 8, characterized in that, The high-potential region includes: a first conductivity type well region formed on the surface portion of the main surface, and a drain region formed on the surface portion of the well region. The reduced surface electric field region is formed in the surface portion of the drift region in the region between the well region and the source region.

11. The semiconductor device according to claim 10, characterized in that, The reduced surface electric field region is connected to the well region.

12. The semiconductor device according to claim 8, characterized in that, The reduced surface electric field region is formed only in the region between the source region and the drift region in the drift region.

13. The semiconductor device according to claim 8, characterized in that, The body region surrounds the drain region. The source region is formed in an end-shaped manner on the surface of the body region.

14. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes: A channel region is formed on the surface portion of the body region between the drift region and the source region; A gate insulating film covering the channel region over the main surface; and A gate electrode is formed on the gate insulating film.

15. The semiconductor device according to claim 14, characterized in that, The gate insulating film covers the drift region and the reduced surface electric field region.

16. A semiconductor device, characterized in that, Include: Semiconductor chips have a main surface; High potential regions and low potential regions are formed at intervals on the surface of the main surface; A drift region of the first conductivity type is formed in the area between the high potential region and the low potential region on the surface of the main surface; The first conductivity type of reduced surface electric field region is formed in the surface portion of the drift region as a line extending in the opposite direction of the high potential region and the low potential region, such that a portion of the region that becomes a current path in the drift region is exposed from the main surface, and the reduced surface electric field region has an impurity concentration exceeding that of the drift region. A field-insulating film that covers the drift region and the reduced surface electric field region; as well as The field electrode is formed on the field insulating film and is wound in a linear manner in a top view in a manner that intersects with the reduced surface electric field region.

17. The semiconductor device according to claim 16, characterized in that, The field electrode is composed of a field resistance film electrically connected to the high potential region and the low potential region.

18. The semiconductor device according to claim 16 or 17, characterized in that, The field electrode is orthogonal to the reduced surface electric field region in the top view.

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