Method for manufacturing a fin field effect transistor

Abstract

The present invention provides a method for manufacturing a fin field-effect transistor. The method comprises: providing a semiconductor substrate having a fin; using a first N-type ion to implant N-type ions into a portion of the fin, and performing a first spike annealing process on the fin to form an anti-doping region; using a first dose of a second N-type ion to implant N-type ions into a portion of the fin on both sides of the anti-doping region, and performing a second spike annealing process on the fin to form a shallow doping region; and using a second dose of a second N-type ion to implant N-type ions into the fin on both sides of the anti-doping region and outside the shallow doping region. By forming the anti-doping region, the hot carrier effect is reduced, and the spike annealing process is added to improve the damage caused by the anti-doping ion implantation. The ion implantation method of the source and drain regions is changed, and a high-temperature annealing process is performed on the gate oxide layer to improve the film quality and reduce the negative impact of the hot carrier effect.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a fin field effect transistor. Background Art

[0002] The hot carrier effect is actually caused by the transition of hot carriers in the channel to the gate. Since the kinetic energy required for electrons to cross the Si-SiO2 barrier is 3.2eV, the hole requires 4.9eV, and the collision generation rate of holes is lower than that of electrons, the hot carrier effect of N-type devices is more significant.

[0003] I / O (Input / Output) devices are used when a chip interacts with an external interface. The operating voltage of these devices is generally high and depends on the compatible operating voltage of the external interface (typically 1.8V, 2.5V, 3.3V, or 5V). I / O devices generally use a relatively high operating voltage of 1.8V, which creates a very strong electric field in the channel, allowing carriers to easily acquire greater kinetic energy and thus pass through the Si-SiO2 interface. Therefore, N-type I / O devices are the type of device with relatively poor HCI (hot carrier injection) performance among I / O MOS devices.

[0004] Currently, high-voltage N-type I / O devices are often FinFETs (Fin Field-Effect Transistors). Therefore, this application proposes improvements to the manufacturing method of FinFETs (especially N-type FinFETs) to reduce the negative impact of hot carrier effects. Summary of the Invention

[0005] An object of the present invention is to provide a method for manufacturing a FinFET to reduce the negative impact of hot carrier effects on an N-type FinFET.

[0006] To solve the above technical problems, the present invention provides a method for manufacturing a fin field effect transistor, comprising the following steps:

[0007] Providing a semiconductor substrate having fins, wherein a shallow trench isolation structure is formed between adjacent fins;

[0008] Implanting N-type ions into a partial area of ​​the fin using a first N-type ion, and performing a first spike annealing process on the fin to form an anti-doped region;

[0009] Implanting N-type ions into a portion of the fin on both sides of the anti-doped region with a first dose of second N-type ions, and performing a second spike annealing process on the fin to form a shallowly doped region;

[0010] A second dose of second N-type ions is used to implant N-type ions into the fins on both sides of the anti-doped region and outside the shallow doped region, and a third spike annealing treatment is performed on the fins to form source and drain regions, wherein the second dose is greater than the first dose.

[0011] Preferably, the process parameters for forming the anti-doping region include: the first N-type ions include arsenic ions, the implantation energy is 22KeV to 27KeV, and the implantation dose is 2.7E12 / cm 2 ~3.3E12 / cm 2 .

[0012] Preferably, the anti-doping region extends from the side of the shallow doping region to below at least part of the bottom of the shallow doping region to at least partially surround the shallow doping region, and the anti-doping region is not connected to the shallow doping region, source region and drain region on both sides thereof.

[0013] Preferably, the second N-type ions include phosphorus ions, and the first dose is 3.8E14 / cm 2 ~4.2E14 / cm 2 , the second dose is 1.5E15 / cm 2 ~3.5E15 / cm 2 .

[0014] Preferably, the implantation energy of the second N-type ions when forming the shallow doping region is 15 KeV to 18 KeV, and the implantation energy of the second N-type ions when forming the source region and the drain region is 3 KeV to 4 KeV.

[0015] Preferably, before implanting N-type ions into a partial area of ​​the fin using the first N-type ions, the method further includes:

[0016] implanting P-type ions into the fin to form a P-well in the fin;

[0017] After forming the anti-doping region and before using a first dose of second N-type ions to implant N-type ions into a portion of the fin on both sides of the anti-doping region, the method further includes:

[0018] forming a gate oxide layer covering the top and side surfaces of the fin, and performing a fourth spike annealing process on the gate oxide layer;

[0019] forming a polysilicon layer covering the surface of the gate oxide layer, and etching the polysilicon layer to form a polysilicon gate;

[0020] A shallow doping region and a source region are formed in the P-well on one side of the polysilicon gate, and a shallow doping region and a drain region are formed in the P-well on the other side of the polysilicon gate.

[0021] Preferably, the process parameters for forming the P well include: an implantation energy of 45KeV to 55KeV, an implantation dose of 4.3E12 / cm 2 ~4.7E12 / cm 2 , the P-type ions include boron ions.

[0022] Preferably, among the first spike annealing treatment, the second spike annealing treatment, the third spike annealing treatment and the fourth spike annealing treatment, the process temperature of the first spike annealing treatment is the highest, and the temperature of the second spike annealing treatment is the lowest.

[0023] Preferably, the peak temperature of the first peak annealing treatment is 1000℃~1100℃, and the annealing time is 210ms~230ms; the peak temperature of the second peak annealing treatment is 945℃~955℃, and the annealing time is 210ms~230ms; the peak temperature of the third peak annealing treatment is 980℃~990℃, and the annealing time is 210ms~230ms; the peak temperature of the fourth peak annealing treatment is 945℃~955℃, and the annealing time is 210ms~230ms.

[0024] Preferably, after forming the shallow doped region and before using a second dose of second N-type ions to implant N-type ions into the fins on both sides of the counter-doped region and located outside the shallow doped region, the method further comprises: etching fin trenches on both sides of the counter-doped region and located outside the shallow doped region to form source-drain trenches, and growing a semiconductor epitaxial material different from the fin in the source-drain trenches to form an embedded epitaxial layer;

[0025] Wherein, a second dose of second N-type ions is used to implant N-type ions into the embedded epitaxial layer on both sides of the counter-doped region, and a third spike annealing process is performed on the fin to form a source region and a drain region.

[0026] In the manufacturing method of the fin field-effect transistor provided by the present invention, an anti-doping region is formed between the source region and the drain region to compensate for the loss caused by performing a shallow doping step before an EPI step, thereby weakening the peak electric field value formed in the drain pinch-off region, reducing the substrate current Isub, achieving the effect of reducing the hot carrier effect, and adding a spike annealing process to improve the damage of anti-doping ion implantation.

[0027] Furthermore, compared with the existing technology of sequentially injecting two types of N-type ions, the method of injecting N-type ions in one step in this case can further improve HCI, thereby reducing the negative impact of hot carrier injection effect on high-voltage N-type I / O devices.

[0028] The high-temperature annealing process of the gate oxide layer is also used to improve the film quality and reduce the damage of HCI to the oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic diagram of a semiconductor substrate provided by one embodiment of the present invention;

[0030] Figure 2 The semiconductor substrate provided by one embodiment of the present invention is formed along the Figure 1 Schematic diagram of the X direction;

[0031] Figure 3 The semiconductor substrate provided by one embodiment of the present invention is formed along the shallow doping region Figure 1 Schematic diagram of the X direction;

[0032] Figure 4 The semiconductor substrate provided by one embodiment of the present invention is formed along the epitaxial layer Figure 1 Schematic diagram of the X direction;

[0033] Figure 5 The source and drain regions are formed along the rear edge of the embodiment of the present invention. Figure 1 Schematic diagram of the X direction;

[0034] Figure 6 The gate oxide layer is formed after the embodiment of the present invention Figure 1 Schematic diagram of the Y direction.

[0035] In the figure,

[0036] 1. Semiconductor substrate; 2. Fin; 3. Shallow trench isolation structure; 4. Counter-doped region; 5. Shallow doped region; 6. Epitaxial layer; 7. Source region; 8. Drain region; 9. Gate oxide layer. DETAILED DESCRIPTION

[0037] The following is a further detailed description of the method for manufacturing a FinFET according to the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the accompanying drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0038] The inventors have found that since the operating voltage of N-type I / O devices is relatively high, the hot carrier effect has the greatest impact on them, and N-type I / O devices are often fin field-effect transistors. Therefore, the manufacturing method of fin field-effect transistors is optimized to reduce the negative impact of the hot carrier effect.

[0039] Based on this, the core idea of ​​the present invention is to pre-inject arsenic ions to form an anti-doped region and reduce ion implantation damage through spike annealing; further optimize the ion implantation method of the source and drain regions, optimize HCI, and perform a high-temperature annealing process on the gate oxide layer to improve the film quality and reduce the damage caused by HCI.

[0040] For details, please refer to Figures 1 to 6 , which is a schematic diagram of an embodiment of the present invention. A method for manufacturing a fin field effect transistor, comprising the following steps:

[0041] S1, such as Figure 1 As shown, a semiconductor substrate 1 having fins 2 is provided, and shallow trench isolation structures 3 are formed between adjacent fins 2 .

[0042] The steps of doping the semiconductor substrate 1 with P-type ions include: injecting P-type ions into the fin 2 to form a P well (not shown) in the fin 2, with an injection energy of 45KeV to 55KeV and an injection dose of 4.3E12 / cm 2 ~4.7E12 / cm 2 , P-type ions include boron ions.

[0043] In one example, the energy of the boron ion implantation is 50 KeV and the implantation dose is 4.5E12 / cm 2 , the implantation angle is 4° (the angle between the normal line perpendicular to the semiconductor substrate 1), as shown Figure 1 The direction of the middle arrow is the injection direction of boron ions. The angle between the arrow and the Z direction is 4°. After four rotations, since doping ions need to be injected later to form the anti-doping region 4, the boron ions injected here are deeper than the current technology.

[0044] S2, forming a gate oxide layer 9 covering the top and side of the fin 2, and performing a fourth spike annealing process on the gate oxide layer 9, such as Figure 6 As shown; a polysilicon layer is formed covering the surface of the gate oxide layer 9, and the polysilicon layer is etched to form a polysilicon gate (not shown); wherein a shallowly doped region 5 and a source region 7 are formed in the P-well on one side of the polysilicon gate, and a shallowly doped region 5 and a drain region 8 are formed in the P-well on the other side of the polysilicon gate.

[0045] Among them, the peak temperature of the fourth peak annealing treatment is 945℃~955℃, and the annealing time is 210ms~230ms. After the gate oxide layer 9 is formed, the fourth peak annealing treatment is performed to improve the film quality and further reduce the damage to the gate oxide layer 9 caused by the hot carrier effect.

[0046] In one example, the peak temperature of the fourth peak annealing process is 950° C., and the annealing time is 220 ms.

[0047] S3, using the first N-type ion to implant N-type ions into a portion of the fin 2, and performing a first spike annealing treatment on the fin 2 to form an anti-doping region 4. The process parameters for forming the anti-doping region 4 include: the first N-type ion includes arsenic ions, the implantation energy is 22KeV to 27KeV, and the implantation dose is 2.7E12 / cm 2 ~3.3E12 / cm 2 ,like Figure 2 As shown, the semiconductor substrate 1 and the structure thereon are subjected to a first spike annealing process, wherein the peak temperature of the first spike annealing process is 1000° C. to 1100° C. and the annealing time is 210 ms to 230 ms.

[0048] By injecting arsenic ions into the P-type semiconductor substrate 1, the concentration of P-type ions in the channel is reduced to compensate for the loss of the EPI (Epitaxy) process step of first forming the shallow doped region 5, thereby weakening the peak electric field value formed in the drain pinch-off region, thereby reducing the substrate current Isub and achieving the effect of reducing the hot carrier effect.

[0049] After the N-type ions are implanted to form the anti-doped region 4, a first spike annealing process is performed to reduce the damage caused by the ion implantation and repair the crystal lattice.

[0050] In one example, arsenic ions are selected, the implantation energy is 25 KeV, and the implantation dose is 3E12 / cm 2 The first spike annealing process is performed at a peak temperature of 1000° C. and lasts for 220 ms.

[0051] S4, using the first dose of the second N-type ion implantation to the anti-doping region 4 on both sides of the fin 2 of the partial region of the N-type ion, and the second spike annealing treatment is performed on the fin 2 to form a shallow doping region 5, such as Figure 3 As shown, the second N-type ions include phosphorus ions, and the first dose is 3.8E14 / cm 2 ~4.2E14 / cm 2 The second N-type ion injection energy when forming the shallow doped region 5 is 15KeV~18KeV, the peak temperature of the second spike annealing treatment is 945℃~955℃, and the annealing time is 210ms~230ms, wherein the anti-doped region 4 extends from the side of the shallow doped region 5 to below at least part of the bottom of the subsequently formed shallow doped region 5 to at least partially shallow dope the region 5, and the anti-doped region 4 is not connected to the shallow doped region 5, source region 7, and drain region 8 on both sides thereof.

[0052] After forming the shallow doped region 5, a second spike annealing process is still performed to repair lattice damage.

[0053] In one example, the N-type ions implanted to form the shallow doped region 5 are phosphorus ions, with an implantation energy of 17 KeV and an implantation dose of 4E14 / cm 2 , the injection angle is 30° (the angle between the normal line perpendicular to the semiconductor substrate 1 or the angle between the normal line and the semiconductor substrate 1). Figure 1 The angle between the Z direction and the center is rotated 4 times, and a second spike annealing treatment is performed with a peak temperature of 950°C and an annealing time of 220ms.

[0054] S5, after forming the shallow doping region 5 and before using the second dose of the second N-type ion to implant N-type ions into the fin 2 on both sides of the anti-doping region 4 and outside the shallow doping region 5, further includes performing an EPI process: etching the fin 2 on both sides of the anti-doping region 4 and outside the shallow doping region 5 to form source and drain trenches, and growing a semiconductor epitaxial material different from the fin 2 in the source and drain trenches to form an embedded epitaxial layer 6. The epitaxial layer 6 includes SiGe, such as Figure 4 shown.

[0055] S6, a second dose of second N-type ions is used to implant N-type ions into the fin 2 on both sides of the anti-doped region 4 and outside the shallow doped region 5, and a third spike annealing treatment is performed on the fin 2 to form a source region 7 and a drain region 8, as shown in FIG. Figure 5 As shown, the second N-type ion implantation energy when forming the source region 7 and the drain region 8 is 3KeV to 4KeV, wherein the second dose is greater than the first dose. The second dose is 1.5E15 / cm 2 ~3.5E15 / cm 2 Among the first peak annealing treatment, the second peak annealing treatment, the third peak annealing treatment and the fourth peak annealing treatment, the process temperature of the first peak annealing treatment is the highest, the temperature of the second peak annealing treatment is the lowest, and the peak temperature of the third peak annealing process is 980℃~990℃, and the duration is 210ms~230ms.

[0056] In the conventional method for manufacturing a FinFet device, the steps of forming the source region 7 and the drain region 8 include: firstly, implanting phosphorus ions with an energy of 4 KeV and a dose of 2E15 / cm 2 Then, arsenic ions are injected at an energy of 3KeV and a dose of 2E15 / cm 2 In this case, only one-step ion implantation is adopted, such as only implanting phosphorus ions or arsenic ions, or simultaneously implanting phosphorus ions and arsenic ions in one-step implantation, which can further improve HCI, and adds a third spike annealing process to repair the damage caused by ion implantation when the source region 7 and the drain region 8 are formed, as well as the damage caused by the anti-doping ion implantation. Through the above-mentioned three-step spike annealing treatment, the lattice damage caused by the doping ion implantation can be effectively improved, and the negative impact of the anti-doping ion implantation can be weakened.

[0057] In one example, the second dose of the second N-type ion implanted in one step is phosphorus ion, the implantation energy is 4KeV, and the implantation dose is 2E15 / cm 2 , the injection angle is 0° (the angle between the normal line perpendicular to the semiconductor substrate 1 or the angle between the normal line and the semiconductor substrate 1). Figure 1 The angle between the Z direction and the Z direction is vertically injected into the semiconductor substrate 1 or the top surface of the fin 2.

[0058] In summary, in the method for manufacturing a fin field-effect transistor provided in an embodiment of the present invention, an anti-doping region is formed between the source region and the drain region to compensate for the loss caused by first performing a shallow doping step and then performing an EPI step, thereby weakening the peak electric field value formed in the drain pinch-off region, reducing the substrate current Isub, and achieving the effect of reducing the hot carrier effect. The addition of a spike annealing process improves the damage caused by the anti-doping ion implantation, and the high-temperature annealing process of the gate oxide layer improves the film quality. Furthermore, compared with the existing technology of sequentially implanting two types of N-type ions, the method of implanting N-type ions in one step in this case can further improve HCI, thereby reducing the negative impact of the hot carrier injection effect of high-voltage N-type I / O devices.

[0059] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a fin field effect transistor, characterized in that: The following steps are involved: A semiconductor substrate (1) having fins (2) is provided, wherein a shallow trench isolation structure (3) is formed between adjacent fins (2); Using first N-type ions to implant N-type ions into a partial area of ​​the fin (2), and performing a first spike annealing process on the fin (2) to form an anti-doping region (4); Using a first dose of second N-type ions to implant N-type ions into partial regions of the fins (2) on both sides of the anti-doped region (4), and performing a second spike annealing process on the fins (2) to form shallow doped regions (5); Using a second dose of second N-type ions to implant N-type ions into the fins (2) located on both sides of the counter-doped region (4) and outside the shallow doped region (5), and performing a third spike annealing process on the fins (2) to form a source region (7) and a drain region (8), wherein the second dose is greater than the first dose; The anti-doping region (4) extends from the side of the shallow doping region (5) to below at least part of the bottom of the shallow doping region (5) to at least partially surround the shallow doping region (5), and the anti-doping region (4) is not connected to the shallow doping region (5), the source region (7), and the drain region (8) on both sides thereof.

2. The method for manufacturing a fin field effect transistor according to claim 1, wherein: The process parameters for forming the anti-doping region (4) include: the first N-type ions include arsenic ions, the implantation energy is 22KeV to 27KeV, and the implantation dose is 2.7E12 / cm 2 ~3.3E12 / cm 2 .

3. The method for manufacturing a fin field effect transistor according to claim 1, wherein: The second N-type ions include phosphorus ions, and the first dose is 3.8E14 / cm 2 ~4.2E14 / cm 2 , the second dose is 1.5E15 / cm 2 ~3.5E15 / cm 2 .

4. The method for manufacturing a fin field effect transistor according to claim 1, wherein: The second N-type ion implantation energy when forming the shallow doping region (5) is 15KeV to 18KeV, and the second N-type ion implantation energy when forming the source region (7) and the drain region (8) is 3KeV to 4KeV.

5. The method for manufacturing a fin field effect transistor according to claim 1, wherein: Before using the first N-type ions to implant N-type ions into a partial area of ​​the fin (2), the method further includes: Implanting P-type ions into the fin (2) to form a P-well in the fin (2); After forming the anti-doping region (4) and before using a first dose of second N-type ions to implant N-type ions into partial regions of the fin (2) on both sides of the anti-doping region (4), the method further includes: forming a gate oxide layer (9) covering the top and side surfaces of the fin (2), and performing a fourth spike annealing process on the gate oxide layer (9); forming a polysilicon layer covering the surface of the gate oxide layer (9), and etching the polysilicon layer to form a polysilicon gate; A shallow doping region (5) and a source region (7) are formed in the P-well on one side of the polysilicon gate, and a shallow doping region (5) and a drain region (8) are formed in the P-well on the other side of the polysilicon gate.

6. The method for manufacturing a fin field effect transistor according to claim 5, wherein: The process parameters for forming the P well include: an implantation energy of 45KeV to 55KeV, an implantation dose of 4.3E12 / cm 2 ~4.7E12 / cm 2 , the P-type ions include boron ions.

7. The method for manufacturing a fin field effect transistor according to claim 5, wherein: Among the first spike annealing process, the second spike annealing process, the third spike annealing process, and the fourth spike annealing process, the process temperature of the first spike annealing process is the highest, and the temperature of the second spike annealing process is the lowest.

8. The method for manufacturing a fin field effect transistor according to claim 5, wherein: The peak temperature of the first peak annealing treatment is 1000℃~1100℃, and the annealing time is 210ms~230ms; the peak temperature of the second peak annealing treatment is 945℃~955℃, and the annealing time is 210ms~230ms; the peak temperature of the third peak annealing treatment is 980℃~990℃, and the annealing time is 210ms~230ms; the peak temperature of the fourth peak annealing treatment is 945℃~955℃, and the annealing time is 210ms~230ms.

9. The method for manufacturing a fin field effect transistor according to claim 1, wherein: After forming the shallow doping region (5), and before using a second dose of second N-type ions to implant N-type ions into the fins (2) on both sides of the counter-doping region (4) and located outside the shallow doping region (5), the method further includes: etching the fins (2) on both sides of the counter-doping region (4) and located outside the shallow doping region (5) to form source-drain trenches, and growing a semiconductor epitaxial material different from that of the fins (2) in the source-drain trenches to form embedded epitaxial layers (6); The embedded epitaxial layer (6) on both sides of the counter-doped region (4) is implanted with N-type ions using a second dose of second N-type ions, and the fin (2) is subjected to a third spike annealing process to form a source region (7) and a drain region (8).

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