A system and method for implementing a multi-target long-delay DRFM storage component

Abstract

This invention relates to a radio frequency digital signal storage device, specifically to a system and method for implementing a multi-target long-delay DRFM storage component. It fully utilizes the high bandwidth characteristics of inexpensive dynamic random access memory (DRAM) to achieve high-bandwidth delay. The traditional alternating read / write operation in DRFM is converted into high-delay block read / write and fine-delay alternating read / write. Block read / write is performed in DDR memory, while alternating read / write is performed in the RAM within the FPGA chip. While fully utilizing the high bandwidth of DDR memory, the flexible high-speed random read / write characteristics of high-speed static memory compensate for the shortcomings of on-chip DDR memory in random read / write, achieving ultra-long delay times, reducing costs, achieving multi-target long delay, and improving work efficiency.

Description

Technical Field

[0001] The invention relates to a radio frequency digital signal frequency storage device, and in particular to a realization system and method of a multi-target long delay DRFM storage component. Background Art

[0002] With the continuous development of radar, electronic countermeasures, RF simulation and other technologies, digital RF frequency storage devices (DRFM) have received more and more attention due to their efficient storage and playback capabilities for RF signals. Its working principle is to convert RF analog signals into digital signals through A / D, write them into high-speed memory, perform delay and digital modulation, and then convert them into analog signals through high-speed D / A output. However, with the continuous development of radar and reactance systems, signal bandwidth continues to increase and signal delay continues to increase. Especially in application scenarios such as multi-target echoes or dense false target interference, parallel multi-channel memories are required to store and playback signals, resulting in an explosive growth in the system's demand for storage space. In order to deal with this problem, a common method is to use more advanced FPGA chips to obtain larger internal storage space, or to choose external static RAM to obtain larger storage space. These methods have led to a sharp increase in costs.

[0003] In order to achieve multi-target, the document "Radar Multi-Target Echo Simulation System and Method" provides a low-speed writing and high-speed sampling method to obtain multi-channel data. However, the high-speed sampling method is suitable for small bandwidth and low sampling application scenarios. Due to the limitation of the internal operating frequency of the FPGA, the sampling rate cannot be too high, resulting in a limited number of targets. Summary of the invention

[0004] The object of the present invention is to provide a system and method for realizing a multi-target long-delay DRFM storage component, so as to solve the problem that the hardware cost of DRFM components increases significantly in the application scenario of multi-target echoes.

[0005] The technical problem solution of the present invention:

[0006] A system for implementing a multi-target long-delay DRFM storage component, characterized in that it includes an FPGA chip and a DDR memory, wherein the FPGA chip includes:

[0007] The coarse delay module is used to receive an input data stream, convert the received input data stream and write it into the DDR memory; it is used to read the required data block from the DDR memory according to the target coarse distance, and convert the read data block to obtain a coarse delay data stream and send the coarse delay data stream to the fine delay module;

[0008] A fine delay module, used for configuring the received multiple target difference distances, for receiving the coarse delay data stream and generating a fine delay data stream that meets the requirements according to the current data write address and data read address;

[0009] The control module is used to set the target rough distance according to the target real-time distance and calculate the target difference distance; to control the rough delay module to write the input data stream into the DDR memory; to determine the data block to be written and the data block to be read by the rough delay module according to the target rough distance; to determine the address of the fine delay module to write data and read data according to the calculated target difference distance; and to select the multi-way switch connection mode according to the number and distribution of targets;

[0010] The DDR memory is used to receive the converted input data stream and store it in the form of data blocks.

[0011] It is further defined that the coarse delay module includes:

[0012] Input FIFO, used to receive input data stream, buffer the received input data stream and perform rate / bit width conversion;

[0013] The DDR interface logic module is used to write the converted input data stream into the DDR memory according to the write time slot, and to determine the read address according to the read time slot and the current data write address and the target coarse distance, and read the required data block in the DDR memory according to the read address;

[0014] A coarse delay multiplexer, used for opening a coarse channel connected to a corresponding output FIFO according to a read time slot, and for sending a data block read by a DDR interface logic module to the corresponding output FIFO through the opened coarse channel;

[0015] Output FIFO, number is N, used to buffer the read data blocks and perform bit width / rate conversion, play back into a coarse delay data stream at the speed of the input data stream, and send the coarse delay data stream to the fine delay module, where N is a positive integer greater than 1.

[0016] It is further defined that the fine delay module comprises:

[0017] The number of fine delay multiplexers is M, which are used to open the fine channels between the corresponding dual-port RAMs according to multiple target difference distances specified by the user, and to receive the coarse delay data stream sent by the corresponding output FIFO, where M is a positive integer greater than 1;

[0018] The dual-port RAMs are M in number and are connected one-to-one with the fine delay multiplexers, and are used to receive the coarse delay data stream through the fine channel and write the coarse delay data stream in time sequence, and to obtain the fine delay data stream according to the current data read address determined by the current data write address and the current target difference distance.

[0019] It is further defined that the input data stream sends the input data stream to each fine delay multiplexer, and each of the fine delay multiplexers is connected to all output FIFOs.

[0020] It is further defined that the control module includes:

[0021] A DDR interface logic control module, used for controlling the DDR interface logic module to write a data block no larger than half of the input FIFO storage space in the DDR memory, and for controlling the DDR interface logic module to read a required data block according to a given target coarse distance;

[0022] A coarse delay multiplexer control module, used to open a corresponding coarse channel in the coarse delay multiplexer according to a read time slot;

[0023] Output FIFO control module, used to enable and open the corresponding output FIFO;

[0024] A fine delay multiplexer control module is used to control the switch of the fine channel between the corresponding fine delay multiplexer and the output FIFO according to the target quantity and target difference distance set by the user;

[0025] The dual-port RAM control module is used to control the dual-port RAM to write a rough delay data flow, and send a data write address and a data read address to the dual-port RAM in real time according to a target difference distance.

[0026] It is further defined that the number M of the dual-port RAMs satisfies:

[0027] M<80%*(FPGA storage space-N*output FIFO storage space-input FIFO storage space) / dual-port RAM storage space.

[0028] A method for implementing a multi-target long-delay DRFM storage component, characterized in that the implementation system based on the multi-target long-delay DRFM storage component comprises the following steps:

[0029] S1, write the input data stream into the DDR memory;

[0030] S2, calculating the target difference distance according to the received target real-time distance and target rough distance, and generating a rough delay data stream;

[0031] S3. Obtain fine delay data streams corresponding to multiple targets through the coarse delay data stream and multiple target difference distances.

[0032] It is further defined that the above step S1 includes the following steps:

[0033] S11, receiving an input data stream, buffering the received input data stream and performing rate / bit width conversion;

[0034] S12, writing the input data stream into the DDR memory through controlling the DDR interface logic according to the write time slot to a data block that is less than or equal to half of the input FIFO storage space.

[0035] It is further defined that the above step S2 includes the following steps:

[0036] S21, receiving multiple target real-time distances specified by the user, matching the read time slots according to the number and position of the targets, and calculating the coarse delay data block address difference according to the target real-time distances and the current write data block address, thereby obtaining the read data block address;

[0037] S22, control the DDR interface logic, determine the current data read address according to the current data write data block address and the target coarse distance according to the read time slot, and read the required data block in the DDR memory according to the read address;

[0038] S23, the coarse delay multiplexer opens the corresponding coarse channel of the output FIFO according to the read time slot, enables the output FIFO corresponding to the coarse channel to be opened, and writes the read data block into the corresponding output FIFO;

[0039] S24. The data blocks written into the output FIFO are played back into a coarse delayed data stream according to the speed of the input data stream.

[0040] It is further defined that the above step S3 includes the following steps:

[0041] S31, configuring the target difference distances to be output to the corresponding number of fine delay multiplexers one by one according to the multiple target coarse distances specified by the user, and accessing the corresponding coarse delay data stream through the corresponding output FIFO according to the configured target difference distances;

[0042] S32, write the coarse delay data stream into the dual-port RAM corresponding to the fine delay multiplexer in time sequence, determine the current read address according to the difference distance between the current data write address and the current target, read out the corresponding fine delay data stream from different dual-port RAMs, and realize multi-target precise distance delay.

[0043] The beneficial effects of the present invention are:

[0044] 1. Make full use of the large bandwidth characteristics of cheap dynamic random access memory to achieve large bandwidth delay; convert the traditional alternating read and write in DRFM into large delay block read and write and fine delay alternating read and write. The block read and write are completed in the DDR memory, and the alternating read and write are completed in the ROM in the FPGA chip. While making full use of the large bandwidth of the DDR memory, the flexible high-speed random read and write characteristics of the high-speed static memory are used to make up for the shortcomings of the DDR memory in random read and write, and achieve an ultra-long delay time.

[0045] 2. Use the block and time slot reading and writing method, reasonably select the data block size and time slot length, realize the time-sharing multiplexing of the large bandwidth of DDR memory, give full play to the advantages of large bandwidth, low cost and large capacity of DDR memory during continuous reading and writing, and realize the storage and playback of multi-channel signals under large bandwidth.

[0046] 3. The fine delay module and the coarse delay module are fully connected, so that the coarse delay module can be connected to the RAM in any fine delay module, providing a flexible and sufficient configuration solution, making the entire system more flexible and diverse in the selection of independent channels and independent targets. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 This is a schematic diagram of the system structure of Embodiment 1 of the present invention;

[0048] Figure 2 This is a flow chart of the steps of obtaining a coarse delayed data stream in embodiment 2 of the present invention. DETAILED DESCRIPTION

[0049] Example 1

[0050] refer to Figure 1 , this embodiment provides an implementation system of a multi-target long-delay DRFM storage component, including an FPGA chip and a DDR memory.

[0051] Among them, FPGA chips include:

[0052] The coarse delay module is used to receive an input data stream, convert the received input data stream and write it into the DDR memory; it is used to read the required data block from the DDR memory according to the target real-time distance, and convert the read data block to obtain a coarse delay data stream and send the coarse delay data stream to the fine delay module;

[0053] The fine delay module is used to receive the target real-time distance and configure it, and is used to receive the coarse delay data stream and write the address and read the address according to the data given by the control module to generate the fine delay data stream that meets the requirements;

[0054] The control module is used to give a target rough distance and calculate a target differential distance according to the target real-time distance; to control the rough delay module to write the input data stream into the DDR memory; to determine the address of the data block to be written and the address of the data block to be read from the rough delay module according to the target rough distance; to give the address of writing data and reading data to the fine delay module according to the calculated target differential distance; to read out the fine delay data stream according to the target differential distance; and to select the multi-way switch connection mode according to the number and distribution of targets.

[0055] Specifically, the coarse delay module includes:

[0056] An input FIFO is used to receive an input data stream, to buffer the received input data stream, and to perform rate / bit width conversion;

[0057] The input data stream is continuously written into the input FIFO, which buffers the written input data stream and converts the rate and bit width of the input data stream to complete the conversion from the signal processing clock domain to the DDR interface clock domain.

[0058] The DDR interface logic module is used to write the input data stream converted by the input FIFO into the DDR memory in the form of data blocks according to the write time slot, and to read the required data blocks from the DDR memory according to the read time slot;

[0059] When the data stream is transferred from the input FIFO to the DDR memory, it needs to be implemented through the DDR interface logic. The converted input data stream is stored in the DDR memory in the form of data blocks through the DDR interface logic module according to the write time slot. When data is subsequently read from the DDR memory, the required data blocks are read from the DDR interface logic module according to the read time slot to complete the buffering of the input data stream written to the DDR memory.

[0060] The DDR interface logic module implements the data reading and writing of the external DDR chip. The reading and writing of the data stream is completed in several equally spaced time slots, such as Figure 2As shown. The write data occupies one time slot, and each of the N read modules occupies one time slot, for a total of N + 1 time slots. Assuming that the time of each time slot is τ, there are N target outputs, the data stream bandwidth is Bdata, and the DDR bandwidth is Bddr, then the constraint relationship between the number of targets that the DDR module can achieve and the input data stream is: (N + 1)*Bdata < Bddr. In actual use, N should be selected considering the loss of DDR refresh time, the loss of read / write conversion bandwidth, etc. The write time slot writes the buffered data stream into a continuous address range of the DDR memory. Considering the low read / write efficiency of DDR memory fragmentation, multi-module interleaving should be used in combination with the RANK and BANK designs of the DDR memory for read / write, ensuring that the addresses are aligned during read / write in each time slot, without row address rewriting during read / write in the same time slot, and selecting the largest possible read / write volume according to the system design requirements.

[0061] A coarse delay multiplexer, used to open the coarse channel connected to the corresponding output FIFO according to the read time slot, for sending the data block read by the DDR interface logic module to the corresponding output FIFO through the opened coarse channel;

[0062] There are N output FIFOs, used to buffer the read data blocks, perform bit width / rate conversion, replay the data blocks into a coarse delay data stream at the speed of the input data stream, and send the coarse delay data stream to the fine delay module, where N is a positive integer greater than 1;

[0063] The input end of the coarse delay multiplexer is connected to the output end of the DDR memory. The coarse delay multiplexer is connected to N output FIFOs. There are N coarse channels in the coarse delay multiplexer. Each output FIFO is connected to a corresponding coarse channel. Each coarse channel is used to read different time slots through the DDR interface logic module. The delay of each target is determined by the difference between the read block address and the write block address selected during the corresponding read time slot. After performing bit width / rate conversion on the read data blocks, any coarse channel switch can be selected according to the need to read the corresponding time slot from the DDR memory to obtain the coarse delay data stream. After buffering the high-speed data read in different time slots, it is replayed into a continuous data stream and sent to the fine delay module. The capacity of the input FIFO and the output FIFO should be selected to be greater than or equal to twice the storage capacity corresponding to the coarse delay step. At the same time, the input FIFO and the output FIFO can complete clock domain conversion.

[0064] The minimum delay step is determined by the amount of data contained in each read / write time slot. According to the above, the amount of data transmitted each time is large, so the delay step is large, and only large-step delays can be achieved. However, since the DDR capacity can reach the GB level, ultra-long delays can be achieved.

[0065] The fine delay module includes:

[0066] The number of fine delay multiplexers is M, which are used to receive the target real-time distance specified by the user and to be configured, and are used to receive the coarse delay data stream sent by the corresponding output FIFO, where M is a positive integer greater than 1; the input data stream sends the input data stream to each fine delay multiplexer, and each of the fine delay multiplexers is connected to all the output FIFOs;

[0067] There are multiple precision delay multiplexers, each precision delay multiplexer is connected to 1 to N output FIFOs. It is also possible to select that each precision delay multiplexer is connected to 1 to N output FIFOs and is also directly connected to the input data stream. At the same time, when the precision delay multiplexer is turned on, it will be configured according to the target real-time distance specified by the user.

[0068] Dual-port RAMs, the number of which is M and which are connected to the fine delay multiplexers in a one-to-one correspondence, are used to receive the coarse delay data stream and write the coarse delay data stream in a time sequence, and are used to obtain the fine delay data stream according to the current precise read address determined by the difference distance between the current data write address and the current target;

[0069] The dual-port RAM can delay according to the sampling clock, so it can achieve very high delay accuracy. The storage depth of the dual-port RAM needs to be greater than the minimum step of the coarse delay step in order to achieve accurate delay in all ranges. The internal storage resources of the entire FPGA only need to meet the needs of the input and output FIFO and M dual-port RAMs, and the storage resources consumed are only at the KB level, so a large number of independent targets can be achieved on a relatively cheap FPGA.

[0070] The control module includes:

[0071] The DDR interface logic control module is used to control the DDR interface logic module to write a data block no larger than half of the input FIFO storage space in the DDR memory according to the write time slot, and to control the DDR interface logic module to determine the read address according to the current data write address and the target coarse distance according to the read time slot, and read the required data block in the DDR memory according to the read address;

[0072] A coarse delay multiplexer control module, used to open different coarse delay multiplexers according to the read time slot;

[0073] Output FIFO control module, used to enable and open the corresponding output FIFO operation;

[0074] A fine delay multiplexer control module, used to control a fine channel switch between the fine delay multiplexer and a corresponding output FIFO according to a configured target real-time distance;

[0075] A dual-port RAM control module, used for controlling the coarse delay data stream to be written into the dual-port RAM, and for sending data write addresses and read addresses to the fine delay dual-port RAM in real time according to a target difference distance;

[0076] The number M of dual-port RAMs satisfies:

[0077] M<80%*(FPGA storage space-N*output FIFO storage space-input FIFO storage space) / dual-port RAM storage space.

[0078] Explain by specific products:

[0079] Large bandwidth ultra-long delay DRFM memory, instantaneous bandwidth reaches 1.6GHz, maximum delay time exceeds 100ms, delay step is 4ns, two completely independent coarse channels, each coarse channel has 2 targets, a total of 4 targets DRFM memory. Take one of the targets (assuming it is target 1) with a distance of 50km and a delay of 333.33333μs as an example.

[0080] The FPGA chip is Xilinx Kintex UltraScale KU060 FPGA, which contains 726K logic units and 38Mbit modular memory (Block RAM); DDR memory has two groups of 8 DDR4 memories. Each group is 64bit wide, each group has 8GByte capacity, and the interface clock is 1200MHz. At this time, the total bandwidth of the DDR4 memory interface is 38.4GB / s; the signal bandwidth is set to 1.6GHz, the equivalent sampling rate is selected to 4GHz, and the AD bit width is 16bit, then the required bandwidth of the data stream is: 8GB / s.

[0081] The address lines of DDR4 memory select row, column, and BANK modes. The lowest 3 bits are fixed, the second lowest 3 bits are BANK, the middle 10 bits are columns, and the highest 15 bits are rows. To ensure the highest read and write efficiency, a multi-module cross-read and write method is used. The read and write between each address increment are performed between different BANKs, and in the read and write of a time slot, only the BANK and column change but not the row.

[0082] Each write time slot writes 64KB, which corresponds to writing to DDR within 2.5μs after caching 8.192μs of data stream data in the input FIFO. To enhance the adaptability, the input FIFO capacity should be selected to have a data block size greater than or equal to 2 times, in this example, 192KB is selected.

[0083] The coarse delay multiplexer selects 1 input and 2 outputs. The input comes from the DDR interface logic module, and the output is connected to 2 output FIFOs and is controlled by the control module.

[0084] The read time slot N is selected as 2, and the corresponding output FIFO is 2, realizing two completely independent coarse channels. Each read time slot uses 2.73μs to complete the reading of 64KB data, realizing a coarse delay of 64KB (corresponding to 8.192μs) for the data stream.

[0085] For target 1 at 50 km, the control module controls the DDR interface logic module to read the data block at a position 40 away from the real-time written data block to form a data stream. At this time, the delay of the coarse delayed data stream after the coarse delay is 8.192*40=327.68μs.

[0086] The precision delay multiplexer selects 4 channels. Each precision delay multiplexer has 3 inputs, which are the direct input of the input data stream and two output FIFO inputs. Each precision delay multiplexer outputs 1 precision channel, which is output to the corresponding dual-port RAM. The precision delay multiplexer control module connects different precision delay multiplexers to the corresponding dual-port RAM according to the delay requirements of different targets.

[0087] The dual-port RAM selects 4 channels, that is, M is 4, and each RAM storage depth selects 512KB, corresponding to a delay of 32.768μs. The precise delay is achieved by the difference between the read and write addresses. The fine delay of 4ns can be supplemented in the 8.192μs delay step of the coarse delay. The clock signal in the signal processing clock domain selects 250MHz, 205MHz*16=4GHz, so 16 channels work in parallel to achieve an equivalent 4GHz sampling rate. For target 1 at 50 kilometers, the dual-port RAM control module controls the read address and write address of the dual-port RAM to differ by 1413, corresponding to a delay of 5.652μs, forming a precise delay data stream. The delay of this precise delay data stream relative to the input signal is 327.68+5.652=333.332μs. The corresponding distance is 49.9998km, realizing the simulation of the 50km target.

[0088] Two completely independent coarse channels can be realized by two read time slots, and each coarse channel can be connected to four independent dual-port RAMs. The targets connected to the same output FIFO are relatively independent within the range of 512KB storage depth (corresponding to 32.768μs delay). According to the needs, you can choose to generate two targets for each coarse channel, or one channel generates one independent target and the other coarse channel generates three relatively independent targets.

[0089] For the multi-target ultra-long delay DRFM memory, the instantaneous bandwidth reaches 400MHz, the maximum delay time exceeds 100ms, the delay step is 4ns, and there are 8 completely independent output FIFOs. Each of the 4 fine delay multiplexers receives 4 4-target DRFM memories for a total of 32 targets. For example, one of the targets (assuming it is target 2) is 320km away and has a delay of 2133.33333μs.

[0090] At this time, the FPGA chip selected is Xilinx Kintex UltraScale KU085 FPGA, which contains 1088K logic units and 56.9Mbit modular memory (Block RAM); the DDR memory has two groups of 8 DDR4 memories, each with a bit width of 64 bits, a capacity of 8GByte, and an interface clock of 1200MHz / s. At this time, the total bandwidth of the DDR memory interface is 38.4GB / s; the signal bandwidth is set to 400MHz, the equivalent sampling rate is 1GHz, and the AD bit width is 16bit, then the data flow bandwidth is: 2GB / s.

[0091] The address lines of DDR4 memory select row, column, and BANK modes. The lowest 3 bits are fixed, the second lowest 3 bits are BANK, the middle 10 bits are columns, and the highest 15 bits are rows. To ensure the highest read and write efficiency, a multi-module cross-read and write method is used. The read and write between each address increment are performed between different BANKs, and in the read and write of a time slot, only the BANK and column change but not the row.

[0092] Select 64KB to write in each write time slot, which corresponds to writing to the DDR4 memory within 3.64μs after caching 32.768μs of input data stream in the input FIFO each time; to enhance the adaptability of the input FIFO capacity, select a delay block size that should be greater than or equal to 2 times. In this example, select 192KB.

[0093] The coarse delay multiplexer selects 1 input and 8 outputs. The input comes from the DDR interface logic module, and the output is connected to 8 output FIFOs and is controlled by the control module.

[0094] Select 8 read time slots, that is, N is 8, and the corresponding output FIFO is 8, realizing 8 completely independent coarse channels. Each read time slot uses 3.64μs to complete the reading of 64KB data, and realizes a coarse delay of 64KB (corresponding to 8.192μs) for the data stream. For target 2 at 320 kilometers, the DDR interface logic control module controls the DDR interface logic to read the data block at a location 65 kilometers away from the real-time write data block, forming a coarse delay data stream. At this time, the coarse delay data stream delay after coarse delay is 32.768*65=2129.92μs.

[0095] 32 precision delay multiplexers are selected, each precision delay multiplexer has 9 inputs, namely direct input of input data stream and 8 output FIFO inputs. The output of each precision delay multiplexer is 1 precision channel, which is output to the corresponding dual-port RAM. The selection of precision delay multiplexers is controlled by the precision delay multiplexer control module. Different precision delay multiplexers are connected to the dual-port RAM according to the delay requirements of different targets.

[0096] The dual-port RAM is selected as 32 channels, that is, M is 32, and the storage depth of each RAM is selected as 64KB (corresponding to 32.768μs). The precise delay is achieved by the difference between the read and write addresses, and the fine delay with a step of 4ns can be supplemented in the 32.768μs delay step of the coarse delay. The clock signal in the signal processing clock domain is selected as 250MHz, and the 4 fine channels work in parallel to achieve an equivalent sampling rate of 1GHz.

[0097] For target 2 at 320 km, the dual-port RAM control module controls the read address and write address of the dual-port RAM to differ by 853, corresponding to a delay of 3.412μs, forming a precise delay data stream. The delay of this data stream relative to the input signal is 2129.92+3.412=2133.332μs. The corresponding distance is 319.9998km, realizing the simulation of the 320km target.

[0098] Eight read time slots can realize eight completely independent fine channels, each of which can be connected to four independent dual-port RAMs. The targets connected to the same output FIFO are relatively independent within the range of 64KB storage depth (corresponding to 8.192μs delay). According to the requirements, four targets are generated for each fine channel, that is, there are eight completely independent fine channels, and each fine channel has four relatively independent targets.

[0099] Example 2

[0100] refer to Figure 2 This embodiment provides a method for implementing a multi-target long delay DRFM storage component, including the following steps:

[0101] S1, write the input data stream into the DDR memory;

[0102] S11, receiving an input data stream, buffering the received input data stream and performing rate / bit width conversion;

[0103] S12, writing the input data stream into the DDR memory through controlling the DDR interface logic according to the write time slot to a data block that is less than or equal to half of the input FIFO storage space.

[0104] S2, calculating the target difference distance according to the received target real-time distance and target rough distance, and generating a rough delay data stream;

[0105] S21, receiving multiple target real-time distances specified by the user, matching the read time slots according to the number and position of the targets, and calculating the coarse delay data block address difference according to the target real-time distances and the current write data block address, thereby obtaining the read data block address;

[0106] S22, control the DDR interface logic, determine the current data read address according to the current data write data block address and the target coarse distance according to the read time slot, and read the required data block in the DDR memory according to the read address;

[0107] S23, the coarse delay multiplexer opens the corresponding coarse channel of the output FIFO according to the read time slot, enables the output FIFO corresponding to the coarse channel to be opened, and writes the read data block into the corresponding output FIFO;

[0108] S24. The data blocks written into the output FIFO are played back into a coarse delayed data stream according to the speed of the input data stream.

[0109] S3, obtaining fine delay data streams corresponding to multiple targets through the coarse delay data stream and multiple target difference distances;

[0110] S31, configuring the target difference distances to be output to the corresponding number of fine delay multiplexers one by one according to the multiple target coarse distances specified by the user, and accessing the corresponding coarse delay data stream through the corresponding output FIFO according to the configured target difference distances;

[0111] S32, write the coarse delay data stream into the dual-port RAM corresponding to the fine delay multiplexer in time sequence, determine the current read address according to the difference distance between the current data write address and the current target, read out the corresponding fine delay data stream from different dual-port RAMs, and realize multi-target precise distance delay.

Claims

1. A system for implementing a multi-target long-delay DRFM storage component, characterized in that: It includes an FPGA chip and a DDR memory, wherein the FPGA chip includes: The coarse delay module is used to receive an input data stream, convert the received input data stream and write it into the DDR memory; it is used to read the required data block from the DDR memory according to the target coarse distance, and convert the read data block to obtain a coarse delay data stream and send the coarse delay data stream to the fine delay module; A fine delay module, used for configuring the received multiple target difference distances, for receiving the coarse delay data stream and generating a fine delay data stream that meets the requirements according to the current data write address and data read address; The control module is used to set the target rough distance according to the target real-time distance and calculate the target difference distance; to control the rough delay module to write the input data stream into the DDR memory; to determine the address of the data block to be written and the address of the data block to be read from the rough delay module according to the target rough distance; to determine the address of the data to be written and the data to be read from the fine delay module according to the calculated target difference distance; and to select the multi-way switch connection mode according to the number and distribution of targets; The DDR memory is used to receive the converted input data stream and store it in the form of data blocks; Target difference distance = target real-time distance - target rough distance.

2. The implementation system of the multi-target long delay DRFM storage component according to claim 1 is characterized in that: The coarse delay module comprises: Input FIFO, used to receive input data stream, buffer the received input data stream and perform rate / bit width conversion; The DDR interface logic module is used to write the converted input data stream into the DDR memory according to the write time slot, and to determine the read address according to the read time slot and the current data write address and the target coarse distance, and read the required data block in the DDR memory according to the read address; A coarse delay multiplexer, used for coarsely matching the read time slot according to the target quantity and the target, opening a coarse channel connected to the corresponding output FIFO according to the read time slot, and sending the data block read by the DDR interface logic module to the corresponding output FIFO through the opened coarse channel; Output FIFO, number is N, used to buffer the read data blocks and perform bit width / rate conversion, play back into a coarse delay data stream at the speed of the input data stream, and send the coarse delay data stream to the fine delay module, where N is a positive integer greater than 1.

3. The implementation system of the multi-target long delay DRFM storage component according to claim 2 is characterized in that: The fine delay module comprises: Fine delay multiplexers, the number of which is M, used to open fine channels between corresponding dual-port RAMs according to multiple target difference distances specified by a user, and to receive coarse delay data streams sent by corresponding output FIFOs, where M is a positive integer greater than 1; The dual-port RAMs are M in number and are connected one-to-one with the fine delay multiplexers, and are used to receive the coarse delay data stream through the fine channel and write the coarse delay data stream in time sequence, and to obtain the fine delay data stream according to the current data read address determined by the current data write address and the current target difference distance.

4. The implementation system of the multi-target long delay DRFM storage component according to claim 3 is characterized in that: The input data stream sends the input data stream to each fine delay multiplexer, and each of the fine delay multiplexers is connected to all output FIFOs.

5. The implementation system of the multi-target long delay DRFM storage component according to claim 4 is characterized in that: The control module comprises: A DDR interface logic control module, used for controlling the DDR interface logic module to write a data block no larger than half of the input FIFO storage space in the DDR memory, and for controlling the DDR interface logic module to read a required data block according to a given target coarse distance; A coarse delay multiplexer control module, used to open a corresponding coarse channel in the coarse delay multiplexer according to a read time slot; Output FIFO control module, used to enable and open the corresponding output FIFO; A fine delay multiplexer control module is used to control the switch of the fine channel between the corresponding fine delay multiplexer and the output FIFO according to the target quantity and target difference distance set by the user; The dual-port RAM control module is used to control the dual-port RAM to write a rough delay data flow, and send a data write address and a data read address to the dual-port RAM in real time according to a target difference distance.

6. The implementation system of the multi-target long delay DRFM storage component according to claim 5 is characterized in that: The number M of the dual-port RAMs satisfies: M<80%*(FPGA storage space-N*output FIFO storage space-input FIFO storage space) / dual-port RAM storage space.

7. A method for implementing a multi-target long-delay DRFM storage component, characterized in that: The implementation system of the multi-target long delay DRFM storage component according to claim 6 comprises the following steps: S1, write the input data stream into the DDR memory; S2, calculating the target difference distance according to the received target real-time distance and target rough distance, and generating a rough delay data stream; S3. Obtain fine delay data streams corresponding to multiple targets through the coarse delay data stream and multiple target difference distances.

8. The method for implementing the multi-target long delay DRFM storage component according to claim 7, characterized in that: The above step S1 includes the following steps: S11, receiving an input data stream, buffering the received input data stream and performing rate / bit width conversion; S12, writing the input data stream into the DDR memory through controlling the DDR interface logic according to the write time slot to a data block that is less than or equal to half of the input FIFO storage space.

9. The method for implementing the multi-target long delay DRFM storage component according to claim 8, characterized in that: The above step S2 includes the following steps: S21, receiving multiple target real-time distances specified by the user, calculating the rough delayed data block address difference according to the target quantity and the target rough matching read time slot, according to the target real-time distance and the current write data block address, thereby obtaining the read data block address; S22, control the DDR interface logic, determine the current data read address according to the current data write data block address and the target coarse distance according to the read time slot, and read the required data block in the DDR memory according to the read address; S23, the coarse delay multiplexer opens the corresponding coarse channel of the output FIFO according to the read time slot, enables the output FIFO corresponding to the coarse channel to be opened, and writes the read data block into the corresponding output FIFO; S24. The data blocks written into the output FIFO are played back into a coarse delayed data stream according to the speed of the input data stream.

10. The method for implementing the multi-target long delay DRFM storage component according to claim 9, characterized in that: The above step S3 includes the following steps: S31, configuring the target difference distances to be output to the corresponding number of fine delay multiplexers one by one according to the multiple target coarse distances specified by the user, and accessing the corresponding coarse delay data stream through the corresponding output FIFO according to the configured target difference distances; S32, write the coarse delay data stream into the dual-port RAM corresponding to the fine delay multiplexer in time sequence, determine the current read address according to the difference distance between the current data write address and the current target, read out the corresponding fine delay data stream from different dual-port RAMs, and realize multi-target precise distance delay.

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