Semiconductor integrated circuit, multi-chip package, and method of operation of semiconductor integrated circuit

Abstract

Embodiments provide a semiconductor integrated circuit capable of identifying a logic unit number of a memory chip itself and a total number of loaded chips based on an electrical signal detected by a plurality of memory chips within a multi-chip package, a multi-chip package, and a method of operation of a semiconductor integrated circuit. The semiconductor integrated circuit of the embodiments includes a multi-chip package including a plurality of memory chips, and a controller that controls the multi-chip package. The plurality of memory chips includes a logic control section having a logic unit circuit that detects a potential from a wiring pad. The logic unit circuit judges a master chip and a slave chip based on the potential detected from the wiring pad, the master chip transmits a pulse count and a state response instruction to the slave chip, whereby the slave chip sets a logic unit number of the memory chip itself, and the master chip sets a total number of loaded chips based on state information from the slave chip.

Description

[0001]

[0002] This application claims priority to Japanese Patent Application No. 2021-044422 (Filing date: March 18, 2021). This application incorporates the entire contents of the base application by reference. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor integrated circuit, a multi-chip package, and a method of operation of a semiconductor integrated circuit. BACKGROUND

[0004] As a nonvolatile semiconductor storage device, a NAND flash memory is known. It is known that in the case where a plurality of memory chips are constituted, each memory chip is identified by rewriting a register stored in a ROM region of a memory cell array from the outside after being enclosed in a package. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a semiconductor integrated circuit, a multi-chip package, and a method of operation of a semiconductor integrated circuit, which can identify the number of logical units of a memory chip itself and the total number of chips loaded based on an electrical signal detected by a plurality of memory chips in a multi-chip package.

[0006] The semiconductor integrated circuit of the embodiment includes a multi-chip package including a plurality of memory chips, and a controller that controls the multi-chip package. The plurality of memory chips includes a logical control section having a logical unit circuit that detects a potential from a wiring pad. The logical unit circuit judges a master chip and a slave chip based on the potential detected from the wiring pad. The master chip transmits a pulse count and a state response command to the slave chip, whereby the slave chip sets the number of logical units of the memory chip itself. The master chip sets the total number of chips loaded based on state information from the slave chip. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram showing a configuration example of a semiconductor integrated circuit of the embodiment.

[0008] Figure 2 is a block diagram showing an internal configuration example of a memory package of the embodiment.

[0009] Figure 3 is a block diagram showing a circuit configuration example of a memory chip of the embodiment.

[0010] Figure 4 is a flowchart showing an initialization operation sequence of a memory chip after power-on.

[0011] ​Figure 5 is a table example of read values of each memory chip based on wiring of bonding pads of the memory chip shown in FIG. 8. Figure 3

[0012] Figure 6 is a table example of output values of the encoder circuit based on the logic unit circuit.

[0013] Figure 7A is a flowchart of the operation of the master chip MC in the LUN and MCM setting.

[0014] Figure 7B is a flowchart of the operation of the slave chip SC in the LUN and MCM setting.

[0015] Figure 8A is a timing chart showing a response sequence based on the pulse count "001" and the state response instruction.

[0016] Figure 8B is a timing chart showing a response sequence based on the pulse count "010" and the state response instruction.

[0017] Figure 8C is a timing chart showing a response sequence based on the pulse count "011" and the state response instruction.

[0018] Figure 8D is a timing chart showing a response sequence based on the pulse count "100" and the state response instruction.

[0019] Figure 9 is a block diagram showing an internal structure example of the memory package of the modification example of the embodiment.

[0020] Figure 10 is a block diagram showing a circuit structure example of the memory chip of the modification example of the embodiment.

[0021] Figure 11 is a sectional view showing a mounting structure example of the memory package of the modification example of the embodiment.

[0022] Figure 12 is a perspective view showing a mounting structure example of the memory package of the modification example of the embodiment.

[0023] Figure 13 is a plan view showing a configuration example of the solder balls of the memory package of the modification example of the embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, the embodiment will be described with reference to the accompanying drawings. In the description of the drawings described below, the same or similar parts are denoted by the same or similar reference numerals. The drawings are schematic.

[0025] ​In addition, the following embodiment illustrates a device, a method for embodying the technical idea, and is not limited in terms of the material, shape, configuration, arrangement, and the like of each component. The embodiment can be modified in various ways within the scope of the claims.

[0026] In the following description, a logical unit number (Logical Unit Number), a multi-chip module (Multi-Chip Module) are sometimes expressed as LUN, MCM for simplicity of presentation.

[0027] [Embodiment]

[0028] (Semiconductor integrated circuit)

[0029] An example of a block structure of a semiconductor integrated circuit 100 according to the embodiment is shown in Figure 1 The semiconductor integrated circuit 100 is connected to a host device 1 via a host interface 2, and functions as an external storage device of the host device 1. In addition, the host device 1 is, for example, a personal computer, a tablet, a smartphone, a mobile phone, a camera device, or the like. In the following description, the host device 1 is also referred to as a host 1. In addition, the host interface 2 is also referred to as a host I / F 2.

[0030] The semiconductor integrated circuit 100 has a nonvolatile semiconductor storage device 10, a controller 20, and a NAND interface 30 as shown in Figure 1 The nonvolatile semiconductor storage device 10 is, for example, a NAND flash memory. In addition, as a nonvolatile memory, it is not limited to a nonvolatile semiconductor memory such as a NAND flash memory, but can be a memory such as a ReRAM (Resistance Random Access Memory), a FeRAM (Ferroelectric Random Access Memory), or the like that can store data. In the following description, as an example of the nonvolatile semiconductor storage device 10, it is referred to as a NAND flash memory 10. In addition, the NAND interface 30 is referred to as a NAND I / F 30.

[0031] The NAND flash memory 10 is configured to have a multi-chip package 15. In addition, the multi-chip package 15 is configured by a plurality of memory chips (for example, #0 to #3). Each memory chip has a storage unit array in which a plurality of storage units are arranged in a matrix. Each storage unit can perform multivalued storage. Each memory chip is configured by arranging a plurality of physical blocks as a data erase unit. In addition, the NAND flash memory 10 performs data writing and data reading per physical page. A physical block is configured by a plurality of physical pages.

[0032] The controller 20 receives an instruction from the host 1 and controls the NAND flash memory 10 based on the received instruction. Specifically, the controller 20 writes data instructed to be written from the host 1 into the NAND flash memory 10, and reads out data instructed to be read from the host 1 from the NAND flash memory 10 and sends to the host 1. The controller 20 is electrically connected to the NAND flash memory 10 through the NAND I / F 30. The NAND flash memory 10 non-volatile stores data.

[0033] The NAND I / F 30 receives and transmits, for example, each of a chip enable signal (hereinafter, referred to as / CE), an instruction latch enable signal (hereinafter, referred to as / RE), an address latch enable signal (hereinafter, referred to as / WP), a write enable signal (hereinafter, referred to as / WE), a read enable signal (hereinafter, referred to as / RE), a write protect signal (hereinafter, referred to as / WP), I / O <7:0>, and a data strobe signal (hereinafter, referred to as DQS) via a separate wiring.

[0034] (Internal structure example of the multi-chip package)

[0035] An internal structure example of the multi-chip package 15 constituting the NAND flash memory 10 of the embodiment will be described.

[0036] An example of the internal structure of the multi-chip package 15 constituting the NAND flash memory 10 of the embodiment is shown in Figure 2 In the present embodiment, Figure 1 The NAND flash memory 10 of the present embodiment is constituted by, for example, one multi-chip package 15. However, the NAND flash memory 10 can be constituted by a plurality of multi-chip packages 15.

[0037] The multi-chip package 15 has a plurality of (in this case, four) memory chips #0 to #3 as shown in Figure 2

[0038] The memory chips #0 to #3 are electrically connected by separate internal wirings for each of / CE, CLE, ALE, / WE, / RE, / WP, I / O <7:0>, and DQS. For example, I / O0 of the multi-chip package 15 is commonly connected with the memory chips #0 to #3 within the multi-chip package 15. Similarly, I / O1 of the multi-chip package 15 is commonly connected with the memory chips #0 to #3 within the multi-chip package 15. The same applies to other signals.

[0039] (Internal circuit example of the memory chip)

[0040] Next, an internal circuit example of the memory chips #0 to #3 will be described.

[0041] An example of the internal circuit of the memory chips #0 to #3 is shown in Figure 3 ​All memory chips #0 to #3 have the same structure, so the structure of memory chip #0 will be described here.

[0042] Memory chip #0, such as Figure 3 As shown, it includes an I / O control circuit 111, a logic control circuit 112, a voltage generation circuit 113, a register control circuit 114, a column control circuit 115, a data register 116, a sense amplifier 117, a row control circuit 118, a memory cell array 130, a ROM region 131, and multiple internal wiring pads 160 (here, 160A and 160B). Furthermore, the internal wiring pads 160 are an example of wiring pads.

[0043] I / O control circuit 111 is a buffer circuit for transmitting and receiving I / O signals with controller 20 via the connection wiring of I / O signal input pins (I / O0-I / O7). Based on the signals received by logic control circuit 112, I / O control circuit 111 allocates and stores the instructions, addresses, and data (write data) fetched as I / O signals via I / O signals I / O0-I / O7 into register control circuit 114 or data register 116.

[0044] The logic control circuit 112 accepts various control signal inputs via various control signal input pins (CE, ALE, etc.). The logic control circuit 112 includes a state transition circuit (state machine) that performs state transitions based on the received control signals, controlling the overall operation of the memory chip #0.

[0045] Logic control circuit 112, such as Figure 3 As shown, it includes a LUN register 140, an MCM register 141, and a logic unit circuit 142. Furthermore, the logic unit circuit 142 includes an encoder circuit and a comparator circuit. Details will be explained later.

[0046] The LUN register 140 is a register for storing LUN information. The so-called LUN information is n-bit (n is an integer of 2 or more) information for identifying individual memory chips. Specifically, in the case where four memory chips are loaded in the multi-chip package 15, the logic unit circuit 142 identifies the LUNs by numbering them, for example, by "00" to "11". Specifically, if the memory chip is "LUN=00", it is known as the first memory chip of "Memory Chip #0". Similarly, if the memory chip is "LUN=01", it is known as the second memory chip of "Memory Chip #1". Further, if the memory chip is "LUN=11", it is known as the last memory chip of "Memory Chip #3". That is, if which chip of the first is accessed from the LUN information, it is known which block is intended to be accessed. For example, in the case where the memory chip is structured to have 0 to 999 blocks, the memory chip #0 is 0 to 999 blocks, the memory chip of the memory chip #1 becomes 1000 to 1999 blocks, and the memory chip of the memory chip #3 becomes 3000 to 3999 blocks. Here, in the case where the 1200th block is intended to be accessed, the 1200th block of the second memory chip #1 can be selected by the LUN information of LUN=01.

[0047] The MCM register 141 is a register for storing MCM information. The MCM information is information indicating the total number of chips of the memory chips loaded in the multi-chip package 15. Further, the MCM information is n-bit (n is an integer of 2 or more) information. Specifically, in the case where the memory chips are loaded in the multi-chip package 15 by four, the MCM information becomes MCM=11.

[0048] The logic unit circuit 142 reads electrical signals via a plurality of internal wiring pads 160 (here, 160A or 160B). Further, the logic unit circuit 142 can also be provided with a plurality of physical joining pads PD (here, PD1 to PD2) for reading electrical potentials. In the following description, the physical joining pads PD will be referred to as joining pads PD.

[0049] The plurality of joining pads PD (here, PD1, PD2) of the memory chips #0 to #3 are supplied with electrical potentials from the plurality of internal wiring pads 160 (here, 160A, 160B) in a combination unique within the memory chip, for example. That is, the plurality of joining pads PD can also be wired to the plurality of internal wiring pads 160 in a combination unique within the memory chip to supply electrical potentials.

[0050] The logic unit circuit 142 functions to set the LUN for each memory chip by means of a combination of potentials read from internal wiring pads 160A and / or 160B via bonding pads PD1 and PD2. Alternatively, it can have bonding pads PD with n bits (n being an integer greater than or equal to 2) based on the number of N memory chips loaded in the multi-chip package 15. For example, in the case of 8 memory chips, the number of 3-bit bonding pads PD for identifying the memory chips is 3. That is, the number of bonding pads PD can also be 3. However, it is not actually limited to these examples.

[0051] Internal wiring pads 160A and 160B are each electrically connected, for example, to either the power supply potential Vcc or the ground potential GND. Figure 3 In this configuration, internal wiring pad 160A is the ground potential GND, and internal wiring pad 160B is the power supply potential Vcc. The bonding pads PD1 and PD2 of memory chip #0 are electrically connected to internal wiring pad 160A. Furthermore, in the case of memory chip #1, for example, bonding pad PD1 is electrically connected to internal wiring pad 160B, and bonding pad PD2 is electrically connected to internal wiring pad 160A. In the following description, the "H" level (connected to power supply potential Vcc) is set to "1", and the "L" level (connected to ground potential GND) is set to "0". In the following description, the "H" level is referred to as "1", and the "L" level is referred to as "0".

[0052] The logic control circuit 112 instructs the voltage generation circuit 113 on the voltage value to be generated and the power supply timing. The voltage generation circuit 113, under the control of the logic control circuit 112, supplies power to the memory cell array 130 and its peripheral circuits. The register control circuit 114 stores status information indicating whether writing to the memory cell array 130 was successful, status information indicating whether erasing of the memory cell array 130 was successful, etc. This status information is sent to the controller 20 as response signals via the I / O control circuit 111.

[0053] Register control circuit 114 holds instruction, address, and status information. Register control circuit 114 transfers the address to row control circuit 118 and sense amplifier 117, and transfers the instruction to logic control circuit 112.

[0054] The column control circuit 115, the sense amplifier 117, and the row control circuit 118 perform access to the memory cell array 130 based on the control of the logic control circuit 112.

[0055] The column control circuit 115 selects and activates the bit line corresponding to the column address. The row control circuit 118 selects the word line corresponding to the row address and activates the selected word line. The sense amplifier 117 applies a voltage to the bit line selected by the column control circuit 115, and writes data stored in the data register 116 to the memory cell transistor located at the intersection of the word line selected by the row control circuit 118 and the bit line selected by the column control circuit 115. In addition, the sense amplifier 117 saves the read data in the data register 116 via the bit line selected by the column control circuit 115 and the word line selected by the row control circuit 118. The data saved in the data register 116 is sent to the I / O control circuit 111 through the data line, and is transferred from the I / O control circuit 111 to the controller 20.

[0056] The memory cell array 130 is configured by arranging memory cells of the NAND type, and stores write data from the host 1.

[0057] The memory cell array 130 can also be configured to have a ROM area 131 in which management information of the semiconductor integrated circuit 100 is stored. The ROM area 131 is a part of the memory cell array 130, and is an area configured by memory cells of the NAND type, like the memory cell array 130. For example, the ROM area 131 is rewritable by the manufacturer of the memory chip #0 or the manufacturer of the semiconductor integrated circuit 100, but is not accessible (readable, writable, erasable) by the user of the semiconductor integrated circuit 100. The ROM area 131 stores various kinds of management information.

[0058] As explained above, according to the embodiment, each memory chip #0 to #3 is provided with a plurality of internal wiring pads 160. The logic unit circuit 142 detects the potential read from the plurality of internal wiring pads 160 (160A, 160B) and sets the LUN. Further, the logic unit circuit 142 calculates the total number of chips loaded in the multi-chip package 15, that is, the MCM information, based on the LUN information of each memory chip #0 to #3. The logic unit circuit 142 determines the total capacitance of the semiconductor integrated circuit 100 by deciding the MCM information. In addition, the method of action regarding the setting of the LUN of the memory chip and the MCM will be described later.

[0059] (Action example of initialization)

[0060] Next, the initialization action at the time of power-on of each memory chip will be described. Each memory chip reads the potential from a plurality of bonding pads PD provided to the logic unit circuit 142 at the time of power-on. In addition, the logic unit circuit 142 performs initialization of the LUN register 140.

[0061] Example of action of initialization Figure 4is indicated. One example of a table of read values of each memory chip based on the wiring between the plurality of bonding pads PD (PD1, PD2) and the plurality of internal wiring pads 160 is indicated as follows. Figure 5 is indicated. In addition, one example of a table based on the output value of the encoder circuit possessed by the logic unit circuit 142 is indicated as follows. Figure 6 .

[0062] In step Sll, the logic unit circuit 142 detects the potential from the bonding pads PD and reads "1" or "0" of the electric signal. Specifically, as indicated in Figure 5 , each memory chip reads the electric signal from the bonding pads PD1, PD2, for example.

[0063] In step S12, the logic unit circuit 142 reads the output value outputted by the encoder circuit as indicated in Figure 6 . Specifically, the logic unit circuit 142 inputs "0" as an initial count, for example, and reads "000" outputted by the encoder circuit. In addition, the logic unit circuit 142 increments the count value by 1 to "1" after reading.

[0064] In step S13, the logic unit circuit 142 sets the output value of the encoder circuit as an initial value in the LUN register 140. Specifically, the logic unit circuit 142 writes "000" outputted by the encoder circuit as an initial count to the LUN register 140. In addition, the LUN register 140 can also be written with 2-bit information, i.e., "00", for example.

[0065] As explained above, according to the embodiment, the logic unit circuit 142 reads the electric signal from the plurality of (in this case, 2) bonding pads PD1, PD2 by the initialization action at the time of power-on. In addition, the logic unit circuit 142 writes the output value outputted from the encoder circuit to the LUN register 140.

[0066] (Action Example of Setting LUN and MCM)

[0067] Next, the action of setting the LUN and the MCM will be explained. After the initialization action at the time of power-on, each memory chip is explained as divided into the master chip MC and the slave chip SC.

[0068] The master chip MC is the first memory chip #0 of the memory chips in the multi-chip package 15, for example, as indicated in Figure 2 . The slave chip SC is the second memory chip #1 of the memory chips in the multi-chip package 15, for example, as indicated in Figure 2The memory chips #1 to #3 other than the first memory chip #0 in the multi-chip package 15 are shown. Each memory chip in the multi-chip package 15 recognizes the LUN and the MCM in each memory chip #0 to #3, and thus the master chip MC becomes the master of the MCM and the setting operation of the MCM.

[0069] The master chip MC and the slave chip SC are connected to each other as shown. Figure 2 As shown, the I / O signals are commonly connected. The master chip MC can exchange signals with the slave chip SC via the I / O signals, for example.

[0070] An example of the operation of the master chip MC is shown as shown. Figure 7A An example of the operation of the slave chip SC is shown as shown. Figure 7B An example of the operation of the slave chip SC is shown as shown.

[0071] In the operation of setting the LUN and the MCM at the time of power-on, the logic unit circuit 142 selects the master chip MC and the slave chip SC based on the signals read from the bonding pads PD1 and PD2. The memory chip selected as the master chip MC sets each slave chip SC by transmitting a pulse count to the slave chip SC. The master chip MC receives the status signal from the slave chip SC by the status response instruction and sets the MCM. The following is an example of the detailed flow of the operation of setting the LUN and the MCM at the time of power-on.

[0072] In step S21, each memory chip reads the potential from the bonding pads PD at the time of power-on by the initialization (S11 to S13). In addition, the LUN of each memory chip is initialized, and the LUN information is stored in the LUN register 140.

[0073] In step S22, the logic unit circuit 142 judges whether the value stored in the LUN register 140 coincides with the value "00" of the electrical signal read from the bonding pads. The logic unit circuit 142 goes to step S23 in the case of coincidence with "00". The logic unit circuit 142 goes to step S31 in the case of non-coincidence with "00". That is, the steps after step S23 are the operation of the master chip MC. In addition, the steps after step S31 are the operation of the slave chip SC.

[0074] (Operation of Master Chip)

[0075] In step S23, the logic unit circuit 142 transmits the pulse count to the slave chip SC. Specifically, the logic unit circuit 142 outputs the count value "1" to the encoder circuit, for example, and outputs the output value "001" output from the encoder circuit as the pulse count to the slave chip SC. That is, the logic unit circuit 142 transmits the pulse count for the count value using the encoder circuit in order to recognize the slave chip SC. The pulse count is the pulse count used by the master chip MC and the slave chip SC in order to recognize the LUN of each memory chip. In the following description, the pulse count is also referred to as a pulse waveform or a pulse clock number.

[0076] In step S24, the logic unit circuit 142 transmits a state response instruction to the slave chip SC after saving the pulse count received from the slave chip SC. Specifically, the logic unit circuit 142 transmits the pulse count "001", for example, and requests a response from the slave chip SC as the memory chip #1.

[0077] In step S25, the logic unit circuit 142 determines whether or not the state response from the slave chip SC is received. The logic unit circuit 142 proceeds to step S26 in the case where the state response from the slave chip SC is received. In addition, the logic unit circuit 142 proceeds to step S27 in the case where the state response from the slave chip SC is not received. The state response refers to the case where the slave chip SC transmits the state information of the signal of the "H" level to the master chip MC, for example, in the presence of the slave chip SC.

[0078] In step S26, the logic unit circuit 142 increments the counter by 1. Specifically, the logic unit circuit 142 increments the count value of the counter by 1. For example, in the case where the count value is "1", the count value is incremented to "2".

[0079] In step S27, the logic unit circuit 142 determines whether or not the state response is received up to a prescribed number of times (7 times in this example). Specifically, the logic unit circuit 142 proceeds to step S28 in the case where the state response is received up to the prescribed number of times (7 times in this example), for example. The logic unit circuit 142 returns to step S23 in the case where the state response is not received up to the prescribed number of times (7 times in this example). The prescribed number of times refers to the number of occurrences of the pulse count used to recognize the LUN of the slave chip SC. That is, if there is the state response up to the memory chip #3 and there is no state response after the memory chip #4, the memory chips loaded in the multi-chip package 15 can determine that there are four. That is, the logic unit circuit 142 determines the total number of the loaded memory chips based on the state information from the slave chip SC.

[0080] In step S28, the logic unit circuit 142 sets the total number of the memory chips judged to be loaded in the MCM register 141. Further, the logic unit circuit 142 can also transmit an instruction for setting the MCM register 141 to the slave chip SC via the I / O signal.

[0081] (Action of slave chip)

[0082] In step S31, the logic unit circuit 142 proceeds to step S32 in a case where the received pulse count coincides with the value of the electric signal read from the bonding pad. The logic unit circuit 142 proceeds to step S34 in a case where the received pulse count does not coincide with the value of the electric signal read from the bonding pad. Specifically, the logic unit circuit 142 receives the pulse count transmitted by the master chip MC. Further, the logic unit circuit 142 compares the received pulse count with the value of the electric signal read from the bonding pad using a comparator circuit. Further, the logic unit circuit 142 counts the number of times the pulse count is received.

[0083] In step S32, the logic unit circuit 142 saves the pulse count transmitted by the master chip MC and overwrites the LUN information from the initial value. That is, the logic unit circuit 142 writes the pulse count in the LUN register 140 to set the LUN information in a case where the received pulse count coincides with the value of the electric signal read from the bonding pad PD. Specifically, the memory chip #1 of the slave chip receives the pulse count, for example, and writes the pulse count in the LUN register 140 to set the LUN information in a case where the pulse count coincides with the value of the electric signal read from the bonding pad PD. In addition, in a case where the value of the electric signal read from the bonding pad PD is 2-bit information, it is also possible to compare with the 2-bit information of the pulse count.

[0084] In step S33, the logic unit circuit 142 receives the state response instruction transmitted by the master chip MC. Further, the logic unit circuit 142 transmits the state information to the master chip MC via the I / O signal on the basis of the pulse count received by each slave chip SC. Further, the logic unit circuit 142 transmits the state information to the master chip MC after receiving the state response instruction of the pulse count.

[0085] In step S34, the logic unit circuit 142 judges whether the number of times the pulse count is received is completed for a prescribed number of times. Specifically, the logic unit circuit 142 proceeds to step S35 in a case where the number of times the pulse count is received is completed for a prescribed number of times. In a case where the number of times the pulse count is received is not completed for a prescribed number of times, the logic unit circuit 142 returns to step S31.

[0086] In step S35, the logic unit circuit 142 sets the MCM register 141. The response action of the master chip MC and the slave chip SC will be described later using a timing chart example of the action.

[0087] (Action example of response determination of master chip MC and slave chip SC)

[0088] Next, the response action between the master chip and the slave chip at the time of setting the LUN and the MCM will be described with a timing chart.

[0089] An example of the timing chart of the response action of the master chip MC and the slave chip SC in the case where the master chip MC has transmitted the pulse count "001" as the pulse waveform is shown as Figure 8A Similarly, an example of the timing chart in the case where the master chip MC has transmitted the pulse count "010" as the pulse waveform is shown as Figure 8B Similarly, an example of the timing chart in the case where the master chip MC has transmitted the pulse count "010" as the pulse waveform is shown as Figure 8C Similarly, an example of the timing chart in the case where the master chip MC has transmitted the pulse count "010" as the pulse waveform is shown as Figure 8D Further, the case where the master chip MC has transmitted the pulse count "101" to "111" as the pulse waveform is omitted.

[0090] (Action example of case where pulse count "001" is transmitted)

[0091] During TO to Tl, the master chip MC transmits the pulse count "001" to the slave chip SC as shown in Figure 8A

[0092] During Tl to T2, the memory chips #1 to #3 as the slave chip SC receive the pulse count transmitted from the master chip MC.

[0093] During T2 to T3, the memory chips #1 to #3 as the slave chip SC compare the received pulse count with the read signal.

[0094] During T3 to T4, the memory chip #1 in which the received pulse count coincides with the read signal saves the pulse count. Specifically, the memory chip #1, for example, overwrites the LUN information and sets it in the LUN register 140. The memory chips #2 and #3 in which the received pulse count does not coincide with the read signal confirm whether the pulse count of the prescribed number of times has been received.

[0095] During T4 to T5, the master chip MC transmits the state response instruction.

[0096] ​During the period of T5 to T6, the memory chip #2 of the slave chip SC transmits the status information to the master chip MC.

[0097] During the period of T6 to T7, the master chip MC receives the status information from the slave chip SC.

[0098] After T7, the master chip MC receives the status information, and thus accumulates the count of the chips loaded in the multi-chip package 15.

[0099] (Case of transmitting the pulse count "010")

[0100] During the period of TO to Tl, the master chip MC transmits the pulse count "010" to the slave chip SC as shown in FIG. 10. Figure 8B

[0101] During the period of Tl to T2, the memory chips #1 to #3 of the slave chip SC receive the pulse count transmitted from the master chip MC.

[0102] During the period of T2 to T3, the memory chips #1 to #3 of the slave chip SC compare the received pulse count with the read signal.

[0103] During the period of T3 to T4, the memory chip #2 in which the received pulse count coincides with the read signal stores the pulse count. Specifically, the memory chip #2, for example, overwrites the LUN information and sets in the LUN register 140. The memory chips #1 and #3 in which the received pulse count does not coincide with the read signal confirm whether the pulse count of the prescribed number of times is received.

[0104] During the period of T5 to T6, the memory chip #2 of the slave chip SC transmits the status information to the master chip MC.

[0105] During the period of T6 to T7, the master chip MC receives the status information from the slave chip SC.

[0106] After T7, the master chip MC receives the status information, and thus accumulates the count of the chips loaded in the multi-chip package 15.

[0107] (Case of transmitting the pulse count "011")

[0108] During the period of TO to Tl, the master chip MC transmits the pulse count "011" to the slave chip SC as shown in FIG. 11. Figure 8C

[0109] During the period of Tl to T2, the memory chips #1 to #3 of the slave chip SC receive the pulse count transmitted from the master chip MC.

[0110] ​​During T2-T3, the memory chips #1-#3 of the slave chip SC compare whether the received pulse count coincides with the read signal.

[0111] During T3-T4, the memory chip #3 in which the received pulse count coincides with the read signal stores the pulse count. Specifically, the memory chip #3 overwrites the LUN information, for example, and sets it in the LUN register 140. The memory chips #1, #2 in which the received pulse count does not coincide with the read signal confirm whether the pulse count has been received a prescribed number of times.

[0112] During T5-T6, the memory chip #3 of the slave chip SC transmits the status information to the master chip MC.

[0113] During T6-T7, the master chip MC receives the status information from the slave chip SC.

[0114] After T7, the master chip MC receives the status information, and therefore accumulates the count of the chips loaded in the multi-chip package 15.

[0115] (Case in which the pulse count "100" is transmitted)

[0116] During T0-T1, the master chip MC transmits the pulse count "100" to the slave chip SC as shown in Figure 8D

[0117] During T1-T2, the memory chips #1-#3 of the slave chip SC receive the pulse count transmitted from the master chip MC.

[0118] During T2-T3, the memory chips #1-#3 of the slave chip SC compare whether the received pulse count coincides with the read signal.

[0119] During T3-T4, the memory chips #1, #2, #3 in which the received pulse count does not coincide with the read signal confirm whether the pulse count has been received a prescribed number of times.

[0120] During T5-T6, since all of the slave chips SC do not coincide, no status information is transmitted.

[0121] During T6-T7, the master chip MC does not receive the status information from the slave chip SC, and therefore judges that there is no memory chip #4.

[0122] After T7, since no status information is received, the master chip MC determines the total number of chips loaded in the multi-chip package 15. Further, in this example of the timing chart, the total number of loaded chips is decided at the time when there is no status information from the slave chip SC, but it can be decided, for example, as described above, after confirming that the status information from the slave chip SC has reached a prescribed number of 7 times.​

[0123] As explained above, according to the embodiment, the master chip MC sends a pulse count to the slave chips SC. Each slave chip SC compares the pulse count from the master chip MC with the electrical signal read from the bonding pads, and if they match, sets it in a register. The master chip MC sends a status response command to the slave chips SC, and the slave chips SC send status information to the master chip MC. Based on the status information of the slave chips SC, the master chip MC accumulates the MCM and determines the MCM. The master chip MC sets the determined MCM in the MCM register 141. Furthermore, since the semiconductor integrated circuit 100 can identify LUN information by each memory chip based on the potential read from the bonding pads PD, it is also possible that the master chip MC does not send a pulse count to the slave chips SC, but instead determines the total number of loaded chips by sending a status response command to the slave chips SC from the beginning.

[0124] (Effects of the implementation method)

[0125] According to the embodiment, when the power is turned on, the logic unit circuit 142 can automatically set the LUN by reading the potential from the bonding pads (PD) of each memory chip. Furthermore, the logic unit circuit 142 calculates the total number (MCM) of memory chips loaded within the multi-chip package 15 based on the LUN information of each memory chip. Therefore, the logic unit circuit 142 can determine the total capacity within the multi-chip package 15 based on the total number (MCM) of memory chips loaded within the multi-chip package 15.

[0126] [Variations on the implementation method]

[0127] (Example of the internal structure of a multi-chip package)

[0128] An example of the internal structure of the multi-chip package 15A of the NAND flash memory 10 constituting a modified embodiment will be described.

[0129] For example, an internal structure of the multi-chip package 15A of the NAND flash memory 10 constituting a variation of the implementation embodiment. Figure 9 As shown. The multi-chip package 15 of this embodiment is as follows. Figure 3 The structure shown connects potentials in a unique combination through the wiring between the internal wiring pads 160 within each memory chip and the physical bonding pads PD of the logic cell circuits 142 within each memory chip. Compared to the structure of the multi-chip package 15 in this embodiment, the modified multi-chip package 15A of this embodiment has multiple external wiring pads 170 within it. That is, the multi-chip package 15A has the following structure, as shown... Figure 9As shown, the potentials are connected in a manner that becomes a unique combination by wiring between the external wiring pads 170A, 170B within the multi-chip package 15A and the bonding pads PD possessed by the logic unit circuit 142 within each memory chip. Further, as for other structures, the multi-chip package 15A is the same as the multi-chip package 15 of the present embodiment. Further, the external wiring pads 170 are an example of wiring pads.

[0130] Each of the external wiring pads 170A, 170B is electrically connected to, for example, any one of the power supply potential Vcc or the ground potential GND. In Figure 9 In the present embodiment, the external wiring pad 170A is the ground potential GND. In addition, the external wiring pad 170B is the power supply potential Vcc. The bonding pads PD1, PD2 of the memory chip #0A are commonly electrically connected to the external wiring pad 170A. The bonding pad PD1 of the memory chip #1A is connected to the external wiring pad 170A, and the bonding pad PD2 is electrically connected to the external wiring pad 170B. The bonding pad PD1 of the memory chip #2A is connected to the external wiring pad 170B, and the bonding pad PD2 is electrically connected to the external wiring pad 170A. The bonding pads PD1, PD2 of the memory chip #3A are commonly electrically connected to the external wiring pad 170B.

[0131] (Example of internal circuit of memory chip)

[0132] Next, an example of the internal circuit of the memory chips #0A to #3A of the modified example of the present embodiment will be described.

[0133] An example of the internal circuit of the memory chips #0A to #3A is shown as shown in FIG. 17. Each of the memory chips #0A to #3A has the same structure, and thus the structure of the memory chip #0A will be described here. Figure 10 An example of the internal circuit of the memory chips #0A to #3A is shown as shown in FIG. 17. Each of the memory chips #0A to #3A has the same structure, and thus the structure of the memory chip #0A will be described here.

[0134] The difference in the structure of the internal circuit of the memory chip #0A and the memory chip #0 is the structure of reading the potential that determines the setting of the LUN from the external wiring pad 170 outside each memory chip. Further, the basic operation of the multi-chip package 15A is the same as the basic operation of the multi-chip package 15.

[0135] (Examples of cross-sectional view and plan view showing internal structure of multi-chip package 15A)

[0136] Figure 11 is an example of a cross-sectional view showing an example of the internal structure of the multi-chip package 15A. Figure 9 is an example of a cross-sectional view showing an example of the internal structure of the multi-chip package 15A. Figure 12 is an example of a perspective view showing an example of the internal structure of a part of the multi-chip package 15A. Figure 13 is an example of a plan view showing the back surface of the multi-chip package 15A.

[0137] The multi-chip package 15A of the modification of the embodiment includes, as shown in Figure 11

[0138] The bonding wire 9 electrically connects the bonding pads PD provided at the end edge portions of the stacked memory chips #0 to #3 to the external wiring pads 170 provided at the end edge portion of the wiring substrate 7, as shown in Figure 11 12

[0139] The external wiring pads 170 are electrically connected to the solder balls 50 by wiring patterns formed on the surface and the back surface of the wiring substrate 7. The pattern formed on the surface and the wiring pattern formed on the back surface are connected by the via 23.

[0140] The solder balls 50 are input and output pins of the multi-chip package 15A. The solder balls 50 include, among the input and output pins, each control signal pin, each I / O signal pin, and the like, as shown in Figure 13 Figure 13 In the drawing, Vcc is a power potential pin, Vss is a ground potential pin, NU is an unused pin, and NC is an unconnected pin. The NU pin is indicated by a circular line. That is, the multi-chip package 15A uses the NU pin of the solder ball 50 to connect the potential to the pad PD via the external wiring pad 170.

[0141] (Effect of the modification of the embodiment)

[0142] The multi-chip package 15A can set the LUN by electrically wiring the bonding pads PD of each memory chip to the external wiring pads 170 when assembling the multi-chip package 15A in which the memory chips are mounted.

[0143] The multi-chip package 15A can set the potential of the potential at which the logic unit circuit 142 reads by using the NU pin of the solder ball 50. Thus, after the multi-chip package 15A is assembled, the LUN can be automatically set for the memory chips in the multi-chip package 15A at the time of power-on from the potential setting of the NU pin.

[0144] ​​​​Several embodiments of the present application are described, but these embodiments are presented by way of example only, and are not intended to limit the scope of the application. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the application. That is, for example, there are various ways of the circuit structure between the master chip MC and the slave chip SC, and the circuit structure that transmits the information of the LUN and the MCM to each other, and these embodiments and variations thereof are included in the scope or spirit of the application, and are included in the scope of the application and equivalents thereof recited in the claims.

[0145] Explanation of Reference Numerals

[0146] 10 Nonvolatile semiconductor memory device

[0147] 15 Multi-chip package

[0148] 100 Semiconductor integrated circuit

[0149] 111 I / O control section

[0150] 112 Logic control section

[0151] 113 Voltage generation circuit

[0152] 114 Register control section

[0153] 115 Column control circuit

[0154] 116 Data register

[0155] 117 Sense amplifier

[0156] 118 Row control circuit

[0157] 130 Memory cell array

[0158] 140 LUN register

[0159] 141 MCM register

[0160] 142 Logic unit circuit

[0161] 160A 160B • • • Internal wiring pad

[0162] 170A 171B • • • External wiring pad

[0163] #0 to #3 • • • Memory chip

[0164] PD1 to 2 • • • Physical bonding pad

Claims

1. A semiconductor integrated circuit, comprising: a multi-chip package having a plurality of memory chips; and a controller that controls the multi-chip package, wherein the plurality of memory chips has a logic control section having a logic unit circuit that detects a potential from a wiring pad, wherein the logic unit circuit judges a master chip and a slave chip based on the potential detected from the wiring pad, the master chip transmits a pulse count and a state response command to the slave chip, whereby the slave chip sets a logic unit number of its own memory chip, and the master chip sets a total number of chips loaded based on state information from the slave chip.

2. The semiconductor integrated circuit according to claim 1, wherein the wiring pad has an internal wiring pad within the plurality of memory chips.

3. The semiconductor integrated circuit according to claim 1, wherein the wiring pad has an external wiring pad outside the plurality of memory chips.

4. The semiconductor integrated circuit according to claim 1, wherein the logic unit circuit further has a physical bonding pad.

5. The semiconductor integrated circuit according to claim 1, wherein the logic control section has an LUN register that stores information of a logic unit number.

6. The semiconductor integrated circuit according to claim 1, wherein the logic control section has an MCM register that stores information of a total number of memory chips loaded in the multi-chip package.

7. The semiconductor integrated circuit according to claim 1, wherein the logic unit circuit further has an encoder circuit that outputs a pulse count transmitted to the slave chip using a value output from the encoder of the master chip.

8. The semiconductor integrated circuit according to claim 1, wherein the logic unit circuit further has a comparator circuit that compares a signal of the potential detected from the wiring pad with a signal of the pulse count transmitted to the slave chip from the master chip.

9. The semiconductor integrated circuit according to claim 1, wherein the multi-chip package has a solder ball that inputs and outputs a signal, and the multi-chip package sets a potential at which the logic unit circuit reads a potential, using an unused pin of the solder ball for a user.

10. A multi-chip package having a plurality of memory chips, wherein the plurality of memory chips has a logic control section having a logic unit circuit that detects a potential from a wiring pad, wherein the logic unit circuit judges a master chip and a slave chip based on the potential detected from the wiring pad, the master chip transmits a pulse count and a state response command to the slave chip, whereby the slave chip sets a logic unit number of its own memory chip, and the master chip sets a total number of chips loaded based on state information from the slave chip.

11. The multi-chip package according to claim 10, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The wiring pad has an internal wiring pad inside the plurality of memory chips.

12. The multi-chip package according to claim 10, wherein The wiring pad has an external wiring pad outside the plurality of memory chips.

13. The multi-chip package according to claim 10, wherein The logic unit circuit further has a physical bonding pad.

14. The multi-chip package according to claim 10, wherein The logic control section has a LUN register that stores information of a logic unit number.

15. The multi-chip package according to claim 10, wherein The logic control section has a MCM register that stores information of a total number of memory chips loaded in the multi-chip package.

16. The multi-chip package according to claim 10, wherein The logic unit circuit further has an encoder circuit that outputs a pulse count transmitted to the slave chip using a value output from the encoder circuit of the master chip.

17. The multi-chip package according to claim 10, wherein The logic unit circuit further has a comparator circuit that compares a signal of the potential detected from the wiring pad with a signal of the pulse count transmitted from the master chip to the slave chip.

18. A method of operating a semiconductor integrated circuit that includes a multi-chip package including a plurality of memory chips and a controller that controls the multi-chip package, In the method of operating the semiconductor integrated circuit, A logic unit circuit included in each of the plurality of memory chips detects a potential from a wiring pad, The logic unit circuit included in each of the plurality of memory chips determines a master chip and a slave chip based on the potential detected from the wiring pad, A pulse count and a status response instruction are transmitted by the master chip, A logic unit number of the slave chip is set based on the pulse count transmitted by the master chip, Status information is transmitted by the slave chip, The master chip that receives the status information determines a total number of memory chips loaded in the multi-chip package.

19. The method of operating the semiconductor integrated circuit according to claim 18, wherein The potential detected from the wiring pad includes identification information of each memory chip in the multi-chip package.

20. The method of operating the semiconductor integrated circuit according to claim 18, wherein The potential is detected from the wiring pad at the time of turning on a power supply.

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