Semiconductor devices

Abstract

The semiconductor device of the embodiment comprises a plurality of semiconductor elements, an insulating component, a first terminal, a second terminal and a plurality of control terminals. The plurality of semiconductor elements respectively include a semiconductor portion, a first electrode on the back side of the semiconductor portion, a second electrode on the surface and a control electrode on the surface, and are arranged in a first direction from the first electrode toward the second electrode. The plurality of semiconductor elements are connected in series, including a first element at one end and a second element at the other end. The insulating component has a first surface facing the first element and a second surface facing the second element. The first terminal is electrically connected to the first electrode of the first element, the second terminal is electrically connected to the second electrode of the second element, and the plurality of control terminals are electrically connected to the control electrode. The second terminal and the plurality of control terminals are arranged on one side of the first surface side and the second surface side.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2021-43577 (filing date: March 17, 2021), and the entire contents of the basic application are cited by reference to the basic application. Technical Field

[0002] The present invention relates to semiconductor devices. Background Art

[0003] A semiconductor device with a high withstand voltage can be realized by connecting a plurality of semiconductor elements in series. However, if a plurality of semiconductor elements are arranged in a plane, the mounting area of ​​the semiconductor device on the circuit board increases. Summary of the invention

[0004] An object of the present invention is to provide a semiconductor device having a high withstand voltage and capable of reducing the mounting area.

[0005] The semiconductor device of the embodiment includes a plurality of semiconductor elements, an insulating member, a first terminal, a second terminal, and a plurality of control terminals. The plurality of semiconductor elements respectively include a semiconductor portion, a first electrode provided on the back surface of the semiconductor portion, a second electrode provided on the surface of the semiconductor portion opposite to the back surface, and a control electrode provided on the surface of the semiconductor portion and controlling the current flowing between the first electrode and the second electrode. The plurality of semiconductor elements are arranged in a first direction from the first electrode toward the second electrode. The plurality of semiconductor elements are connected in series by electrically connecting the second electrode to other first electrodes between semiconductor elements adjacent in the first direction, and include a first semiconductor element provided at one end of the series connection and a second semiconductor element provided at the other end. The insulating member has a first surface facing the first semiconductor element and a second surface facing the second semiconductor element when the plurality of semiconductor elements are arranged in the first direction, and the first surface and the second surface intersect with the first direction. The first terminal is electrically connected to the first electrode of the first semiconductor element. The second terminal is electrically connected to the second electrode of the second semiconductor element and is provided on one of the first surface side and the second surface side of the insulating member. The plurality of control terminals are electrically connected to the control electrodes of the plurality of semiconductor elements, are provided separately from each other on one of the first surface side and the second surface side of the insulating member, and are separated from the second terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a schematic cross-sectional view showing the semiconductor device according to the first embodiment.

[0007] Figure 2A and Figure 2B It is a schematic diagram showing a semiconductor element according to the first embodiment.

[0008] Figure 3A to Figure 3C It is a schematic diagram showing a semiconductor device according to the first embodiment.

[0009] Figure 4A and Figure 4B This is a schematic diagram showing a semiconductor device according to a first modification example of the first embodiment.

[0010] Figure 5A to Figure 8B It is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a first modification example of the first embodiment.

[0011] FIG. 9A to FIG. 9D It is a schematic diagram showing wiring of the semiconductor device according to the first embodiment.

[0012] Fig.10 It is a schematic cross-sectional view showing a semiconductor device according to a second modification example of the first embodiment.

[0013] Figures 11A to 14B It is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a second modification example of the first embodiment.

[0014] Figures 15A to 15C It is a schematic diagram showing a semiconductor device according to the second embodiment.

[0015] Fig.16A and Fig. 16B This is another schematic diagram showing the semiconductor device according to the second embodiment.

[0016] Figures 17A to 17C This is a schematic diagram showing a semiconductor device according to a first modification example of the second embodiment.

[0017] Fig.18 This is another schematic diagram showing the semiconductor device according to the first modification example of the second embodiment.

[0018] Figures 19A to 19C This is a schematic diagram showing a semiconductor device according to a second modification example of the second embodiment.

[0019] Figure 20A to Figure 20C This is a schematic diagram showing a semiconductor device according to a third modified example of the second embodiment. DETAILED DESCRIPTION

[0020] Below, while referring to the attached Figure 1The embodiments are described while the same reference numerals are assigned to the same parts in the figures and their detailed description is appropriately omitted, and the different parts are described. In addition, the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. are not necessarily the same as the actual parts. In addition, even when the same parts are shown, the sizes or ratios of each other may be shown differently according to the drawings.

[0021] Furthermore, the configuration and structure of each part are described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X direction, Y direction, and Z direction, respectively. In addition, there is a case where the Z direction is set as the upper direction and the opposite direction is set as the lower direction for description.

[0022] (First embodiment)

[0023] Figure 1 It is a schematic cross-sectional view showing the semiconductor device 1 according to the first embodiment.

[0024] Figure 2A and Figure 2B It is a schematic diagram showing the semiconductor element Tr according to the first embodiment.

[0025] like Figure 1 As shown, the semiconductor device 1 includes a plurality of semiconductor elements Tr1 to Tr4, an insulating member IM, a first terminal DT, a second terminal ST, and a control terminal GT1. The semiconductor element Tr is, for example, a MOS transistor. In the following, the semiconductor elements Tr1 to Tr4 are sometimes described as semiconductor elements Tr.

[0026] like Figure 2A and Figure 2B As shown, the semiconductor element Tr includes a semiconductor portion SP, a first electrode DE, a second electrode SE, a control electrode GE, a control wire GW, and a control pad GP.

[0027] The semiconductor portion SP is, for example, silicon. The semiconductor portion SP has, for example, a back surface BS and a front surface FS. The first electrode DE is, for example, a drain electrode, and is provided on the back surface BS of the semiconductor portion SP. The second electrode SE is, for example, a source electrode, and is provided on the front surface FS of the semiconductor portion SP. The first electrode DE and the second electrode SE are, for example, metal layers containing copper.

[0028] The semiconductor portion SP has a trench TR provided on the surface FS side, and the control electrode GE is provided, for example, inside the trench TR. The control electrode GE is, for example, a gate electrode, and controls the current flowing between the first electrode DE and the second electrode SE. The control electrode GE is, for example, polysilicon having conductivity. The control electrode GE is provided between the semiconductor portion SP and the second electrode SE. The control electrode GE is electrically insulated from the semiconductor portion SP by, for example, a gate insulating film 21. In addition, the control electrode GE is electrically insulated from the second electrode SE by, for example, an interlayer insulating film 23.

[0029] The semiconductor portion SP includes, for example, a first conductivity type first semiconductor layer 11, a second conductivity type second semiconductor layer 13, a first conductivity type third semiconductor layer 15, and a second conductivity type fourth semiconductor layer 17. For example, the first conductivity type is n type, and the second conductivity type is p type.

[0030] The first semiconductor layer 11 is, for example, an n-type drift layer. The first semiconductor layer 11 extends between the first electrode DE and the second electrode SE. The trench TR has, for example, a depth from the surface FS of the semiconductor portion SP to the first semiconductor layer 11. The control electrode GE faces the first semiconductor layer 11, for example, via the gate insulating film 21.

[0031] The second semiconductor layer 13 is, for example, a p-type diffusion layer. The second semiconductor layer 13 is provided between the first semiconductor layer 11 and the second electrode SE. A plurality of control electrodes GE are provided in the semiconductor portion SP, and the second semiconductor layer 13 is provided between adjacent control electrodes GE. The second semiconductor layer 13 faces the control electrode GE, for example, via the gate insulating film 21 .

[0032] The third semiconductor layer 15 is, for example, an n-type source layer. The third semiconductor layer 15 is provided between the second semiconductor layer 13 and the second electrode SE. The second semiconductor layer 13 and the second electrode SE are electrically connected.

[0033] The fourth semiconductor layer 17 is, for example, a p-type contact layer and is provided, for example, between the second semiconductor layer 13 and the second electrode SE. The fourth semiconductor layer 17 contains the second conductivity type impurity at a higher concentration than the second conductivity type impurity in the second semiconductor layer 13 .

[0034] The semiconductor portion SP has a contact trench CT provided between adjacent control electrodes GE, and the second electrode SE has a portion extending into the inside of the contact trench CT. The second electrode SE is electrically connected to the third semiconductor layer 15 and the fourth semiconductor layer 17 exposed in the inside of the contact trench CT. The second semiconductor layer 13 is electrically connected to the second electrode SE via the fourth semiconductor layer 17.

[0035] The control wiring GW and the control pad GP are provided on the surface FS of the semiconductor portion SP. The control wiring GW and the control pad GP are electrically insulated from the semiconductor portion SP by, for example, a passivation film 25 covering the surface FS of the semiconductor portion SP. The control wiring GW and the control pad GP are provided separately from the second electrode SE. The control wiring GW and the control pad GP are, for example, a metal layer containing copper.

[0036] like Figure 2B As shown in FIG. 1 , the control wire GW is electrically connected to the control electrode GE. The control wire GW is connected to the control pad GP, and the control pad GP is electrically connected to the control electrode GE via the control wire GW.

[0037] like Figure 1 As shown, the plurality of semiconductor elements Tr1 to Tr4 are arranged in the first direction (Z direction) from the first electrode DE toward the second electrode SE, for example. The plurality of semiconductor elements Tr1 to Tr4 electrically connect the second electrode SE on one side to the first electrode DE on the other side between adjacent semiconductor elements Tr. The plurality of semiconductor elements Tr1 to Tr4 are connected in series.

[0038] The second electrode SE1 of the semiconductor element Tr1 is electrically connected to the first electrode DE2 of the semiconductor element Tr2 via, for example, the intermediate wiring MI1 .

[0039] The second electrode SE2 of the semiconductor element Tr2 is electrically connected to the first electrode DE3 of the semiconductor element Tr3 via, for example, the intermediate wiring MI2 .

[0040] The second electrode SE3 of the semiconductor element Tr3 is electrically connected to the first electrode DE4 of the semiconductor element Tr4 via, for example, the intermediate wiring MI3 .

[0041] The semiconductor device 1 further includes control terminals GT2 to GT4 and control wirings GI1 to GI4 (see Figure 3A to Figure 3C ).

[0042] The semiconductor element Tr1 is located at one end of the series connection of the semiconductor elements Tr1 to Tr4. The first electrode DE1 of the semiconductor element Tr1 is electrically connected to the first terminal DT. The first terminal DT is, for example, a drain terminal of the semiconductor device 1.

[0043] The semiconductor element Tr4 is located at the other end of the series connection of the semiconductor elements Tr1 to Tr4. The second electrode SE4 of the semiconductor element Tr4 is electrically connected to the second terminal ST, for example, via the intermediate wiring MI4. The second terminal ST is, for example, a source terminal of the semiconductor device 1.

[0044] The semiconductor elements Tr1 to Tr4 are sealed in an insulating member IM, for example. The insulating member IM contains, for example, epoxy resin. The insulating member IM includes, for example, a first surface S1 and a second surface S2 that intersect the Z direction. The first surface S1 is located on the opposite side of the second surface S2, and the first terminal DT is, for example, provided on the first surface S1. The second terminal ST and the control terminal GT1 are, for example, provided separately from each other on the second surface S2.

[0045] A plurality of control wirings GI1 to GI4 are provided in the insulating member IM. The control wirings GI1 to GI4 are electrically connected to the control pads GP1 to GP4 of the semiconductor elements Tr1 to Tr4, respectively.

[0046] The control wiring GI1 is electrically connected to the control pad GP1 of the semiconductor element Tr1 and to the control terminal GT1 via the contact plug GL1.

[0047] Figure 3A to Figure 3C It is a schematic diagram showing the semiconductor device 1 according to the first embodiment.

[0048] Figure 3A It is a schematic plan view showing the second surface S2 of the insulating member IM.

[0049] Figure 3B It is along Figure 3A A cross-sectional view along line A-A shown in FIG.

[0050] in addition, Figure 1 It is along Figure 3A A cross-sectional view of the line BB shown in FIG.

[0051] Figure 3C It is a schematic plan view showing the first surface S1 of the insulating member IM.

[0052] like Figure 3A As shown, the second terminal ST and the plurality of control terminals GT1 to GT4 are provided on the second surface S2 of the insulating member IM. The second terminal ST is provided separately from the plurality of control terminals GT1 to GT4. The plurality of control terminals GT1 to GT4 are provided separately from each other.

[0053] like Figure 3B As shown, the control terminal GT1 is electrically connected to the control wiring GI1 via the contact plug GL1. The control terminal GT2 is electrically connected to the control wiring GI2 via the contact plug GL2. The control terminal GT3 is electrically connected to the control wiring GI3 via the contact plug GL3. The control terminal GT4 is electrically connected to the control wiring GI4 via the contact plug GL4.

[0054] like Figure 3C As shown, the first terminal DT is provided on the first surface S1 of the insulating member IM.

[0055] Figure 4A and Figure 4B It is a schematic diagram showing a semiconductor device 2 according to a first modification example of the first embodiment. Figure 4A It is a cross-sectional view showing the structure of the semiconductor device 2 . Figure 4B It is a schematic diagram showing the second surface S2 of the insulating member IM.

[0056] like Figure 4A As shown, the semiconductor device 2 includes a plurality of semiconductor elements Tr1 to Tr4 arranged in the Z direction. The semiconductor elements Tr1 to Tr4 are sealed in the insulating member IM and connected in series via intermediate wirings MI1 to MI3.

[0057] The semiconductor device 2 further includes an intermediate wiring MI0. The intermediate wiring MI0 is provided on the first surface S1 of the insulating member IM. The semiconductor element Tr1 is located at one end of the series connection of the semiconductor elements Tr1 to Tr4 and is electrically connected to the intermediate wiring MI0.

[0058] like Figure 4B As shown, the first terminal DT, the second terminal ST, and the plurality of control terminals GT1 to GT4 are provided on the second surface S2 of the insulating member IM.

[0059] The first terminal DT is electrically connected to the intermediate wiring MI0 via a contact plug DP extending into the insulating member IM (see Figure 4A ). The first terminal DT is electrically connected to the semiconductor element Tr1 via the contact plug DP and the intermediate wiring MI0.

[0060] The second terminal ST is electrically connected to the semiconductor element Tr4 via the intermediate wiring MI4. The semiconductor element Tr4 is located at the other end of the series connection of the plurality of semiconductor elements Tr1 to Tr4.

[0061] The plurality of control terminals GT1 to GT4 are electrically connected to the control pads GP1 to GP4 of the semiconductor elements Tr1 to Tr4 through the contact plugs GL1 to GL4 and the control wirings GI1 to GI4, respectively (see Figure 3B ).

[0062] Next, refer to Figure 5A to Figure 8B , a method for manufacturing the semiconductor device 2 according to the first modification example of the first embodiment is described. Figure 5A to Figure 8B 2 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device 2. The semiconductor device 1 is also manufactured through the same manufacturing process.

[0063] like Figure 5AAs shown, a first insulating member IM1 is prepared. The first insulating member IM1 has a front surface and a back surface intersecting the Z direction. The same is true for the second insulating member IM2 to the fourth insulating member IM4 and other components.

[0064] The first insulating member IM1 has a metal layer 31 provided on the back surface thereof. The first insulating member IM1 is, for example, a glass epoxy substrate. The metal layer 31 is, for example, a copper foil.

[0065] like Figure 5B As shown, after forming the recess 33 on the first insulating member IM1, the semiconductor element Tr1 is arranged inside the recess 33. The recess 33 is formed by, for example, laser processing. The recess 33 is formed deeper than the thickness of the semiconductor element Tr1. The semiconductor element Tr1 is arranged so that the first electrode DE1 is in contact with the bottom surface of the recess 33.

[0066] like Figure 5C As shown, after the inside of the recess 33 is filled with resin and the semiconductor element Tr1 is sealed, the surface of the first insulating member IM1 is flattened. The inside of the recess 33 is filled with, for example, epoxy resin. Then, a metal layer 35 is formed on the surface of the first insulating member IM1. The metal layer 35 is attached to the surface of the first insulating member IM1 via, for example, an adhesive layer (not shown). The metal layer 35 is, for example, copper foil.

[0067] like Figure 5D As shown in FIG. 1 , the metal layer 31 and the metal layer 35 are patterned into a predetermined shape on the back and the front of the first insulating member IM1. The metal layer 31 is patterned so as to include a portion facing the first electrode DE of the semiconductor element Tr1 via a portion of the first insulating member IM1. The metal layer 35 is patterned so as to include a portion facing the second electrode SE1 and the control pad GP1 of the semiconductor element Tr1 via another portion of the first insulating member IM1.

[0068] like Figure 5E As shown, on the back side of the first insulating member IM1, a plurality of contact holes DCH1 connected to the first electrode DE1 of the semiconductor element Tr1 are formed. The contact holes DCH1 are formed by selectively removing a portion of the metal layer 31 and the first insulating member IM1. In addition, on the front side of the first insulating member IM1, a plurality of contact holes SCH1 connected to the second electrode SE1 of the semiconductor element Tr1 and a contact hole GCH1 connected to the control pad GP1 are formed. The contact holes SCH1 and GCH1 are formed by selectively removing a portion of the metal layer 35 and the first insulating member IM1.

[0069] like Fig. 5FAs shown, on the back side of the first insulating member IM1, a contact metal 31a is formed so as to fill the inside of the contact hole DCH1. The contact metal 31a is formed, for example, by a copper plating method. Thus, an intermediate wiring MI0 is formed on the back side of the first insulating member IM1. The intermediate wiring MI0 is electrically connected to the first electrode DE1 of the semiconductor element Tr1 via the contact metal 31a.

[0070] Furthermore, contact metals 35a and 35b are formed on the surface side of the first insulating member IM1 to fill the inside of the contact holes SCH1 and GCH1. The contact metals 35a and 35b are formed, for example, by copper plating. Thus, the intermediate wiring MI1 and the control wiring GI1 are formed. The intermediate wiring MI1 is electrically connected to the second electrode SE1 of the semiconductor element Tr1 via the contact metal 35a. The control wiring GI1 is electrically connected to the control pad GP1 of the semiconductor element Tr1 via the contact metal 35b.

[0071] like Fig. 6A As shown, a first insulating layer IMa is formed on the surface of the first insulating member IM1. The first insulating layer IMa is formed so as to cover the intermediate wiring MI1 and the control wiring GI1. The first insulating layer IMa is, for example, a semi-cured resin layer, i.e., a so-called prepreg. The prepreg contains, for example, epoxy resin and glass fiber.

[0072] like Figure 6B As shown in FIG. 1 , a plurality of contact holes DCH2 are formed in the first insulating layer Ima. The contact holes DCH2 are formed so as to communicate with the intermediate wiring MI1.

[0073] like Figure 6C As shown in FIG. 1 , a contact metal 37 is formed to fill the inside of the contact hole DCH2. The contact metal 37 is formed by, for example, copper plating.

[0074] like Fig.6D As shown in FIG. 1 , a second insulating member IM2 is formed on the first insulating layer Ima. The second insulating member IM2 is, for example, a prepreg. The second insulating member IM2 has an opening 39. The opening 39 exposes, for example, the first insulating layer IMa and the contact metal 37.

[0075] like Fig. 7A As shown, the semiconductor element Tr2 is arranged inside the opening 39. The semiconductor element Tr2 is fixed to the surface of the first insulating layer IMa using, for example, a conductive adhesive. The semiconductor element Tr2 is arranged on the bottom surface of the opening 39 so as to electrically connect the first electrode DE2 and the contact metal 37.

[0076] like Figure 7BAs shown, the semiconductor element Tr2 is sealed in the opening 39. For example, epoxy resin is filled in the opening 39 so as to cover the semiconductor element Tr2. Next, after the surface of the second insulating member IM2 is flattened, a metal layer 41 is formed on the surface of the second insulating member IM2. The metal layer 41 is, for example, copper foil.

[0077] like Figure 7C As shown, a plurality of contact holes SCH2 and contact holes GCH2 are formed on the second insulating member IM2. The contact hole SCH2 is formed in a manner connected to the second electrode SE2 of the semiconductor element Tr2. The contact hole GCH2 is formed in a manner connected to the control pad GP2 of the semiconductor element Tr2. The contact holes SCH2 and GCH2 are formed by removing a portion of the metal layer 41 and a portion of the second insulating member IM2.

[0078] like Fig.7D As shown in FIG. 1 , a contact metal 41a is formed to fill the inside of the contact hole SCH2. In addition, a contact metal 41b is formed to fill the inside of the contact hole GCH2. The contact metals 41a and 41b are formed by, for example, copper plating.

[0079] The contact metal 41a is formed so as to be connected to the metal layer 41. The intermediate wiring MI2 includes the contact metal 41a and the metal layer 41. The intermediate wiring MI2 is electrically connected to the second electrode SE2 of the semiconductor element Tr2 via the contact metal 41a.

[0080] The contact metal 41b is formed so as to be connected to the other metal layers 41. The control wiring GI2 includes the contact metal 41b and the other metal layers 41. The control wiring GI2 is electrically connected to the control pad GP2 of the semiconductor element Tr2 via the contact metal 41b.

[0081] Then, by repeatedly Figures 6A to 7D In the manufacturing process shown, the third insulating member IM3 and the fourth insulating member IM4 are formed.

[0082] like Fig. 8A As shown, the third insulating member IM3 is provided on the second insulating member IM2, and the semiconductor element Tr3 is sealed therein. The fourth insulating member IM4 is provided on the third insulating member IM3, and the semiconductor element Tr4 is sealed therein.

[0083] A second insulating layer IMb is formed between the second insulating member IM2 and the third insulating member IM3. The second insulating layer IMb includes an intermediate wiring MI2 and a control wiring GI2. The intermediate wiring MI2 is formed so as to be electrically connected to the second electrode SE2 of the semiconductor element Tr2 and the first electrode DE3 of the semiconductor element Tr3. The control wiring GI2 is formed so as to be electrically connected to the control pad GP2 of the semiconductor element Tr2.

[0084] A third insulating layer IMc is formed between the third insulating member IM3 and the fourth insulating member IM4. The third insulating layer IMc includes an intermediate wiring MI3 and a control wiring GI3. The intermediate wiring MI3 is formed so as to be electrically connected to the second electrode SE3 of the semiconductor element Tr3 and the first electrode DE4 of the semiconductor element Tr4. The control wiring GI3 is formed so as to be electrically connected to the control pad GP3 of the semiconductor element Tr3.

[0085] A fourth insulating layer IMd is formed on the fourth insulating member IM4. The fourth insulating layer IMd is, for example, a prepreg. The fourth insulating layer IMd is formed so as to cover the intermediate wiring MI4 and the control wiring GI4. The intermediate wiring MI4 is electrically connected to the second electrode SE4 of the semiconductor element Tr4 via the contact metal 45a. The control wiring GI4 is electrically connected to the control pad GP4 of the semiconductor element Tr4 via the contact metal 45b.

[0086] The intermediate wirings MI3, MI4, and the control wirings GI3 and GI4 are manufactured through the same process as the intermediate wiring MI2 and the control wiring GI2 (see Figure 7A to Figure 7D ) is formed.

[0087] like Figure 8B As shown, the first terminal DT, the second terminal ST and the control terminals GT1 to GT4 (refer to Figure 4B ) is formed on the fourth insulating layer IMd. The first terminal DT, the second terminal ST and the control terminals GT1 to GT4 are formed, for example, by patterning the copper foil on the fourth insulating layer IMd. The second terminal ST is formed so as to be electrically connected to the intermediate wiring MI4 via the contact metal 47 extending into the fourth insulating layer IMd.

[0088] Next, a contact plug DP is formed in the insulating member IM, and the first terminal DT is electrically connected to the intermediate wiring MI0 (see Figure 4A ). Furthermore, contact plugs GL1 to GL4 are formed in the insulating member IM, and the control wirings GI1 to GI4 are electrically connected to the control terminals GT1 to GT4, respectively (see Figure 3B ). The insulating member IM is formed by, for example, curing and integrating the first insulating member IM1 to the fourth insulating member IM4 and the first insulating layer IMa to the fourth insulating layer IMd.

[0089] FIG. 9A to FIG. 9D It is a schematic diagram showing wiring of the semiconductor devices 1 and 2 according to the first embodiment. FIG. 9A to FIG. 9D It is a plan view showing the intermediate wirings MI1 to MI4 and the control wirings GI1 to GI4 provided on the first to fourth insulating members IM1 to IM4.

[0090] For example, the intermediate wirings MI1 to MI4 are connected to the second electrode SE ( Figure 2B In addition, the control wirings GI1 to GI4 are arranged so as to connect the control pads GP (see Figure 2B ) are connected to control terminals GT1~GT4.

[0091] Fig.10 1 is a schematic cross-sectional view showing a semiconductor device 3 according to a second modification of the first embodiment. The semiconductor device 3 includes semiconductor elements Tr1 to Tr4. The semiconductor elements Tr1 to Tr4 are connected in series and sealed inside the insulating member IM. The first terminal DT, the second terminal ST, and the control terminals GT1 to GT4 are provided on the second surface S2 of the insulating member IM.

[0092] The semiconductor element Tr1 is electrically connected to the semiconductor element Tr2 via the intermediate wiring MI1. In addition, the control pad GP1 of the semiconductor element Tr1 is electrically connected to the control wiring GI1. The intermediate wiring MI1 and the control wiring GI1 are provided in the first insulating layer IMa.

[0093] The intermediate wiring MI1 includes metal layers 51a, 53 and a conductive member 55a. The metal layer 51a is provided on the surface of the first insulating member IM1. The metal layer 53 is provided on the back surface of the second insulating member IM2. The metal layers 51a and 53 are connected via a conductive member 55a.

[0094] The conductive member 55a includes a portion penetrating the metal layer 51a and a portion of the first insulating member IM1 to be in contact with the second electrode SE1 of the semiconductor element Tr1. The intermediate wiring MI1 is electrically connected to the second electrode SE1 of the semiconductor element Tr1 via the conductive member 55a.

[0095] The conductive member 55a includes a portion penetrating the metal layer 53 and a portion of the second insulating member IM2 to be in contact with the first electrode DE2 of the semiconductor element Tr2. The intermediate wiring MI1 is electrically connected to the first electrode DE2 of the semiconductor element Tr2 via the conductive member 55a.

[0096] The control wiring GI1 includes a metal layer 51b and a conductive component 55b. The metal layer 51b is provided on the surface of the first insulating component IM1. The conductive component 55b is provided so as to cover the metal layer 51b. The conductive component 55b includes a portion that penetrates the metal layer 51b and another portion of the first insulating component IM1 and is in contact with the control pad GP1 of the semiconductor element Tr1. The control wiring GI1 is electrically connected to the control pad GP1 of the semiconductor element Tr1 via the conductive component 55b.

[0097] The semiconductor element Tr2 is electrically connected to the semiconductor element Tr3 via the intermediate wiring MI2. In addition, the control pad GP2 of the semiconductor element Tr2 is electrically connected to the control wiring GI2. The intermediate wiring MI2 and the control wiring GI2 are provided in the second insulating layer IMb.

[0098] The intermediate wiring MI2 includes metal layers 61a, 63 and a conductive member 65a. The metal layer 61a is provided on the surface of the second insulating member IM2. The metal layer 63 is provided on the back surface of the third insulating member IM3. The metal layers 61a and 63 are electrically connected via the conductive member 65a.

[0099] The conductive member 65a includes a portion penetrating the metal layer 61a and a portion of the second insulating member IM2 to be in contact with the second electrode SE2 of the semiconductor element Tr2. The intermediate wiring MI2 is electrically connected to the second electrode SE2 of the semiconductor element Tr2 via the conductive member 65a.

[0100] The conductive member 65a includes a portion penetrating the metal layer 63 and a portion of the third insulating member IM3 to be in contact with the first electrode DE3 of the semiconductor element Tr3. The intermediate wiring MI2 is electrically connected to the first electrode DE3 of the semiconductor element Tr3 via the conductive member 65a.

[0101] The control wiring GI2 includes a metal layer 61b and a conductive component 65b. The metal layer 61b is provided on the surface of the second insulating component IM2. The conductive component 65b is provided in a manner covering the metal layer 61b. The conductive component 65b includes a portion that penetrates the metal layer 61b and another portion of the second insulating component IM2 and is in contact with the control pad GP2 of the semiconductor element Tr2. The control wiring GI2 is electrically connected to the control pad GP2 of the semiconductor element Tr2 via the conductive component 65b.

[0102] The semiconductor element Tr3 is electrically connected to the semiconductor element Tr4 via the intermediate wiring MI3. In addition, the control pad GP3 of the semiconductor element Tr3 is electrically connected to the control wiring GI3. The intermediate wiring MI3 and the control wiring GI3 are provided in the third insulating layer IMc.

[0103] The intermediate wiring MI3 includes metal layers 71a and 73 and a conductive member 75a. The metal layer 71a is provided on the surface of the third insulating member IM3. The metal layer 73 is provided on the back surface of the fourth insulating member IM4. The metal layer 71a and the metal layer 73 are connected via the conductive member 75a.

[0104] The conductive member 75a includes a portion penetrating the metal layer 71a and a portion of the third insulating member IM3 to be in contact with the second electrode SE3 of the semiconductor element Tr3. The intermediate wiring MI3 is electrically connected to the second electrode SE3 of the semiconductor element Tr3 via the conductive member 75a.

[0105] The conductive member 75a includes a portion penetrating the metal layer 73 and a portion of the fourth insulating member IM4 to be in contact with the first electrode DE4 of the semiconductor element Tr4. The intermediate wiring MI3 is electrically connected to the first electrode DE4 of the semiconductor element Tr4 via the conductive member 75a.

[0106] The control wiring GI3 includes a metal layer 71b and a conductive component 75b. The metal layer 71b is provided on the surface of the third insulating component IM3. The conductive component 75b is provided in a manner covering the metal layer 71b. The conductive component 75b includes a portion that penetrates the metal layer 71b and another portion of the third insulating component IM3 and is in contact with the control pad GP3 of the semiconductor element Tr3. The control wiring GI3 is electrically connected to the control pad GP3 of the semiconductor element Tr3 via the conductive component 75b.

[0107] The semiconductor device 3 further includes an intermediate wiring MI0, an intermediate wiring MI4, and a control wiring GI4. The intermediate wiring MI0 is electrically connected to the semiconductor element Tr1, the intermediate wiring MI4 is electrically connected to the semiconductor element Tr4, and the control wiring GI4 is electrically connected to the control pad GP4 of the semiconductor element Tr4.

[0108] The intermediate wiring MI0 is provided on the first surface S1 of the insulating member IM. The intermediate wiring MI0 is connected to the first insulating member IM1 via a contact metal 31a (see Fig. 5F ) is electrically connected to the first electrode DE1 of the semiconductor element Tr1.

[0109] The intermediate wiring MI4 and the control wiring GI4 are provided on the surface of the fourth insulating member IM4. The intermediate wiring MI4 is connected to the fourth insulating member IM4 via a contact metal 45a (see Fig. 8A ) is electrically connected to the second electrode SE4 of the semiconductor element Tr4. The control wiring GI4 is connected to the fourth insulating member IM4 via a contact metal 45b (see Fig. 8A ) is electrically connected to the control pad GP4 of the semiconductor element Tr4.

[0110] The first terminal DT is electrically connected to the semiconductor element Tr1 via the contact plug DP and the intermediate wiring MI0 extending into the insulating member IM.

[0111] The second terminal ST is electrically connected to the intermediate wiring MI4 via a contact metal 47 extending into the fourth insulating layer IMd covering the intermediate wiring MI4.

[0112] Control terminals GT1 to GT4 (see Figure 3B ) are electrically connected to the control wirings GI1 to GI4 via the contact plugs GL1 to GL4 extending into the insulating member IM.

[0113] Next, refer to FIG. 11A to FIG. 11D , Figures 12A to 12C , Fig.13 , Fig.14A and Fig. 14B , a method for manufacturing the semiconductor device 3 is described. FIG. 11A to FIG. 11D , Figures 12A to 12C , Fig.13 , Fig.14A and Fig. 14B It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device 3.

[0114] like Fig.11A As shown in FIG. 1 , the semiconductor element Tr1 is arranged inside the first insulating member IM1. On the back surface of the first insulating member IM1, an intermediate wiring MI0 (see FIG. 1 ) is formed. Figure 5A to Figure 5F ). In addition, metal layers 51a and 51b are formed on the surface of the first insulating member IM1. The metal layers 51a and 51b are, for example, copper foils, and are attached to the first insulating member IM1 via an adhesive layer (not shown).

[0115] Furthermore, a contact hole SCH1 is formed to communicate from the surface of the metal layer 51a to the second electrode SE1 of the semiconductor element Tr1. Also, a contact hole GCH1 is formed to communicate from the surface of the metal layer 51b to the control pad GP1 of the semiconductor element Tr1.

[0116] like Fig. 11B As shown, the semiconductor element Tr2 is arranged inside the second insulating component IM2. Furthermore, metal layers 53, 61a and 61b are formed on the back surface and the surface of the second insulating component IM2. The metal layer 53 is formed on the back surface of the second insulating component IM2. In addition, the metal layer 61a and the metal layer 61b are formed on the surface of the second insulating component IM2. The metal layers 53, 61a and 61b are, for example, copper foils, and are attached to the second insulating component IM2 via an adhesive layer not shown.

[0117] Furthermore, a contact hole DCH2 is formed to connect to the first electrode DE2 of the semiconductor element Tr2 from the surface of the metal layer 53. In addition, a contact hole SCH2 is formed to connect to the second electrode SE2 of the semiconductor element Tr2 from the surface of the metal layer 61a. A contact hole GCH2 is formed to connect to the control pad GP2 of the semiconductor element Tr2 from the surface of the metal layer 61b.

[0118] like Fig. 11C As shown, the semiconductor element Tr3 is arranged inside the third insulating component IM3. Furthermore, metal layers 63, 71a and 71b are formed on the back surface and the surface of the third insulating component IM3. The metal layer 63 is formed on the back surface of the third insulating component IM3. In addition, the metal layers 71a and 71b are formed on the surface of the third insulating component IM3. The metal layers 63, 71a and 71b are, for example, copper foils and are attached to the third insulating component IM3 via an adhesive layer not shown.

[0119] Furthermore, a contact hole DCH3 is formed to connect to the first electrode DE3 of the semiconductor element Tr3 from the back surface of the metal layer 63. In addition, a contact hole SCH3 is formed to connect to the second electrode SE3 of the semiconductor element Tr3 from the surface of the metal layer 71a. A contact hole GCH3 is formed to connect to the control pad GP3 of the semiconductor element Tr3 from the surface of the metal layer 71b.

[0120] like Fig.11D As shown in FIG. 1 , the semiconductor element Tr4 is arranged inside the fourth insulating member IM4. Furthermore, a metal layer 73, an intermediate wiring MI4, and a control wiring GI4 are formed on the back surface and the surface of the fourth insulating member IM4. The metal layer 73 is formed on the back surface of the fourth insulating member IM4. The intermediate wiring MI4 and the control wiring GI4 are formed on the surface of the third insulating member IM3 (see FIG. 1 ). Figure 5D to Figure 5F ).

[0121] The metal layer 73 is, for example, a copper foil, and is bonded to the fourth insulating member IM4 via an adhesive layer (not shown). Furthermore, a contact hole DCH4 is formed from the lower surface of the metal layer 73 to communicate with the first electrode DE4 of the semiconductor element Tr4.

[0122] The intermediate wiring MI4 is connected to the contact metal 45a (see Fig. 8A ) is electrically connected to the second electrode SE4 of the semiconductor element Tr4. In addition, the control wiring GI4 is connected to the second electrode SE4 of the semiconductor element Tr4 via the contact metal 45b (see Fig. 8A ) is electrically connected to the control pad GP4 of the semiconductor element Tr4.

[0123] like Fig. 12AAs shown, a first insulating layer IMa is formed on the surface of the first insulating member IM1. The first insulating layer IMa is, for example, a prepreg, and has an opening 57a and an opening 57b. The metal layer 51a and the contact hole SCH1 are exposed at the opening 57a. In addition, the metal layer 51b and the contact hole GCH1 are exposed at the opening 57b.

[0124] like Fig. 12B As shown, a second insulating layer IMb is formed on the surface of the second insulating member IM2. The second insulating layer IMb is, for example, a prepreg, and has an opening 67a and an opening 67b. The metal layer 61a and the contact hole SCH2 are exposed at the opening 67a. In addition, the metal layer 61b and the contact hole GCH2 are exposed at the opening 67b.

[0125] like Fig. 12C As shown, a third insulating layer IMc is formed on the surface of the third insulating member IM3. The third insulating layer IMc is, for example, a prepreg, and has an opening 77a and an opening 77b. The metal layer 71a and the contact hole SCH3 are exposed at the opening 77a. In addition, the metal layer 71b and the contact hole GCH3 are exposed at the opening 77b.

[0126] like Fig.13 As shown in FIG. 1 , the openings 57a and 57b of the first insulating layer IMa are filled with conductive components 55a and 55b, respectively. Similarly, the openings 67a and 67b of the second insulating layer IMb are filled with conductive components 65a and 65b, respectively. Furthermore, the openings 77a and 77b of the third insulating layer IMc are filled with conductive components 75a and 75b, respectively. Each conductive component is, for example, a conductive resin containing a conductive paste or metal particles.

[0127] The conductive member 55a is filled in the contact hole SCH1 and is in contact with the second electrode SE1 of the semiconductor element Tr1. In addition, the conductive member 55b is filled in the contact hole GCH1 and is in contact with the control pad GP1 of the semiconductor element Tr1 (see Fig. 12A ).

[0128] The conductive member 65a is filled in the contact hole SCH2 and is in contact with the second electrode SE2 of the semiconductor element Tr2. In addition, the conductive member 65b is filled in the contact hole GCH2 and is in contact with the control pad GP2 of the semiconductor element Tr2 (see Fig. 12B ).

[0129] The conductive member 75a is filled in the contact hole SCH3 and is in contact with the second electrode SE3 of the semiconductor element Tr3. In addition, the conductive member 75b is filled in the contact hole GCH3 and is in contact with the control pad GP3 of the semiconductor element Tr3 (see Fig. 12C ).

[0130] Next, the first insulating member IM1 to the fourth insulating member IM4 are arranged, for example, in the Z direction. The first insulating layer Ima faces the back surface of the second insulating member IM2. The second insulating layer IMb faces the back surface of the third insulating member IM3. The third insulating layer IMc faces the back surface of the fourth insulating member IM4.

[0131] like Fig.14A As shown, the first insulating component IM1 to the fourth insulating component IM4 are bonded with the first insulating layer IMa to the third insulating layer IMc sandwiched therebetween. The first insulating layer IMa to the third insulating layer IMc contain, for example, a thermosetting resin, and the first insulating component IM1 to the fourth insulating component IM4 are bonded and hardened, for example, by applying pressure in the up-down direction at a high temperature.

[0132] An intermediate wiring MI1 and a control wiring GI1 are formed between the first insulating member IM1 and the second insulating member IM2. The intermediate wiring MI1 includes a metal layer 51a, a metal layer 53, and a conductive member 55a. The conductive member 55a extends to the contact hole DCH2 (see Fig.13 ) is connected to the first electrode DE2 of the second semiconductor element Tr2. The control wiring GI1 includes a metal layer 51b and a conductive member 55b.

[0133] The intermediate wiring MI1 is formed to electrically connect the second electrode SE1 of the semiconductor element Tr1 and the first electrode DE2 of the semiconductor element Tr2 via the conductive member 55a. The control wiring GI1 is electrically connected to the control pad GP1 of the semiconductor element Tr1 via the conductive member 55b.

[0134] The intermediate wiring MI2 and the control wiring GI2 are formed between the second insulating member IM2 and the third insulating member IM3. The intermediate wiring MI2 includes a metal layer 61a, a metal layer 63, and a conductive member 65a. The conductive member 65a extends to the contact hole DCH3 (see Fig.13 ) is connected to the first electrode DE3 of the third semiconductor element Tr3. The control wiring GI2 includes a metal layer 61b and a conductive member 65b.

[0135] The intermediate wiring MI2 is formed to electrically connect the second electrode SE2 of the semiconductor element Tr2 and the first electrode DE3 of the semiconductor element Tr3 via the conductive member 65a. The control wiring GI2 is electrically connected to the control pad GP2 of the semiconductor element Tr2 via the conductive member 55b.

[0136] An intermediate wiring MI3 and a control wiring GI3 are formed between the third insulating member IM3 and the fourth insulating member IM4. The intermediate wiring MI3 includes a metal layer 71a, a metal layer 73, and a conductive member 75a. The conductive member 75a extends to the contact hole DCH4 (see Fig.13 ) is connected to the first electrode DE4 of the fourth semiconductor element Tr4. The control wiring GI3 includes a metal layer 71b and a conductive member 75b.

[0137] The intermediate wiring MI3 is formed to electrically connect the second electrode SE3 of the semiconductor element Tr3 and the first electrode DE4 of the semiconductor element Tr4 via the conductive member 75a. The control wiring GI3 is electrically connected to the control pad GP3 of the semiconductor element Tr3 via the conductive member 75b.

[0138] like Fig. 14B As shown, after forming the fourth insulating layer IMd on the surface of the fourth insulating member IM4, the first terminal DT, the second terminal ST and the control terminals GT1 to GT4 are formed on the surface of the fourth insulating layer IMd (see Figure 4B The second terminal ST is connected to the fourth insulating layer IMd via a contact metal 47 (see Figure 8B ) is electrically connected to the intermediate wiring MI4.

[0139] Next, a contact plug DP is formed in the insulating member IM, and the first terminal DT is electrically connected to the intermediate wiring MI0 (see Figure 4A ). Furthermore, contact plugs GL1 to GL4 are formed in the insulating member IM to electrically connect the control wirings GI1 to GI4 to the control terminals GT1 to GT4, respectively (see Figure 3B ). The insulating member IM includes, for example, first to fourth insulating members IM1 to IM4 and first to fourth insulating layers IMa to IMd.

[0140] As shown in the above-mentioned embodiment, the semiconductor elements Tr1 to Tr4 are arranged in a row in the direction (Z direction) from the first surface S1 of the insulating member IM toward the second surface S2, and are connected in series. Thus, semiconductor devices 1 to 3 with high withstand voltage can be realized. In addition, the semiconductor devices 1 to 3 are mounted with the first surface S1 facing the circuit substrate. Thus, the mounting area of ​​the semiconductor devices 1 to 3 can be reduced.

[0141] Furthermore, it is preferable that the capacitance between the first electrode DE and the second electrode SE of the semiconductor elements Tr1 to Tr4 is substantially the same. For example, the first semiconductor layer 11 and the second semiconductor layer 13 are configured to have a pn junction (see Figure 2A ) is substantially the same in each semiconductor element Tr. Thus, voltage is uniformly applied to the semiconductor elements Tr1 to Tr4 connected in series, and the withstand voltage of the semiconductor devices 1 to 3 can be improved.

[0142] (Second embodiment)

[0143] Figures 15A to 15C , Fig.16Aand Fig. 16B It is a schematic diagram showing a semiconductor device 4 according to the second embodiment. Fig.15A and Fig. 15C It is a plan view showing the structure of the semiconductor device 4 . Fig.16A It is a plan view showing the back surface of the semiconductor device 4 . Fig. 15B It is along Fig.15A A cross-sectional view along line EE shown in FIG. Fig. 16B It is along Fig.16A A cross-sectional view taken along line F-F as shown in FIG.

[0144] Figures 15A to 15C As shown, the semiconductor device 4 includes semiconductor elements Tr1, Tr2, a first terminal DT, a second terminal ST, control terminals GT1, GT2, and an insulating resin member RM1. The first terminal DT, the second terminal ST, and the control terminals GT1, GT2 are metal plates containing copper, for example, and are so-called conductors.

[0145] The semiconductor elements Tr1 and Tr2 are stacked on the first terminal DT. The first terminal DT and the first electrode DE1 (see Figure 2A )Electrical connection.

[0146] like Fig.15A As shown, the second terminal ST is electrically connected to the second electrode SE2 of the semiconductor element Tr2, for example, through a metal wire SW. The control terminal GT1 is electrically connected to the control pad GP1 of the semiconductor element Tr1, for example, through a metal wire CW1. The control terminal GT2 is electrically connected to the control pad GP2 of the semiconductor element Tr2, for example, through a metal wire CW2.

[0147] like Fig. 15B As shown, the semiconductor elements Tr1 and Tr2 are sealed on the first terminal DT by a resin member RM. The resin member RM is, for example, epoxy resin. The semiconductor element Tr1 is bonded to the first terminal DT via a conductive bonding material (not shown) such as a solder material. In addition, the semiconductor element Tr2 is connected to the semiconductor element Tr1 via another conductive bonding material (not shown).

[0148] like Fig. 15C As shown in FIG. 1 , the semiconductor element Tr2 is stacked on the second electrode SE1 of the semiconductor element Tr1. The first electrode DE2 (see FIG. 1 ) of the semiconductor element Tr2 Figure 2A ) is electrically connected to the second electrode SE1 of the semiconductor element Tr1. That is, the semiconductor elements Tr1 and Tr2 are connected in series.

[0149] In the state of being stacked on the first terminal DT, the second electrode SE1 and the control pad GP1 of the semiconductor element Tr1 are arranged in the X direction. On the other hand, the second electrode SE2 and the control pad GP2 of the semiconductor element Tr2 are arranged in the -Y direction (the opposite direction of the Y direction). In this way, by arranging the semiconductor element Tr1 and the semiconductor element Tr2 in the orthogonal direction, it is possible to stack in a manner that the semiconductor element Tr2 does not cover the control pad GP1 of the semiconductor element Tr1. Thus, the control pad GP1 of the semiconductor element Tr1 and the control pad GP2 of the semiconductor element Tr2 can be electrically connected to the control terminal GT1 and the control terminal GT2 via the metal wires CW1 and CW2, respectively.

[0150] like Fig.16A As shown, the semiconductor device 4 is configured such that the first terminal DT, the second terminal ST and the control terminals GT1 and GT2 are exposed on the back surface. Thus, the semiconductor elements Tr1 and Tr2 are electrically connected to the circuit board via solder, for example, and the mounting area of ​​the semiconductor device 4 can be reduced.

[0151] like Fig. 16B As shown in FIG. 1 , a resin member RM2 may be filled in the space between the first terminal DT and the semiconductor element Tr2. The resin member RM2 is provided below the control pad GP2 before the metal wire CW2 is bonded to the control pad GP2 of the semiconductor element Tr2. Thus, the strength of the portion of the semiconductor element Tr2 where the control pad GP2 is provided can be improved, and damage or cracks of the semiconductor element Tr2 caused by the load when the metal wire CW2 is bonded to the control pad GP2 can be prevented.

[0152] Figures 17A to 17C and Fig.18 It is a schematic diagram showing a semiconductor device 5 according to a first modification example of the second embodiment.

[0153] like Figures 17A to 17C As shown in FIG. 1 , the semiconductor device 5 includes semiconductor elements Tr1 to Tr4, a first terminal DT, a second terminal ST, control terminals GT1 to GT4, and resin members RM1 to RM4. The semiconductor elements Tr1 to Tr4 are sequentially stacked on the first terminal DT. The first terminal DT and the first electrode DE1 (see FIG. 1 ) of the semiconductor element Tr1 Figure 2A )Electrical connection.

[0154] like Fig.17AAs shown, the second terminal ST is electrically connected to the second electrode SE4 of the semiconductor element Tr4, for example, through the metal wire SW. The control terminal GT1 is electrically connected to the control pad GP1 of the semiconductor element Tr1, for example, through the metal wire CW1. The control terminal GT2 is electrically connected to the control pad GP2 of the semiconductor element Tr2, for example, through the metal wire CW2. The control terminal GT3 is electrically connected to the control pad GP3 of the semiconductor element Tr3, for example, through the metal wire CW3. The control terminal GT4 is electrically connected to the control pad GP4 of the semiconductor element Tr4, for example, through the metal wire CW4.

[0155] The semiconductor element Tr2 is stacked on the second electrode SE1 of the semiconductor element Tr1 (see Fig. 15C ). The first electrode DE2 of the semiconductor element Tr2 is electrically connected to the second electrode SE1 of the semiconductor element Tr1. That is, the semiconductor elements Tr1 and Tr2 are connected in series. Similarly, the first electrode DE3 of the semiconductor element Tr3 is electrically connected to the second electrode SE2 of the semiconductor element Tr2, and the semiconductor elements Tr2 and Tr3 are connected in series. The first electrode DE4 of the semiconductor element Tr4 is electrically connected to the second electrode SE3 of the semiconductor element Tr3, and the semiconductor elements Tr3 and Tr4 are connected in series.

[0156] In a state of being stacked on the first terminal DT, the second electrode SE1 of the semiconductor element Tr1 and the control pad GP1 are arranged in the X direction (see Fig. 15C The second electrode SE2 of the semiconductor element Tr2 and the control pad GP2 are arranged in the -Y direction (refer to Fig.15A ). The second electrode SE3 and the control pad GP3 of the semiconductor element Tr3 are arranged in the -X direction (the opposite direction to the X direction). The second electrode SE4 and the control pad GP4 of the semiconductor element Tr4 are arranged in the Y direction.

[0157] By arranging the semiconductor elements Tr1 to Tr4 alternately in the orthogonal direction, the semiconductor elements Tr1 to Tr4 are arranged so as not to cover the control pads GP1 to GP4 . Thus, the metal wires CW1 to CW4 can be connected to the control pads GP1 to GP4 , respectively.

[0158] like Fig. 17B As shown, the semiconductor elements Tr1 to Tr4 are sealed on the first terminal DT by the resin member RM. The semiconductor element Tr1 is bonded to the first terminal DT via a conductive bonding material (not shown), for example. In addition, the semiconductor elements Tr1 to Tr4 are electrically connected to the adjacent semiconductor element Tr via other conductive bonding materials (not shown).

[0159] In addition, you can Fig. 17B and Fig. 17CAs shown in FIG. 1 , the space between the first terminal DT and the semiconductor element Tr2 is filled with a resin member RM2. The resin member RM2 is provided below the control pad GP2 of the semiconductor element Tr2. Furthermore, resin members RM3 and RM4 may be provided in the space between the first terminal DT and the semiconductor elements Tr3 and Tr4, respectively. Thus, it is possible to prevent the semiconductor elements Tr2 to Tr4 from being damaged or cracked due to the load when the metal wires CW2 to CW4 are connected to the control pads GP2 to GP4, respectively.

[0160] like Fig.18 As shown, the semiconductor device 5 is configured such that the first terminal DT, the second terminal ST, and the control terminals GT1 to GT4 are exposed on the back surface. Thus, the semiconductor elements Tr1 to Tr4 are electrically connected to the circuit board via solder, for example, and the mounting area of ​​the semiconductor device 5 can be reduced.

[0161] Figures 19A to 19C It is a schematic diagram showing a semiconductor device 6 according to a second modification example of the second embodiment.

[0162] like Fig.19A and Fig.19B As shown, the semiconductor device 6 includes semiconductor elements Tr1 to Tr4, a first terminal DT, a second terminal ST, control terminals GT1 to GT4, and a resin member RM1. The semiconductor elements Tr1 to Tr4 are sequentially stacked on the first terminal DT. The first terminal DT and the first electrode DE1 of the semiconductor element Tr1 (see Figure 2A )Electrical connection.

[0163] like Fig.19A As shown, the second terminal ST is electrically connected to the second electrode SE4 of the semiconductor element Tr4 through, for example, a metal connector SC. The metal connector SC is, for example, a metal plate made of copper, and is connected to the second electrode SE4 and the second terminal ST via a conductive bonding member.

[0164] The control terminal GT1 is electrically connected to the control pad GP1 of the semiconductor element Tr1, for example, through a metal wire CW1. The control terminal GT2 is electrically connected to the control pad GP2 of the semiconductor element Tr2, for example, through a metal wire CW2. The control terminal GT3 is electrically connected to the control pad GP3 of the semiconductor element Tr3, for example, through a metal wire CW3. The control terminal GT4 is electrically connected to the control pad GP4 of the semiconductor element Tr4, for example, through a metal wire CW4.

[0165] The semiconductor element Tr2 is stacked on the second electrode SE1 of the semiconductor element Tr1. The first electrode DE2 of the semiconductor element Tr2 is electrically connected to the second electrode SE1 of the semiconductor element Tr1, and the semiconductor elements Tr1 and Tr2 are connected in series. Similarly, the first electrode DE3 of the semiconductor element Tr3 is electrically connected to the second electrode SE2 of the semiconductor element Tr2, and the semiconductor elements Tr2 and Tr3 are connected in series. The first electrode DE4 of the semiconductor element Tr4 is electrically connected to the second electrode SE3 of the semiconductor element Tr3, and the semiconductor elements Tr3 and Tr4 are connected in series.

[0166] The chip size of the semiconductor element Tr2 is smaller than the chip size of the semiconductor element Tr1, and the semiconductor element Tr2 is stacked on the semiconductor element Tr1 in such a manner that the control pad GP1 of the semiconductor element Tr1 is exposed. Similarly, the chip size of the semiconductor element Tr3 is smaller than the chip size of the semiconductor element Tr2, and the semiconductor element Tr3 is stacked on the semiconductor element Tr2 in such a manner that the control pad GP2 of the semiconductor element Tr2 is exposed. In addition, the chip size of the semiconductor element Tr4 is smaller than the chip size of the semiconductor element Tr3, and the semiconductor element Tr4 is stacked on the semiconductor element Tr3 in such a manner that the control pad GP3 of the semiconductor element Tr3 is exposed.

[0167] like Fig.19B As shown, the semiconductor elements Tr1 to Tr4 are sealed on the first terminal DT by a resin member RM. The semiconductor element Tr1 is bonded to the first terminal DT by, for example, a conductive bonding material (not shown). In addition, the semiconductor elements Tr1 to Tr4 are electrically connected to adjacent semiconductor elements Tr via different conductive bonding materials (not shown).

[0168] like Fig.19C As shown, the semiconductor device 6 is configured such that the first terminal DT, the second terminal ST, and the control terminals GT1 to GT4 are exposed on the back surface. Thus, the semiconductor elements Tr1 to Tr4 are electrically connected to the circuit board via solder, for example, and the mounting area of ​​the semiconductor device 6 can be reduced.

[0169] Figure 20A to Figure 20C It is a schematic diagram showing a semiconductor device 7 according to a third modification example of the second embodiment.

[0170] like Figure 20A to Figure 20C As shown, the semiconductor device 7 includes semiconductor elements Tr1 to Tr4, a first terminal DT, a second terminal ST, control terminals GT1 to GT4, and a resin member RM1. The semiconductor elements Tr1 to Tr4 are sequentially stacked on the first terminal DT. The first terminal DT and the first electrode DE1 of the semiconductor element Tr1 (see Figure 2A )Electrical connection.

[0171] like Fig. 20A As shown, the second terminal ST is electrically connected to the second electrode SE4 of the semiconductor element Tr4, for example, through a metal connector SC. The control terminal GT1 is electrically connected to the control pad GP1, for example, through a metal wire CW1. The control terminal GT2 is electrically connected to the control pad GP2, for example, through a metal wire CW2. The control terminal GT3 is electrically connected to the control pad GP3, for example, through a metal wire CW3. The control terminal GT4 is electrically connected to the control pad GP4, for example, through a metal wire CW4. In this example, the control pads GP1 to GP3 are, for example, provided on the surface of the semiconductor element Tr4.

[0172] like Fig. 20B As shown, the semiconductor elements Tr1 to Tr4 are sealed on the first terminal DT by the resin member RM1. The semiconductor element Tr1 is bonded to the first terminal DT by, for example, a conductive bonding material (not shown). In addition, the semiconductor elements Tr1 to Tr4 are electrically connected to the adjacent semiconductor element Tr via different conductive bonding materials (not shown).

[0173] The first electrode DE2 of the semiconductor element Tr2 is electrically connected to the second electrode SE1 of the semiconductor element Tr1, and the semiconductor elements Tr1 and Tr2 are connected in series. Similarly, the first electrode DE3 of the semiconductor element Tr3 is electrically connected to the second electrode SE2 of the semiconductor element Tr2, and the semiconductor elements Tr2 and Tr3 are connected in series. The first electrode DE4 of the semiconductor element Tr4 is electrically connected to the second electrode SE3 of the semiconductor element Tr3, and the semiconductor elements Tr3 and Tr4 are connected in series.

[0174] like Fig. 20C As shown, the control pad GP1 is electrically connected to the control wiring GW1 of the semiconductor element Tr1 via the contact plug CP1. The contact plug CP1 is provided to connect from the surface of the semiconductor element Tr4 to the control wiring GW1 of the semiconductor element Tr1. The contact plug CP1 is electrically insulated from the semiconductor elements Tr2 to Tr4 by the insulating film 27a.

[0175] The control pad GP2 is electrically connected to the control wiring GW2 of the semiconductor element Tr2 via the contact plug CP2. The contact plug CP2 is provided so as to communicate from the surface of the semiconductor element Tr4 to the control wiring GW2 of the semiconductor element Tr2. The contact plug CP2 is electrically insulated from the semiconductor elements Tr3 and Tr4 by the insulating film 27b.

[0176] The control pad GP3 is electrically connected to the control wiring GW3 of the semiconductor element Tr3 via the contact plug CP3. The contact plug CP3 is provided so as to communicate from the surface of the semiconductor element Tr4 to the control wiring GW3 of the semiconductor element Tr3. In addition, the contact plug CP3 is electrically insulated from the semiconductor element Tr4 by the insulating film 27c.

[0177] In the semiconductor device 7, the first terminal DT, the second terminal ST, and the control terminals GT1 to GT4 are configured to be exposed on the back surface thereof (see Fig.18 ) Thus, the semiconductor elements Tr1 to Tr4 are electrically connected to the circuit board via, for example, a solder material, and the mounting area of ​​the semiconductor device 7 can be reduced.

[0178] In the present embodiment, it is also preferable that the capacitance between the first electrode DE and the second electrode SE of the semiconductor elements Tr1 to Tr4 is substantially the same. Thus, voltage is uniformly applied to the semiconductor elements Tr1 to Tr4 connected in series, and the withstand voltage of the semiconductor devices 1 to 3 can be improved.

[0179] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device, characterized in that: have: A plurality of semiconductor elements, each including a semiconductor portion, a first electrode provided on the back surface of the semiconductor portion, a second electrode provided on the surface of the semiconductor portion opposite to the back surface, and a control electrode provided on the surface of the semiconductor portion and controlling a current flowing between the first electrode and the second electrode, the plurality of semiconductor elements being arranged in a first direction from the first electrode toward the second electrode and including a first semiconductor element, a second semiconductor element, a first-end semiconductor element, and a second-end semiconductor element, the second semiconductor element being adjacent to the first semiconductor element, and being connected in series by electrically connecting the second electrode of the first semiconductor element to the first electrode of the second semiconductor element, the first-end semiconductor element being provided at one end of the series connection, and the second-end semiconductor element being provided at the other end of the series connection; An insulating member enclosing the plurality of semiconductor elements arranged in the first direction, having a first surface facing the first semiconductor element and a second surface facing the second semiconductor element, the first surface and the second surface intersecting the first direction; a first terminal electrically connected to the first electrode of the first semiconductor element; a second terminal electrically connected to the second electrode of the second semiconductor element and provided on one of the first surface side and the second surface side of the insulating member; as well as A plurality of control terminals are electrically connected to the control electrodes of the plurality of semiconductor elements, respectively, and are provided separately from each other on one of the first surface side and the second surface side of the insulating member and are separated from the second terminal.

2. The semiconductor device according to claim 1, wherein The first terminal is provided on the first surface side of the insulating member; The second terminal and the plurality of control terminals are provided on the second surface side of the insulating member.

3. The semiconductor device according to claim 1, wherein: The first terminal, the second terminal and the plurality of control terminals are provided on the second surface side of the insulating member; The first terminal is separated from the second terminal and the plurality of control terminals.

4. The semiconductor device according to claim 1, wherein: The device further includes a first conductive member which is provided in the insulating member and electrically connects the control electrodes of the plurality of semiconductor elements and the plurality of control terminals, respectively.

5. The semiconductor device according to claim 3, wherein: A second conductive member is further provided in the insulating member and electrically connects the first electrode of the first semiconductor element to the second terminal.

6. The semiconductor device according to claim 1, wherein: Also provided are a plurality of wirings for electrically connecting the plurality of semiconductor elements; One of the plurality of wirings electrically connects the second electrode of the first semiconductor element and the first electrode of the second semiconductor element; The insulating member has a structure in which first members and second members are alternately stacked, each of the plurality of semiconductor elements is built in the first member, and each of the second members includes the plurality of wirings.

7. The semiconductor device according to claim 6, wherein: The first part of the insulating member has a plurality of contact holes communicating with the second electrode; The wiring includes a plurality of contact portions extending into the plurality of contact holes respectively and a metal layer provided on the first member, and the plurality of contact portions are connected to the metal layer and are electrically connected to the second electrode via the contact portions.

8. The semiconductor device according to claim 1, wherein The first terminal, the second terminal and the plurality of control terminals are provided on the first surface side of the insulating member; The first terminal is separated from the second terminal and the plurality of control terminals.

9. The semiconductor device according to claim 8, wherein: The plurality of semiconductor elements are stacked in the first direction; The insulating member covers the plurality of semiconductor elements.

10. The semiconductor device according to claim 7, wherein: One of the plurality of semiconductor elements includes the second electrode and the control electrode arranged in a second direction along the surface of the semiconductor portion; The other semiconductor element provided on the one semiconductor element includes the second electrode and the control electrode arranged in a third direction, and the third direction is a direction along the surface of the semiconductor portion and perpendicular to the second direction.

11. The semiconductor device according to claim 10, wherein: Each of the plurality of semiconductor elements has a first width in the second direction and a second width in the third direction, and the first width is narrower than the second width.

12. The semiconductor device according to claim 10, wherein: The control electrodes of the plurality of semiconductor elements are electrically connected to the plurality of control terminals via metal wires, respectively.

13. The semiconductor device according to claim 9, wherein: One of the plurality of semiconductor elements has a chip size larger than chip sizes of other semiconductor elements stacked on the one semiconductor element.

14. The semiconductor device according to claim 8, wherein The first terminal, the second terminal, and the plurality of control terminals each have a back surface exposed on the first surface of the insulating member and a surface covered by the insulating member.

15. The semiconductor device according to claim 1, wherein The plurality of semiconductor elements each have the same capacitance between the first electrode and the second electrode.

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