Semiconductor device

Abstract

An embodiment provides a semiconductor device capable of reducing parasitic capacitance. The semiconductor device of this embodiment includes first and third electrodes, first and third semiconductor regions, a gate electrode, and first and second insulating portions. The first semiconductor region is disposed on the first electrode. The second semiconductor region is disposed on the first semiconductor region. The third semiconductor region is disposed on the second semiconductor region. The second electrode is electrically connected to the third semiconductor region. The third electrode is arranged side-by-side with the first and second semiconductor regions. The gate electrode is disposed between the third electrode and the second semiconductor region. The first insulating portion is disposed between the third electrode and the first semiconductor region. The first insulating portion includes first and second insulating regions and a gap region. The first insulating region faces the third electrode. The second insulating region faces the first semiconductor region. The gap region is located between the first insulating region and the second insulating region. The second insulating portion is disposed between the gate electrode and the second semiconductor region.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-45559 (filed on March 19, 2021). The entire contents of the basic application are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] Semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) are used in applications such as power conversion. Reduction of parasitic capacitance is required for semiconductor devices. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor device capable of reducing parasitic capacitance.

[0006] A semiconductor device according to an embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a second electrode, a third electrode, a gate electrode, a first insulating portion, and a second insulating portion. The first semiconductor region is disposed on the first electrode. The second semiconductor region is disposed on the first semiconductor region. The third semiconductor region is selectively disposed on the second semiconductor region. The second electrode is disposed on the third semiconductor region and electrically connected to the third semiconductor region. The third electrode is arranged side-by-side with the first semiconductor region and the second semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The gate electrode is disposed between the third electrode and the second semiconductor region in the second direction. The first insulating portion is disposed between the third electrode and the first semiconductor region in the second direction. The first insulating portion includes a first insulating region, a second insulating region, and at least one gap region. The first insulating region faces the third electrode in the second direction. The second insulating region faces the first semiconductor region in the second direction. The gap region is located between the first insulating region and the second insulating region in the second direction. The second insulating portion is disposed between the gate electrode and the second semiconductor region in the second direction. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0008] Figure 2 (a)~ Figure 4 (c) is a process cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0009] Figure 5 (a)~ Figure 6 (b) is a process cross-sectional view showing a modified example of the manufacturing process of the semiconductor device according to the first embodiment.

[0010] Figure 7 (a)~ Figure 8 (b) is a process cross-sectional view showing another variation of the manufacturing process of the semiconductor device according to the first embodiment.

[0011] Figure 9 This is a cross-sectional view showing the semiconductor device according to the second embodiment. Detailed Implementation

[0012] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0013] The accompanying drawings are schematic or conceptual, and the relationships between the thicknesses and widths of the parts, as well as the ratios between the dimensions, may not necessarily match the actual situation. Even when representing the same parts, there may be instances where the dimensions and ratios are represented differently depending on the accompanying drawings.

[0014] In this specification and the accompanying drawings, the same descriptions are given to the same elements as those already described, and detailed descriptions are omitted where appropriate.

[0015] In the following description and accompanying figures, n + n - and p + The expressions 'p' and 'p' represent the relative levels of impurity concentration. Specifically, a '+' sign indicates a relatively higher impurity concentration than a '-' sign without either '+' or '-', while a '-' sign indicates a relatively lower impurity concentration than a 'p' sign without 'p'. When each region contains both acceptor and donor impurities, these expressions represent the relative levels of the actual impurity concentration after these impurities have mutually compensated for each other.

[0016] Regarding the embodiments described below, each embodiment can also be implemented by inverting the p-type and n-type of each semiconductor region.

[0017] (First Implementation)

[0018] Figure 1This is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0019] The semiconductor device 100 in the first embodiment is, for example, a MOSFET. Figure 1 As shown, the semiconductor device 100 of the first embodiment has n - Type 1 (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n-type + Type source region 3 (third semiconductor region), p + Type contact area 4, n + The structure includes a drain region 5, a gate electrode 10, an FP electrode 20 (third electrode), a drain electrode 31 (first electrode), a source electrode 32 (second electrode), a via 35, an FP insulating portion 40 (first insulating portion), a gate insulating portion 50 (second insulating portion), and an interlayer insulating portion 60 (third insulating portion). Additionally, "FP" stands for "field plate".

[0020] In the following descriptions of the various embodiments, a first direction D1, a second direction D2, and a third direction D3 are used. The direction from the drain electrode 31 toward n... - The direction of the drift region 1 is designated as the first direction D1. A direction perpendicular to the first direction D1 is designated as the second direction D2. A direction perpendicular to the first direction D1 and intersecting the second direction D2 is designated as the third direction D3. Furthermore, for ease of explanation, the direction from the drain electrode 31 towards n... - The direction of the drift region 1 is called "up," and its opposite direction is called "down." These directions are based on the drain electrode 31 and n. - The relative positional relationship of the drift region 1 is independent of the direction of gravity.

[0021] like Figure 1 As shown, a drain electrode 31 is provided on the lower surface of the semiconductor device 100. An n-thickness layer is placed above the drain electrode 31. + Type drift region 5 is provided with n - Type-drift region 1. n - Type-drift region 1 separated by n + The p-type drift region 5 is electrically connected to the drain electrode 31. The p-type base region 2 is located at the n-type base. - Above the p-type drift region 1. An n-type base is selectively provided above the p-type base region 2. + Type source pole region 3 and p + Type 4 contact area.

[0022] FP electrode 20 is in the second direction D2 with n - The p-type drift region 1 and the p-type base region 2 are arranged side by side. That is, the FP electrode 20 is disposed in the second direction D2, adjacent to the n-type drift region 2.- The position where the p-type drift region 1 and the p-type base region 2 overlap. The FP electrode 20 can also overlap with the n-type base region 2 in the second direction D2. + The source region 3 is arranged side by side. That is, the FP electrode 20 can also be positioned in the second direction D2, adjacent to n. + The location of the overlapping of the source pole region 3.

[0023] The FP insulating part 40 is disposed on the FP electrode 20 and n in the second direction D2. - Between type drift region 1. In this example, a portion of the FP insulation 40 is disposed on the FP electrode 20 and n in the second direction D2. - Between the drift regions 1, another portion of the FP insulating portion 40 is disposed between the FP electrode 20 and the gate electrode 10 in the second direction D2. Thus, the gate electrode 10 and the FP electrode 20 are electrically isolated from each other.

[0024] The FP insulating portion 40 includes a first insulating region 41, a second insulating region 42, and at least one void region 48. The first insulating region 41 faces the FP electrode 20 in the second direction D2. In this example, the first insulating region 41 is in contact with the FP electrode 20 in the second direction D2. The second insulating region 42 is in contact with the FP electrode 20 in the second direction D2. - Type Drift Region 1 is opposite. In this example, the second insulating region 42 is opposite to n in the second direction D2. - Type drift region 1 contacts. The gap region 48 is located between the first insulating region 41 and the second insulating region 42 in the second direction D2. The gap region 48 is a gap (air gap) provided inside the FP insulating part 40. The gap region 48 may contain air, or it may be a vacuum.

[0025] The gap region 48, for example, does not overlap with the FP electrode 20 in the first direction D1. The gap region 48, for example, is parallel to the FP electrode 20 in the second direction D2. The lower end of the gap region 48 is, for example, located at the same height as the lower end of the FP electrode 20. The upper end of the gap region 48 is, for example, located below the upper end of the FP electrode 20.

[0026] In this example, the FP insulation portion 40 also includes a third insulation region 43, a fourth insulation region 44, and a fifth insulation region 48.

[0027] The third insulating region 43 is disposed below the void region 48 and below the FP electrode 20. A portion of the third insulating region 43 is located in the first direction D1 between the void region 48 and n. - Between type drift region 1. Another part of the third insulating region 43 is located on the first direction D1 between FP electrode 20 and n. -Between type drift regions 1. The third insulating region 43, for example, has a first portion 43a and a second portion 43b. The first portion 43a is disposed in the first direction D1 between the second portion 43b and n. - Between the drift regions 1. That is, the second part 43b is disposed above the first part 43a.

[0028] The thickness L3 of the third insulating region 43 in the first direction D1 is, for example, greater than the thickness L1 of the first insulating region 41 in the second direction D2. Furthermore, the thickness L3 of the third insulating region 43 in the first direction D1 is, for example, greater than the thickness L2 of the second insulating region 42 in the second direction D2. In this example, the thickness L1 is the same as the thickness L2. The thickness L1 may also be greater than or less than the thickness L2. The thickness L3 is expressed as the sum of the thickness L3a of the first portion 43a in the first direction D1 and the thickness L3b of the second portion 43b in the first direction D1. The thickness L3a is, for example, the same as the thickness L2.

[0029] A fourth insulating region 44 is disposed above the gap region 48, the first insulating region 41, and the fifth insulating region 45. A portion of the fourth insulating region 44 is disposed between the gap region 48 and the source electrode 32 in the first direction D1. Another portion of the fourth insulating region 44 is disposed between the first insulating region 41 and the source electrode 32 in the first direction D1. A further portion of the fourth insulating region 44 is disposed between the fifth insulating region 45 and the source electrode 32 in the first direction D1.

[0030] A fifth insulating region 45 is disposed in the second direction D2 between the first insulating region 41 and the second insulating region 42. Thus, the fifth insulating region 45 divides the gap region 48 in the second direction D2. The thickness L5 of the fifth insulating region 45 in the second direction D2 is, for example, the same as the thickness L2. The thickness L5 can also be larger or smaller than the thickness L2.

[0031] In this example, a fifth insulating region 45 is provided between the first insulating region 41 and the second insulating region 42. The FP insulating part 40 includes a first gap region 48a and a second gap region 48b arranged along the second direction. That is, the gap region 48 includes the first gap region 48a and the second gap region 48b. The first gap region 48a is located between the first insulating region 41 and the fifth insulating region 45 in the second direction D2. The second gap region 48b is located between the fifth insulating region 45 and the second insulating region 42 in the second direction D2.

[0032] In this example, the width W1 of the second direction D2 of the first gap region 48a is the same as the width W2 of the second direction D2 of the second gap region 48b. The width W1 can also be larger or smaller than the width W2. Thus, the widths of each gap region 48 can be the same or different. For example, the width of each gap region 48 can be smaller than the width W3 of the second direction D2 of the FP electrode 20.

[0033] Alternatively, multiple fifth insulating regions 45 can be arranged along the second direction D2. That is, the gap region 48 can be divided into three or more parts along the second direction D2. Furthermore, the fifth insulating region 45 may not be provided. That is, the gap region 48 may not be divided along the second direction D2.

[0034] The gate electrode 10 is disposed in the second direction D2 between the FP electrode 20 and the p-type base region 2, and between the FP electrode 20 and the n-type base region 2. + Between the source pole region 3.

[0035] The gate insulating portion 50 is disposed in the second direction D2 between the gate electrode 10 and the p-type base region 2, and between the gate electrode 10 and the n-type base region 2. + Between the source and source regions 3. Alternatively, the gate insulating portion 50 may be disposed on the gate electrode 10 and n in the second direction D2. - Between type drift regions 1.

[0036] The FP electrode 20 is sandwiched between FP insulating portions 40 in the second direction D2. That is, the FP insulating portions 40 are provided on both sides of the FP electrode 20 in the second direction D2. Furthermore, the FP electrode 20 and the FP insulating portions 40 are sandwiched between n in the second direction D2. - Between type-1 drift regions. That is, n - The drift region 1 is provided on both sides of the FP electrode 20 and the FP insulating part 40 in the second direction D2. Multiple FP electrodes 20 and FP insulating parts 40 are provided along the second direction D2. The FP electrodes 20 and FP insulating parts 40 are continuously provided along the third direction D3.

[0037] Multiple gate electrodes 10 are disposed along the second direction D2. The gate electrodes 10 are continuously disposed along the third direction D3. An FP electrode 20 is disposed between two gate electrodes 10 along the second direction D2. p-type base regions 2 and n... + Type source pole region 3 and p + Type contact region 4 is provided at a position opposite to the plurality of gate electrodes 10 respectively. The structure of the FP insulating portion 40 arranged on both sides of the FP electrode 20 is approximately symmetrical in the second direction D2 with the FP electrode 20 as the center.

[0038] Interlayer insulation 60 is disposed in the p-type base region 2, n+ The source region 3, gate electrode 10, FP electrode 20, and FP insulating portion 40 are located above them. The interlayer insulating portion 60 is located on the n-th layer in the first direction D1. + Between the source region 3 and the source electrode 32, between the gate electrode 10 and the source electrode 32, between the FP electrode 20 and the source electrode 32, and between the FP insulating portion 40 and the source electrode 32.

[0039] The source electrode 32 is disposed on the interlayer insulation portion 60. The source electrode 32 is located in the p-type base region 2, n + The source electrode 32, gate electrode 10, FP electrode 20, and FP insulating portion 40 are located above the source electrode 32, gate electrode 10, FP electrode 20, and FP insulating portion 40. A columnar through-hole 35 extending along the first direction D1 is provided between the source electrode 32 and the p-type base region 2. The through-hole 35 extends from the lower surface of the source electrode 32 along the first direction D1 into the interlayer insulating portion 60 and the n-type base region 40. + It extends (or passes through) the p-type source region 3 and reaches the p-type base region 2. The p-type base region 2 and the n-type source region 2... + The source region 3 is electrically connected to the source electrode 32 through a via 35. For example, the source electrode 32 is connected to a plurality of n electrodes arranged along the second direction D2 through the via 35. + The source region is electrically connected.

[0040] p + The p-type contact region 4 is located between the p-type base region 2 and the through hole 35. The p-type base region 2 is connected to the through hole 35 via the p-type contact region 4. + The contact area 4 and the through hole 35 are electrically connected to the source electrode 32. In this example, p + Type contact area 4 is located in a ratio of n + The lower part of the source pole region 3.

[0041] The FP electrode 20 is electrically connected to the source electrode 32. Each FP electrode 20 is electrically connected to the source electrode 32, for example, at the end of the third direction D3 via a connecting portion.

[0042] The gate electrode 10 is electrically separated from the source electrode 32. The gate electrode 10 is electrically connected to the gate pad, for example, at the end of the third-direction D3, via a gate wiring.

[0043] The operation of the semiconductor device 100 will be explained.

[0044] When a positive voltage is applied to the drain electrode 31 relative to the source electrode 32, a voltage above a threshold value is applied to the gate electrode 10. This forms a channel (inversion layer) in the p-type base region 2, and the semiconductor device 100 becomes conductive. Electrons flow through the channel from the source electrode 32 to the drain electrode 31. Then, when the voltage applied to the gate electrode 10 falls below the threshold value, the channel in the p-type base region 2 disappears, and the semiconductor device 100 becomes cut off.

[0045] When the semiconductor device 100 switches to the off state, the positive voltage applied to the drain electrode 31 relative to the source electrode 32 increases. That is, n - The potential difference between the drift region 1 and the FP electrode 20 increases. This increase in potential difference causes a change in the potential between the FP insulation portion 40 and the n... - The interface of drift region 1 faces n - Type drift region 1, depletion layer expansion. The depletion layer mainly extends along the first direction D1 and the second direction D2, and the depletion layers extending from adjacent FP insulation portions 40 are connected to each other. Thus, the depletion layer is formed in n - The depletion layer extends substantially over the portion between adjacent FP insulating portions 40 in the drift region 1. By expanding this depletion layer, the withstand voltage of the semiconductor device 100 can be improved. Alternatively, while maintaining the withstand voltage of the semiconductor device 100, the n-value can be increased. - The concentration of impurities that become donors in the drift region 1 reduces the on-resistance of the semiconductor device 100.

[0046] An example of the materials used to describe the various components of the semiconductor device 100.

[0047] n - Type 1 drift region, p-type base region 2, n + Type source pole region 3, p + Type contact area 4 and n + The drain region 5 contains silicon, silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. When using silicon as the semiconductor material, arsenic, phosphorus, or antimony can be used as the donor impurity. Boron can be used as the acceptor impurity.

[0048] The gate electrode 10 and FP electrode 20 are made of conductive materials such as polysilicon. Impurities may also be added to the conductive material. The FP insulating portion 40, gate insulating portion 50, and interlayer insulating portion 60 are made of insulating materials. For example, the FP insulating portion 40, gate insulating portion 50, and interlayer insulating portion 60 are made of silicon oxide or silicon nitride. The drain electrode 31 and source electrode 32 are made of metals such as aluminum or copper. The via 35 is made of metals such as tungsten, aluminum, or copper.

[0049] Next, use Figure 2 (a)~ Figure 4 (c) An example of a method for manufacturing a semiconductor device 100 is described.

[0050] Figure 2 (a)~ Figure 2 (c) Figure 3 (a)~ Figure 3 (c) and Figure 4 (a)~ Figure 4 (c) is a process cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0051] First, prepare a set of n + Type semiconductor layers 5a and n - A semiconductor substrate with a semiconductor layer 1a. Then, by photolithography and etching using resist R1, the n-type semiconductor layer 1a is formed. - The surface of the semiconductor layer 1a is formed with a main channel T1 recessed in the first direction D1 and a side channel T2 extending in the third direction D3. Figure 2 (a) The depth of the main channel T1 is, for example, the same as the depth of the side channel T2. The width of the main channel T1, i.e., the length of the second direction D2, is, for example, wider than the width of the side channel T2.

[0052] Then, remove the resist R1, so that n - The semiconductor layer 1a is thermally oxidized, thereby forming the inner wall along the main channel T1, the inner wall along the side channel T2, and n. - An insulating layer IL1 is located on the upper surface of the semiconductor layer 1a. Thus, n is located between the main channel T1 and the side channel T2. - Type semiconductor layer 1a and n located between each other in side channel T2 - The semiconductor layer 1a is respectively formed as an insulating layer IL1 spanning the entire region in the second direction D2. Then, by anisotropic CVD, an insulating layer IL2 of the same material as the insulating layer IL1 is formed at the bottom of the main channel T1 and the side channel T2. Figure 2 (b) Anisotropic CVD can be performed, for example, by plasma CVD. The insulating layer IL2 can also be made of a material with a different dielectric constant than the insulating layer IL1. The formation of the insulating layer IL2 can be performed as needed or omitted.

[0053] Then, an insulating layer IL3 is formed by sealing the upper part of the main channel T1 and the side channel T2 using CAP-CVD (CAP vapor deposition method). Figure 2 (c) Insulating layer IL3 is formed, for example, as part of insulating layer IL3 located below the upper end of the side channel T2. This forms a first void region 48a and a second void region 48b. CAP-CVD is performed, for example, by atmospheric pressure CVD using a poorly layered silane or similar material.

[0054] Then, the insulating layer IL3 blocking the upper part of the main channel T1 is removed by etching, and a conductive layer is formed inside the main channel T1. The FP electrode 20 is formed by back etching the upper surface of this conductive layer. Then, the upper part of the FP electrode 20 is thermally oxidized, thereby forming an insulating layer IL4 along the upper surface of the FP electrode 20. Figure 3 (a)). The formation of the insulating layer IL4 is optional and can be omitted.

[0055] Then, by using photolithography and etching with resist R2, a portion of insulating layers IL1 and IL3 is removed, leaving n - The upper surface and inner surface of the semiconductor layer 1a are exposed, and in n - A channel T3 is formed between the semiconductor layer 1a and the insulating layer IL3. Figure 3 (b)). At this time, the lower end of the channel T3 is positioned above the lower end of the insulating layer IL3.

[0056] Then, make the exposed n - Thermal oxidation of the inner surface of the type semiconductor layer 1a, thereby forming along n - An insulating layer IL5 is formed on the inner surface of the semiconductor layer 1a. Then, a conductive layer is formed inside the channel T3. The gate electrode 10 is formed by etching back the upper surface of this conductive layer. Figure 3 (c)). Then, a portion of the insulating layers IL1 and IL3 are removed by etching.

[0057] Then, towards n located on the side of insulating layer IL5 - In the p-type semiconductor layer 1a, impurities that become acceptors and impurities that become donors are sequentially implanted with ions. This forms the p-type base region 2 and the n-type base region 3. + Type source region 3. Then, an insulating layer IL6 is formed on the gate electrode 10, insulating layer IL3, insulating layer IL4 and insulating layer IL5. Figure 4 (a)).

[0058] Then, along the first direction D1, the insulating layer IL6 and n are formed. + The source region 3 extends (or passes through) and reaches the opening of the p-type base region 2, through which a portion of the ions in the p-type base region 2 are implanted as acceptors, thus forming a p-type base region 2. + Type contact area 4. Then, a covering n is formed. + Type source pole region 3, p + The metal layer of contact region 4 and insulating layer IL6. Thus, source electrode 32 and via 35 are formed. Figure 4 (b)).

[0059] Then, grinding n+ The back side of semiconductor layer 5a extends all the way to n + Until the semiconductor layer 5a reaches the specified thickness, in n + A metal layer is formed on the semiconductor layer 5a. Thus, a drain electrode 31 is formed. Figure 4 (c)).

[0060] Through the above processes, we obtain Figure 1 The semiconductor device 100 is shown. - Type semiconductor layer 1a, for example, with n - The drift region is equivalent to type 1. + Type semiconductor layer 5a, for example, with n + The drain region 5 corresponds to the first insulating region 41, the second insulating region 42, the first portion 43a of the third insulating region 43, and the fifth insulating region 45. The insulating layer IL2 corresponds to the second portion 43b of the third insulating region 43. The insulating layer IL3 corresponds to the fourth insulating region 44. A portion of the insulating layer IL5 corresponds to the gate insulating portion 50. The insulating layer IL6 corresponds to the interlayer insulating portion 60.

[0061] Furthermore, regarding the aforementioned manufacturing methods, unless otherwise specified, the formation of each insulating layer and each conductive layer can be achieved using CVD (Chemical Vapor Deposition). The formation of each metal layer can be achieved using PVD (Physical Vapor Deposition) or plating.

[0062] In addition, regarding the etching of each insulating layer and each conductive layer, unless otherwise specified, the RIE (Reactive Ion Etching) method and CDE (Chemical Dry Etching) method can be appropriately selected.

[0063] Next, use Figure 5 (a)~ Figure 6 (b) A variation of the manufacturing method of the semiconductor device 100 will be described.

[0064] Figure 5 (a)~ Figure 5 (c) Figure 6 (a) and Figure 6 (b) is a process cross-sectional view showing a modified example of the manufacturing process of the semiconductor device according to the first embodiment.

[0065] In this variation, first prepare a set of n + Type semiconductor layers 5a and n -The semiconductor substrate of type semiconductor layer 1a is formed by photolithography and etching using resist R1, in n - The main channel T1 is formed on the surface of the semiconductor layer 1a. Figure 5 (a)).

[0066] Then, remove the resist R1, so that n - The semiconductor layer 1a is thermally oxidized, thereby forming the inner wall and n along the main channel T1. - An insulating layer IL11 is formed on the upper surface of the semiconductor layer 1a. Then, an insulating layer IL12 is formed at the bottom of the main channel T1. Next, a conductive layer is formed inside the main channel T1, and the upper surface of this conductive layer is etched back to form the FP electrode 20. Then, the upper part of the FP electrode 20 is thermally oxidized to form an insulating layer IL13 along the upper surface of the FP electrode 20. Figure 5 (b)).

[0067] Then, on the side of the FP electrode 20, a portion of the insulating layer IL11 is removed from n. - The surface of semiconductor layer 1a is in n - A side channel T2 is formed in the semiconductor layer 1a. Figure 5 (c)). Then, make n - The semiconductor layer 1a is thermally oxidized, thereby forming an insulating layer IL14 along the side channel T2. Figure 6 (a)). Then, an insulating layer IL15 is formed in a manner that seals the upper part of the side channel T2. Figure 6 (b)).

[0068] Subsequent processes can be integrated with the above-mentioned self- Figure 3 (b) Subsequent processes are performed in the same manner. Furthermore, insulating layers IL11 and IL14 are equivalent to insulating layer IL1. Insulating layer IL12 is equivalent to insulating layer IL2. Insulating layer IL13 is equivalent to insulating layer IL4. Insulating layer IL15 is equivalent to insulating layer IL3.

[0069] Thus, even if the method of forming the side channel T2 after forming the FP electrode 20, and then forming the insulating layer of the side channel T2, is used, the semiconductor device 100 can be manufactured.

[0070] Next, use Figure 7 (a)~ Figure 8 (b) Another variation of the method for manufacturing the semiconductor device 100 will be described.

[0071] Figure 7 (a)~ Figure 7 (c) Figure 8 (a) and Figure 8 (b) is a process cross-sectional view showing another variation of the manufacturing process of the semiconductor device according to the first embodiment.

[0072] In this variation, first prepare a set of n + Type semiconductor layers 5a and n - The semiconductor substrate of type semiconductor layer 1a is formed by photolithography using photoresist R1 on n - The main channel T1 is formed on the surface of the semiconductor layer 1a. Figure 7 (a)).

[0073] Then, remove the resist R1, so that n - The semiconductor layer 1a is thermally oxidized, thereby forming the inner wall and n along the main channel T1. - An insulating layer IL21 is formed on the upper surface of the semiconductor layer 1a. Then, a conductive layer IL is formed inside the main channel T1, thereby forming the FP electrode 20. Figure 7 (b)).

[0074] Then, the upper surface of the insulating layer IL21 is etched back, thereby making n - The upper surface of the semiconductor layer 1a is exposed ( Figure 7 (c)). Then, using photolithography and anisotropic etching with resist R2, a side channel T2 is formed in the insulating layer IL21 from the surface of the insulating layer IL21 on the side of the FP electrode 20. Figure 8 (a)).

[0075] Then, the resist R2 is removed to form an insulating layer IL22 that seals the upper part of the side channel T2. Next, the insulating layer IL22 above the FP electrode 20 is removed, and the upper part of the FP electrode 20 is thermally oxidized, thereby forming an insulating layer IL23 along the upper surface of the FP electrode 20. Figure 8 (b)).

[0076] Subsequent processes can be integrated with the above-mentioned self- Figure 3 (b) Subsequent processes are performed in the same manner. Furthermore, insulating layer IL21 is equivalent to insulating layers IL1 and IL2. Insulating layer IL22 is equivalent to insulating layer IL3. Insulating layer IL23 is equivalent to insulating layer IL4.

[0077] Thus, even if the side channel T2 is formed inside the insulating layer after the FP electrode 20 and the insulating layer are formed, the semiconductor device 100 can still be manufactured.

[0078] Here, the function and effects of this embodiment will be explained.

[0079] As a means of reducing parasitic capacitance in a semiconductor device, increasing the thickness of the FP insulating portion 40 disposed around the FP electrode 20 can be considered. However, increasing the thickness of the FP insulating portion 40 increases wafer warpage, potentially causing malfunctions in wafer transport.

[0080] In the semiconductor device of this embodiment, by providing a gap region 48 inside the FP insulating portion 40, the increase in the thickness of the FP insulating portion 40 can be suppressed, and the overall dielectric constant of the FP insulating portion 40 can be reduced, thereby reducing parasitic capacitance. Furthermore, since the gap region 48 can absorb wafer warpage, transport defects caused by wafer warpage can be suppressed. Moreover, since the relative dielectric constant in air or vacuum is lower than that in silicon oxide, the insulation of the FP insulating portion 40 can be improved by providing the gap region 48 compared to the case where the gap region 48 is not provided (i.e., the FP insulating portion 40 is entirely formed of silicon oxide). Therefore, by providing the gap region 48, the thickness of the FP insulating portion 40 can be reduced compared to the case where the gap region 48 is not provided. This reduces the manufacturing time and cost of the semiconductor device.

[0081] (Second Implementation)

[0082] Figure 9 This is a cross-sectional view showing the semiconductor device according to the second embodiment.

[0083] like Figure 9 As shown, in the semiconductor device 200 of the second embodiment, a fourth insulating portion 70 is provided in the second direction D2 between the gate electrode 10 and the fourth insulating region 44. Otherwise, it is the same as the semiconductor device 100 of the first embodiment. The fourth insulating portion 70 comprises an insulating material. The fourth insulating portion 70 comprises, for example, silicon oxide or silicon nitride.

[0084] The fourth insulating portion 70 can be formed, for example, by the method described below. For example, in the above-described... Figure 3 In step (b), the channel T3 is formed such that a portion of the insulating layer IL1 remains between the channel T3 and the insulating layer IL3, thereby forming the fourth insulating portion 70. Alternatively, for example, it could be in the above-described... Figure 3 In step (b), oxygen permeates through the insulating layer IL3 to thermally oxidize a portion of the gate electrode 10 that is in contact with the insulating layer IL3, thereby forming the fourth insulating portion 70.

[0085] In the semiconductor device 200, by providing a gap region 48 inside the FP insulating portion 40, the increase in the thickness of the FP insulating portion 40 can be suppressed, and parasitic capacitance can be reduced. Furthermore, by providing the gap region 48, transport defects caused by wafer warping can be suppressed. Moreover, by providing the gap region 48, the thickness of the FP insulating portion 40 can be reduced compared to the case where the gap region 48 is not provided.

[0086] As described above, according to embodiments of the present invention, a semiconductor device capable of reducing parasitic capacitance is provided.

[0087] The above examples illustrate several embodiments of the present invention, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents. Furthermore, the foregoing embodiments can be combined with each other for implementation.

Claims

1. A semiconductor device, characterized in that, have: First electrode; A first semiconductor region of a first conductivity type is disposed on the first electrode; A second semiconductor region of a second conductivity type is disposed on top of the first semiconductor region; The third semiconductor region of the first conductivity type is selectively disposed on the second semiconductor region; The second electrode is disposed on the third semiconductor region and electrically connected to the third semiconductor region; The third electrode is positioned alongside the first semiconductor region and the second semiconductor region in a second direction perpendicular to the first direction, wherein the first direction extends from the first electrode toward the first semiconductor region. A gate electrode is disposed between the third electrode and the second semiconductor region in the second direction; A first insulating portion is disposed between the third electrode and the first semiconductor region in the second direction, including a first insulating region, a second insulating region, and at least one gap region. The first insulating region is opposite to the third electrode in the second direction, the second insulating region is opposite to the first semiconductor region in the second direction, and the at least one gap region is located between the first insulating region and the second insulating region in the second direction. as well as A second insulating portion is disposed between the gate electrode and the second semiconductor region in the second direction. The first insulating portion includes a fifth insulating region located in the second direction between the first insulating region and the second insulating region. The void region includes: a first void region located between the first insulating region and the fifth insulating region in the second direction; The second gap region is located between the fifth insulating region and the second insulating region in the second direction.

2. The semiconductor device according to claim 1, characterized in that, The void region does not overlap with the third electrode in the first direction.

3. The semiconductor device according to claim 1, characterized in that, The first insulating portion includes a third insulating region, which is located in the first direction between the void region and the first semiconductor region and between the third electrode and the first semiconductor region.

4. The semiconductor device according to claim 3, characterized in that, The thickness of the third insulating region in the first direction is greater than the thickness of the second insulating region in the second direction.

5. The semiconductor device according to claim 1, characterized in that, The first insulating portion includes a fourth insulating region located in the first direction between the void region and the second electrode.

6. The semiconductor device according to claim 2, characterized in that, The first insulating portion includes a fourth insulating region located in the first direction between the void region and the second electrode.

7. The semiconductor device according to claim 3, characterized in that, The first insulating portion includes a fourth insulating region located in the first direction between the void region and the second electrode.

8. The semiconductor device according to claim 4, characterized in that, The first insulating portion includes a fourth insulating region located in the first direction between the void region and the second electrode.

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