Clock recovery circuit and method

Abstract

The present invention provides a clock recovery circuit and method. The clock recovery circuit may include: a data limiter configured to generate an output data value based on an input signal; a first error block; a phase adjustment loop including: a first error limiter configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data value; a second error block configured to selectively output the first error signal in response to a second pattern in the output data value; and a voltage threshold modification circuit configured to adjust the threshold voltage based on the output of the second error block; a voltage-controlled oscillator, wherein the data limiter and the first error limiter are clocked based on the output of the voltage-controlled oscillator; and a loop filter configured to control the frequency of the voltage-controlled oscillator based on the output of the first error block.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 162,883 filed on March 18, 2021, U.S. Provisional Patent Application No. 63 / 227,605 filed on July 30, 2021, and U.S. Patent Application No. 17 / 508,898 filed on October 22, 2021, all of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present application relates generally to timing recovery in high-speed serial links, and more particularly to systems and methods for symbol spaced mode adaptive dual-loop clock recovery for high-speed serial links. Background Art

[0004] High-speed serial links (commonly referred to as serializers / deserializers (SerDes)) are widely used as interfaces in electronic devices such as electronic displays. As the amount of data transmitted through such high-speed serial links increases (e.g., due to increased display resolution, color depth, and / or refresh rate), the interface speed also increases accordingly. As the speed increases, the power and silicon area of ​​the communication receiver of the interface also increase. Timing recovery or clock and data recovery (CDR) is a key function in such serial links for ensuring the correct transmission and reception of data. In addition, it is desirable to perform timing recovery while saving power, area, and design complexity of the serial interface. Summary of the invention

[0005] According to some embodiments, a clock recovery circuit is described. The clock recovery circuit may include: a data slicer configured to generate an output data value based on an input signal; a first error block; a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data value; a second error block configured to selectively output the first error signal in response to a second pattern in the output data value; and a voltage threshold modification circuit configured to adjust the threshold voltage based on an output of the second error block; a voltage controlled oscillator, wherein the data slicer and the first error slicer are clocked based on an output of the voltage controlled oscillator; and a loop filter configured to control a frequency of the voltage controlled oscillator based on an output of the first error block.

[0006] The first error signal may be positive in response to the input voltage being greater than the threshold voltage, or negative in response to the input voltage being equal to or less than the threshold voltage.

[0007] The voltage threshold modification circuit may include a state machine configured to selectively increment the threshold voltage in response to an input voltage to the first error limiter being greater than the threshold voltage.

[0008] The input voltage of the first error limiter may be the output of the voltage controlled oscillator.

[0009] The threshold voltage may be initially set based on the peak value of the input signal.

[0010] The first mode and the second mode may be different modes.

[0011] The first mode and the second mode may each include 3 bits in the output data value.

[0012] The loop filter may be a low pass filter configured to filter noise from the output signal.

[0013] The phase adjustment loop may further include a second error limiter configured to generate a second error signal based on a comparison of a negative value of the threshold voltage and the input voltage.

[0014] The first error block may be further configured to selectively output an inverted second error signal in response to a third pattern in the output data values, wherein the third pattern is complementary to the first pattern.

[0015] The second error block may be further configured to selectively output a second error signal in response to a fourth pattern in the output data values, wherein the fourth pattern is complementary to the second pattern.

[0016] According to some embodiments, a clock recovery method is described. The method may include: generating an output data value based on an input signal by a data slicer; generating a first error signal based on a comparison of a threshold voltage with an input voltage by a first error slicer; selectively outputting the first error signal by a first error block in response to a first pattern in the output data value; selectively outputting the first error signal by a second error block in response to a second pattern in the output data value; adjusting the threshold voltage by a voltage threshold modification circuit based on an output of the second error block; clocking the data slicer and the first error slicer by a voltage controlled oscillator; and controlling the frequency of the voltage controlled oscillator by a loop filter based on the output of the first error block.

[0017] The first error signal may be positive in response to the input voltage being greater than the threshold voltage, or negative in response to the input voltage being equal to or less than the threshold voltage.

[0018] Adjusting the threshold voltage may further include selectively incrementing the threshold voltage in response to an input voltage of the first error limiter being greater than the threshold voltage.

[0019] The input voltage of the first error limiter may be the output of the voltage controlled oscillator.

[0020] The method may further include initially setting the threshold voltage based on a peak value of the input signal.

[0021] The first mode and the second mode may each include 3 bits in the output data value.

[0022] The method may further include generating, by a second error limiter, a second error signal based on a comparison of a negative value of the threshold voltage with the input voltage.

[0023] The method may further include selectively outputting, by the first error block, an inverted second error signal in response to a third pattern in the output data values, wherein the third pattern is complementary to the first pattern.

[0024] The method may further include selectively outputting, by the second error block, a second error signal in response to a fourth pattern in the output data values, wherein the fourth pattern is complementary to the second pattern.

[0025] The scope of the present invention is defined by the claims incorporated into this section by reference. By considering the following detailed description of one or more embodiments, those skilled in the art will more completely understand the embodiments of the present invention and realize the additional advantages of the present invention. The accompanying drawings will be described with reference to the drawings that are first briefly described. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a block diagram of an example slicer according to various embodiments of the present disclosure.

[0027] Figure 2 is a block diagram of an example high-speed serial link according to various embodiments of the present disclosure.

[0028] Figure 3 is a table showing example cases of error blocks according to various embodiments of the present disclosure.

[0029] Figure 4 is a diagram of an example data eye according to various embodiments of the present disclosure.

[0030] Figure 5 is a table showing another set of example cases of error blocks according to various embodiments of the present disclosure.

[0031] Figure 6 is a flow chart illustrating a method for performing clock recovery according to various embodiments of the present disclosure.

[0032] The embodiments of the present disclosure and their advantages are best understood by referring to the detailed description below. Unless otherwise specified, the same reference numerals represent the same elements throughout the drawings and written description, and therefore their description will not be repeated. In the accompanying drawings, the relative sizes of elements, layers and regions may be exaggerated for clarity. DETAILED DESCRIPTION

[0033] The various aspects of some embodiments of the present disclosure and the methods for realizing these aspects can be more easily understood by referring to the detailed description and drawings of the embodiments. Hereinafter, the embodiments will be described in more detail with reference to the drawings. However, the described embodiments can be embodied in various different forms and should not be interpreted as being limited to the embodiments shown in this article. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements and technologies that are not necessary for those of ordinary skill in the art to fully understand the aspects of the present disclosure may not be described.

[0034] The present disclosure describes a technique for timing recovery or clock recovery in a high-speed serial link (SerDes). The SerDes system and method described in the present disclosure utilize two feedback loops operated by a single 1-bit sampler (also referred to as a slicer). The slicer samples the voltage difference between the incoming input data signal and the offset threshold voltage at the data symbol rate. The first feedback loop, which will be referred to as the frequency acquisition loop in this article, adapts the threshold voltage, and the second feedback loop, which will be referred to as the phase adjustment loop in this article, automatically reacts to adjust the sampling phase. In addition, the described system and method include a data signal bit pattern screening function for generating an error signal fed to the two feedback loops, and the clock and data recovery (CDR) jointly optimizes the threshold voltage and the sampling phase so that a specific target standard can be achieved. The mode screening function can be set to rely only on the current bit value of the frequency acquisition loop driving the voltage-controlled oscillator (VCO), thereby avoiding the problem of losing frequency lock when the data bit is a repeated 1010 clock pattern. On the other hand, the phase adjustment loop can screen out different mode groups to optimize the locked phase and achieve various pulse responses. Accordingly, systems and methods are described for timing recovery while saving power, area, and design complexity of a serial interface.

[0035] Clock recovery algorithms fall into two broad categories: oversampled or baud rate (also known as symbol spaced). In a high-speed serial link (SerDes) utilizing oversampled timing recovery, two samples are taken per unit interval (UI) with a spacing or distance of half the UI between the two samples. One UI can be defined as 1 / data rate = 1 symbol time = T. Accordingly, the timing information of the signal can be derived using, for example, the well-known early-late algorithm. Although the early-late algorithm is a robust algorithm, the disadvantage is that the receiver must generate a clock twice as fast as the data rate. In systems utilizing baud rate timing recovery (e.g., the bang-bang or Mueller-Mueller method, which is a popular clock recovery technique used in many digital receivers (e.g., receivers based on analog-to-digital converters (ADCs)), only one sample is taken per UI. However, this technique requires samples to be obtained from at least 2 UIs to derive timing error information, and is typically implemented in the digital domain. Accordingly, such known techniques require additional clock phases and additional limiters, all of which result in increased power consumption.

[0036] Embodiments of the present disclosure describe techniques for performing timing recovery or clock and data recovery (CDR) (where only one sample is taken per UI by using only the sign of the error rather than the amplitude), and are also not dependent on the ADC. Additionally, in some techniques, however, frequency lock is lost when a specific pattern (e.g., a clock pattern such as 1010) is transmitted to a receiver, but embodiments of the present disclosure provide techniques that can achieve frequency lock for all types of data patterns (including repeating clock patterns such as 1010). Accordingly, frequency lock can be achieved faster than other known techniques. For example, for a Nyquist channel loss of 10dB to 35dB at a data rate of 10Gbps, a lock range of 500000ppm can be achieved when the transmitter is transmitting a clock pattern, and a lock range of 30000ppm can be achieved when the transmitter is transmitting a random non-return-to-zero (NRZ) data bit sequence. In addition, frequency lock can be achieved in less than 2μs, and depending on the channel loss, the jitter caused by inter-symbol interference (ISI) may be between about 1 picosecond RMS and 5 picosecond RMS.

[0037] Various timing recovery mechanisms can be distinguished by the manner in which they generate and process the timing errors caused by the phase detector to adjust the receiver clock. According to embodiments of the present disclosure, a basic form of the timing error function is utilized for frequency acquisition, and multiple timing errors are used for phase optimization. Accordingly, the described techniques utilize a data slicer and an error slicer operating from the same clock signal, and do not utilize a cross-slicer.

[0038] Figure 1An example block diagram of a limiter 102 is shown. In some embodiments, the working principle of the limiter 102 is to compare the input signal 104 (e.g., an analog voltage) with the threshold 106 and generate an error output 108. As shown, the limiter 102 receives the input signal 104 and generates the error output 108 based on the comparison result of the input signal 104 and the threshold 106. Accordingly, the limiter 102 outputs +1 (e.g., a positive error) when the voltage of the input signal 104 is greater than the threshold 106, and outputs -1 (e.g., a negative error) when the voltage of the input signal 104 is less than the threshold 106. According to various embodiments of the present disclosure, the threshold of the data limiter is zero, and the threshold of the error limiter is initially at a predetermined threshold voltage Vth of approximately 100mV to 400mV (see Figure 2 ) and then the threshold voltage for the optimized sampling phase.

[0039] Figure 2 2 is a block diagram of an example high-speed serial link 200 according to various embodiments of the present disclosure. The high-speed serial link 200 includes a transmitter (TX) 202, a receiver 210, and a channel 204 connecting the transmitter 202 to the receiver 210. In some embodiments, the transmitter 202 may be a linear finite impulse response filter (FIR), and the receiver 210 may be a continuous time linear equalizer (CTLE). Accordingly, the transmitter 202 transmits a serial data signal 212 through the channel 204 to the receiver 210 using a transmitter clock signal (TX CLK) 214 as a clock and data recovery (CDR) input V in (t). In some embodiments, noise 206 may be introduced to the CDR input V in (t) in.

[0040] In some embodiments, the CDR input V in (t) can be calculated as follows:

[0041] V in (t)=∑ k d k p(t-kT)+n(t),

[0042] Among them, d k denotes the transmitted alphabet (+1 / -1 for NRZ signaling), n(t) is noise typically modeled as additive white Gaussian noise (AWGN), p(t) denotes the impulse response of the entire channel including the analog front end (AFE), and kT denotes time in T seconds, where T is the symbol period. For example, the serial data signal 212 is sampled every T seconds (1UI=T seconds), so the time sequence of sampling the serial data signal 212 becomes T, 2T, 3T, etc. It can be assumed that the transmitted alphabet d kare independent and identically distributed (IID).

[0043] In some embodiments, the receiver 210 includes an analog front end (AFE) 205, a frequency acquisition loop 216, and a phase adjustment loop 208. The AFE 205 can be any of many front-end circuits known to those skilled in the art, and will not be described in further detail here. According to an embodiment, the phase adjustment of the phase adjustment loop 208 is automatically performed based on specific parameters (such as based on the bit pattern of the input data bits). Accordingly, the frequency acquisition loop 216 and the phase adjustment loop 208 work with each other to achieve different goals, and when both goals are met, the receiver 210 becomes stable. For example, the goal of the frequency acquisition loop 216 can be to achieve a specific frequency, while the goal of the phase adjustment loop 208 can be to achieve a specific phase. Before both goals are met, the frequency acquisition loop 216 and the phase adjustment loop 208 continue to strive to meet their own goals. In some embodiments, the operating speed of the frequency acquisition loop 216 is about 100 times faster than the operating speed of the phase adjustment loop 208.

[0044] In some embodiments, the frequency acquisition loop 216 includes a data slicer 218 configured to sample the serial data signal 212 received from the transmitter 202. In some embodiments, the threshold voltage is set to zero. Accordingly, the data slicer 218 outputs the received serial data signal 212. The output of the data slicer 218 can be coupled to the first error block 220, which will be described in more detail later. The output of the first error block 220 can be coupled to a loop filter 230 (e.g., a proportional integral loop filter). In some embodiments, the loop filter 230 can be a standard loop filter configured to filter out noise that can be picked up when, for example, the serial data signal 212 is transmitted through the channel 204. Then, the filtered serial data signal 212 is output from the loop filter 230 to control the voltage controlled oscillator (VCO) 232. The loop filter 230 can be a standard loop filter such as, for example, a low-pass filter known to those of ordinary skill in the art, and therefore the details will be omitted.

[0045] In some embodiments, the phase adjustment loop 208 includes an error limiter 222 and a second error block 224. The error limiter 222 may be similar to the error limiter 222, except that the threshold is initially set and then subsequently adjusted to optimize the threshold voltage. Figure 1 , and the behavior of the error limiter 222 is similar to that of the data limiter 218.

[0046] Back to Figure 2, the error limiter 222 receives an input signal from the voltage controlled oscillator 232 and a threshold voltage Vth as a comparison voltage. In some embodiments, the threshold voltage Vth can be a predetermined arbitrary value greater than zero, such as, for example, about 100mV to 400mV. In some embodiments, the predetermined threshold voltage Vth can be set to a value of about half of the peak input signal. However, the threshold voltage Vth can be set to any value as long as the threshold voltage Vth is not set so low that the error value is mainly +1 or is not set so high that the error value is mainly -1.

[0047] In some embodiments, the error output from the error limiter 222 is provided to a first error block 220 in the frequency acquisition loop 216. The first error block 220 can be configured to perform a first function f1 if a specific pattern (e.g., a predetermined pattern) of bits is detected in the input serial data signal 212. Similarly, the same error output from the error limiter 222 is also provided to a second error block 224 in the phase adjustment loop 208. The second error block 224 can be configured to perform a second function f2 if a specific pattern (e.g., a predetermined pattern) of bits is detected in the input serial data signal 212. In some embodiments, the first error block 220 and the second error block 224 are configured to look for different patterns of bits, which will be described in more detail later.

[0048] In some embodiments, when the mode criteria of the first error block 220 are met, the output of the second error block 224 is provided to a voltage threshold modification circuit 226 that adjusts a threshold voltage Vth that is ultimately fed back to the error limiter 222. The voltage threshold modification circuit 226 may include a circuit configured to selectively increment the threshold voltage Vth in response to the input voltage of the error limiter 222 being greater than the threshold voltage Vth. Accordingly, the phase adjustment loop 208 controls the threshold voltage Vth, and the threshold voltage Vth is used to control the error limiter 222. The error limiter 222 generates an error that is provided to both the first error block 220 and the second error block 224. When their mode criteria are met, each of the first error block 220 and the second error block 224 performs a different function, and when the function f1 of the first error block 220 and the function f2 of the second error block 224 are merged, the phase adjustment loop 208 and the frequency acquisition loop 216 are converged, the threshold voltage Vth is no longer updated, and frequency lock is achieved.

[0049] Figure 3 is a table showing an example case of an error block. In the table, the main loop refers to the frequency acquisition loop 216, and the auxiliary loop refers to the phase adjustment loop 208. In the present disclosure, the symbol It refers to the average value of the error divided by Previous Data (d n-1)=0、Current Data(d n )=1、Next Data(d n+1 )=0. In other words, the function is executed only when the data pattern of 010 is detected. The symbol "X" means that the bit can be 0 or 1. So, for example, the symbol X1X for the main loop means that the function does not care whether the previous data bit and the next data bit are 1 or 0, but only cares that the current data bit is 1.

[0050] For example, in case #1, whenever the serial data signal 212 exhibits a 3-bit pattern of 011, the error from the second error block 224 may be applied to the auxiliary loop. Unlike case #1, in case #2, the error from the second error block 224 is applied to the auxiliary loop only when the bit pattern is 110. In other words, if the bit pattern is not 110, the auxiliary loop ignores the error. In case #3, when the bit pattern corresponds to X10, the error from the second error block 224 may be applied to the auxiliary loop. In other words, the previous data bit is ignored, and only the current data bit and the next data bit are screened so that the current data bit is 1 and the next data bit is 0. Similarly, in case #4, when the bit pattern is 01X, the error from the second error block 224 may be applied to the auxiliary loop. In other words, the next data bit is ignored, and only the previous data bit and the current data bit are screened so that the previous data bit is 0 and the current data bit is 1. In this way, the first error block 220 and the second error block 224 can obtain the same error output from the error limiter 222, but only apply the error to its corresponding primary loop or secondary loop when the bit pattern screening criteria are met. Figure 3 Four example cases are shown by way of example in FIG. 1 , but other variations of the bit patterns are also applicable.

[0051] Accordingly, the threshold voltage Vth in the phase adjustment loop 208 (i.e., the auxiliary loop) can be adjusted by applying the error from the second error block 224 to the phase adjustment loop 208 until a frequency lock condition is achieved. Thus, for example, in case #1 and case #2, when the impulse response value h 1 =h -1 In case #3, when h 1 = 0, frequency lock is achieved, and in case #4, when h -1 =0, frequency lock is achieved.

[0052] Back to Figure 2 , the error output from the error limiter 222 is also provided to the first error block 220 in the frequency acquisition loop 216. Similar to the second error block 224, the first error block 220 also screens a predetermined bit pattern. Figure 3 As provided in , the first error block 220 can be configured to look for an X1X pattern (which means any time the current data bit is a 1), and the error is applied to the frequency acquisition loop 216 (ie, the main loop).

[0053] In some embodiments, Figure 2 As shown in , when the error from the first error block 220 is applied to the frequency acquisition loop 216, the error is filtered by the loop filter 230 (e.g., a proportional integral loop filter), and the output of the loop filter 230 controls the VCO frequency. In some embodiments, an error value of +1 is used to increase the VCO frequency, and an error value of -1 is used to decrease the VCO frequency. Therefore, the error (i.e., timing error) information can be used to drive the timing recovery loop. Figure 4 As shown in , once the timing recovery is locked, the expected value of the signal voltage at the sampling time is is equal to the threshold. Here, Figure 4 is a diagram of an example data eye according to an embodiment of the present disclosure. Here, is defined as the average of the signal voltage at the sampling instants.

[0054] In some embodiments, Figure 3 As shown in , the error signal entering the VCO (or any other clock generation block) is adjusted based on a bit pattern that is different from the bit pattern used for the phase optimization loop (e.g., phase adjustment loop 208). Therefore, although the errors of the two loops are the same output of the error limiter 222, the loops are adjusted based on different patterns. The error information entering the VCO loop directly affects the frequency, but the error entering the phase optimization loop only affects the threshold voltage Vth, and when the timing error is driven to zero, the loop converges so that the error entering the VCO loop is equal to the error entering the phase optimization loop. In some embodiments, the VCO loop is substantially faster (e.g., about 10 times to about 100 times) than the phase optimization loop to adjust the phase for the new threshold voltage Vth.

[0055] In some embodiments, the frequency acquisition loop 216 is able to acquire frequency lock even when the transmitter 202 is transmitting data bits having a clock pattern (e.g., repeating 1010). This is advantageous because the initial portion of the data signal typically includes a clock pattern, and therefore, by acquiring frequency lock during this clock pattern, the amount of time it takes to achieve frequency lock can be greatly improved (e.g., reduced). Although frequency lock can be achieved using a random data sequence as previously described, if the transmitter 202 is transmitting a clock pattern with lower inter-symbol interference (ISI), then acquiring frequency lock is much faster. In a Mueller-Mueller phase detector, the timing error information is represented by X k *A k-1 -Xk-1 *A k Since only the sign information is available in the SerDes, the equation becomes Sign(X k )*d k-1 -Sign(X k-1 )*d k , for the 1010 mode, the result is always 0, which prevents any timing information from reaching the CDR. In various embodiments of the present disclosure, E(V in )=V 4h6eshol； =h 0 , and thus, allows the CDR to lock in a clock mode (eg, 1010). For example, with a starting ppm offset of 500000 using the 1010 clock mode, frequency lock within 2 μs may be achievable.

[0056] In some embodiments, additional bit patterns may be implemented (such as Figure 3 ), and additional limiters may be included to achieve the same result. Figure 5 An example of the supplemented screening bit pattern is shown in FIG. Accordingly, the first error block 220 can be configured to apply the error to the main loop when the bit pattern is X0X (which means when the current data bit is zero). It can be seen that the bit pattern X0X is the complement of X1X. Similarly, the second error block 224 can be configured to apply the error to the main loop when the bit pattern is 100, 001, X01, 10X (which is the complement of X1X) in case #1 to case #4, respectively. Figure 3 The error is applied to the auxiliary loop when the error is applied to the auxiliary loop (the complement of 011, 110, X10, 01X in case #1 to case #4). In some embodiments, such complementary filtering can be performed by including an additional error limiter configured to look at the threshold voltage Vth of the opposite polarity. In other words, Figure 3 The error limiter utilized together with the screening pattern shown in looks at the positive threshold voltage +Vth to apply the error to the auxiliary loop. In some embodiments, another error limiter can be implemented to look at the negative threshold voltage -Vth and to achieve the same result using the supplemented screening bit pattern. Accordingly, the bandwidth of the feedback loop can be doubled.

[0057] Figure 66 is a flow chart illustrating a method 600 for performing clock recovery according to various embodiments of the present disclosure. Accordingly, in some embodiments, at step 602, an output data value is generated by the data slicer 218 based on an input signal. Next, at step 604, a first error signal is generated by the error slicer 222 (also referred to as a first error slicer) based on a comparison of a threshold voltage with an input voltage. At step 606, the first error signal may be selectively output by the first error block 220 in response to a first pattern in the output data value. Next, at step 608, the first error signal may be selectively output by the second error block 224 in response to a second pattern in the output data value. Next, at step 610, the threshold voltage may be adjusted by the voltage threshold modification circuit 226 based on the output of the second error block 224. At step 612, the data slicer 218 and the error slicer 222 may be clocked by the voltage controlled oscillator 232, in other words, the data slicer 218 and the error slicer 222 may be clocked based on the output of the voltage controlled oscillator 232. In some embodiments, at step 614, the frequency of the voltage controlled oscillator 232 may be controlled by the loop filter 230 based on the output of the first error block 220. Accordingly, clock and data recovery may be performed in a high-speed serial link to jointly optimize the threshold voltage and sampling phase to achieve a target standard.

[0058] Unless otherwise specified, the same reference numerals, characters or combinations thereof denote the same elements throughout the drawings and written description, and thus their description will not be repeated. Further, parts that are irrelevant or unrelated to the description of the embodiment may not be shown to make the description clear.

[0059] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. Additionally, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other feature, attribute, property, etc. of the elements.

[0060] In the detailed description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other examples, well-known structures and devices are shown in block diagram form to avoid unnecessary confusion of the various embodiments.

[0061] For ease of explanation, spatial relative terms such as "below", "below", "down", "below", "above" and "on" can be used in this article to describe the relationship between an element or feature and another (some) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element described as "below", "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the example terms "below" and "below" can include both above and below orientations. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this shows that the first part is arranged on the upper side or lower side of the second part based on the direction of gravity without being limited to its upper side.

[0062] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "coupled to" another element, layer, region, or component, the element, layer, region, or component may be formed directly on, directly on, directly connected to, or coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or coupled to the other element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. Additionally, this may collectively represent direct or indirect coupling or connection, as well as integral or non-integral coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, the layer, region or component may be directly electrically connected or coupled to the other layer, region and / or component, or there may be intervening layers, regions or components. However, "direct connection / direct coupling" refers to a component being directly connected or coupled to another component without an intermediate component. At the same time, other expressions such as "between," "directly between," or "adjacent to," and "directly adjacent to" that describe the relationship between components may be similarly interpreted. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0063] It will be understood that, although the terms "first", "second", "third", etc. can be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are used to distinguish an element, component, area, layer or part from another element, component, area, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, area, layer or part described below can be referred to as the second element, component, area, layer or part. Describing an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish elements of different categories or groups in this article. For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0064] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0065] The terms used in this article are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in this article, the singular forms "one" and "an" are also intended to include plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include", "comprise", "contain", and "have" indicate the presence of the features, integral bodies, steps, operations, elements, and / or parts, but do not exclude the presence or increase of one or more other features, integral bodies, steps, operations, elements, parts, and / or their groups.

[0066] As used herein, the terms "substantially," "approximately," "approximately," and similar terms are used as approximate terms rather than terms of degree, and are intended to take into account the inherent deviations of measured or calculated values ​​that will be recognized by those skilled in the art. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "approximately" or "approximately" as used herein include the value and mean within an acceptable deviation range for the particular value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations of the value or within ±30%, ±20%, ±10%, ±5% of the value. Further, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure."

[0067] When one or more embodiments may be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described successively may be performed substantially simultaneously or in an order opposite to the described order.

[0068] In addition, any numerical range disclosed and / or recorded in this article is intended to include all sub-ranges of the same numerical precision contained in the recorded range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the recorded minimum value 1.0 and the recorded maximum value 10.0 (and including the recorded minimum value 1.0 and the recorded maximum value 10.0), that is, with a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit recorded in this article is intended to include all lower numerical limits contained therein, and any minimum numerical limit recorded in this specification is intended to include all higher numerical limits contained therein. Accordingly, the applicant reserves the right to modify the application documents including the claims to clearly record any sub-range contained in the range clearly recorded in this article. All such ranges are intended to be inherently described in this specification so that the modification for clearly recording any such sub-range will meet the requirements of Article 26, Paragraph 3 of the Chinese Patent Law and Article 33 of the Chinese Patent Law.

[0069] The electronic or electrical devices and / or any other related devices or components according to the embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware to process data or digital signals. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or a separate IC chip. Further, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), or a printed circuit board (PCB), or formed on a substrate. The circuit hardware may include, for example, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a graphics processing unit (GPU), a programmable logic device such as a field programmable gate array (FPGA), and a general or dedicated central processing unit (CPU) configured to execute instructions stored in a non-temporary storage medium.

[0070] Further, the various components of these devices can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. Computer program instructions are stored in a memory that can be implemented in a computing device using a standard memory device (such as, for example, a random access memory (RAM)). Computer program instructions may also be stored in other non-temporary computer-readable media (such as, for example, a CD-ROM or a flash drive, etc.). In addition, those skilled in the art will recognize that, without departing from the spirit and scope of the embodiments of the present disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed on one or more other computing devices.

[0071] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and / or this specification, and unless explicitly defined as such in this article, these terms should not be interpreted in an idealized or overly formal sense.

[0072] The embodiments described herein are merely examples. Those skilled in the art may recognize various alternative embodiments from those specifically disclosed. Those alternative embodiments are also intended to be within the scope of this disclosure. Therefore, the embodiments are limited only by the appended claims and their equivalents.

Claims

1. A circuit comprising: a data slicer configured to generate an output data value based on an input signal; The first error block; as well as Phase adjustment loop, including: a first error limiter configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values; a second error block configured to selectively output the first error signal in response to a second pattern in the output data values; and a voltage threshold modification circuit configured to adjust the threshold voltage based on an output of the second error block, The first mode and the second mode are different modes.

2. The circuit according to claim 1, wherein In response to the input voltage being greater than the threshold voltage, the first error signal is a positive value, or wherein in response to the input voltage being equal to or less than the threshold voltage, the first error signal is a negative value.

3. The circuit according to claim 2, wherein: The voltage threshold modification circuit comprises: A state machine is configured to selectively increment the threshold voltage in response to the input voltage of the first error limiter being greater than the threshold voltage.

4. The circuit according to claim 3, further comprising: a voltage controlled oscillator, wherein the data slicer and the first error slicer are clocked based on an output of the voltage controlled oscillator, The input voltage of the first error limiter is the output of the voltage-controlled oscillator.

5. The circuit according to claim 4, further comprising: a loop filter configured to control the frequency of the voltage controlled oscillator based on the output of the first error block, The loop filter is a low-pass filter configured to filter out noise from the output signal.

6. The circuit according to claim 4, wherein: The threshold voltage is initially set based on a peak value of the input signal.

7. The circuit according to claim 1, wherein: The first pattern and the second pattern each include 3 bits in the output data value.

8. The circuit according to claim 1, wherein: The phase adjustment loop further comprises: A second error limiter is configured to generate a second error signal based on a comparison of a negative value of the threshold voltage and the input voltage.

9. The circuit according to claim 8, wherein The first error block is further configured to selectively output an inverted second error signal in response to a third pattern in the output data values, wherein the third pattern is complementary to the first pattern.

10. The circuit according to claim 9, wherein: The second error block is further configured to selectively output the second error signal in response to a fourth pattern in the output data values, wherein the fourth pattern is complementary to the second pattern.

11. A method comprising: generating, by a data slicer, an output data value based on an input signal; generating a first error signal by a first error limiter based on a threshold voltage and an input voltage; selectively outputting, by a first error block, the first error signal in response to a first pattern in the output data values; selectively outputting, by a second error block, the first error signal in response to a second pattern in the output data values ​​that is different from the first pattern; as well as The threshold voltage is adjusted by a voltage threshold modification circuit based on an output of the second error block.

12. The method according to claim 11, wherein: In response to the input voltage being greater than the threshold voltage, the first error signal is a positive value, or wherein in response to the input voltage being equal to or less than the threshold voltage, the first error signal is a negative value.

13. The method according to claim 12, wherein: The adjusting the threshold voltage further comprises: The threshold voltage is selectively incremented in response to the input voltage of the first error limiter being greater than the threshold voltage.

14. The method according to claim 13, further comprising: The data slicer and the first error slicer are clocked by a voltage controlled oscillator, The input voltage of the first error limiter is the output of the voltage-controlled oscillator.

15. The method according to claim 14, further comprising: The threshold voltage is initially set based on a peak value of the input signal.

16. The method according to claim 11, wherein: The first pattern and the second pattern each include 3 bits in the output data value.

17. The method according to claim 11, further comprising: A second error signal is generated by a second error limiter based on a comparison of a negative value of the threshold voltage and the input voltage.

18. The method according to claim 17, further comprising: An inverted second error signal is selectively output by the first error block in response to a third pattern in the output data values, wherein the third pattern is complementary to the first pattern.

19. The method according to claim 18, further comprising: The second error signal is selectively output by the second error block in response to a fourth pattern in the output data values, wherein the fourth pattern is complementary to the second pattern.

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