Data transmission circuit, method and storage device

Abstract

The present application relates to a data transmission circuit, method and storage device, wherein the data transmission circuit includes a comparison module, a data conversion module and a read-write conversion circuit, wherein the comparison module is used to compare the first data on the received data bus with the second data on the global data line, and output a comparison result of whether the number of bits that are different between the first data and the second data exceeds a preset threshold; the data conversion module is used to invert the first data and transmit it to the global data line if the comparison result exceeds the preset threshold, and transmit the first data to the global data line if the comparison result does not exceed the preset threshold; the read-write conversion circuit is used to transmit the data on the global data line to the complementary local data line if the comparison result exceeds the preset threshold, and transmit the data on the global data line to the local data line if the comparison result does not exceed the preset threshold. The present application effectively reduces the power consumption during data transmission.

Description

Technical Field

[0001] The present application relates to the field of semiconductor storage technology, and in particular to a data transmission circuit, method and storage device. Background Art

[0002] With the rapid development of semiconductor technology, the market has higher and higher requirements on the storage capacity and power saving performance of semiconductor storage devices, which puts higher requirements on the power saving performance of the peripheral circuit area and storage array area of ​​the control circuit used to control reading and writing in the semiconductor storage device.

[0003] However, due to the increase in the density and number of memory cells in the memory cell array, in the process of writing data into the semiconductor memory device, the data is written into the data bus via the data terminal and transmitted to the subsequent data line. The length of the data transmission path increases, resulting in increased power consumption and reduced data transmission rate when the written data is transmitted to the local data line via the data terminal.

[0004] If it is possible to reduce the energy consumption in the process of writing data transmitted from a data terminal to a local data line while ensuring that the density and number of storage cells in a storage cell array are not reduced, it will increase the possibility of further improving the storage capacity and reducing energy consumption of semiconductor storage devices. Summary of the invention

[0005] Based on this, it is necessary to provide a data transmission circuit, method and storage device to address the technical problems in the above-mentioned background technology, so as to effectively reduce the energy consumption of writing data in the process of transmitting it to the subsequent data line via the data terminal.

[0006] To achieve the above-mentioned purpose and other purposes, the first aspect of the present application provides a data transmission circuit, including a comparison module, a data conversion module and a read-write conversion circuit, the comparison module is used to receive first data on a data bus and second data on a global data line, and compare the first data with the second data to output a comparison result of whether the number of bits that are different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width; the data conversion module is electrically connected to the data bus, the comparison module, and the global data line, and is used to invert the first data and transmit it to the global data line when the comparison result exceeds the preset threshold, and to transmit the first data to the global data line when the comparison result does not exceed the preset threshold; the read-write conversion circuit is electrically connected to the global data line, the local data line and the complementary local data line, and is used to transmit the data on the global data line to the complementary local data line when the comparison result exceeds the preset threshold, and to transmit the data on the global data line to the local data line when the comparison result does not exceed the preset threshold.

[0007] In the data transmission circuit in the above embodiment, a comparison module is set to receive the first data on the data bus and the second data on the global data line, and the first data and the second data are compared to output a comparison result of whether the number of bits that are different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width, so that when the comparison result exceeds the preset threshold, the data conversion module inverts the first data and transmits it to the global data line, and when the comparison result does not exceed the preset threshold, the first data is transmitted to the global data line, and the number of flips of data during transmission via the data bus, the global data line and the local data line, or via the data bus, the global data line and the complementary local data line is reduced under the premise of ensuring the accuracy of data transmission, so as to effectively reduce the power consumption during the transmission via the data bus, the global data line and the local data line, or via the data bus, the global data line and the complementary local data line. Thus, the energy consumption of the semiconductor storage device is reduced while ensuring that the density and number of storage cells in the storage cell array are not reduced.

[0008] In one embodiment, the read-write conversion circuit is configured as:

[0009] In the case where the comparison result exceeds the preset threshold, when the global data line is at a high potential, pulling the local data line to a low potential; and

[0010] In the case that the comparison result does not exceed the preset threshold, when the global data line is at a high potential, the complementary local data line is pulled down to a low potential.

[0011] In the data transmission circuit in the above embodiment, the read-write conversion circuit is configured to: when the comparison result output by the comparison module exceeds the preset threshold, when the global data line is at a high potential, pull the local data line to a low potential; and when the comparison result does not exceed the preset threshold, when the global data line is at a high potential, pull the complementary local data line to a low potential. In this way, when the comparison result exceeds the preset threshold, the read-write conversion circuit transfers the data on the global data line to the complementary local data line, and when the comparison result does not exceed the preset threshold, transfers the data on the global data line to the local data line, so that the data on the data bus can be accurately transmitted to the local data line or the complementary local data line, and the number of flips during the data transmission process is reduced, so as to effectively reduce the power consumption during the data transmission process via the data bus, the global data line and the local data line, or via the data bus, the global data line and the complementary local data line.

[0012] In one embodiment, the preset threshold is half of the preset bit width; the comparison module includes a comparison unit and a state identification unit, the comparison unit is used to compare the first data and the second data bit by bit, and output the comparison state data of each bit; the state identification unit is electrically connected to the comparison unit, and is used to count the comparison state data of each bit, and output the comparison result according to the statistical result.

[0013] In one embodiment, the data conversion module includes a first transmission unit, a first inverting unit, a second transmission unit and a second inverting unit. The first transmission unit is electrically connected to the data bus and the global data line, and is electrically connected to the output end of the state identification unit through the first inverting unit, and is used to transmit the first data to the global data line when the comparison result does not exceed the preset threshold value; the second transmission unit is electrically connected to the global data line and the output end of the state identification unit, and is electrically connected to the data bus through the second inverting unit, and is used to invert the first data and transmit it to the global data line when the comparison result exceeds the preset threshold value.

[0014] In one embodiment, the data conversion module is electrically connected to the read-write conversion circuit through a data bus buffer module; the data bus buffer module is also electrically connected to the state identification unit, for generating a data polarity identification signal according to the comparison result; wherein the data bus buffer module includes a write unit, and the write unit is used to transmit the first data or the first data after inversion to the global data line.

[0015] In one embodiment, the read-write conversion circuit includes a write enable module and a write drive circuit, the write enable module generates a write enable signal and a write enable inverse signal according to the data polarity identification signal and the initial write enable signal; the write drive circuit is used to generate third data according to the write enable signal, the write enable inverse signal and the second data, and transmit the third data to the local data line or the complementary local data line.

[0016] In one embodiment, the write enable module includes a first inverter, a first NOR gate, a second inverter and a second NOR gate, the first inverter is configured as: the input end is electrically connected to the initial write enable signal, and the output end outputs the first write enable inverse signal; the first NOR gate is configured as: the input end is electrically connected to the data polarity identification signal and the output end of the first inverter, and the output end outputs the write enable signal; the second inverter is configured as: the input end is electrically connected to the data polarity identification signal, and the output end outputs the data polarity identification inverse signal; the second NOR gate is configured as: the input end is electrically connected to the output end of the second inverter and the output end of the first inverter, and the output end outputs the write enable inverse signal.

[0017] In one embodiment, the write drive circuit includes a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit and a sixth switch unit, the first switch unit is used to electrically connect the complementary local data line and the global data line according to the write enable inverse signal; the second switch unit is configured as: the control end is electrically connected to the global data line, the first end is electrically connected to the local data line, and the second end is electrically connected to the first node; the third switch unit is used to electrically connect the first node and ground according to the write enable inverse signal; the fourth switch unit is used to electrically connect the local data line and the global data line according to the write enable signal; the fifth switch unit is configured as: the control end is electrically connected to the global data line, the first end is electrically connected to the complementary local data line, and the second end is electrically connected to the second node; the sixth switch unit is used to electrically connect the second node and ground according to the write enable signal.

[0018] In one embodiment, the data conversion module is further used to invert the second data and transmit it to the data bus when the comparison result exceeds the preset threshold, and to transmit the second data to the data bus when the comparison result does not exceed the preset threshold.

[0019] In one embodiment, the data conversion module also includes a third transmission unit, a third inverting unit, a fourth transmission unit and a fourth inverting unit. The third transmission unit is electrically connected to the data bus and the global data line, and is electrically connected to the output end of the comparison module through the third inverting unit, and is used to transmit the second data to the data bus when the comparison result does not exceed the preset threshold value; the fourth transmission unit is electrically connected to the data bus, the output end of the comparison module, and is electrically connected to the global data line through the fourth inverting unit, and is used to invert the second data and transmit it to the data bus when the comparison result exceeds the preset threshold value.

[0020] In one embodiment, the data bus buffer module further includes a reading unit, and the reading unit is used to transmit the second data to a third transmission unit, or to invert the second data through the fourth inversion unit and then transmit it to a fourth transmission unit.

[0021] In one embodiment, the data transmission circuit further includes a precharging circuit, which is electrically connected to the local data line and the complementary local data line, and is used to precharge the local data line and the complementary local data line to a high potential before the global data line transmits data to the local data line or the complementary local data line, so that when the comparison result output by the comparison module exceeds a preset threshold, the read-write conversion circuit pulls down the local data line to a low potential when the global data line is at a high potential to achieve data transmission; and when the comparison result does not exceed the preset threshold, the read-write conversion circuit pulls down the complementary local data line to a low potential when the global data line is at a high potential to achieve data transmission.

[0022] A second aspect of the present application provides a storage device, comprising any data transmission circuit described in any embodiment of the present application, for storing and transmitting data of a read operation or a write operation.

[0023] A third aspect of the present application provides a data transmission method, including:

[0024] Compare first data on a data bus with second data on a global data line, and output a comparison result of whether the number of bits that are different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width;

[0025] If the comparison result exceeds a preset threshold, the first data is inverted and then transmitted to the global data line; otherwise, the first data is transmitted to the global data line;

[0026] When the comparison result exceeds the preset threshold, the data on the global data line is transmitted to the complementary local data line, and when the comparison result does not exceed the preset threshold, the data on the global data line is transmitted to the local data line, wherein the local data line and the complementary local data line transmit signals with opposite phases.

[0027] In one of the embodiments, the preset threshold is half of the preset bit width, and the method further includes:

[0028] If the comparison result exceeds the preset threshold, the second data is inverted and then transmitted to the data bus; otherwise, the second data is transmitted to the data bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 A schematic diagram of a circuit principle of a data transmission circuit provided in the first embodiment of the present application;

[0031] Figure 2 A schematic diagram of a circuit principle of a data transmission circuit provided in the second embodiment of the present application;

[0032] Figure 3a A schematic diagram of a circuit principle of a data transmission circuit provided in the third embodiment of the present application;

[0033] Figure 3b for Figure 3a A schematic diagram of an implementation method;

[0034] Figure 4 A schematic diagram of a circuit principle of a data transmission circuit provided in a fourth embodiment of the present application;

[0035] Figure 5 A schematic diagram of a circuit principle of a data transmission circuit provided in a fifth embodiment of the present application;

[0036] Figure 6A circuit diagram of a write enable module in a data transmission circuit provided in an embodiment of the present application;

[0037] Figure 7 A circuit diagram of a write drive circuit in a data transmission circuit provided in an embodiment of the present application;

[0038] Figure 8a A schematic diagram of a circuit principle of a data transmission circuit provided in a sixth embodiment of the present application;

[0039] Figure 8b for Figure 8a A schematic diagram of an implementation method;

[0040] Fig. 9 A schematic diagram of a circuit principle of a data transmission circuit provided in the seventh embodiment of the present application;

[0041] Fig.10 A schematic diagram of a circuit principle of a data transmission circuit provided in an eighth embodiment of the present application;

[0042] Fig.11 A structural block diagram of a storage device provided in an embodiment of the present application;

[0043] Fig.12 A flowchart of a data transmission method provided in an embodiment of the present application;

[0044] Fig.13 A flowchart of a data transmission method provided in another embodiment of the present application is shown.

[0045] Description of reference numerals:

[0046] 100. Data transmission circuit; 10. Comparison module; 20. Data conversion module; 30. Data bus; 40. Global data line; 11. Comparison unit; 12. State identification unit; 21. First transmission unit; 22. First inverting unit; 23. Second transmission unit; 24. Second inverting unit; 25. Third transmission unit; 26. Third inverting unit; 27. Fourth transmission unit; 28. Fourth inverting unit; 50. Data bus buffer module; 51. Write unit; 52. Read unit; 70. Read-write conversion circuit; 71. Write enable module; 72. Write drive circuit; 73. Read drive circuit; 721. First switch unit; 722. Second switch unit; 723. Third switch unit; 724. Fourth switch unit; 725. Fifth switch unit; 726. Sixth switch unit; 81. Local data line; 82. Complementary local data line; 90. Precharge circuit; 200. Storage device. DETAILED DESCRIPTION

[0047] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present application belongs. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. In addition, certain terms used throughout the specification and the claims that follow refer to specific elements. It will be understood by those skilled in the art that manufacturers may refer to elements by different names. This document does not intend to distinguish between elements with different names but the same functions. In the following description and embodiments, the terms "include" and "include" are open-ended and should therefore be interpreted as "include, but not limited to...". Similarly, the term "connection" is intended to express an indirect or direct electrical connection. Accordingly, if a device is connected to another device, the connection can be completed by a direct electrical connection or by an indirect electrical connection through other devices and connectors.

[0049] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0050] Please refer to Figure 1In one embodiment of the present application, a data transmission circuit 100 is provided, including a comparison module 10, a data conversion module 20 and a read-write conversion circuit 70, wherein the comparison module 10 is used to receive first data on a data bus 30 and second data on a global data line 40, and compare the first data with the second data to output a comparison result of whether the number of bits that are different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width; the data conversion module 20 is electrically connected to the data bus 30, the comparison module 10, and the global data line 40, and is used to invert the first data and transmit it to the global data line 40 when the comparison result exceeds the preset threshold, and transmit the first data to the global data line 40 when the comparison result does not exceed the preset threshold; the read-write conversion circuit 70 is electrically connected to the global data line 40, the local data line 81, and the complementary local data line 82, and is used to transmit the data on the global data line 40 to the complementary local data line 82 when the comparison result exceeds the preset threshold, and transmit the data on the global data line 40 to the local data line 81 when the comparison result does not exceed the preset threshold.

[0051] In one embodiment, the local data line 81 and the complementary local data line 82 transmit signals with opposite phases.

[0052] As an example, please refer to Figure 1 , by setting a comparison module 10 to receive the first data on the data bus 30 and the second data on the global data line 40, and compare the first data with the second data to output a comparison result of whether the number of bits that are different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width, so that the data conversion module 20 inverts the first data and transmits it to the global data line 40 when the comparison result exceeds the preset threshold, and transmits the first data to the global data line 40 when the comparison result does not exceed the preset threshold, and reduces the number of flips during the transmission of data via the data bus 30, the global data line 40 and the local data line 81, or the data via the data bus 30, the global data line 40 and the complementary local data line 82, while ensuring the accuracy of data transmission, so as to effectively reduce the power consumption during the transmission of data via the data bus 30, the global data line 40 and the local data line 81, or the data via the data bus 30, the global data line 40 and the complementary local data line 82. Thereby, the energy consumption of the semiconductor memory device 200 is reduced while ensuring that the density and number of memory cells in the memory cell array are not reduced. Since the data transmitted by the local data line 81 and the complementary local data line 82 can be used as references to each other, the accuracy of data transmission to the subsequent circuit is improved while ensuring the data transmission efficiency.

[0053] It should be noted that the data bus 30 in the embodiment of the present application is intended to schematically illustrate the preceding data line of the global data line 40 in the process of writing data into the semiconductor storage device, and is not intended to limit the present application.

[0054] For further information, please refer to Figure 1 In one embodiment of the present application, the read-write conversion circuit 70 is configured as follows:

[0055] When the comparison result exceeds the preset threshold, when the global data line 40 is at a high potential, the local data line 81 is pulled down to a low potential; and

[0056] When the comparison result does not exceed the preset threshold, when the global data line 40 is at a high potential, the complementary local data line 82 is pulled down to a low potential.

[0057] As an example, please refer to Figure 1 , by configuring the read-write conversion circuit 70 to: when the comparison result output by the comparison module 10 exceeds the preset threshold, when the global data line 40 is at a high potential, pull the local data line 81 down to a low potential; and when the comparison result does not exceed the preset threshold, when the global data line 40 is at a high potential, pull the complementary local data line 82 down to a low potential. It is convenient for the read-write conversion circuit 70 to transfer the data on the global data line 40 to the complementary local data line 82 when the comparison result exceeds the preset threshold, and to transfer the data on the global data line 40 to the local data line 81 when the comparison result does not exceed the preset threshold, so that the data on the data bus 30 can be accurately transmitted to the local data line 81 or the complementary local data line 82, and the number of flips during the data transmission process is reduced, so as to effectively reduce the power consumption during the data transmission process via the data bus 30, the global data line 40 and the local data line 81, or the data via the data bus 30, the global data line 40 and the complementary local data line 82.

[0058] For further information, please refer to Figure 2 In one embodiment of the present application, the preset threshold is half of the preset bit width; the comparison module 10 includes a comparison unit 11 and a state recognition unit 12, the comparison unit 11 is used to compare the first data and the second data bit by bit, and output the comparison state data of each bit; the state recognition unit 12 is electrically connected to the comparison unit 11, and is used to count the comparison state data of each bit, and output the comparison result according to the statistical result. This embodiment reduces the number of data flips while ensuring the accuracy of data transmission, so as to effectively reduce the power consumption during data transmission.

[0059] As an example, see Figure 3a and Figure 3bIn one embodiment of the present application, the data conversion module 20 includes a first transmission unit 21, a first inverting unit 22, a second transmission unit 23 and a second inverting unit 24. The first transmission unit 21 is electrically connected to the data bus 30 and the global data line 40, and is electrically connected to the output end of the state recognition unit 12 through the first inverting unit 22, and is used to transmit the first data to the global data line 40 when the comparison result output by the comparison module 10 does not exceed the preset threshold value; the second transmission unit 23 is electrically connected to the global data line 40 and the output end of the state recognition unit 12, and is electrically connected to the data bus 30 through the second inverting unit 24, and is used to invert the first data and transmit it to the global data line 40 when the comparison result output by the comparison module 10 exceeds the preset threshold value.

[0060] For further information, please refer to Figure 4 In one embodiment of the present application, the data conversion module 20 is electrically connected to the read-write conversion circuit 70 through the data bus buffer module 50; the data bus buffer module 50 is also electrically connected to the state recognition unit 12, for generating a data polarity identification signal according to the comparison result; wherein the data bus buffer module 50 includes a write unit 51, and the write unit 51 is used to transmit the first data or the first data after inversion to the global data line 40. The number of data flips is reduced while ensuring the accuracy of data transmission, and the power consumption of data in the process of writing the data into the global data line 40 via the data bus 30 is effectively reduced.

[0061] For further information, please refer to Figure 5 In one embodiment of the present application, the read-write conversion circuit 70 includes a write enable module 71 and a write drive circuit 72. The write enable module 71 generates a write enable signal WrEn and a write enable inverse signal WrEn_ according to the data polarity identification signal pl and the initial write enable signal WrEn; the write drive circuit 72 is used to generate third data according to the write enable signal WrEn, the write enable inverse signal WrEn_ and the second data, and transmit the third data to the local data line 81 or the complementary local data line 82 to ensure the accuracy of data transmission.

[0062] For further information, please refer to Figure 6In one embodiment of the present application, the write enable module 71 includes a first inverter Inv1, a first NOR gate Nor1, a second inverter Inv2 and a second NOR gate Nor2. The first inverter Inv1 is configured as follows: the input end is electrically connected to the initial write enable signal WrEn, and the output end outputs the first write enable inverse signal We1_; the first NOR gate Nor1 is configured as follows: the input end is electrically connected to the data polarity identification signal pl and the output end of the first inverter Inv1, and the output end outputs the write enable signal WrEn; the second inverter Inv2 is configured as follows: the input end is electrically connected to the data polarity identification signal pl, and the output end outputs the data polarity identification inverse signal Pl_; the second NOR gate Nor2 is configured as follows: the input end is electrically connected to the output end of the second inverter Inv2 and the output end of the first inverter Inv1, and the output end outputs the write enable inverse signal WrEn_. Thus, the write driver circuit 72 can be controlled according to the write enable signal WrEn and the write enable inverse signal WrEn_ to generate third data according to the data on the global data line 40, and the third data can be transmitted to the local data line LIO or the complementary local data line LIO_ to realize the recovery of the transmitted data and ensure the accuracy of data transmission.

[0063] For further information, please refer to Figure 7 In one embodiment of the present application, the write drive circuit 72 includes a first switch unit 721, a second switch unit 722, a third switch unit 723, a fourth switch unit 724, a fifth switch unit 725 and a sixth switch unit 726. The first switch unit 721 is used to electrically connect the complementary local data line LIO_ and the global data line YIO according to the write enable inverse signal WrEn_; the second switch unit 722 is configured as: the control end is electrically connected to the global data line YIO, the first end is electrically connected to the local data line LIO, and the second end is electrically connected to the first node a; the third switch unit 723 is used to electrically connect the first node a and the ground according to the write enable inverse signal WrEn_; the fourth switch unit 724 is used to electrically connect the local data line LIO and the global data line YIO according to the write enable signal WrEn; the fifth switch unit 725 is configured as: the control end is electrically connected to the global data line YIO, the first end is electrically connected to the complementary local data line LIO_, and the second end is electrically connected to the second node b; the sixth switch unit 726 is used to electrically connect the second node b and the ground according to the write enable signal WrEn. This embodiment reduces the number of flips during the data writing process, thereby effectively reducing the power consumption when data is written into the local data line LIO or the complementary local data line LIO_ via the data bus Data bus and the global data line YIO, and especially reduces the data flipping of the global data line YIO.

[0064] For further information, please refer to Figure 8a and Figure 8bIn one embodiment of the present application, the data conversion module 20 is further used to invert the second data and transmit it to the data bus 30 when the comparison result output by the comparison unit 11 exceeds a preset threshold value, such as half of a preset bit width, and is also used to transmit the second data to the data bus 30 when the comparison result does not exceed the preset threshold value. For example, in the process of reading data, when the comparison result output by the comparison unit 11 exceeds a preset threshold value, such as half of a preset bit width, the data conversion module 20 inverts the second data provided by the global data line 40 and transmits it to the data bus 30, and when the comparison result output by the comparison unit 11 does not exceed the preset threshold value, the data conversion module 20 transmits the second data provided by the global data line 40 to the data bus 30. This effectively reduces the power consumption of the read data in the process of transmitting it to the data bus 30 via the global data line 40.

[0065] For further information, please refer to Fig. 9 In one embodiment of the present application, the data conversion module 20 further includes a third transmission unit 25, a third inverting unit 26, a fourth transmission unit 27 and a fourth inverting unit 28. The third transmission unit 25 is electrically connected to the data bus 30 and the global data line 40, and is electrically connected to the output end of the comparison module 10 through the third inverting unit 26, and is used to transmit the second data to the data bus 30 when the comparison result output by the comparison module 10 does not exceed the preset threshold value; the fourth transmission unit 27 is electrically connected to the data bus 30 and the output end of the comparison module 10, and is electrically connected to the global data line 40 through the fourth inverting unit 28, and is used to invert the second data and transmit it to the data bus 30 when the comparison result output by the comparison module 10 exceeds the preset threshold value. This embodiment can accurately transmit the data on the global data line to the data bus, and reduce the number of flips during the data transmission process, so as to effectively reduce the power consumption of the data during the data reading process and the data transmission process via the global data line and the data bus.

[0066] For further information, please refer to Fig.10In one embodiment of the present application, the data bus buffer module 50 further includes a read unit 52, which is used to transmit the second data to the third transmission unit 25, or to invert the second data through the fourth inversion unit 28 and transmit it to the fourth transmission unit 27. For example, in the process of reading data, when the comparison result output by the comparison unit 11 exceeds a preset threshold value, such as half of a preset bit width, the fourth transmission unit 27 inverts the second data provided by the global data line YIO and transmits it to the data bus 30, and when the comparison result output by the comparison unit 11 does not exceed the preset threshold value, the third transmission unit 25 transmits the second data provided by the global data line 40 to the data bus 30. This embodiment can effectively reduce the power consumption of the read data in the process of transmitting it to the data bus 30 via the global data line 40.

[0067] For further information, please refer to Fig.11 In one embodiment of the present application, a storage device 200 is provided, comprising a transmission circuit 100 described in any one of the embodiments of the present application, for storing and transmitting data of a read operation or a write operation.

[0068] For the specific definition of the storage device 200 in the above embodiment, reference may be made to the specific definition of the transmission circuit 100 above, which will not be repeated here.

[0069] For further information, please refer to Fig.12 In one embodiment of the present application, a data transmission method is provided, comprising:

[0070] Step 102, comparing first data on the data bus with second data on the global data line, and outputting a comparison result of whether the number of bits that are different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width;

[0071] Step 104, if the comparison result exceeds a preset threshold, the first data is inverted and then transmitted to the global data line; otherwise, the first data is transmitted to the global data line;

[0072] Step 106, when the comparison result exceeds the preset threshold, the data on the global data line is transferred to the complementary local data line, and when the comparison result does not exceed the preset threshold, the data on the global data line is transferred to the local data line.

[0073] In one embodiment, the local data line and the complementary local data line transmit signals with opposite phases.

[0074] For details, please continue to refer to Fig.12, by comparing the first data on the data bus with the second data on the global data line, and outputting the comparison result of whether the number of bits that are different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width; if the comparison result exceeds the preset threshold, the first data is inverted and transmitted to the global data line; otherwise, the first data is transmitted to the global data line; and if the comparison result exceeds the preset threshold, the second data is inverted and transmitted to the data bus, and if the comparison result does not exceed the preset threshold, the second data is transmitted to the data bus. Since the transmitted data generally includes a data string composed of 0 and 1, by applying the power saving algorithm to the data transmission process via the data bus, the global data line and the local data line, or the data transmission process via the data bus, the global data line and the complementary local data line, the number of data flips is reduced under the premise of ensuring the accuracy of data transmission, so as to effectively reduce the power consumption during the data transmission process via the data bus, the global data line and the local data line, or the data transmission process via the data bus, the global data line and the complementary local data line. Thereby, the energy consumption of the semiconductor storage device is reduced while ensuring that the density and number of storage cells in the storage cell array are not reduced. Since the data transmitted by the local data line and the complementary local data line can serve as a reference to each other, the accuracy of data transmission to the subsequent circuit is improved while ensuring the data transmission efficiency.

[0075] For further information, please refer to Fig.13 In one embodiment of the present application, the method includes:

[0076] Step 102, comparing first data on the data bus with second data on the global data line, and outputting a comparison result of whether the number of bits that are different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width;

[0077] Step 1041, if the comparison result exceeds a preset threshold, the first data is inverted and then transmitted to the global data line; otherwise, the first data is transmitted to the global data line, and the preset threshold is half of the preset bit width;

[0078] Step 106, if the comparison result exceeds the preset threshold, the data on the global data line is transferred to the complementary local data line, and if the comparison result does not exceed the preset threshold, the data on the global data line is transferred to the local data line;

[0079] Step 108: If the comparison result exceeds the preset threshold, the second data is inverted and then transmitted to the data bus; otherwise, the second data is transmitted to the data bus.

[0080] As an example, please refer to Fig.10 and Fig.13 In the process of writing data, when the comparison result output by the comparison module 10 exceeds the preset threshold, for example, half of the preset bit width, the second transmission unit 23 inverts the first data and transmits it to the global data line 40; and when the comparison result output by the comparison module 10 does not exceed the preset threshold, the first transmission unit 21 transmits the first data to the global data line 40. This effectively reduces the power consumption of the written data in the process of being transmitted to the global data line 40 via the data bus 30. In the process of reading data, when the comparison result output by the comparison unit 11 exceeds the preset threshold, the fourth transmission unit 27 inverts the second data provided by the global data line 40 and transmits it to the data bus 30, and when the comparison result output by the comparison unit 11 does not exceed the preset threshold, the third transmission unit 25 transmits the second data provided by the global data line 40 to the data bus 30. This embodiment can effectively reduce the power consumption of the read data in the process of being transmitted to the data bus 30 via the global data line 40.

[0081] In one embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the data transmission method described in any embodiment of the present application is implemented.

[0082] It should be understood that although Fig.12 , Fig.13 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Fig.12 , Fig.13 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0083] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0084] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present invention.

[0085] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A data transmission circuit, characterized in that: include: a comparison module, configured to receive first data on a data bus and second data on a global data line, and compare the first data with the second data to output a comparison result of whether the number of bits that are different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width; a data conversion module, electrically connected to the data bus, the comparison module, and the global data line, and configured to invert the first data and transmit it to the global data line if the comparison result exceeds a preset threshold, and transmit the first data to the global data line if the comparison result does not exceed the preset threshold; a read-write conversion circuit, electrically connected to the global data line, the local data line and the complementary local data line, for transferring the data on the global data line to the complementary local data line when the comparison result exceeds a preset threshold, and for transferring the data on the global data line to the local data line when the comparison result does not exceed the preset threshold; The preset threshold is half of the preset bit width; the comparison module includes: a comparing unit, used for comparing the first data and the second data bit by bit, and outputting comparison status data of each bit; A state recognition unit, electrically connected to the comparison unit, for collecting statistics on each bit of the comparison state data and outputting the comparison result according to the statistical result; The data conversion module is electrically connected to the read-write conversion circuit via a data bus buffer module; The data bus buffer module is also electrically connected to the state identification unit, and is used to generate a data polarity identification signal according to the comparison result; Wherein, the data bus buffer module comprises a writing unit, and the writing unit is used to transmit the first data or the first data after being inverted to the global data line; The read-write conversion circuit comprises: A write enable module, wherein the write enable module generates a write enable signal and a write enable inverse signal according to the data polarity identification signal and the initial write enable signal; A write driving circuit is used to generate third data according to the write enable signal, the write enable inverse signal and the second data, and transmit the third data to the local data line or the complementary local data line.

2. The data transmission circuit according to claim 1, characterized in that: The read-write conversion circuit is configured as follows: In the case where the comparison result exceeds the preset threshold, when the global data line is at a high potential, the local data line is pulled down to a low potential; as well as In the case that the comparison result does not exceed the preset threshold, when the global data line is at a high potential, the complementary local data line is pulled down to a low potential.

3. The data transmission circuit according to claim 1, characterized in that: The data conversion module comprises: a first transmission unit, electrically connected to the data bus and the global data line, and electrically connected to the output end of the state recognition unit through a first inverting unit, and configured to transmit the first data to the global data line when the comparison result does not exceed the preset threshold; A second transmission unit is electrically connected to the global data line and the output end of the state identification unit, and is electrically connected to the data bus through a second inverting unit, and is used for inverting the first data and transmitting it to the global data line when the comparison result exceeds the preset threshold.

4. The data transmission circuit according to claim 1, characterized in that: The write enable module comprises: A first inverter is configured to: have an input terminal electrically connected to an initial write enable signal, and an output terminal output a first write enable inverse signal; A first NOR gate, configured as follows: an input end electrically connected to the data polarity identification signal and an output end of the first inverter, and an output end outputting a write enable signal; A second inverter is configured to: have an input terminal electrically connected to a data polarity identification signal, and an output terminal output a data polarity identification inverse signal; The second NOR gate is configured as follows: an input end is electrically connected to an output end of the second inverter and an output end of the first inverter, and an output end outputs a write enable inverse signal.

5. The data transmission circuit according to claim 4, characterized in that: The write drive circuit comprises: a first switch unit, configured to electrically connect the complementary local data line and the global data line according to the write enable inverse signal; A second switch unit is configured as follows: a control end is electrically connected to the global data line, a first end is electrically connected to the local data line, and a second end is electrically connected to the first node; a third switch unit, configured to electrically connect the first node and ground according to the write enable inverse signal; a fourth switch unit, configured to electrically connect the local data line and the global data line according to the write enable signal; A fifth switch unit is configured as follows: a control end is electrically connected to the global data line, a first end is electrically connected to the complementary local data line, and a second end is electrically connected to the second node; A sixth switch unit is used to electrically connect the second node and ground according to the write enable signal.

6. The data transmission circuit according to any one of claims 1 to 5, characterized in that: The data conversion module is further used to invert the second data and transmit it to the data bus when the comparison result exceeds the preset threshold, and to transmit the second data to the data bus when the comparison result does not exceed the preset threshold.

7. The data transmission circuit according to claim 6, characterized in that: The data conversion module also includes: a third transmission unit, electrically connected to the data bus and the global data line, and electrically connected to the output end of the comparison module through a third inverting unit, and configured to transmit the second data to the data bus when the comparison result does not exceed the preset threshold; A fourth transmission unit is electrically connected to the data bus, the output end of the comparison module, and is electrically connected to the global data line through a fourth inverting unit, and is used for inverting the second data and transmitting it to the data bus when the comparison result exceeds the preset threshold.

8. The data transmission circuit according to claim 7, characterized in that: The data bus buffer module also includes: The reading unit is used to transmit the second data to the third transmission unit, or to invert the second data through the fourth inversion unit and then transmit it to the fourth transmission unit.

9. The data transmission circuit according to any one of claims 1 to 5, characterized in that: Also includes: A precharge circuit is electrically connected to the local data line and the complementary local data line, and is used to precharge the local data line and the complementary local data line to a high potential before the global data line transmits data to the local data line or the complementary local data line.

10. A storage device, characterized in that: include: The data transmission circuit according to any one of claims 1 to 9, is used to store and transmit data of a read operation or a write operation.

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