Light emitting control unit and control method thereof, gate driving circuit and display device

Abstract

The present application discloses a light-emitting control unit and a control method thereof, a gate driving circuit and a display device. The light-emitting control unit of the embodiment of the present application includes: a setting subcircuit, including a first transistor and a second transistor, the first end of the first transistor is connected to the first power signal end, the second end is connected to the first node, and the control end is connected to the clock signal end independent of the shift register unit, the first end of the second transistor is connected to the second node, the second end is connected to the second power signal end, and the control end is connected to the clock signal end; a reset subcircuit, in response to the control of the reset signal, the first node is reset through the second power signal and the potential of the second node is pulled up through the first power signal; an output subcircuit, based on the potential control of the first node and the second node, the first power signal or the second power signal is output. The embodiment of the present application provides a light-emitting control unit with a simple structure through the setting subcircuit, the reset subcircuit and the output subcircuit.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a light emitting control unit and a control method thereof, a gate driving circuit and a display device. Background Art

[0002] The more mature technologies in the display field are LCD display technology and active matrix OLED display technology. The display device formed by OLED display technology has a fast response speed and can maximize the contrast, so OLED display devices are expected to become the next generation of mainstream display products.

[0003] Generally, an OLED display device includes: a display panel and a gate driving circuit (GOA circuit) directly formed on the panel, wherein the gate driving circuit includes a shift register unit for forming a pixel scanning signal and a light control circuit for forming a light emitting control signal EM of the pixel, and the light emitting control signal is used to control the light emitting control tube in the pixel driving circuit.

[0004] The light-emitting control tube is used to control the light-emitting time of the pixel. It is a pulse signal in a frame of image. In the related technology, it is usually a PWM module or a cascade unit, which is not conducive to narrow frame design. Summary of the invention

[0005] In order to solve at least one of the above problems, the first aspect of the present application provides a light emitting control unit, characterized in that it includes:

[0006] A setting subcircuit, comprising a first transistor and a second transistor, wherein the first terminal of the first transistor is electrically connected to the first power signal terminal, the second terminal is electrically connected to the first node, and the control terminal is electrically connected to the clock signal terminal independent of the shift register unit; the first terminal of the second transistor is electrically connected to the second node, the second terminal is electrically connected to the second power signal terminal, and the control terminal is electrically connected to the clock signal terminal, and is configured to set the first node through the first power signal of the first power signal terminal in response to the control of the clock signal of the clock signal terminal and pull down the potential of the second node through the second power signal of the second power signal terminal;

[0007] a reset subcircuit, in response to the control of the reset signal of the reset signal terminal, resetting the first node through the second power signal and pulling up the potential of the second node through the first power signal; and

[0008] The output subcircuit controls the output of the first power signal or the second power signal based on the potential of the first node and the potential of the second node.

[0009] In some optional embodiments, the reset subcircuit includes: a third transistor and a fourth transistor,

[0010] Among them, the first end of the third transistor is electrically connected to the first power signal end, the second end is electrically connected to the second node, and the control end is electrically connected to the reset signal end; the first end of the fourth transistor is electrically connected to the first node, the second end is electrically connected to the second power signal end, and the control end is electrically connected to the second node.

[0011] In some optional embodiments, the output subcircuit includes a fifth transistor and a sixth transistor,

[0012] Among them, the first end of the fifth transistor is electrically connected to the first power signal end, the second end is electrically connected to the output end, and the control end is electrically connected to the first node; the first end of the sixth transistor is electrically connected to the output end, the second end is electrically connected to the second power signal end, and the control end is electrically connected to the second node.

[0013] In some optional embodiments, a storage subcircuit is further included, the storage subcircuit includes a first storage capacitor and a second storage capacitor.

[0014] The first end of the first storage capacitor is electrically connected to the first node, and the second end is electrically connected to the output end. The first end of the second storage capacitor is electrically connected to the second node, and the second end is electrically connected to the second power signal end.

[0015] In some optional embodiments, the first power signal at the first power signal terminal is a high level signal, and the second power signal at the second power signal terminal is a low level signal.

[0016] In some optional embodiments, the transistor in the light emitting control unit is an N-type transistor or a P-type transistor.

[0017] A second aspect of the present application provides a gate driving circuit, comprising: a plurality of cascaded shift register units and a plurality of light emitting control units as described above, wherein the light emitting control units correspond to the shift register units one by one,

[0018] Wherein, the output end of each shift register unit is electrically connected to the reset signal end of the corresponding light emitting control unit; and

[0019] Each shift register unit includes a first clock signal terminal electrically connected to a first clock signal line, and the shift register unit generates a gate scanning signal under the control of a clock signal connected to the first clock signal terminal.

[0020] The clock signal end of each light emitting control unit is electrically connected to the second clock signal line, and the first clock signal line and the second clock signal line are independent clock signal lines.

[0021] A third aspect of the present application provides a display device, comprising the gate driving circuit described above.

[0022] A fourth aspect of the present application provides a light emission control method for the light emission control unit described above, comprising:

[0023] In the first stage, the setting subcircuit transmits the first power signal to the first node in response to the received setting signal, so that the output end of the output subcircuit outputs the first power signal.

[0024] In the second stage, the reset signal transmits the first power signal to the second node in response to the received reset signal, so as to reset the first node through the second power signal and make the output end of the output subcircuit output the second power signal; and

[0025] In the third stage, the setting signal is applied to the setting subcircuit again so that the output end of the output subcircuit outputs the first power signal.

[0026] In some optional embodiments,

[0027] The light emitting control unit further includes a storage subcircuit, the storage subcircuit includes a first storage capacitor and a second storage capacitor, wherein a first end of the first storage capacitor is electrically connected to the first node, and a second end is electrically connected to the output terminal, a first end of the second storage capacitor is electrically connected to the second node, and a second end is electrically connected to the second power signal terminal,

[0028] The method further comprises:

[0029] In the second phase, the potentials of the first node and the second node are maintained by the first storage capacitor and the second storage capacitor.

[0030] The beneficial effects of this application are as follows:

[0031] In response to the existing problems, the present application develops a light-emitting control unit and a control method thereof, a gate driving circuit and a display device. The light-emitting control unit is provided with a setting subcircuit, a reset subcircuit and an output subcircuit, and the setting subcircuit is set to include a first transistor and a second transistor, which is configured to set a first node through a first power signal at a first power signal end in response to the control of a clock signal at a clock signal end, and to pull down the potential of a second node through a second power signal at a second power signal end, thereby providing a stable light-emitting control signal with a simple circuit structure, and the structure does not require cascading, which is conducive to a narrow frame design; in addition, by electrically connecting the control ends of the first transistor and the second transistor to a clock signal end independent of a shift register unit, the light-emitting time of a pixel can be flexibly controlled through an independent clock signal, and the application has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic structural block diagram showing main sub-circuits included in a light emitting control unit according to an embodiment of the present application;

[0034] Figure 2 A schematic circuit diagram showing a light emitting control unit according to an embodiment of the present application;

[0035] Figure 3 A schematic timing diagram of a light emitting control unit according to an embodiment of the present application is shown;

[0036] Figure 4 A cascade diagram of a shift register unit and a light emitting control unit according to an embodiment of the present application is shown;

[0037] Figure 5 Show Figure 4 A schematic diagram of a shift register unit in the cascade diagram shown;

[0038] Figure 6 A schematic diagram showing a shift register unit in a display device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0039] In order to more clearly illustrate the present application, the present application is further described below in conjunction with preferred embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the present application.

[0040] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "one", "one" and other similar words do not indicate a quantitative limit, but indicate that there is at least one. "Include" or "comprises" and other similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0041] The transistor used in the embodiment of the present application can be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, there is no difference between the source and drain. In the embodiment of the present application, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first end, the other electrode is called the second end, and the gate is called the control end. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiments are explained with N-type transistors. When an N-type transistor is used, the first end is the drain of the N-type transistor, and the second end is the source of the N-type transistor. When the gate inputs a high level, the source and drain are turned on. On the contrary, when the gate inputs a low level, the source and drain are turned on. It can be thought that the use of P-type transistors is something that a person skilled in the art can easily think of without paying creative labor, so it is also within the scope of protection of the embodiments of the present application.

[0042] Based on the above problems, refer to Figure 1 As shown, an embodiment of the present application provides a light emitting control unit, comprising:

[0043] The setting sub-circuit 110 includes a first transistor T1 and a second transistor T2, wherein the first end of the first transistor T1 is electrically connected to the first power signal terminal VGH, the second end is electrically connected to the first node Q, and the control end is electrically connected to the clock signal terminal CLK independent of the shift register unit; the first end of the second transistor T2 is electrically connected to the second node QB, the second end is electrically connected to the second power signal terminal VGL, and the control end is electrically connected to the clock signal terminal CLK, and is configured to set the first node Q through the first power signal of the first power signal terminal VGH in response to the control of the clock signal of the clock signal terminal CLK and pull down the potential of the second node QB through the second power signal of the second power signal terminal VGL;

[0044] The reset sub-circuit 120, in response to the control of the reset signal of the reset signal terminal IN(n), resets the first node Q through the second power signal and pulls up the potential of the second node QB through the first power signal; and

[0045] The output sub-circuit 130 controls the output of the first power signal or the second power signal based on the potential of the first node Q and the potential of the second node QB.

[0046] In the present embodiment, a light emitting control unit having a setting subcircuit, a reset subcircuit and an output subcircuit is provided, and the setting subcircuit is set to include a first transistor and a second transistor, which is configured to set the first node through the first power signal of the first power signal end in response to the control of the clock signal of the clock signal end and pull down the potential of the second node through the second power signal of the second power signal end, thereby being able to provide a stable light emitting control signal with a simple circuit structure, and the structure does not need to be cascaded, which is conducive to narrow frame design; in addition, by electrically connecting the control ends of the first transistor and the second transistor to the clock signal end independent of the shift register unit, the light emitting time of the pixel can be flexibly controlled through an independent clock signal.

[0047] In a specific embodiment, in combination Figure 1 and Figure 2 As shown, Figure 1 shows a schematic structural block diagram of main sub-circuits included in a shift register unit according to an embodiment of the present application, Figure 2 Show satisfaction Figure 1 A circuit diagram of a more specific circuit of the structural block diagram shown in FIG. In the figure, n represents the nth light emitting control unit, n is a positive integer greater than or equal to 1 and less than or equal to N, and N represents the total number of light emitting control units in the display device.

[0048] Reference Figure 1 and Figure 2 As shown, the light emitting control unit includes: a setting subcircuit 110 , a resetting subcircuit 120 and an output subcircuit 130 .

[0049] In particular, the setting subcircuit 110 includes a first transistor T1 and a second transistor T2. The first end of the first transistor T1 is electrically connected to the first power signal terminal VGH, the second end is electrically connected to the first node Q, and the control end is electrically connected to the clock signal terminal CLK; the first end of the second transistor T2 is connected to the second node QB, the second end is electrically connected to the second power signal terminal VGL, and the control end is also electrically connected to the clock signal terminal CLK. The clock signal terminal CLK is required to be a clock signal terminal independent of the shift register unit. The setting subcircuit 110 is configured to set the first node Q through the first power signal of the first power signal terminal VGH in response to the control of the clock signal of the clock signal terminal CLK and pull down the potential of the second node QB through the second power signal of the second power signal terminal VGL.

[0050] Specifically, in the present application, the first power signal of the first power signal terminal VGH is at a high level, and the second power signal of the second power signal terminal VGL is at a low level. When the clock signal of the clock signal terminal CLK is at a high level, the first transistor T1 and the second transistor T2 are turned on, and the first transistor T1 transmits the high-level first power signal of the first power signal terminal VGH to the first node Q, setting it; the second transistor T2 transmits the low-level second power signal of the second power signal terminal VGL to the second node QB, pulling down the potential of the second node QB.

[0051] Continue to refer to Figure 1 As shown, the reset subcircuit 120 is electrically connected to the first node Q, the second node QB, the first power signal terminal VGH, the second power signal terminal VGL, and the reset signal terminal IN(n), and is configured to reset the first node Q through the second power signal in response to the control of the reset signal of the reset signal terminal IN(n) and pull up the potential of the second node QB through the first power signal.

[0052] Specifically, refer to Figure 2 As shown, the reset sub-circuit 120 includes a third transistor T3 and a fourth transistor T4. The first end of the third transistor T3 is electrically connected to the first power signal terminal VGH, the second end is electrically connected to the second node QB, and the control end is electrically connected to the reset signal terminal IN(n). The first end of the fourth transistor T4 is electrically connected to the first node Q, the second end is electrically connected to the second power signal terminal VGL, and the control end is electrically connected to the second node QB.

[0053] When the reset signal of the reset signal terminal IN(n) is at a high level, the third transistor T3 is turned on, and the third transistor T3 transmits the high-level first power signal of the first power signal terminal VGH to the second node QB, and pulls up the potential of the second node QB through the first power signal; at this time, because the potential of the second node QB is high, the fourth transistor T4 is also turned on, and the first node Q is reset through the low-level second power signal.

[0054] Continue to refer to Figure 1 As shown, the output subcircuit 130 is electrically connected to the first node Q, the second node QB, the first power signal terminal VGH, and the second power signal terminal VGL, and is configured to control the output of the first power signal or the second power signal based on the potential of the first node Q and the potential of the second node QB.

[0055] Specifically, refer to Figure 2As shown, the output sub-circuit 130 includes a fifth transistor T5 and a sixth transistor T6. The first end of the fifth transistor T5 is electrically connected to the first power signal terminal VGH, the second end is electrically connected to the output terminal EM(n), and the control end is electrically connected to the first node Q. The first end of the sixth transistor T6 is electrically connected to the output terminal EM(n), the second end is electrically connected to the second power signal terminal VGL, and the control end is electrically connected to the second node QB.

[0056] When the potential of the first node Q is high and the potential of the second node QB is low, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, and the output terminal EM(n) outputs the first power signal, and the output signal is a high level; when the potential of the first node Q is low and the potential of the second node QB is high, the fifth transistor T5 is turned off and the sixth transistor T6 is turned on, and the output terminal EM(n) outputs the second power signal, and the output signal is a low level.

[0057] In this example, refer to Figure 2 As shown, the light emitting control unit further includes a storage unit, and the storage unit includes a first storage capacitor C1 and a second storage capacitor C2. The first end of the first storage capacitor C1 is electrically connected to the first node Q, and the second end is electrically connected to the output terminal, and the first end of the second storage capacitor C2 is electrically connected to the second node QB, and the second end is electrically connected to the second power signal terminal VGL. The first storage capacitor C1 and the second storage capacitor C2 are used to maintain the potential of the first node Q and the second node QB, so that when the potential of the first node Q and the second node QB does not change, the output terminal EM(n) always maintains a stable output.

[0058] In order to further understand the structure and function of the embodiments of the present application, Figure 2 The circuit diagram and Figure 3 The specific timing diagram shown describes the timing function of the light-emitting control unit in detail. It should be pointed out that because the light-emitting control unit of the present application is only an independent unit circuit and there is no cascade, in order to emphasize the role of the light-emitting control unit in a specific application, the clock signal timing of the clock signal terminals CLK(n) and CLK(n+1) of the nth light-emitting control unit and the n+1th light-emitting control unit, the reset signal timing of the reset signal terminals IN(n) and IN(n+1), and the output signal timing of the corresponding output terminals EM(n) and EM(n+1) are respectively given. In addition, CKL1, CLK2, CLK3, and CLK4 respectively represent the timing signals of the clock signal lines corresponding to the multiple clock signal terminals when there are multiple light-emitting control units. In this example, it is assumed that the light-emitting control terminal of the nth light-emitting control unit corresponds to the timing signal of CLK1.

[0059] Specifically, in the first stage t1, the clock signal of the clock signal terminal CLK(n) is at a high level, the first transistor T1 is turned on, and the potential of the first node Q is set to high. At the same time, since the control terminal of the second transistor T2 is also electrically connected to the clock signal terminal CLK, the second transistor T2 is also turned on, and the low-level first power supply signal is transmitted to the second node QB, pulling down the potential of the node; at the same time, the potential of the reset signal terminal IN(n) is low, and has no effect on the first node Q and the second node QB; at this time, because the first node Q is at a high level and the second node QB is at a low level, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, and the output terminal EM(n) outputs a high-level output signal.

[0060] In the second stage t2, the clock signal of the clock signal terminal CLK(n) becomes a low level, the first transistor T1 and the second transistor T2 are turned off, at this time, the potential of the reset signal terminal IN(n) is high, the third transistor T3 is turned on, and the high-level first power supply signal is transmitted to the second node QB, because the potential of the second node QB is high, the fourth transistor T4 is turned on, and the low-level second power supply signal is transmitted to the first node Q through the fourth transistor T4; therefore, the first node Q is at a low level, and the second node QB is at a high level, the fifth transistor T5 is turned off and the sixth transistor T6 is turned on, and the output terminal EM(n) outputs a low-level output signal.

[0061] Furthermore, in time period t2', the clock signal of the clock signal terminal CLK(n) and the reset signal of the reset signal terminal IN(n) are both at low level, the fifth transistor T5 and the sixth transistor T6 are both turned off, and in the absence of other circuit structures, the output terminal EM(n) floats, and it may be impossible to ensure that the output terminal EM(n) stably outputs the correct level.

[0062] In the present application, because a storage unit is set, specifically by connecting a first storage capacitor C1 between the control terminal and the second terminal of the fifth transistor T5, and connecting a second storage capacitor C2 between the control terminal and the second terminal of the sixth transistor T6, in the time period t2', the second storage capacitor C1 and the second storage capacitor C2 simultaneously play a potential holding role, and the output terminal EM(n) maintains the potential output of the second stage t2, that is, outputs a low-level signal, and this stage can be called a potential holding stage.

[0063] Next, in the third stage t3, the clock signal at the clock signal terminal CLK(n) becomes high again, the first transistor T1 and the second transistor T2 are turned on at the same time, the first transistor T1 sets the first node Q to a high level again, the second transistor T2 again pulls down the potential of the second node QB through the low-level second power supply signal, and the potential of the reset signal terminal IN(n) remains at a low level, the third transistor T3 and the fourth transistor T4 are turned off; at this time, the first node Q is at a high level, and the second node QB is at a low level, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, and the output terminal EM(n) outputs a high-level output signal again.

[0064] Therefore, after the first stage t1, the second stage t2 and the third stage t3, through the cooperation of each transistor, the output terminal EM(n) can output a negative pulse signal with only the period t2 and the period t2' being low level and the other periods being high level.

[0065] From the above analysis, it can be seen that the starting period of the negative pulse signal is controlled by the reset signal terminal IN(n), and the pulse width of the negative pulse signal is substantially determined by the clock signal of the clock signal terminal CLK. In the present application, by setting the clock signal terminal CLK to be independent of the shift register unit, the clock signal of the clock signal terminal CLK is not affected by other circuits, that is, the pulse width of the light-emitting control signal can be freely controlled, so that the light-emitting control unit of the embodiment of the present application can flexibly control the light-emitting duration of the pixel.

[0066] In addition, the light emitting control unit of the embodiment of the present application solves the problem of uncertain output when the output terminal EM(n) is floating by setting a storage unit, so that a correct and stable light emitting control signal can be outputted at all times.

[0067] Furthermore, combined with Figure 3 It can be seen from the above timing analysis that, because the light emission control is performed between each row of pixels by row scanning, if the nth light emission control unit corresponding to the nth row of pixels and the n+1th light emission control unit corresponding to the n+1th row of pixels are to output negative pulse signals in sequence, it is only necessary to control the reset signals of the reset signal terminals IN(n) and IN(n+1) and the clock signal terminals CLK(n) and CLK(n+1) to be separated by a high-level clock cycle, and the reset signal terminals IN(n) and IN(n+1) can be assisted by the shift register unit of the gate drive circuit, therefore, it is only necessary to provide a clock signal terminal with timing changes. Therefore, the embodiment of the present application realizes a light emission control unit without cascading by connecting and coordinating transistors between the setting subcircuit, the reset subcircuit and the output subcircuit. Each light emission control unit has only 6 transistors, occupies a small area, is conducive to narrow frame design, meets the current industry's application requirements for narrow frame display products, and has broad application prospects.

[0068] Based on the same inventive concept, Figure 4 As shown, an embodiment of the present application also provides a gate driving circuit, including: 4 cascaded shift register units 20-1, 20-2, 20-3 and 20-4; and 4 light-emitting control units 10-1, 10-2, 10-3 and 10-4 corresponding to each shift register unit, wherein the light-emitting control unit is the light-emitting control unit described in the above embodiment.

[0069] Each shift register unit outputs a pixel scanning signal, and each light emitting control unit is electrically connected to a corresponding shift register unit to output a light emitting control signal for controlling the pixel to emit light.

[0070] It should be noted that although Figure 4 The example shows a case including 4 shift register units and 4 light-emitting control units, but the present application is not limited to this. Those skilled in the art can set the number of cascaded shift register units and the corresponding number of light-emitting control units according to the number of pixel rows (or columns) to be scanned.

[0071] In this embodiment, by providing cascaded shift register units and a light emitting control unit electrically connected to each shift register unit, and each light emitting control unit includes the set subcircuit, reset subcircuit and output subcircuit described in the above embodiment, it is possible to use a light emitting control unit with a simple structure to complete the light emitting control of each row (or column) of pixels, and the light emitting control unit independent of the clock signal end can flexibly control the light emitting time of the pixel, which has broad application prospects.

[0072] Specifically, in order to more clearly explain the connection relationship and function between the shift register unit and the light emitting control unit, Figure 5 A circuit structure of a shift register unit of a specific example is given.

[0073] Reference Figure 5 As shown, in Figure 5The main parts of a conventional shift register unit are shown in FIG. Among them, the shift register unit includes an input sub-circuit composed of a transistor M1, a pull-up sub-circuit composed of a transistor M2 and a capacitor C, and a reset sub-circuit composed of a transistor M3. The input sub-circuit transmits the signal of the high-level signal terminal VDD to the pull-up node PU under the control of the input signal of the input signal terminal STU; the pull-up sub-circuit transmits the clock signal of the clock signal terminal CK to the output terminal CR under the control of the potential of the pull-up node PU, that is, it can be considered that the shift register unit outputs a scan signal under the control of the clock signal connected to the clock signal terminal CK (that is, the first clock signal terminal); the reset sub-circuit resets the pull-up node through the low-level signal terminal VGL under the control of the signal of the reset signal terminal TRS. Among them, the inverter is a simplified summary of the circuit functions of the pull-down sub-circuit and the pull-down control sub-circuit, which reflects the signal relationship between the pull-up node PU and the pull-down node PU. In addition, referring to Figure 4 As shown, the shift register unit further includes a noise reduction subcircuit, which includes a transistor M4 and a transistor M5. The noise reduction subcircuit is configured to reduce the noise of the pull-up node PU through the transistor M4 and reduce the noise of the output terminal CR through the transistor M5 under the control of the pull-down node PU.

[0074] In order to further reflect the signal end of the pull-down sub-circuit and the pull-down control sub-circuit, Figure 5 On the basis Figure 6 A schematic diagram of a typical circuit including a pull-down subcircuit and a pull-down control subcircuit is further provided.

[0075] Reference Figure 6 As shown, in this example, the pull-down control subcircuit includes a transistor M6, and the pull-down subcircuit includes a transistor M7. The pull-down control subcircuit is electrically connected to the clock signal terminal CKB and the pull-down node PD, and transmits the clock signal of the clock signal terminal CKB to the pull-down node PD under the control of the clock signal terminal CKB; the pull-down subcircuit is electrically connected to the pull-up node PU, the pull-down node PD, and the low-level signal terminal VGL, and is configured to pull down the potential of the pull-down node PD through the low-level signal terminal VGL under the control of the pull-up node PU.

[0076] It should be noted that Figure 5 and Figure 6 The circuit structure in the embodiment is only exemplary and is not intended to limit the specific structure of the shift register unit included in the gate drive circuit. The pull-up subcircuit, reset subcircuit, noise reduction subcircuit, pull-down control subcircuit and the specific number of transistors in the pull-down subcircuit are not limited to Figure 5 and Figure 6 As shown, no further details are given here.

[0077] Further, Figure 6 As an example, continue to refer to the circuit structure shown in Figure 4The figure shows the connection relationship between the shift register unit and the light emitting control unit.

[0078] Specifically, the clock signal terminal CK and the clock signal terminal CKB of the first-stage shift register unit 20-1 are electrically connected to the clock signal line ck and the clock signal line ckb, respectively; the clock signal line CK and the clock signal line CKB of the second-stage shift register unit 20-2 are electrically connected to the clock signal line ckb and the clock signal line ck, respectively; and so on and so forth, and the connection is alternately repeated in two stages. When no distinction is required, the clock signal line electrically connected to the clock signal terminal CK is called the first clock signal line; the reset signal terminal TRS of the shift register units 20-1, 20-2, 20-3, and 20-4 is electrically connected to the input signal line Trs; the high-level signal terminal VDD is electrically connected to the high-level signal line DC; the input terminal STU of the shift register of the first-stage shift register unit 20-1 is connected to the input signal, and the input terminals in the subsequent shift register units are all electrically connected to the output terminal CR of the shift register unit of the previous stage.

[0079] Further, the output terminal CR of each level of the shift register unit is electrically connected to each corresponding light-emitting control unit, that is, the output terminal CR of the first level shift register unit 20-1 is electrically connected to the input terminal IN of the light-emitting control unit 10-1, the output terminal CR of the second level shift register unit 20-2 is electrically connected to the input terminal IN of the light-emitting control unit 10-2, the output terminal CR of the third level shift register unit 20-3 is electrically connected to the input terminal IN of the light-emitting control unit 10-3, and the output terminal CR of the fourth level shift register unit 20-4 is electrically connected to the input terminal IN of the light-emitting control unit 10-4. In the present application, by utilizing the step-by-step shifting characteristics of the shift register unit, the third transistor T3 and the fourth transistor T4 in the light-emitting control unit are controlled to be turned on, so as to control each light-emitting control unit to output a light-emitting control signal of a negative level step by step.

[0080] In addition, refer to Figure 4 It can be seen that the clock signal terminals CLK of the light-emitting control units 10-1, 10-2, 10-3, and 10-4 are connected to a clock signal line that is independent of the clock signal line of the shift register unit. In other words, when the clock signal line connected to the clock signal terminal CLK is called the second clock signal line, the second clock signal line connected to the clock signal terminal of the light-emitting control unit and the first clock signal line electrically connected to the shift register unit are independent clock signal lines. Through this setting, the negative pulse width of each light-emitting control unit can be independently controlled, so that the light-emitting duration of the light-emitting control unit is not restricted by the circuit of the shift register, and the pulse width of the light-emitting control signal is more flexible.

[0081] In addition, those skilled in the art should also understand that the present application is not intended to limit the specific number of clock signal lines. When the number of light-emitting control units is greater, if four clock signal lines still need to be set, it is only necessary to make the clock signal level of the fifth clock signal end consistent with the clock signal level of the first clock signal end. Figure 3 As shown in the timing diagram, as long as the duty cycle of the clock signal of each clock signal line is 1 / 4, only 4 clock signal lines are needed to meet the design of any number of light-emitting control units. The setting of other numbers of clock signal lines is similar and will not be repeated here.

[0082] Based on the same inventive concept, the third aspect of the present application provides a display device, comprising the gate driving circuit described in the above embodiment.

[0083] It is worth noting that the gate driving circuit of the embodiment of the present application can be applied to various forms of display devices. Those skilled in the art should understand that all display devices based on the gate driving circuit working mode of the present application are within the protection scope of the present application.

[0084] Corresponding to the same inventive concept, the fourth aspect of the present application provides a control method for the light emitting control unit of the embodiment of the present application, comprising:

[0085] In the first stage, a high-level signal is provided to the input terminal as an input signal, and the input subcircuit transmits the input signal to the pull-up node to pull up the potential of the pull-up node;

[0086] In the first stage, the setting subcircuit transmits the first power signal to the first node in response to the received setting signal, so that the output end of the output subcircuit outputs the first power signal.

[0087] In the second stage, the reset signal transmits the first power signal to the second node in response to the received reset signal, so as to reset the first node through the second power signal and make the output end of the output subcircuit output the second power signal; and

[0088] In the third stage, the setting signal is applied to the setting subcircuit again so that the output end of the output subcircuit outputs the first power signal.

[0089] Specifically, when a storage unit is included, the method further comprises:

[0090] In the second phase, the potentials of the first node and the second node are maintained by the first storage capacitor and the second storage capacitor.

[0091] It should be noted that the above control method is combined with the above Figure 3 The various stages described are consistent and the specific process will not be repeated.

[0092] The above method utilizes a light-emitting control unit having a set subcircuit, a reset subcircuit and an output subcircuit, and enables each transistor to cooperate with each other through the above first stage, second stage and third stage, so as to provide a stable light-emitting control signal with a simple circuit structure, and the structure does not need to be cascaded, which is conducive to a narrow frame design; in addition, by electrically connecting the control terminals of the first transistor and the second transistor to a clock signal terminal independent of the shift register unit, the light-emitting time of the pixel can be flexibly controlled through an independent clock signal.

[0093] In response to the existing problems, the present application develops a light-emitting control unit and a control method thereof, a gate driving circuit and a display device. The light-emitting control unit is provided with a setting subcircuit, a reset subcircuit and an output subcircuit, and the setting subcircuit is set to include a first transistor and a second transistor, which is configured to set a first node through a first power signal at a first power signal end in response to the control of a clock signal at a clock signal end, and to pull down the potential of a second node through a second power signal at a second power signal end, thereby providing a stable light-emitting control signal with a simple circuit structure, and the structure does not require cascading, which is conducive to a narrow frame design; in addition, by electrically connecting the control ends of the first transistor and the second transistor to a clock signal end independent of a shift register unit, the light-emitting time of a pixel can be flexibly controlled through an independent clock signal, and the application has broad application prospects.

[0094] Obviously, the above embodiments of the present application are merely examples for clearly illustrating the present application, and are not limitations on the implementation methods of the present application. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present application are still within the scope of protection of the present application.

Claims

1. A light emitting control unit, characterized in that: include: A setting subcircuit, comprising a first transistor and a second transistor, wherein the first terminal of the first transistor is electrically connected to a first power signal terminal, the second terminal is electrically connected to a first node, and the control terminal is electrically connected to a clock signal terminal independent of a shift register unit; the first terminal of the second transistor is electrically connected to a second node, the second terminal is electrically connected to a second power signal terminal, and the control terminal is electrically connected to the clock signal terminal, and is configured to set the first node through a first power signal at the first power signal terminal in response to control of a clock signal at the clock signal terminal and pull down a potential of the second node through a second power signal at the second power signal terminal; a reset subcircuit, in response to the control of the reset signal at the reset signal terminal, resetting the first node through the second power signal and pulling up the potential of the second node through the first power signal; as well as The output sub-circuit controls output of the first power signal or the second power signal based on the potential of the first node and the potential of the second node.

2. The light emitting control unit according to claim 1, characterized in that: The reset subcircuit comprises: a third transistor and a fourth transistor, Among them, the first end of the third transistor is electrically connected to the first power signal end, the second end is electrically connected to the second node, and the control end is electrically connected to the reset signal end; the first end of the fourth transistor is electrically connected to the first node, the second end is electrically connected to the second power signal end, and the control end is electrically connected to the second node.

3. The light emitting control unit according to claim 1, characterized in that: The output sub-circuit includes a fifth transistor and a sixth transistor, Among them, the first end of the fifth transistor is electrically connected to the first power signal end, the second end is electrically connected to the output end, and the control end is electrically connected to the first node; the first end of the sixth transistor is electrically connected to the output end, the second end is electrically connected to the second power signal end, and the control end is electrically connected to the second node.

4. The light emitting control unit according to claim 3, characterized in that: The storage subcircuit includes a first storage capacitor and a second storage capacitor. The first end of the first storage capacitor is electrically connected to the first node, and the second end is electrically connected to the output end; the first end of the second storage capacitor is electrically connected to the second node, and the second end is electrically connected to the second power signal end.

5. The light emitting control unit according to claim 1, characterized in that: The first power signal at the first power signal end is a high level signal, and the second power signal at the second power signal end is a low level signal.

6. The light emitting control unit according to claim 1, characterized in that: The transistor in the light emitting control unit is an N-type transistor or a P-type transistor.

7. A gate drive circuit, characterized in that: include: A plurality of cascaded shift register units and a plurality of light emitting control units according to any one of claims 1 to 6, wherein the light emitting control units correspond to the shift register units one by one, Wherein, the output end of each of the shift register units is electrically connected to the reset signal end of the corresponding light emitting control unit; and Each of the shift register units includes a first clock signal terminal electrically connected to a first clock signal line, and the shift register unit generates a gate scanning signal under the control of a clock signal connected to the first clock signal terminal. The clock signal end of each of the light emitting control units is electrically connected to a second clock signal line, and the first clock signal line and the second clock signal line are independent of each other.

8. A display device, characterized in that: Includes the gate drive circuit as claimed in claim 7.

9. A light emitting control method for a light emitting control unit according to any one of claims 1 to 6, characterized in that: include: In the first stage, the setting subcircuit transmits the first power signal to the first node in response to the received clock signal, so that the output end of the output subcircuit outputs the first power signal. In the second stage, the reset signal transmits the first power signal to the second node in response to the received reset signal, so as to reset the first node through the second power signal and make the output end of the output subcircuit output the second power signal; as well as In the third stage, the clock signal is applied to the setting subcircuit again so that the output end of the output subcircuit outputs the first power signal.

10. The light emission control method according to claim 9, characterized in that: The light emitting control unit further includes a storage subcircuit, the storage subcircuit includes a first storage capacitor and a second storage capacitor, wherein a first end of the first storage capacitor is electrically connected to the first node, and a second end is electrically connected to the output end, a first end of the second storage capacitor is electrically connected to the second node, and a second end is electrically connected to the second power signal end, The method further comprises: In the second stage, the potentials of the first node and the second node are maintained by the first storage capacitor and the second storage capacitor.

Images