A method for forming a gate oxide layer of a GaN MOS HEMT and a method for manufacturing the GaN MOS HEMT

Abstract

The present invention provides a method for forming a gate oxide layer of a GaN MOS HEMT and a method for manufacturing a GaN MOS HEMT. First, a Si epitaxial layer is formed above the GaN epitaxial layer of the GaN MOS HEMT, and then the Si epitaxial layer is oxidized by a thermal oxidation method so that the entire Si epitaxial layer is oxidized into a SiO2 layer, and this SiO2 layer serves as the gate oxide layer. The above method of the present invention avoids damage to the epitaxial layer by plasma, improves the interface state between the SiO2 layer and the GaN epitaxial layer, significantly improves the performance of the device, and improves the control ability of the gate over the channel. In addition, by strictly controlling the time and temperature of thermal oxidation, the entire Si epitaxial layer is oxidized while the GaN in the GaN epitaxial layer is not oxidized. At the same time, in order to further prevent the GaN epitaxial layer from being oxidized, the method of the present invention can also inject C ions at the interface between the Si epitaxial layer and the GaN epitaxial layer, and the C ions help to prevent the GaN epitaxial layer from being oxidized, thereby ensuring the performance of the device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to a method for forming a gate oxide layer of a GaN MOS HEMT and a method for manufacturing the GaN MOS HEMT. Background Art

[0002] Compared with traditional Si semiconductor devices, the third-generation semiconductor GaN has the advantages of large band gap (3.45eV), high breakdown field strength (3.3×106V / cm) and large saturated electron mobility (2.7×107cm / s), and can work in higher voltage, higher frequency and higher temperature environments. In addition, GaN is a direct band gap semiconductor, and its application in LED, semiconductor laser and other fields is expanding.

[0003] like Figure 1 As shown in the figure, GaN power devices mainly generate piezoelectric effect through polarization of heterojunction, and generate two-dimensional electron gas (2D EG, 2D electron gas) at the heterojunction junction. The speed of this electron gas is 2.7 times faster than that of ordinary electrons, making the device faster. Therefore, this type of device structure is also called HEMT (High Electron Mobility Transistor) or HFET (Hetro-Junction Field Effect Transistor, heterojunction field effect transistor), and is currently commonly used in the RF field.

[0004] AlGaN / GaN HEMT devices have broad application prospects in the high-frequency field. However, for traditional Schottky gates, the manufacturing process of the contact pad is complicated, requiring at least four layers of metal: Ti / Al / Ni / Au, which has a serious leakage problem, and GaN HEMT is a normally on device, which brings many inconveniences to the use of the device. In order to suppress the gate leakage current, the GaN HEMT structure introduces a metal-oxide-semiconductor (MOS) structure. A large number of experiments have shown that the gate oxide layer enables the gate voltage to modulate the channel very well, which can effectively control the threshold voltage and realize an enhancement-mode device. In addition, the gate leakage current of the GaN MOSHEMT is 4 to 6 orders of magnitude smaller than the gate leakage current of the GaN Schottky gate HEMT.

[0005] However, the bandgap width of Ga2O3 is 4.8eV, which is a wide bandgap semiconductor and is not suitable as a gate oxide layer. Therefore, Ga2O3 cannot be grown as a gate oxide layer by thermal oxidation itself.

[0006] At present, the main growth method of gate oxide layer is to grow SiO2 by plasma enhanced chemical vapor deposition (PECVD). Since SiO2 is deposited on the GaN surface, direct plasma contact with the device will cause damage, so a lot of interface states and dangling bonds will be introduced at the interface of SiO2 and GaN, and the interface quality is poor. High density of interface states will lead to Fermi pinning, making the gate unable to effectively control the gate voltage, resulting in threshold voltage drift. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for forming a gate oxide layer of a GaN MOS HEMT and a method for manufacturing a GaN MOS HEMT, so as to solve the problems faced by the process of forming a gate oxide layer in the prior art, and the problem that the interface quality between the formed gate oxide layer and GaN is poor, thereby causing the threshold voltage drift of the HEMT.

[0008] To achieve the above object and other related objects, the present invention provides a method for forming a gate oxide layer of a GaN MOS HEMT, the method comprising the following steps:

[0009] forming a Si epitaxial layer on a GaN epitaxial layer of a GaN MOS HEMT;

[0010] The Si epitaxial layer is thermally oxidized so that the Si epitaxial layer is completely oxidized to form a SiO2 layer, and the SiO2 layer serves as a gate oxide layer.

[0011] Optionally, before thermally oxidizing the Si epitaxial layer, the method further includes: implanting C ions into an interface between the Si epitaxial layer and the GaN epitaxial layer.

[0012] Optionally, the implanted C ion concentration is between 1E11 / cm 2 ~1E14 / cm 2 .

[0013] Optionally, the thickness of the Si epitaxial layer is determined according to the required thickness of the gate oxide layer, wherein the thickness of the Si epitaxial layer is t Si The thickness of the gate oxide layer t ox satisfy:

[0014]

[0015] Among them, N ox is the density of Si in SiO2, N Si is the density of Si in elemental Si.

[0016] Optionally, the method further includes thinning the gate oxide layer.

[0017] Optionally, the method further includes forming a high-k dielectric layer above the gate oxide layer.

[0018] The present invention also provides a method for manufacturing a GaN MOS HEMT, the method comprising the following steps:

[0019] providing a substrate;

[0020] forming a GaN epitaxial layer on the substrate;

[0021] forming a Si epitaxial layer on the GaN epitaxial layer;

[0022] Thermally oxidizing the Si epitaxial layer means that the Si epitaxial layer is completely oxidized to form a SiO2 layer, and the SiO2 layer serves as a gate oxide layer;

[0023] A gate is formed on the gate oxide layer, and a source and a drain are formed on the GaN epitaxial layer.

[0024] Optionally, forming a GaN epitaxial layer on the substrate includes sequentially forming a nucleation layer, a buffer layer, an isolation layer, a charge supply layer and a barrier layer on the substrate.

[0025] Optionally, before thermally oxidizing the Si epitaxial layer, the method further includes: implanting C ions into an interface between the Si epitaxial layer and the GaN epitaxial layer.

[0026] Optionally, the implanted C ion concentration is between 1E11 / cm 2 ~1E14 / cm 2 .

[0027] Optionally, the thickness of the Si epitaxial layer is determined according to the required thickness of the gate oxide layer, wherein the thickness of the Si epitaxial layer is t Si The thickness of the gate oxide layer t ox satisfy:

[0028]

[0029] Among them, N ox is the density of Si in SiO2, N Si is the density of Si in elemental Si.

[0030] Optionally, the method further includes thinning the gate oxide layer.

[0031] Optionally, the method further includes forming a high-k dielectric layer above the gate oxide layer.

[0032] As described above, the method for forming a gate oxide layer of a GaN MOS HEMT and the method for manufacturing a GaN MOS HEMT provided by the present invention have at least the following beneficial effects:

[0033] The gate oxide layer forming method of GaN MOS HEMT and the manufacturing method of GaN MOS HEMT of the present invention first form a Si epitaxial layer on the GaN epitaxial layer of GaN MOS HEMT, and then oxidize the Si epitaxial layer by thermal oxidation, so that the Si epitaxial layer is completely oxidized into a SiO2 layer, and the SiO2 layer is used as a gate oxide layer. The above method of the present invention avoids damage to the epitaxial layer by plasma, improves the interface state between the SiO2 layer and the GaN epitaxial layer, significantly improves the performance of the device, and improves the control ability of the gate over the channel. In addition, by strictly controlling the time and temperature of thermal oxidation, the Si epitaxial layer is completely oxidized while the GaN in the GaN epitaxial layer is not oxidized. At the same time, in order to further prevent the GaN epitaxial layer from being oxidized, the method of the present invention can also implant C ions at the interface between the Si epitaxial layer and the GaN epitaxial layer, and the C ions help to prevent the GaN epitaxial layer from being oxidized, thereby ensuring the performance of the device.

[0034] In the present invention, in order to ensure the thickness of the gate oxide layer, if the thickness of the gate oxide layer SiO2 exceeds the thickness required by the device, the SiO2 layer can be thinned, for example, by CMP; if the thickness of the gate oxide layer SiO2 is insufficient and the control ability of the channel is insufficient, a high-k dielectric layer can be continued to be grown on the SiO2 layer, for example, an Al2O3 or HfO2 layer can be grown by the ALD method. As described above, the present invention can ensure the desired ideal gate oxide layer thickness, enhance the control ability of the channel, and improve the performance of the GaN device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the structure of GaN HEMT in the prior art.

[0036] Figure 2 It is a schematic flow chart of a method for forming a gate oxide layer of a GaN MOS HEMT provided in the first embodiment of the present invention.

[0037] Figure 3 The schematic diagram shows a structure in which a Si epitaxial layer is formed on the GaN epitaxial layer of a GaN MOS HEMT.

[0038] Figure 4 Display as Figure 3 The schematic diagram of the structure in which the Si epitaxial layer is oxidized to form a gate oxide layer SiO2 is shown.

[0039] Figure 5 It is a schematic diagram showing the implantation of C ions at the interface between the Si epitaxial layer and the GaN epitaxial layer in an alternative embodiment of the first embodiment of the present invention.

[0040] Figure 6It is a schematic flow chart of a method for manufacturing a GaN MOS HEMT provided in the second embodiment of the present invention.

[0041] Figure 7 It shows a schematic diagram of the structure of forming a GaN epitaxial layer on a substrate.

[0042] Figure 8 Displayed as Figure 7 Schematic diagram of the structure in which a Si epitaxial layer is formed on the GaN epitaxial layer.

[0043] Fig. 9 Display as Figure 8 The schematic diagram of the structure in which the Si epitaxial layer is oxidized to form a gate oxide layer SiO2 is shown.

[0044] Fig.10 Displayed as Fig. 9 A schematic diagram of the structure in which a gate, a source and a drain are formed is shown.

[0045] Fig.11 It is a schematic diagram showing the implantation of C ions at the interface between the Si epitaxial layer and the GaN epitaxial layer in an optional embodiment of the second embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] See also Figure 2 to Figure 11 It should be noted that the illustrations provided in the embodiments of the present invention are only schematic illustrations of the basic concept of the present invention, and thus the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] Embodiment 1

[0049] This embodiment provides a gate oxide layer of a GaN MOS HEMT, such as Figure 2 As shown, the method comprises the following steps:

[0050] Step S101: forming a Si epitaxial layer on the GaN epitaxial layer of the GaN MOS HEMT;

[0051] like Figure 3As shown, a GaN epitaxial layer 101 is formed on the substrate 100. The GaN epitaxial layer 101 is a multi-layer material layer, for example, it may include an AlN nucleation layer, a GaN buffer layer, an AlGaN isolation layer, an AlGaN charge supply layer, a GaN barrier layer, etc. A Si epitaxial layer 102 is epitaxially grown on the formed GaN epitaxial layer 101. The thickness of the Si epitaxial layer 102 can be determined according to the thickness of the gate oxide layer required by the device, for example, the thickness of the Si epitaxial layer 102 is approximately less than 22nm.

[0052] Step S102: thermally oxidizing the Si epitaxial layer to completely oxidize the Si epitaxial layer to form a SiO2 layer, and the SiO2 layer serves as a gate oxide layer.

[0053] like Figure 4 As shown, the Si epitaxial layer 102 is oxidized so that the Si epitaxial layer is completely oxidized to form a SiO2 layer 103, which serves as a gate oxide layer of the GaN MOS HEMT.

[0054] In this embodiment, the Si epitaxial layer is oxidized by thermal oxidation, and the oxidation temperature is usually controlled between 900° C. and 1200° C. During the thermal oxidation process, the temperature and time of the reaction are strictly controlled, so that the Si epitaxial layer is completely oxidized to form a SiO2 layer, and on the other hand, the reaction gas O2 and Si are prevented from diffusing into the GaN epitaxial layer, causing oxidation of GaN and affecting the performance of the device.

[0055] According to the principle that the number of Si atoms in the Si epitaxial layer and the number of Si atoms in the SiO2 layer remain unchanged before and after oxidation, we can get: t Si N si =t ox N ox (1)

[0056] Among them, t si is the thickness of the Si epitaxial layer, N Si is the density of Si atoms in the Si epitaxial layer, specifically 5×10 22 atoms / cm 3 ;t ox is the thickness of the SiO2 layer, N ox is the density of Si atoms in the SiO2 layer, specifically 2.2×10 22 atoms / cm 3 .

[0057] According to the above formula (1) and the final desired or required thickness of the SiO2 layer, the thickness t of the Si epitaxial layer grown on the GaN epitaxial layer can be determined. Si :

[0058] In the above method, the thickness of the SiO2 layer finally formed may be less than or greater than the desired thickness of the gate oxide layer, and compensation can be made for different situations. When the thickness of the SiO2 layer exceeds the thickness of the gate oxide layer required by the device, part of the SiO2 layer can be removed by thinning to meet the desired thickness, for example, it can be thinned by chemical mechanical polishing. When the thickness of the SiO2 layer cannot meet the thickness of the gate oxide layer required by the device, and the control ability of the channel is insufficient, a high-k dielectric layer can be continued to grow on the SiO2 layer, and the high-k dielectric layer and the SiO2 layer serve as the gate oxide layer together to meet the desired thickness. For example, Al2O3 or HfO2 can be grown on the SiO2 layer by atomic layer deposition.

[0059] As described above, a Si epitaxial layer is epitaxially grown on the GaN epitaxial layer, and then the Si epitaxial layer is completely oxidized into a SiO2 layer by thermal oxidation, thereby obtaining a SiO2-GaN interface with a good cross-sectional state, which can significantly improve the performance of the device. At the same time, it can ensure the desired gate oxide layer thickness required by the device and improve the control ability of the device channel layer.

[0060] In an alternative embodiment of this embodiment, if Figure 5 As shown, before oxidizing the Si epitaxial layer, it also includes: injecting carbon C ions into the interface between the Si epitaxial layer and the GaN epitaxial layer. The presence of C ions can effectively prevent O2 or Si from diffusing into the GaN epitaxial layer, thereby effectively preventing GaN from being oxidized to form Ga2O3, thereby ensuring the performance of the device. In a preferred embodiment, the concentration of the injected C ions is between 1E11 / cm 2 ~1E14 / cm 2 .

[0061] The above method of this embodiment uses a thermal oxidation method instead of a PECVD method to form a SiO2 layer as a gate oxide layer on the GaN epitaxial layer, thereby avoiding damage to the epitaxial layer by plasma, improving the interface state between the SiO2 layer and the GaN epitaxial layer, significantly improving the performance of the device, and improving the gate's control over the channel. In addition, by strictly controlling the time and temperature of thermal oxidation, the Si epitaxial layer is completely oxidized while the GaN in the GaN epitaxial layer is not oxidized. At the same time, in order to further prevent the GaN epitaxial layer from being oxidized, the method of the present invention can also inject C ions at the interface between the Si epitaxial layer and the GaN epitaxial layer. The C ions help prevent the GaN epitaxial layer from being oxidized, thereby ensuring the performance of the device.

[0062] Embodiment 2

[0063] This embodiment provides a method for manufacturing a GaN MOS HEMT, such as Figure 6As shown, the method comprises the following steps:

[0064] Step S201: providing a substrate;

[0065] Step S202: forming a GaN epitaxial layer on the substrate;

[0066] GaN MOS HEMT devices usually use Si substrate or SiC substrate, such as Figure 7 As shown, the substrate 200 provided in this embodiment takes a Si substrate as an example. A GaN epitaxial layer 201 is formed on the substrate 200. In an optional embodiment, the formation of the GaN epitaxial layer 201 includes sequentially forming a nucleation layer 2011, a buffer layer 2012, an isolation layer 2013, a charge supply layer 2014 and a barrier layer 2015 on the substrate. Preferably, the nucleation layer 2011 is an AlN layer with a thickness of about 1 μm, the buffer layer 2012 is a GaN layer with a thickness of about 2 μm, the isolation layer 2013 is an AlGaN layer with a thickness of about 1 nm, the charge supply layer 2014 is an AlGaN layer with a thickness of about 20 nm, and the barrier layer 2015 is a GaN layer with a thickness of about 3 nm. The buffer layer 2012 and the isolation layer 2013 form a heterojunction.

[0067] Step S203: forming a Si epitaxial layer on the GaN epitaxial layer;

[0068] like Figure 8 As shown, a Si epitaxial layer 202 is epitaxially grown on the formed GaN epitaxial layer. The thickness of the Si epitaxial layer 102 can be determined according to the thickness of the gate oxide layer required by the device. For example, the thickness of the Si epitaxial layer 202 is approximately less than 22 nm.

[0069] Step S204: thermally oxidizing the Si epitaxial layer to completely oxidize the Si epitaxial layer to form a SiO2 layer, and the SiO2 layer serves as a gate oxide layer;

[0070] like Fig. 9 As shown, the Si epitaxial layer 202 is oxidized so that the Si epitaxial layer is completely oxidized to form a SiO2 layer 203, which serves as a gate oxide layer of the GaN MOS HEMT.

[0071] In this embodiment, the Si epitaxial layer is oxidized by thermal oxidation, and the oxidation temperature is usually controlled between 900° C. and 1200° C. During the thermal oxidation process, the temperature and time of the reaction are strictly controlled, so that the Si epitaxial layer is completely oxidized to form a SiO2 layer, and on the other hand, the reaction gas O2 and Si are prevented from diffusing into the GaN epitaxial layer, causing oxidation of GaN and affecting the performance of the device.

[0072] According to the principle that the number of Si atoms in the Si epitaxial layer and the number of Si atoms in the SiO2 layer remain unchanged before and after oxidation, we can get: t Si N Si =t ox N ox (1)

[0073] Among them, t Si is the thickness of the Si epitaxial layer, N Si is the density of Si atoms in the Si epitaxial layer, specifically 5×10 22 atoms / cm 3 ;t ox is the thickness of the SiO2 layer, N ox is the density of Si atoms in the SiO2 layer, specifically 2.2×10 22 atoms / cm 3 .

[0074] According to the above formula (1) and the final desired or required thickness of the SiO2 layer, the thickness t of the Si epitaxial layer grown on the GaN epitaxial layer can be determined. Si :

[0075] In the above method, the thickness of the SiO2 layer finally formed may be less than or greater than the desired thickness of the gate oxide layer, and compensation can be made for different situations. When the thickness of the SiO2 layer exceeds the thickness of the gate oxide layer required by the device, part of the SiO2 layer can be removed by thinning to meet the desired thickness, for example, it can be thinned by chemical mechanical polishing. When the thickness of the SiO2 layer cannot meet the thickness of the gate oxide layer required by the device, and the control ability of the channel is insufficient, a high-k dielectric layer can be continued to grow on the SiO2 layer, and the high-k dielectric layer and the SiO2 layer serve as the gate oxide layer together to meet the desired thickness. For example, Al2O3 or HfO2 can be grown on the SiO2 layer by atomic layer deposition.

[0076] As described above, a Si epitaxial layer is epitaxially grown on the GaN epitaxial layer, and then the Si epitaxial layer is completely oxidized into a SiO2 layer by thermal oxidation, thereby obtaining a SiO2-GaN interface with a good cross-sectional state, which can significantly improve the performance of the device. At the same time, it can ensure the desired gate oxide layer thickness required by the device and improve the control ability of the device channel layer.

[0077] Step S205: forming a gate on the gate oxide layer, and forming a source and a drain on the GaN epitaxial layer.

[0078] like Fig.10As shown, a gate 204 is formed on the gate oxide layer 203, and a source 205 and a drain 206 are formed on the GaN epitaxial layers on both sides of the gate. When a voltage is applied to the device through the gate, the heterojunction formed by the buffer layer 2012 and the isolation layer 2013 produces a piezoelectric effect, and finally a two-dimensional electron gas 2D EG (2-D electron gas) is generated at the junction of the heterojunction.

[0079] In this embodiment, the AlN nucleation layer, the GaN buffer layer, the AlGaN isolation layer, the AlGaN charge supply layer, and the GaN barrier layer are sequentially epitaxially grown on the substrate in step 202, and the source S, the drain D, and the gate G are manufactured in step 205, all of which can adopt the commonly used GaN MOS process flow.

[0080] In an alternative embodiment of this embodiment, if Fig.11 As shown, before oxidizing the Si epitaxial layer, it also includes: injecting carbon C ions into the interface between the Si epitaxial layer and the GaN epitaxial layer. The presence of C ions can effectively prevent O2 or Si from diffusing into the GaN epitaxial layer, thereby effectively preventing GaN from being oxidized to form Ga2O3, thereby ensuring the performance of the device. In a preferred embodiment, the concentration of the injected C ions is between 1E11 / cm 2 ~1E14 / cm 2 .

[0081] In summary, the method for forming a gate oxide layer of a GaN MOS HEMT and the method for manufacturing a GaN MOS HEMT provided by the present invention have at least the following beneficial effects:

[0082] The gate oxide layer forming method of GaN MOS HEMT and the manufacturing method of GaN MOS HEMT of the present invention first form a Si epitaxial layer on the GaN epitaxial layer of GaN MOS HEMT, and then oxidize the Si epitaxial layer by thermal oxidation, so that the Si epitaxial layer is completely oxidized into a SiO2 layer, and the SiO2 layer is used as a gate oxide layer. The above method of the present invention avoids damage to the epitaxial layer by plasma, improves the interface state between the SiO2 layer and the GaN epitaxial layer, significantly improves the performance of the device, and improves the control ability of the gate over the channel. In addition, by strictly controlling the time and temperature of thermal oxidation, the Si epitaxial layer is completely oxidized while the GaN in the GaN epitaxial layer is not oxidized. At the same time, in order to further prevent the GaN epitaxial layer from being oxidized, the method of the present invention can also implant C ions at the interface between the Si epitaxial layer and the GaN epitaxial layer, and the C ions help to prevent the GaN epitaxial layer from being oxidized, thereby ensuring the performance of the device.

[0083] In the present invention, in order to ensure the thickness of the gate oxide layer, if the thickness of the gate oxide layer SiO2 exceeds the thickness required by the device, the SiO2 layer can be thinned, for example, by CMP; if the thickness of the gate oxide layer SiO2 is insufficient and the control ability of the channel is insufficient, a high-k dielectric layer can be continued to be grown on the SiO2 layer, for example, an ALD method is used to grow an Al2O3 or HfO2 layer, etc. As described above, the present invention can ensure the desired ideal gate oxide layer thickness, enhance the control ability of the channel, and improve the performance of the GaN device.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for forming a gate oxide layer of a GaN MOS HEMT, characterized in that: The following steps are involved: forming a Si epitaxial layer on a GaN epitaxial layer of a GaN MOS HEMT; Implanting C ions into the interface between the Si epitaxial layer and the GaN epitaxial layer; The Si epitaxial layer is thermally oxidized so that the Si epitaxial layer is completely oxidized to form a SiO2 layer, and the SiO2 layer serves as a gate oxide layer.

2. The method for forming a gate oxide layer according to claim 1, wherein: The concentration of implanted C ions is between 1E11 / cm 2 ~ 1E14 / cm 2 .

3. The method for forming a gate oxide layer according to claim 1, wherein: The thickness of the Si epitaxial layer is determined according to the required thickness of the gate oxide layer, wherein the thickness of the Si epitaxial layer t Si The thickness of the gate oxide layer t ox satisfy: ； in, is the density of Si in SiO2, is the density of Si in elemental Si.

4. The method for forming a gate oxide layer according to claim 1, wherein: The method also includes thinning the gate oxide layer.

5. The method for forming a gate oxide layer according to claim 1, wherein: The method also includes forming a high-k dielectric layer above the gate oxide layer.

6. A method for manufacturing a GaN MOS HEMT, characterized in that: The following steps are involved: providing a substrate; forming a GaN epitaxial layer on the substrate; forming a Si epitaxial layer on the GaN epitaxial layer; Implanting C ions into the interface between the Si epitaxial layer and the GaN epitaxial layer; Thermally oxidizing the Si epitaxial layer so that the Si epitaxial layer is completely oxidized to form a SiO2 layer, wherein the SiO2 layer serves as a gate oxide layer; A gate is formed on the gate oxide layer, and a source and a drain are formed on the GaN epitaxial layer.

7. The manufacturing method according to claim 6, characterized in that: Forming a GaN epitaxial layer on the substrate includes sequentially forming a nucleation layer, a buffer layer, an isolation layer, a charge supply layer, and a barrier layer on the substrate.

8. The manufacturing method according to claim 6, characterized in that: The concentration of implanted C ions is between 1E11 / cm 2 ~1E14 / cm 2 .

9. The manufacturing method according to claim 6, characterized in that: The thickness of the Si epitaxial layer is determined according to the required thickness of the gate oxide layer, wherein the thickness of the Si epitaxial layer t Si The thickness of the gate oxide layer t ox satisfy: ； in, is the density of Si in SiO2, is the density of Si in elemental Si.

10. The manufacturing method according to claim 6, characterized in that: The method also includes thinning the gate oxide layer.

11. The manufacturing method according to claim 6, characterized in that: The method also includes forming a high-k dielectric layer above the gate oxide layer.

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