Electrostatic discharge I / O structure

By designing an interleaved stacked upper and lower IO layer connection to form a discharge path, the problems of poor effectiveness and uniformity of electrostatic discharge IO are solved, and the electrostatic discharge efficiency is improved.

CN115132706BActive Publication Date: 2025-10-31SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Patent Information

Application Number
CN202210677897.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-06-15
Publication Date
2025-10-31
Estimated Expiration
2042-06-15

AI Technical Summary

Technical Problem

In related technologies, the lack of effective interconnection between the multiple narrow metal strips of electrostatic discharge IO leads to a decrease in the effectiveness and uniformity of electrostatic discharge IO.

Method used

Design an electrostatic discharge I/O structure in which an upper I/O layer and a lower I/O layer are stacked alternately and connected by multiple I/O strips in the upper and lower layers to form a discharge path.

Benefits of technology

The effectiveness and uniformity of the electrostatic discharge pathway were optimized, thus improving the efficiency of electrostatic discharge.

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Abstract

This application relates to the field of semiconductor integrated circuit manufacturing technology, specifically to an electrostatic discharge (ESD) I / O structure. The ESD I / O structure includes a lower I / O layer and an upper I / O layer; the upper I / O layer includes multiple spaced-apart upper I / O strips on the same layer, and the lower I / O layer includes multiple spaced-apart lower I / O strips on the same layer; the upper and lower I / O strips are staggered and stacked. By connecting the multiple I / O strips of the upper and lower layers together, a discharge path can be formed between any two I / O strips, thereby optimizing the effectiveness and uniformity of the ESD discharge path.
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Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, and specifically to an electrostatic discharge I / O structure. Background Technology

[0002] Input / output interfaces are the link between semiconductor integrated circuits and the controlled object for information exchange. However, static electricity generated during use can enter the integrated circuit through these interfaces, which can easily damage the integrated circuit.

[0003] Therefore, related technologies typically incorporate electrostatic discharge (ESD) paths in the input / output circuits to release generated electrostatic charges. These ESD paths include a power supply terminal IO110 and a ground terminal IO120. Both the power supply terminal IO110 and the ground terminal IO120 include... Figure 1 The multiple narrow strips of metal 130 shown are designed to meet the metal density requirements of semiconductor integrated circuits.

[0004] However, in the related technology, the lack of effective interconnection between the multiple narrow strip metals 130 of the electrostatic discharge IO makes the effectiveness and uniformity of the electrostatic discharge IO worse. Summary of the Invention

[0005] This application provides an electrostatic discharge I / O structure that can solve the problems of poor effectiveness and uniformity of electrostatic discharge I / O in related technologies.

[0006] To address the technical problems described in the background art, this application provides an electrostatic discharge IO structure, which includes a lower IO layer and an upper IO layer.

[0007] The upper IO layer includes multiple upper IO lines spaced apart on the same layer, and the lower IO layer includes multiple lower IO lines spaced apart on the same layer.

[0008] The upper-layer IO bars and the lower-layer IO bars are stacked alternately.

[0009] Optionally, each of the lower layer I / O bars is located at the interval between two adjacent upper layer I / O bars and is in contact with the two adjacent upper layer I / O bars.

[0010] Optionally, the upper IO strip is made of conductive metal.

[0011] Optionally, the material of the lower layer IO strip is conductive metal.

[0012] The technical solution of this application has at least the following advantages: The electrostatic discharge IO structure provided by this application includes multiple narrow metal strips located on the same layer, and is connected together by multiple IO strips in the upper and lower layers, so that a discharge path can be formed between any two IO strips, thereby optimizing the effectiveness and uniformity of the electrostatic discharge path. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0014] Figure 1 A schematic diagram of the electrostatic discharge I / O structure of the related technology is shown;

[0015] Figure 2 This paper shows a cross-sectional view of an electrostatic discharge I / O structure according to an embodiment of the present application.

[0016] Figure 3 A top view of an electrostatic discharge I / O structure according to an embodiment of this application is shown. Detailed Implementation

[0017] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0020] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0021] Figure 2 This paper shows a cross-sectional view of an electrostatic discharge I / O structure according to an embodiment of the present application. Figure 3 This diagram shows a top view of an electrostatic discharge I / O structure according to an embodiment of this application. Figure 2 and Figure 3 As can be seen from this, the electrostatic discharge IO structure includes:

[0022] The lower IO layer and the upper IO layer, the upper IO layer includes a plurality of upper IO bars 220 spaced apart on the same layer, and the lower IO layer includes a plurality of lower IO bars 210 spaced apart on the same layer.

[0023] The upper layer IO strip 220 and the lower layer IO strip 210 are staggered and stacked.

[0024] Each of the lower layer IO strips 210 is located at the interval between two adjacent upper layer IO strips 220 and is in contact with the two adjacent upper layer IO strips 220.

[0025] The upper IO strip 220 is made of conductive metal, and the lower IO strip 210 is made of conductive metal.

[0026] The electrostatic discharge I / O structure provided in this application includes multiple narrow metal strips located on the same layer, which are connected together by multiple metal strips in the upper and lower layers, so that a discharge path can be formed between any two metal strips, thereby optimizing the effectiveness and uniformity of the electrostatic discharge path.

[0027] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. An electrostatic discharge I / O structure, characterized in that, The electrostatic discharge I / O structure includes: a lower I / O layer and an upper I / O layer; The upper IO layer includes multiple upper IO strips spaced apart on the same layer, and the lower IO layer includes multiple lower IO strips spaced apart on the same layer. Both the upper IO strips and the lower IO strips are made of conductive metal. The upper-layer IO bars and the lower-layer IO bars are stacked in an alternating manner; Each of the lower-level I / O bars is located at the interval between two adjacent upper-level I / O bars and is in contact with the two adjacent upper-level I / O bars.

Citation Information

Patent Citations

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