Power semiconductor module structure based on copper-clad ceramic substrate copper-clad pattern design

Abstract

The invention discloses a power semiconductor module structure based on the copper-clad pattern design of a copper-clad ceramic substrate. In this structure, positive and negative copper-clad patterns and three-phase copper-clad patterns are arranged on the copper-clad ceramic substrate. Upper and lower bridge gate signal patterns and Kelvin source signal patterns are hollowed out on the negative copper-clad patterns and the three-phase copper-clad patterns, and corresponding first and second transition connection terminals are arranged. A plurality of upper and lower bridge power semiconductor chips are divided into two groups and symmetrically arranged on the positive copper-clad patterns and the three-phase copper-clad patterns. A floating copper terminal is arranged in the center of each group of power semiconductor chips. The power semiconductor chips of the upper and lower bridges are connected to adjacent three-phase copper-clad patterns and negative copper-clad patterns through current binding wires, the gate is connected to the floating copper terminal through signal binding wires, the floating copper terminal and the Kelvin source are connected to the first and second transition connection terminals, and the gate and Kelvin source signals of the transition connection terminals are connected to the upper and lower bridge gate signal patterns and the Kelvin source signal patterns. This structure realizes the module current sharing characteristic and ensures the reliability of the open tube.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and in particular to a power semiconductor module structure based on a copper-clad ceramic substrate copper-clad pattern design. Background Art

[0002] Power semiconductor modules are circuit modules that combine power semiconductor chips into a whole according to certain functional combinations. They have the advantages of small size and high power density, so they are widely used in the field of new energy vehicles. With the development of high-power and long-range new energy vehicles, the application environment of power semiconductor modules is becoming increasingly harsh, and the current sharing characteristics of power semiconductor modules have received extensive attention.

[0003] With the rapid development of new energy vehicles, Si-based and SiC-based power semiconductor modules have continued to develop. In these high-power application fields, higher and higher requirements are placed on the switching frequency of power semiconductor modules. In order to obtain higher rated currents and lower manufacturing costs, these power semiconductor modules usually adopt a multi-chip parallel packaging structure. However, due to the asymmetry of the current loop of the copper-clad ceramic substrate and the inconsistency of the dynamic and static parameters of the power chip, a large transient unbalanced current will appear between the parallel chips, which brings considerable challenges to the safety and stability of the power semiconductor module.

[0004] In the three-phase AC motor control system, the circuit diagram of the power semiconductor module is as follows Figure 1 As shown, a plurality of power semiconductor chips are connected in parallel in the three-phase circuit, such as the upper bridge power semiconductor chips a1 to a6 and the lower bridge power semiconductor chips b1 to b6 of the U phase in the figure. Figure 2 The U phase circuit diagram is shown in Figure 2 In the circuit diagram, when the upper bridge power semiconductor chips a1 to a6 are turned on and the lower bridge power semiconductor chips b1 to b6 are turned off, the current Ia flows from the positive busbar to the three-phase busbar. The resistance value of the source and gate control loop signals of each power semiconductor chip, the inductance generated by the length, the resistance and inductance between the power semiconductor chips, etc. determine the opening time of each power semiconductor chip. Assuming that the switching time of power semiconductor chip a1 is earlier than that of other power semiconductor chips, a large current will flow through power semiconductor chip a1. In extreme cases, it will cause damage to power semiconductor chip a1. At the same time, if Figure 3As shown, when the lower bridge power semiconductor chips b1 to b6 are turned on and the upper bridge power semiconductor chips a1 to a6 are turned off, the current Ia flows from the three-phase busbar to the negative busbar. In this case, as mentioned above, if the power semiconductor chip b6 closest to the three-phase busbar is turned on earlier than other power semiconductor chips, the current will flow through the power semiconductor chip b6, and in extreme cases, it will damage the power semiconductor chip b6. In this way, the service life and performance of the power semiconductor module are reduced, the control performance of the motor is seriously affected, and there are certain safety hazards.

[0005] Usually, the block diagram of the power semiconductor module in the three-phase AC motor control system is as follows: Figure 4 As shown, it has a positive busbar and a negative busbar on one side of the power semiconductor module and a three-phase busbar on the other side, and 6 or 8 power semiconductor chips are connected in parallel in each phase for carrying large current.

[0006] Among SiC power semiconductors designed for high-speed driving, some are designed with Kelvin sources in the power semiconductors. The Kelvin source connection is to separate the source of the power semiconductor chip into two parts, one part is the main path for large current to flow, and the other part is used for the return path of the gate drive signal. The Kelvin source connection is the same as the gate signal line, which makes the wiring length from the signal terminal to the power semiconductor of each power semiconductor uniform, and can weaken the deviation of the switching time of different power semiconductors. In the case of Kelvin source connection, it is preferred that the total length Ltn of the gate signal line and the Kelvin source signal line in each power semiconductor satisfies the following formula:

[0007] Ltn=Lgn+Lkn

[0008] Among them, Ltn is the total length, Lgn is the gate signal line length, and Lkn is the Kelvin source signal line length. Summary of the invention

[0009] The technical problem to be solved by the present invention is to provide a power semiconductor module structure based on a copper-clad ceramic substrate copper-clad pattern design. The structure adjusts the length of the source and gate loop signal lines of the power semiconductor chip through the current pattern design of the copper-clad ceramic substrate and the bonding wire connection, and then adjusts the opening time of each power semiconductor chip, thereby achieving current sharing characteristics, ensuring the opening reliability of the power semiconductor module, and improving the service life and performance of the power semiconductor module.

[0010] In order to solve the above technical problems, the power semiconductor module structure based on the copper-clad ceramic substrate copper-clad texture design of the present invention includes a copper-clad ceramic substrate, a positive busbar, a negative busbar, a three-phase terminal, a plurality of upper bridge power semiconductor chips and a plurality of lower bridge power semiconductor chips, the positive busbar includes a first positive terminal and a second positive terminal, the copper-clad ceramic substrate has positive copper-clad textures extending from the upper edge to the lower edge on both sides, and negative copper-clad textures are provided between the positive copper-clad textures on both sides from the upper edge to the middle, the negative copper-clad textures form a first branch, a second branch and a third branch from left to right on the upper part of the copper-clad ceramic substrate, and the lower part of the copper-clad ceramic substrate extends from the lower edge to the copper-clad between the positive copper-clad textures on both sides. A three-phase copper-clad pattern is extended on the upper part of the ceramic substrate, and the three-phase copper-clad pattern forms a fourth branch, a middle area and a fifth branch from left to right at the lower part of the copper-clad ceramic substrate, and forms a left area and a right area at the upper part of the copper-clad ceramic substrate. The fourth branch and the fifth branch are respectively located at the left edge and the right edge of the copper-clad ceramic substrate, and the middle area is located between the positive copper-clad patterns on both sides, the left area is located between the first branch and the second branch of the negative copper-clad pattern, and the right area is located between the second branch and the third branch of the negative copper-clad pattern. The lower part of the three-phase copper-clad pattern is hollowed out, and the upper bridge gate signal pattern and the upper bridge Kelvin source signal pattern are arranged at intervals in the hollowed-out part. The middle area of ​​the three-phase copper-clad pattern is hollowed out in the center, and the first transition connection terminal is arranged at intervals in the hollowed-out part. The upper part of the negative copper-clad pattern is hollowed out in the center, and the lower bridge gate signal pattern and the lower bridge Kelvin source signal pattern are arranged at intervals in the hollowed-out part. The second branch of the negative copper-clad pattern is hollowed out in the center, and the second transition connection terminal is arranged at intervals in the hollowed-out part. The first positive terminal and the second positive terminal are respectively arranged on the positive copper-clad patterns on both sides of the copper-clad ceramic substrate and are located at the upper edge. The negative busbar is arranged on the negative copper-clad patterns and is located at the upper edge. The three-phase terminal is arranged on the three-phase copper-clad patterns and is located at the lower edge. The plurality of upper bridge power semiconductor chips are divided into two groups and are arranged on both sides of the copper-clad ceramic substrate. The positive copper-clad lines are located at the bottom of the copper-clad ceramic substrate, and the positive copper-clad lines of each group of upper bridge power semiconductor chips are centrally provided with a first floating copper terminal, and each group of upper bridge power semiconductor chips is connected to adjacent three-phase copper-clad lines via current binding lines, and the gate is connected to the first floating copper terminal, and the Kelvin source is connected to the first transition connection terminal via a signal binding line, and the first floating copper terminal is connected to the first transition connection terminal, and the gate signal and the Kelvin source signal of the first transition connection terminal are respectively connected to the upper bridge gate signal lines and the upper bridge Kelvin source signal lines, and the plurality of lower bridge power semiconductor chips are divided into two groups and are respectively arranged in the left area and the right area of ​​the three-phase copper-clad lines, and the left area and the right area are respectively centrally provided with a second floating copper terminal,Each group of lower bridge power semiconductor chips is connected to adjacent negative electrode copper-clad lines via current bonding wires, the gate is connected to the second floating copper terminal, the Kelvin source is connected to the second transition connection terminal via signal bonding wires, the second floating copper terminal is connected to the second transition connection terminal, and the gate signal and Kelvin source signal of the second transition connection terminal are respectively connected to the lower bridge gate signal lines and the lower bridge Kelvin source signal lines.

[0011] Furthermore, in each group of power semiconductor chips of the plurality of upper-bridge power semiconductor chips and the plurality of lower-bridge power semiconductor chips, a distance between adjacent power semiconductor chips arranged in parallel on the left and right sides is ≤2 mm.

[0012] Furthermore, the distance difference between two groups of power semiconductor chips of the plurality of upper bridge power semiconductor chips and the first transition connection terminal is ≤2 mm, and the distance difference between the first floating copper terminal and the gate of each power semiconductor chip is ≤2 mm.

[0013] Furthermore, the distance difference between two groups of power semiconductor chips of the plurality of lower bridge power semiconductor chips and the second transition connection terminal is ≤2 mm, and the distance difference between the second floating copper terminal and the gate of each power semiconductor chip is ≤2 mm.

[0014] Furthermore, in each group of power semiconductor chips of the plurality of upper bridge power semiconductor chips, the Calvin sources of adjacent power semiconductor chips arranged in parallel on the left and right are connected together through bonding wires, and then connected to the first transition connection terminal through the bonding wires, and the distance difference from the first transition connection terminal to the Calvin source of each power semiconductor chip is ≤5mm.

[0015] Furthermore, in each group of power semiconductor chips of the plurality of lower bridge power semiconductor chips, the Calvin sources of adjacent power semiconductor chips arranged in parallel on the left and right are connected together through bonding wires, and then connected to the second transition connection terminal through the bonding wires, and the distance difference from the second transition connection terminal to the Calvin source of each power semiconductor chip is ≤5mm.

[0016] Furthermore, among the several upper bridge power semiconductor chips and the several lower bridge power semiconductor chips, the difference between the total length of the distance from the gate of each power semiconductor chip to the first floating copper terminal or the second floating copper terminal plus the distance from the Kelvin source of the power semiconductor chip to the first transition connection terminal or the second transition connection terminal is less than or equal to 5 mm.

[0017] Further, the number of upper bridge power semiconductor chips and the number of lower bridge power semiconductor chips are six or eight respectively, and three power semiconductor chips or four power semiconductor chips form a group.

[0018] Furthermore, when three power semiconductor chips form a group, the power semiconductor chips are arranged in a herringbone shape or an inverted herringbone shape; when four power semiconductor chips form a group, the power semiconductor chips are arranged in double rows and double columns.

[0019] Since the power semiconductor module structure designed based on the copper-clad ceramic substrate copper-clad texture of the present invention adopts the above-mentioned technical solution, that is, the structure arranges the positive copper-clad texture, the negative copper-clad texture and the three-phase copper-clad texture on the copper-clad ceramic substrate according to a certain rule, and hollows out the gate signal texture and Kelvin source signal texture of the upper and lower bridges on the negative copper-clad texture and the three-phase copper-clad texture, and sets the corresponding first and second transition connection terminals, a plurality of upper and lower bridge power semiconductor chips are divided into two groups and symmetrically arranged on the positive copper-clad texture and the three-phase copper-clad texture, each group of power semiconductor chips is provided with a floating copper terminal in the center, and the power semiconductor chip of the upper bridge The adjacent three-phase copper-clad lines are connected via current binding lines, the gate is connected to the floating copper terminal via signal binding lines, the floating copper terminal and the Kelvin source are connected to the first transition connection terminal, the gate and Kelvin source signals of the first transition connection terminal are connected to the gate signal lines and the Kelvin source signal lines of the upper bridge, the power semiconductor chip of the lower bridge is connected to the adjacent negative copper-clad lines via current binding lines, the gate is connected to the floating copper terminal via signal binding lines, the floating copper terminal and the Kelvin source are connected to the second transition connection terminal, and the gate and Kelvin source signals of the second transition connection terminal are connected to the gate signal lines and the Kelvin source signal lines of the lower bridge. This structure adjusts the length of the source and gate loop signal lines of the power semiconductor chip through the current pattern design of the copper-clad ceramic substrate and the connection of the bonding line, and then adjusts the opening time of each power semiconductor chip, thereby realizing the current sharing characteristic, ensuring the opening reliability of the power semiconductor module, and improving the service life and performance of the power semiconductor module. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments:

[0021] Figure 1 It is the circuit diagram of the power semiconductor module in the three-phase AC motor control system;

[0022] Figure 2 for Figure 1 Schematic diagram of the flow direction of the upper bridge current of the middle U phase;

[0023] Figure 3 for Figure 1 Schematic diagram of the flow direction of the lower bridge current of the middle U phase;

[0024] Figure 4 This is the block diagram of the power semiconductor module in the three-phase AC motor control system;

[0025] Figure 5 This is a schematic diagram of the structure of a power semiconductor module of the present invention;

[0026] Figure 6 for Figure 5 A magnified schematic diagram of the middle part;

[0027] Figure 7 for Figure 5 The enlarged schematic diagram of the middle B part;

[0028] Figure 8 for Figure 5 Schematic diagram of structural deformation of power semiconductor module Figure 1 ;

[0029] Fig. 9 for Figure 5 Schematic diagram of structural deformation of power semiconductor module Figure 2 ;

[0030] Fig.10 for Figure 5 Schematic diagram of structural deformation of power semiconductor module Figure 3 ;

[0031] Fig.11 Schematic diagram of the series circuit of inductor L and resistor R. DETAILED DESCRIPTION

[0032] Implementation example Figure 5 , Figure 6 and Figure 7As shown, the power semiconductor module structure based on the copper-clad ceramic substrate copper-clad pattern design of the present invention includes a copper-clad ceramic substrate 1, a positive busbar, a negative busbar 3, a three-phase terminal 4, a plurality of upper bridge power semiconductor chips a and a plurality of lower bridge power semiconductor chips b, the positive busbar includes a first positive terminal 21 and a second positive terminal 22, positive copper-clad patterns 11 and 12 are provided on both sides of the copper-clad ceramic substrate 1 from the upper edge to the lower edge, and negative copper-clad patterns 13 are provided between the positive copper-clad patterns 11 and 12 on both sides from the upper edge to the middle, and the negative copper-clad patterns 13 form a first branch 131, a second branch 132 and a third branch 133 from left to right on the upper part of the copper-clad ceramic substrate 1, and the lower part of the copper-clad ceramic substrate 1 on both sides A three-phase copper-clad pattern 14 is provided between the positive copper-clad patterns 11 and 12, extending from the lower edge to the upper part of the copper-clad ceramic substrate 1. The three-phase copper-clad pattern 14 forms a fourth branch 141, a middle area 142 and a fifth branch 143 from left to right at the lower part of the copper-clad ceramic substrate 1, and forms a left area 144 and a right area 155 at the upper part of the copper-clad ceramic substrate 1. The fourth branch 141 and the fifth branch 143 are respectively located at the left edge and the right edge of the copper-clad ceramic substrate 1, and the middle area 142 is located between the positive copper-clad patterns 11 and 12 on both sides. The left area 144 is located between the first branch 131 and the second branch 132 of the negative copper-clad pattern 13, and the right area 145 is located at the negative copper-clad pattern 13. Between the second branch 132 and the third branch 133 of the pattern 13, the lower part of the three-phase copper-clad pattern 14 is hollowed out, and the upper bridge gate signal pattern 15 and the upper bridge Kelvin source signal pattern 16 are arranged at intervals in the hollowed-out part. The middle area of ​​the three-phase copper-clad pattern 14 is hollowed out in the center, and the first transition connection terminal 17 is arranged at intervals in the hollowed-out part. The upper part of the negative copper-clad pattern 13 is hollowed out in the center, and the lower bridge gate signal pattern 18 and the lower bridge Kelvin source signal pattern 19 are arranged at intervals in the hollowed-out part. The second branch 132 of the negative copper-clad pattern 13 is hollowed out in the center, and the second transition connection terminal 20 is arranged at intervals in the hollowed-out part. The first positive terminal 21 and the second positive terminal 22 are respectively arranged on the positive copper-clad patterns 11 on both sides of the copper-clad ceramic substrate 1 , 12 and are located at the upper edge, the negative busbar 3 is arranged on the negative copper-clad pattern 13 and is located at the upper edge, the three-phase terminal 4 is arranged on the three-phase copper-clad pattern 14 and is located at the lower edge, the plurality of upper bridge power semiconductor chips a are divided into two groups of positive copper-clad patterns 11 and 12 arranged on both sides of the copper-clad ceramic substrate 1 and are located at the lower part of the copper-clad ceramic substrate 1, and the positive copper-clad patterns 11 and 12 of each group of upper bridge power semiconductor chips a are centrally provided with a first floating copper terminal 5, each group of upper bridge power semiconductor chips a is connected to adjacent three-phase copper-clad patterns 14 via current binding wires 6, the gate is connected to the first floating copper terminal 5, the Kelvin source is connected to the first transition connection terminal 17 via signal binding wires 7, and the first floating copper terminal 5 is connected to the first transition connection terminal 17,The gate signal and Kelvin source signal of the first transition connection terminal 17 are connected to the upper bridge gate signal pattern 15 and the upper bridge Kelvin source signal pattern 16 respectively. The plurality of lower bridge power semiconductor chips b are divided into two groups and are respectively arranged in the left area 144 and the right area 145 of the three-phase copper-clad pattern 14. The left area 144 and the right area 145 are respectively provided with a second floating copper terminal 8 in the middle. Each group of lower bridge power semiconductor chips b is connected to the adjacent negative electrode copper-clad pattern 13 via the current binding line 9, the gate is connected to the second floating copper terminal 8, and the Kelvin source is connected to the second transition connection terminal 20 via the signal binding line 10. The second floating copper terminal 8 is connected to the second transition connection terminal 20. The gate signal and Kelvin source signal of the second transition connection terminal 20 are respectively connected to the lower bridge gate signal pattern 18 and the lower bridge Kelvin source signal pattern 19.

[0033] Preferably, in each group of power semiconductor chips of the plurality of upper-bridge power semiconductor chips a and the plurality of lower-bridge power semiconductor chips b, a distance between adjacent power semiconductor chips arranged in parallel on the left and right sides is ≤2 mm.

[0034] Preferably, the distance difference between the two groups of power semiconductor chips of the plurality of upper bridge power semiconductor chips a and the first transition connection terminal 17 is ≤2 mm, and the distance difference between the first floating copper terminal 5 and the gate of each power semiconductor chip a is ≤2 mm.

[0035] Preferably, the distance difference between two groups of power semiconductor chips of the plurality of lower bridge power semiconductor chips b and the second transition connection terminal 20 is ≤2 mm, and the distance difference between the second floating copper terminal 8 and the gate of each power semiconductor chip b is ≤2 mm.

[0036] Preferably, in each group of power semiconductor chips of the plurality of upper bridge power semiconductor chips a, the Calvin sources of adjacent power semiconductor chips arranged in parallel on the left and right are connected together through bonding wires, and then connected to the first transition connection terminal 17 through the bonding wires, and the distance difference from the first transition connection terminal 17 to the Calvin source of each power semiconductor chip a is ≤5 mm.

[0037] Preferably, in each group of power semiconductor chips of the plurality of lower bridge power semiconductor chips b, the Calvin sources of adjacent power semiconductor chips arranged in parallel on the left and right are connected together through bonding wires, and then connected to the second transition connection terminal 20 through the bonding wires, and the distance difference from the second transition connection terminal 20 to the Calvin source of each power semiconductor chip b is ≤5 mm.

[0038] Preferably, among the several upper bridge power semiconductor chips a and the several lower bridge power semiconductor chips b, the difference in the total length of the distance from the gate of each power semiconductor chip to the first floating copper terminal 5 or the second floating copper terminal 8 plus the distance from the Kelvin source of the power semiconductor chip to the first transition connection terminal 17 or the second transition connection terminal 20 is less than or equal to 5 mm.

[0039] Preferably, the number of upper-bridge power semiconductor chips a and the number of lower-bridge power semiconductor chips b are six or eight respectively, and three power semiconductor chips or four power semiconductor chips form a group.

[0040] Preferably, when three power semiconductor chips form a group, the power semiconductor chips are arranged in a herringbone shape or an inverted herringbone shape, and when four power semiconductor chips form a group, the power semiconductor chips are arranged in double rows and double columns.

[0041] In the power semiconductor module structure, the current flowing into the first positive terminal 21 and the second positive terminal 22 is divided on the positive copper clad patterns 11 and 12 on both sides of the power semiconductor chip a of the upper bridge, and is connected to the three-phase copper clad patterns 14 through the current bonding lines 6 on the two groups of power semiconductor chips a on the upper bridge, and then merged into the three-phase busbar 4; the two groups of power semiconductor chips b of the lower bridge are arranged in the left area 144 and the right area 145 of the three-phase copper clad patterns 14, and the three-phase busbar 4 is connected to the three-phase copper clad patterns 14; the current flowing into the three-phase busbar 4 flows through the three-phase copper clad patterns 14 where the two groups of power semiconductor chips b of the lower bridge are located, and is connected to the negative copper clad patterns 13 through the current bonding lines 9 on the power semiconductor chips b of the lower bridge, and then flows into the negative busbar 3.

[0042] like Figure 6 As shown, among the lower bridge power semiconductor chips b, the four power semiconductor chips on the left are a group, and the four power semiconductor chips on the right are another group. The current is transmitted to the negative copper clad pattern 13 through the two groups of power semiconductor chips in the lower bridge, and flows into the negative busbar 3; a floating copper terminal 8 is provided in the middle of the four power semiconductor chips on the left in the figure, and the gates of the four power semiconductor chips are connected to the floating copper terminal 8. A floating copper terminal 8 is also provided in the middle of the four power semiconductor chips on the right, and the gates of the four power semiconductor chips are also connected to the floating copper terminal 8. The floating copper terminals 8 on the left and right sides are then connected to the gates of the two groups of power semiconductor chips in the lower bridge through bonding wires. Through the above measures, the connection length Lgn from the gates of the eight power semiconductor chips in the lower bridge to the gate signal pattern 18 of the lower bridge is equal.

[0043] like Figure 7As shown, in the upper bridge power semiconductor chip a, a floating copper terminal 5 is provided in the middle of the four power semiconductor chips on the left, and the gates of the four power semiconductor chips are connected to the floating copper terminal 5. A floating copper terminal 5 is also provided in the middle of the four power semiconductor chips on the right, and the gates of the four power semiconductor chips are also connected to the floating copper terminal 5. The floating copper terminals 5 on the left and right sides are then connected to the gates of the two groups of power semiconductor chips on the upper bridge through bonding wires. Through the above measures, the connection length Lgn from the eight power semiconductor chips on the upper bridge to the gate signal lines 15 of the upper bridge is equal.

[0044] In the power semiconductor module structure, the upper bridge power semiconductor chips a and the lower bridge power semiconductor chips b have six or eight power semiconductor chips respectively. The upper bridge and lower bridge power semiconductor chips are divided into two groups, each group has three or four power semiconductor chips, and a floating copper terminal is provided in the middle of each group of power semiconductor chips. The floating copper terminal is used to connect the gate of each power semiconductor chip.

[0045] Among them, each group of four power semiconductor chips is arranged in double rows and double columns, and the spacing between adjacent power semiconductor chips in each row is less than or equal to 2mm. Since the spacing between the two chips is relatively close, the Kelvin connection length Lkn of the two chips can be regarded as approximately equal; the difference in distances from the left and right groups of power semiconductor chips on the upper bridge to the floating copper terminal is less than or equal to 2mm, and is preferably equal; the gate of each group of power semiconductor chips is connected to the floating copper terminal through a bonding wire, and the floating copper terminals on the left and right sides are then connected to the first transition connection terminal through a bonding wire, and finally connected to the gate signal pattern of the upper bridge; the difference in the length of the gate connection line from the gate signal pattern of the upper bridge to each power semiconductor chip is less than or equal to 5mm, and is preferably equal; the same applies to the lower bridge.

[0046] The Calvin sources of two side-by-side power semiconductor chips in each group of power semiconductor chips are connected together through bonding wires, then connected to the first transition connection terminal through bonding wires, and finally connected to the upper bridge Kelvin source signal lines; the difference in the length of the Kelvin source connection lines from the upper bridge Kelvin source signal lines to each power semiconductor chip is less than or equal to 5mm, preferably equal; the same applies to the lower bridge.

[0047] Figure 8 and Fig. 9 The module structure shown is Figure 5A variation of the invention, wherein the upper bridge and the lower bridge each have six power semiconductor chips, and the six power semiconductor chips of the upper bridge and the lower bridge are divided into two groups, each group has three power semiconductor chips, and the three power semiconductor chips can be arranged in a combination of two upper and one lower, or one upper and two lower; a floating copper terminal is provided in the middle of the three power semiconductor chips, and the position of a single-row power semiconductor chip can be moved in the left and right areas, but not exceeding the left and right range corresponding to two power semiconductor chips. The floating copper terminal in the middle of each group of power semiconductor chips ensures that the difference in the gate connection length from the gate signal pattern to each power semiconductor chip is less than or equal to 5 mm, preferably equal.

[0048] Fig.10 The module structure shown is Figure 5 A variation of this invention, in which the source of large current flowing through the power semiconductor chip and the source of the control signal are not separated, and the same connection signal is used, that is, the source of large current is used instead of the control signal source. Similarly, the difference between the total length Ltn of the length from the gate of each power semiconductor chip to the corresponding gate signal line plus the length from the control signal source of the chip to the corresponding Kelvin source signal line is less than or equal to 5 mm, and preferably they are equal.

[0049] like Fig.11 As shown, the inductor L represents the inductance between the power semiconductor chips, and the resistor R represents the resistance of the power semiconductor chip when it is turned on. In this circuit, the current i (t) generated instantly when the switch S is turned on is shown in Formula 1:

[0050] (1)

[0051] (2)

[0052] That is, when the inductance is large, even if the voltage E is applied, the current i(t) will not flow immediately. According to this principle, through the application of this module structure, the current in each power semiconductor chip can achieve a gradually increasing effect, thereby reducing the large current generated by the current concentrated through a certain power semiconductor chip, improving the current sharing characteristics of the module, and avoiding chip damage.

[0053] The power semiconductor module structure makes Ltn=Lgn+Lkn of each power semiconductor chip of the upper bridge and the lower bridge equal, weakens the deviation of the switching time of each power semiconductor chip of the upper bridge and the lower bridge, solves the current unevenness problem of the power semiconductor module, and improves the reliability of the power semiconductor module.

Claims

1. A power semiconductor module structure based on a copper-clad ceramic substrate copper-clad pattern design, comprising a copper-clad ceramic substrate, a positive busbar, a negative busbar, a three-phase terminal, a plurality of upper bridge power semiconductor chips and a plurality of lower bridge power semiconductor chips, characterized in that: The positive busbar includes a first positive terminal and a second positive terminal, positive copper-clad patterns are provided on both sides of the copper-clad ceramic substrate extending from the upper edge to the lower edge, and negative copper-clad patterns are provided between the positive copper-clad patterns on both sides from the upper edge to the middle, and the negative copper-clad patterns form a first branch, a second branch, and a third branch from left to right on the upper part of the copper-clad ceramic substrate, respectively, and three-phase copper-clad patterns are provided on the lower part of the copper-clad ceramic substrate between the positive copper-clad patterns on both sides, extending from the lower edge to the upper part of the copper-clad ceramic substrate, and the three-phase copper-clad patterns form a fourth branch, a middle area, and a fifth branch from left to right on the lower part of the copper-clad ceramic substrate, and form a left area and a right area on the upper part of the copper-clad ceramic substrate, and the fourth branch and the fifth branch are respectively The left edge and right edge of the copper-clad ceramic substrate and the middle area are located between the positive copper-clad patterns on both sides, the left area is located between the first branch and the second branch of the negative copper-clad patterns, and the right area is located between the second branch and the third branch of the negative copper-clad patterns. The lower part of the three-phase copper-clad patterns is hollowed out, and the upper bridge gate signal patterns and the upper bridge Kelvin source signal patterns are arranged at intervals in the hollowed-out parts. The middle area of ​​the three-phase copper-clad patterns is hollowed out in the center, and the first transition connection terminal is arranged at intervals in the hollowed-out parts. The upper part of the negative copper-clad patterns is hollowed out in the center, and the lower bridge gate signal patterns and the lower bridge Kelvin source signal patterns are arranged at intervals in the hollowed-out parts. The second branch of the negative copper-clad patterns is hollowed out in the center, and the upper bridge gate signal patterns and the lower bridge Kelvin source signal patterns are arranged at intervals in the hollowed-out parts. There is a second transition connection terminal, the first positive terminal and the second positive terminal are respectively arranged on the positive copper-clad lines on both sides of the copper-clad ceramic substrate and are located at the upper edge, the negative busbar is arranged on the negative copper-clad lines and is located at the upper edge, the three-phase terminal is arranged on the three-phase copper-clad lines and is located at the lower edge, the plurality of upper bridge power semiconductor chips are divided into two groups of positive copper-clad lines arranged on both sides of the copper-clad ceramic substrate and are located at the lower part of the copper-clad ceramic substrate, the positive copper-clad lines of each group of upper bridge power semiconductor chips are centrally provided with a first floating copper terminal, each group of upper bridge power semiconductor chips is connected to adjacent three-phase copper-clad lines via current binding lines, the gate is connected to the first floating copper terminal, the Kelvin source is connected to the first transition connection terminal via signal binding lines, and the first floating copper The terminal is connected to the first transition connection terminal, and the gate signal and Kelvin source signal of the first transition connection terminal are respectively connected to the upper bridge gate signal pattern and the upper bridge Kelvin source signal pattern. The plurality of lower bridge power semiconductor chips are divided into two groups and are respectively arranged in the left area and the right area of ​​the three-phase copper cladding pattern. The left area and the right area are respectively provided with a second floating copper terminal in the middle. Each group of lower bridge power semiconductor chips is connected to the adjacent negative copper cladding pattern through the current binding line, the gate is connected to the second floating copper terminal, and the Kelvin source is connected to the second transition connection terminal through the signal binding line. The second floating copper terminal is connected to the second transition connection terminal, and the gate signal and Kelvin source signal of the second transition connection terminal are respectively connected to the lower bridge gate signal pattern and the lower bridge Kelvin source signal pattern.

2. The power semiconductor module structure based on the copper-clad ceramic substrate copper-clad pattern design according to claim 1, characterized in that: In each group of power semiconductor chips of the plurality of upper bridge power semiconductor chips and the plurality of lower bridge power semiconductor chips, a distance between adjacent power semiconductor chips arranged in parallel on the left and right sides is ≤2 mm.

3. The power semiconductor module structure based on the copper-clad ceramic substrate copper-clad pattern design according to claim 1 or 2, characterized in that: The distance difference between the two groups of power semiconductor chips of the plurality of upper bridge power semiconductor chips and the first transition connection terminal is ≤2mm, and the distance difference between the first floating copper terminal and the gate of each power semiconductor chip is ≤2mm.

4. The power semiconductor module structure based on the copper-clad ceramic substrate copper-clad pattern design according to claim 1 or 2, characterized in that: The distance difference between the two groups of power semiconductor chips of the plurality of lower bridge power semiconductor chips and the second transition connection terminal is ≤2mm, and the distance difference between the second floating copper terminal and the gate of each power semiconductor chip is ≤2mm.

5. The power semiconductor module structure based on the copper-clad ceramic substrate copper-clad pattern design according to claim 1, characterized in that: In each group of power semiconductor chips of the plurality of upper bridge power semiconductor chips, the Calvin sources of adjacent power semiconductor chips arranged in parallel on the left and right are connected together through bonding wires, and then connected to the first transition connection terminal through the bonding wires. The distance difference from the first transition connection terminal to the Calvin source of each power semiconductor chip is ≤5mm.

6. The power semiconductor module structure based on the copper-clad ceramic substrate copper-clad pattern design according to claim 1, characterized in that: In each group of power semiconductor chips of the plurality of lower bridge power semiconductor chips, the Calvin sources of adjacent power semiconductor chips arranged in parallel on the left and right are connected together through bonding wires, and then connected to the second transition connection terminal through the bonding wires. The distance difference from the second transition connection terminal to the Calvin source of each power semiconductor chip is ≤5mm.

7. The power semiconductor module structure based on the copper-clad ceramic substrate copper-clad pattern design according to claim 5 or 6, characterized in that: Among the plurality of upper bridge power semiconductor chips and the plurality of lower bridge power semiconductor chips, the difference between the total length of the distance from the gate of each power semiconductor chip to the first floating copper terminal or the second floating copper terminal plus the distance from the Kelvin source of the power semiconductor chip to the first transition connection terminal or the second transition connection terminal is less than or equal to 5 mm.

8. The power semiconductor module structure based on the copper-clad ceramic substrate copper-clad pattern design according to claim 1, characterized in that: The number of upper-bridge power semiconductor chips and the number of lower-bridge power semiconductor chips are six or eight respectively, and three power semiconductor chips or four power semiconductor chips form a group.

9. The power semiconductor module structure based on the copper-clad ceramic substrate copper-clad pattern design according to claim 8, characterized in that: When three power semiconductor chips form a group, the power semiconductor chips are arranged in a herringbone shape or an inverted herringbone shape; when four power semiconductor chips form a group, the power semiconductor chips are arranged in double rows and double columns.

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