A full-bridge phase-shift converter with voltage clamping

Abstract

The application discloses a full-bridge phase-shift converter with voltage clamping, which comprises a transformer, a primary side circuit and a secondary side circuit. The secondary side circuit comprises a first synchronous rectification switch, a second synchronous rectification switch, an output inductor, a plurality of diodes, a capacitor, an energy release unit and an output capacitor. The capacitor provides a clamping voltage. The energy release unit is connected in parallel with the capacitor and converts the clamping voltage into an output voltage. The output capacitor is connected in parallel with the energy release unit and provides the output voltage.

Description

Technical Field

[0001] This invention relates to a full-bridge phase-shift converter, and more particularly to a full-bridge phase-shift converter with voltage clamping. Background Technology

[0002] In the prior art, please refer to Figure 1 As shown, the full-bridge phase-shift converter uses a lag arm and a lead arm formed by four power transistors to perform switching. The lag arm includes the first switch Q1 and the second switch Q2, and the lead arm includes the third switch Q3 and the fourth switch Q4. Furthermore, the first switch Q1 and the fourth switch Q4 together complete one half-cycle (positive half-cycle), while the second switch Q2 and the third switch Q3 complete the other half-cycle (negative half-cycle). Figure 1 As shown, the secondary side of the transformer is a synchronous rectification architecture, but in other circuit architectures it can also be a diode rectification architecture.

[0003] Incidentally, each half-bridge, i.e., the lagging or leading arm, switches with a 50% duty cycle (including dead time considerations). Therefore, the output voltage of the full-bridge phase-shift converter is determined by controlling the phase difference between the two half-bridges. Specifically, the first switch Q1 and the second switch Q2 of the lagging arm operate in complementary mode, and the third switch Q3 and the fourth switch Q4 of the leading arm operate in complementary mode.

[0004] for Figure 1 The traditional full-bridge phase-shift converter architecture shown typically uses synchronous rectification on the secondary side of the transformer due to its high output current. This is exemplified by a rectifier composed of the first synchronous rectifier switch QS1 and the second synchronous rectifier switch QS2, which operate independently. The lagging and leading bridge arms (Q1-Q4) usually operate at their switching frequency, while the first and second synchronous rectifier switches QS1 and QS2 operate at twice that frequency. Because the secondary windings Ws of the transformer have leakage inductance (secondary leakage inductance) LLkS1 and LLkS2, when either the first or second synchronous rectifier switch QS1 is turned off, this leakage inductance LLkS1 and LLkS2, along with the parasitic capacitance of the first and second synchronous rectifier switches QS1 and QS2, generates a high-voltage oscillation (or surge voltage). The magnitude of this oscillation voltage is as follows: Figure 2 As shown, the maximum voltage peak of the switching voltage waveform can even exceed 180 volts, which exceeds the component's rated value, thus generating a large amount of electromagnetic interference (EMI) noise.

[0005] To solve the influence caused by the surge voltage, components with higher voltage rating can be used to withstand the generated surge voltage, however, using components with high voltage rating will cause the increase of the circuit cost. Furthermore, the heat generated during the operation of the components will accumulate inside the circuit, in addition to the decrease of the power conversion efficiency, the heat dissipation problem also needs to be overcome. SUMMARY

[0006] To solve the existing technical problems, the present application provides a full-bridge phase-shift converter with voltage clamping.

[0007] It comprises: a transformer having a primary side winding and a secondary side winding;

[0008] a primary side circuit comprising: a first switch bridge arm; and a second switch bridge arm connected in parallel with the first switch bridge arm;

[0009] a secondary side circuit comprising: a first synchronous rectification switch coupled to a first end of the secondary side winding;

[0010] a second synchronous rectification switch coupled to a second end of the secondary side winding;

[0011] an output inductor coupled to a center tap end of the secondary side winding;

[0012] a first diode having an anode end coupled to the first end;

[0013] a second diode having an anode end coupled to the second end;

[0014] a third diode having an anode end coupled to the center tap end, and a cathode end of the first diode, a cathode end of the second diode and a cathode end of the third diode are connected to a clamping node;

[0015] a capacitor coupled to the clamping node to provide a clamping voltage;

[0016] an energy release unit connected in parallel with the capacitor to convert the clamping voltage into an output voltage; and

[0017] an output capacitor connected in parallel with the energy release unit to provide the output voltage.

[0018] Further, the secondary side winding comprises leakage inductance; wherein the energy generated by the leakage inductance of the secondary side winding is stored in the capacitor.

[0019] Further, the energy release unit comprises: a DC voltage reduction converter having an input side;

[0020] wherein the input side detects the size of the clamping voltage.

[0021] Further, the DC voltage step-down converter converts the clamped voltage to the output voltage according to the magnitude of the clamped voltage.

[0022] Further, the DC voltage step-down converter releases the energy stored in the capacitor to the output capacitor to reduce the magnitude of the clamped voltage when the clamped voltage is greater than a set voltage.

[0023] Further, the DC voltage step-down converter is a switching converter or a linear regulator, and the energy releasing unit further comprises:

[0024] a first resistor; and

[0025] a second resistor connected in series with the first resistor;

[0026] wherein the first resistor and the second resistor are connected to the input side of the switching converter or the linear regulator;

[0027] wherein the clamped voltage obtained on the series branch of the first resistor and the second resistor is a first voltage, and the divided voltage of the clamped voltage obtained on the second resistor is a second voltage.

[0028] Further, the switching converter or the linear regulator receives the first voltage or the second voltage;

[0029] wherein the switching converter or the linear regulator converts the clamped voltage to the output voltage according to the magnitude of the first voltage or the second voltage.

[0030] Further, the switching converter or the linear regulator releases the energy stored in the capacitor to the output capacitor to reduce the magnitude of the clamped voltage when the first voltage is greater than a first set voltage or the second voltage is greater than a second set voltage.

[0031] Further, the first switch bridge arm has a first switch and a second switch connected in series, and the first switch and the second switch are coupled to one end of the primary side winding; the second switch bridge arm has a third switch and a fourth switch connected in series, and the third switch and the fourth switch are coupled to the other end of the primary side winding.

[0032] The present application has the following advantages: when the surge voltage is greater than the preset set voltage, the energy stored in the capacitor can be released to the output capacitor through the DC voltage reduction converter (including but not limited to a switching converter or a linear voltage regulator) to reduce the size of the clamping voltage, thereby allowing the generated surge voltage to be suppressed by energy release, so that higher voltage rated components are not required to achieve surge voltage suppression and maintain power conversion efficiency of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0033] For ease of illustration, the present application is described in detail by the following specific embodiments and drawings.

[0034] Figure 1 Circuit diagram of a full-bridge phase-shift converter of the related art;

[0035] Figure 2 Waveform diagram of the switching voltage of the full-bridge phase-shift converter of the related art;

[0036] Figure 3 Circuit block diagram of the full-bridge phase-shift converter with voltage clamping of the present application;

[0037] Figure 4 Circuit block diagram of the first embodiment of the energy release unit of the present application;

[0038] Figure 5 Circuit block diagram of the second embodiment of the energy release unit of the present application;

[0039] Figure 6 Waveform diagram of the switching voltage of the full-bridge phase-shift converter with voltage clamping of the present application. DETAILED DESCRIPTION

[0040] Please refer to Figure 3 Fig. 1 is a circuit block diagram of the full-bridge phase-shift converter with voltage clamping of the present application. The full-bridge phase-shift converter with voltage clamping includes a transformer TR, a primary side circuit (i.e. a primary side circuit) and a secondary side circuit (i.e. a secondary side circuit).

[0041] The transformer TR has a primary side winding Wp and a secondary side winding Ws. The primary side circuit has a first switch bridge arm Lg1 and a second switch bridge arm Lg2, wherein the second switch bridge arm Lg2 is in parallel with the first switch bridge arm Lg1. The first switch bridge arm Lg1 has a first switch Q1 and a second switch Q2 connected in series, and the first switch Q1 and the second switch Q2 are coupled to one end of the primary side winding Wp (e.g. the positive terminal of the primary side winding Wp). Figure 3the non-punctured end) of the primary side winding Wp. The first switch bridge leg Lg2 has the third switch Q3 and the fourth switch Q4 connected in series, and the third switch Q3 and the fourth switch Q4 are coupled to the other end of the primary side winding Wp (e.g. the non-punctured end) of the primary side winding Wp. Figure 3 the non-punctured end) of the primary side winding Wp. The first switch bridge leg Lg2 has the third switch Q3 and the fourth switch Q4 connected in series, and the third switch Q3 and the fourth switch Q4 are coupled to the other end of the primary side winding Wp (e.g. the non-punctured end) of the primary side winding Wp.

[0042] The secondary side circuit includes a first synchronous rectification switch QS1, a second synchronous rectification switch QS2, an output inductor LO, a first diode DS1, a second diode DS2, a third diode DS3, a capacitor Cb, an energy releasing unit 10, and an output capacitor CO.

[0043] The secondary side winding Ws has secondary side inductances Ns1, Ns2, and there are leakage inductances LLkS1, LLkS2, in Figure 3 The secondary side winding Ws has secondary side inductances Ns1, Ns2, and there are leakage inductances LLkS1, LLkS2, in

[0044] The first synchronous rectification switch QS1 is coupled to the first end N1 of the secondary side winding Ws (i.e. coupled to the secondary side inductance Ns1). The second synchronous rectification switch QS2 is coupled to the second end N2 of the secondary side winding Ws (i.e. coupled to the secondary side inductance Ns2). The output inductor LO is coupled to the center tap end NC of the secondary side winding Ws. The anode end of the first diode DS1 is coupled to the first end N1. The anode end of the second diode DS2 is coupled to the second end N2. The anode end of the third diode DS3 is coupled to the center tap end NC, and the cathode end of the first diode DS1, the cathode end of the second diode DS2, and the cathode end of the third diode DS3 are commonly connected to the clamping node Nb.

[0045] The capacitor Cb is coupled to the clamping node Nb to provide a clamping voltage Vb. The energy generated by the leakage inductances LLkS1, LLkS2 of the secondary side winding Ws is stored in the capacitor Cb. The energy releasing unit 10 has an input side, the input side is in parallel with the capacitor Cb, the input side detects the size of the clamping voltage Vb on the clamping node Nb, and the energy releasing unit 10 is used to convert the clamping voltage Vb into an output voltage VO. The output capacitor CO is in parallel with the energy releasing unit 10 to provide the output voltage VO.

[0046] As shown in Figure 4As shown, it is a circuit block diagram of the first embodiment of the energy releasing unit of the present application. Specifically, the energy releasing unit 10 comprises a first resistor Rup, a second resistor Rdn, and a DC voltage step-down converter, wherein the DC voltage step-down converter is a switching converter 12A. The second resistor Rdn is connected in series with the first resistor Rup. The switching converter 12A is connected between the first resistor Rup and the second resistor Rdn. The clamping voltage Vb obtained across the series connection of the first resistor Rup and the second resistor Rdn is the first voltage, i.e. the voltage across the first resistor Rup and the second resistor Rdn. The voltage obtained across the second resistor Rdn is the second voltage, i.e. the voltage across the second resistor Rdn. It is noted that in different embodiments, the first resistor Rup and the second resistor Rdn can also be integrated into the switching converter 12A, and the voltage detection and voltage division of the clamping voltage Vb can also be achieved. Furthermore, since the first resistor Rup and the second resistor Rdn are mainly used for voltage detection and voltage division, the resistance of the first resistor Rup and the second resistor Rdn is designed to be very large, so that the current flowing through the first resistor Rup and the second resistor Rdn is very small, and the loss generated thereby can be negligible.

[0047] Specifically, the switching converter 12A receives the first voltage or the second voltage. The switching converter 12A converts the clamping voltage Vb (e.g. step-down conversion of the clamping voltage Vb) to an output voltage VO according to the size of the first voltage or the second voltage. When the switching converter 12A detects that the first voltage is greater than a first set value or the second voltage is greater than a second set value, the switching converter 12A releases the energy stored in the capacitor Cb to the output capacitor CO to reduce the clamping voltage Vb. For example, the first set voltage can be preset to 90 volts. When the first synchronous rectification switch QS1 or the second synchronous rectification switch QS2 is turned off, the surge voltage generated by the oscillation of the leakage inductance LLkS1 or LLkS2 and the parasitic capacitance of the first synchronous rectification switch QS1 or the second synchronous rectification switch QS2 (the clamping voltage Vb formed at the clamping node Nb is the first voltage) is greater than the first set voltage (90 volts), and the energy stored in the capacitor Cb is released to the output capacitor CO (the energy generated by the surge voltage can be prevented from continuously and substantially accumulating in the capacitor Cb) by the switching converter 12A to reduce the clamping voltage Vb, so that the generated surge voltage can be suppressed by the energy releasing method, and the higher voltage rated components are not required, and the suppression of the surge voltage can be achieved while maintaining the power conversion efficiency of the circuit.

[0048] Alternatively, the second preset voltage can be set to 30 volts. When the first synchronous rectifier switch QS1 or the second synchronous rectifier switch QS2 is turned off, the surge voltage generated by the oscillation of the leakage inductance LLkS1 or LLkS2 and the parasitic capacitance of the first synchronous rectifier switch QS1 or the second synchronous rectifier switch QS2 (the clamping voltage Vb formed at the clamping node Nb is divided into a second voltage through the design of the resistance values ​​of the first resistor Rup and the second resistor Rdn) is greater than the preset second preset voltage (30 volts). Similarly, the energy stored in the capacitor Cb can be released to the output capacitor CO through the switching converter 12A (which can prevent the energy generated by the surge voltage from continuously and in large quantities from accumulating in the capacitor Cb), thereby reducing the clamping voltage Vb. In this way, the surge voltage generated can be suppressed by releasing energy. Therefore, it is not necessary to select components with higher voltage ratings to achieve surge voltage suppression and maintain the power conversion efficiency of the line.

[0049] like Figure 6 The diagram shown is a waveform representation of the switching voltage of the voltage-clamped full-bridge phase-shift converter of the present invention. Therefore, the maximum voltage peak value of the switching voltage waveform can be suppressed to below 80 volts, which is not only lower than the component's rated value but also prevents the generation of electromagnetic interference (EMI) noise.

[0050] like Figure 5 The diagram shown is a circuit block diagram of a second embodiment of the energy release unit of the present invention. Specifically, the energy release unit 10 includes a first resistor Rup, a second resistor Rdn, and a DC-DC step-down converter.

[0051] The converter, specifically the DC-DC buck converter, is a low-dropout regulator (LDO) 12B. A second resistor, Rdn, is connected in series with the first resistor, Rup. The LDO 12B connects the first resistor Rup and the second resistor Rdn. A clamping voltage Vb is obtained in the series branch of the first resistor Rup and the second resistor Rdn, which is the first voltage, meaning the voltage across the first resistor Rup and the second resistor Rdn. A voltage divider of the clamping voltage Vb across the second resistor Rdn is the second voltage, meaning the voltage across the second resistor Rdn.

[0052] Incidentally, in different embodiments, the first resistor Rup and the second resistor Rdn can also be integrated into the linear regulator 12B, achieving the same voltage detection and voltage division of the clamping voltage Vb. Furthermore, since the primary purpose of the first resistor Rup and the second resistor Rdn is for voltage detection and voltage division, their resistance values ​​are designed to be very large in this invention, resulting in very small current flowing through their paths and negligible losses.

[0053] Specifically, the linear regulator 12B receives the first voltage or the second voltage. The linear regulator 12B converts the clamping voltage Vb (e.g. buck-converts the clamping voltage Vb) to the output voltage VO according to the magnitude of the first voltage or the second voltage. When the linear regulator 12B detects that the first voltage is greater than the first set value or the second voltage is greater than the second set voltage, the linear regulator 12B releases the energy stored in the capacitor Cb to the output capacitor CO to reduce the clamping voltage Vb. For example, the first set voltage can be preset to 90 volts. When the first synchronous rectification switch QS1 or the second synchronous rectification switch QS2 is turned off, the surge voltage generated by the oscillation of the leakage inductance LLkS1 or LLkS2 and the parasitic capacitance of the first synchronous rectification switch QS1 or the second synchronous rectification switch QS2 (the clamping voltage Vb formed at the clamping node Nb is the first voltage) is greater than the preset first set voltage (90 volts), the energy stored in the capacitor Cb is released to the output capacitor CO through the linear regulator 12B (the energy generated by the surge voltage can be prevented from continuously and massively accumulating in the capacitor Cb), so as to reduce the clamping voltage Vb. In this way, the generated surge voltage can be suppressed by the energy release method, so that higher voltage rated components do not need to be selected, and the suppression of the surge voltage can be achieved while maintaining the power conversion efficiency of the circuit.

[0054] Alternatively, the second set voltage can be preset to 30 volts. When the first synchronous rectification switch QS1 or the second synchronous rectification switch QS2 is turned off, the surge voltage generated by the oscillation of the leakage inductance LLkS1 or LLkS2 and the parasitic capacitance of the first synchronous rectification switch QS1 or the second synchronous rectification switch QS2 (the clamping voltage Vb formed at the clamping node Nb is the second voltage by the voltage division of the first resistor Rup and the second resistor Rdn) is greater than the preset second set voltage (30 volts), the energy stored in the capacitor Cb can be released to the output capacitor CO through the linear regulator 12B (the energy generated by the surge voltage can be prevented from continuously and massively accumulating in the capacitor Cb), so as to reduce the clamping voltage Vb. In this way, the generated surge voltage can be suppressed by the energy release method, so that higher voltage rated components do not need to be selected, and the suppression of the surge voltage can be achieved while maintaining the power conversion efficiency of the circuit.

[0055] In summary, the present application has the following features and advantages: when the surge voltage is greater than the preset set voltage, the energy stored in the capacitor Cb can be released to the output capacitor CO through the DC voltage reduction converter (including but not limited to the switching converter 12A or the linear voltage regulator 12B) to reduce the size of the clamping voltage Vb, so that the generated surge voltage can be suppressed by the energy release method, so that higher voltage rated components are not required, and the suppression of the surge voltage can still be achieved while maintaining the power conversion efficiency of the circuit.

[0056] The above is only a detailed description of the preferred embodiments of the present application and the drawings, but the features of the present application are not limited thereto, and are not intended to limit the present application. The scope of the present application should be based on the following patent claims, and any embodiments similar to the spirit and similar changes of the present application should be included in the scope of the present application. Any changes or modifications in the field of the present application can be covered by the patent range of the present application.

Claims

1. A full-bridge phase-shift converter with voltage clamping, characterized in that, It comprises: a transformer having a primary winding and a secondary winding; a primary side circuit comprising: a first switch bridge arm; and a second switch bridge arm in parallel with the first switch bridge arm; a secondary side circuit comprising: a first synchronous rectification switch coupled to a first end of the secondary winding; a second synchronous rectification switch coupled to a second end of the secondary winding; an output inductor coupled to a center tap end of the secondary winding; a first diode having an anode coupled to the first end; a second diode having an anode coupled to the second end; a third diode having an anode coupled to the center tap end, and a cathode of the first diode, a cathode of the second diode and a cathode of the third diode being connected to a clamping node; a capacitor coupled to the clamping node for providing a clamping voltage; an energy release unit in parallel with the capacitor for converting the clamping voltage to an output voltage; and an output capacitor in parallel with the energy release unit for providing the output voltage.

2. The full-bridge phase-shift converter with voltage clamping according to claim 1, characterized in that: The secondary winding comprises a leakage inductance; wherein energy stored in the leakage inductance of the secondary winding is stored in the capacitor.

3. A full-bridge phase-shift converter with voltage clamping according to claim 2, characterized in that: The energy release unit comprises a DC voltage down converter having an input side; wherein the input side detects a magnitude of the clamping voltage.

4. The full-bridge phase-shift converter with voltage clamping according to claim 3, characterized in that: The DC voltage down converter converts the clamping voltage to the output voltage according to the magnitude of the clamping voltage.

5. A full-bridge phase-shift converter with voltage clamping according to claim 4, characterized in that: The DC voltage down converter releases energy stored in the capacitor to the output capacitor to reduce the magnitude of the clamping voltage when the clamping voltage is greater than a set voltage.

6. The full-bridge phase-shift converter with voltage clamping according to claim 3, characterized in that: The DC voltage down converter is a switching converter or a linear regulator, and the energy release unit further comprises: a first resistor; and a second resistor in series with the first resistor; wherein the first resistor and the second resistor are connected to the input side of the switching converter or the linear regulator; wherein a voltage obtained across the first resistor and the second resistor is a first voltage, and a voltage obtained across the second resistor is a second voltage.

7. A full-bridge phase-shift converter with voltage clamping according to claim 6, characterized in that: The switching converter or the linear regulator receives the first voltage or the second voltage; wherein the switching converter or the linear regulator converts the clamping voltage to the output voltage according to the magnitude of the first voltage or the second voltage.

8. The full-bridge phase-shift converter with voltage clamping according to claim 7, characterized in that: The switching converter or the linear regulator releases energy stored in the capacitor to the output capacitor to reduce the magnitude of the clamping voltage when the first voltage is greater than a first set voltage or the second voltage is greater than a second set voltage.

9. The full-bridge phase-shift converter with voltage clamping of claim 1, wherein: The first switch bridge arm has a first switch and a second switch in series, and the first switch and the second switch are coupled to one end of the primary winding; and the second switch bridge arm has a third switch and a fourth switch in series, and the third switch and the fourth switch are coupled to another end of the primary winding.

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