Printed circuit board trace for reducing jaynes effect

Abstract

The present disclosure is titled "Printed Circuit Board Trace for Reducing Janning Effect." Apparatuses and methods for reducing etching within a printed circuit board due to the Janning effect are described, which can be used, for example, in a data storage device, such as a card-type data storage device. Specifically, a contact trace is coupled to a contact finger, which has a substantially greater surface area than the contact trace and is configured to couple the data storage device to a host device. The contact trace is electrically isolated from the rest of the circuit during the manufacturing process. The contact finger and an exposed portion of the contact trace are plated with a common material to reduce Janning etching of the contact trace during manufacturing. The contact trace is then connected to an impedance trace by at least one of a component and a bond wire.

Description

BACKGROUND

[0001] The present application relates generally to printed circuit boards, and more particularly to the configuration of traces and connections within printed circuit boards that are configured to reduce Javan effects between traces and connections containing different metallic materials.

[0002] Printed circuit boards or substrates are used to provide electrical connections between electronic components, such as integrated circuit dies and passive components, and other components mounted on the PCB or substrate, as well as external electrical connections to components mounted on the PCB. Some memory devices, such as hybrid flip-chip products used in card-type applications (e.g., SD cards, microSD cards, USB cards, etc.), use cleaning chemicals to clean the metal components on the substrate prior to applying a finish, such as an organic solderability preservative (“OSP”). Further, the general structure of hybrid flip-chip products features metal fingers that provide connections to a host device and are constructed of a first material. The host device also has associated internal connections or traces that are constructed of a different second metallic material. In contrast to the internal connection points that are electrically connected to the metal fingers, the cleaning chemicals combined with the metal fingers, which have a much larger metallic surface area, create a voltage difference between the metal fingers and the associated internal connection points due to the Javan effect. This voltage difference can cause over-etching of the internal connection points, resulting in a weakening of the electrical potential or an increase in the electrical resistance of the internal connection points or traces. SUMMARY

[0003] Etching the traces in a data storage device during a cleaning process can require the traces to be oversized for a given application to account for potential etching. By controlling the amount of etching due to the Javan effect, the width and thickness of the traces within the data storage device can be better controlled, allowing for accurate determination and maintenance of the trace impedance.

[0004] One embodiment of the present disclosure includes a data storage device including a substrate having a first side and a second side opposite the first side, and a contact finger disposed on the first side of the substrate and configured to interface with a host device. The data storage device also includes a contact trace coupled to the contact finger, the contact trace extending from the first side of the substrate to the second side of the substrate, wherein the contact trace has an exposed portion disposed on the second side of the substrate. The data storage device also includes an impedance trace disposed on the second side of the substrate and configured to be coupled to one or more memory components of the data storage device. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce Javan etching of the first contact trace, and the exposed portion of the contact trace is electrically connected to the impedance trace by at least one of a component and a bond wire.

[0005] In another embodiment of the disclosure, a method for reducing etching due to the Janning effect in a data storage device is described, the method including determining a ratio of a surface area of a contact finger to a surface area of an exposed portion of a contact trace electrically connected to the contact finger, where the contact finger is configured to provide an electrical connection to a host device. The method further includes determining whether the ratio exceeds a predetermined threshold, and in response to determining that the ratio exceeds the predetermined threshold, separating the exposed portion of the contact trace into a contact trace portion and an impedance trace. The contact trace portion and the impedance trace are electrically isolated. The method further includes plating the contact finger and the contact trace portion with a common material, and electrically connecting the contact trace portion and the impedance trace with a component.

[0006] In one embodiment of the disclosure, a card-type data storage device is provided, the card-type data storage device including a substrate having a first side and a second side opposite the first side, and a contact finger disposed on the first side of the substrate and configured to interface with a host device and plated with a plating material. The card-type data storage device further includes a first trace coupled to the first contact finger and extending from the first side of the substrate to the second side of the substrate. The first trace has an exposed portion disposed on the second side of the substrate, the exposed portion plated with the plating material. The card-type data storage device further includes a second trace disposed on the second side of the substrate, where a portion of the second trace is plated with the plating material. The exposed portion of the first trace is electrically connected to the second trace with a connection device. The connection device is connected between the plated portion of the first trace and the plated portion of the second trace.

[0007] Various aspects of the disclosure provide improvements to memory devices. For example, reducing etching due to the Janning effect reduces impedance variations in traces and allows for more precise trace designs. The disclosure can be embodied in various forms. The foregoing summary is intended merely to give general concepts of various aspects of the disclosure and is not intended to limit the scope of the disclosure in any way. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram of one example of a system including a data storage device in accordance with some embodiments.

[0009] Figure 2 is a cross-sectional view of a portion of a substrate for use in a data storage device in accordance with some embodiments.

[0010] Figure 3 is a cross-sectional view of a substrate for use in a data storage device having Janning etching reduction features in accordance with some embodiments.

[0011] Figure 4 is a diagram illustrating a line connection configuration in accordance with some embodiments. Figure 3a cross-sectional view of a substrate.

[0012] Figure 5 is a flowchart showing a process for reducing etching on a contact trace coupled to a contact finger due to JFET voltage on a substrate according to some embodiments. Figure 3 a cross-sectional view of a substrate.

[0013] Figure 6 is a flowchart showing a process for reducing etching on a contact trace coupled to a contact finger due to JFET voltage on a substrate according to some embodiments.

[0014] Figure 7 is a partial substrate layout of a data storage device according to some embodiments.

[0015] Figures 8A to 8C is a manufacturing process for a substrate according to some embodiments. DETAILED DESCRIPTION

[0016] In the following description, numerous specific details are set forth, such as data storage device configurations, etc., in order to provide a thorough understanding of one or more aspects of the present disclosure. It will be apparent to one skilled in the art, however, that these specific details need not be employed to practice the present application. The following description is given for the purposes of exemplification only, and is not intended to limit the scope of the present disclosure. Furthermore, for the purpose of clarity, the description is divided into sections, which are not intended to limit the scope of the present disclosure. Moreover, it will be apparent to one skilled in the art that, although the present disclosure relates to NAND flash memory, the concepts discussed herein are applicable to other types of solid state memory, such as NOR, PCM (“Phase Change Memory”), ReRAM, etc. One skilled in the art will also recognize that, although the present disclosure relates to substrates used in data storage devices, the present disclosure is applicable to substrates used in other types of electronic devices. The present disclosure is applicable to both substrates and printed circuit boards used in electronic devices.

[0017] Figure 1 is a block diagram of one example of a system 100 including a data storage device 102 in communication with a host device 108. The data storage device 102 includes a memory device 104 (e.g., non-volatile memory) coupled to a controller 106.

[0018] One example of structural and functional features provided by the controller 106 is shown in Figure 1 However, the controller 106 is not limited to the structural and functional features provided by the controller 106 in Figure 1 The controller 106 can include fewer or additional structural and functional features not shown in Figure 1

[0019] ​The data storage device 102 and the host device 108 can be operatively coupled by a connection, such as a communication path 110, such as a bus or a wireless connection. In some examples, the data storage device 102 can be embedded within the host device 108. Alternatively, in other examples, the data storage device 102 can be removable from the host device 108 (i.e., “removably” coupled to the host device 108). For example, the data storage device 102 can be removably coupled to the host device 108 according to a removable Universal Serial Bus (USB) configuration. In some implementations, the data storage device 102 can include or correspond to a solid state drive (SSD) that can be used as an embedded storage drive (e.g., a mobile embedded storage drive), an enterprise storage drive (ESD), a client storage device, or a cloud storage drive, or other suitable storage drive.

[0020] The data storage device 102 can be configured to be coupled to the host device 108 by a communication path 110, such as a wired communication path and / or a wireless communication path. For example, the data storage device 102 can include an interface 120 (e.g., a host interface) that enables communication over the communication path 110 between the data storage device 102 and the host device 108, such as when the interface 120 is communicatively coupled to the host device 108. In some embodiments, the communication path 110 can include one or more electrical signal contact pads or contact fingers that provide electrical communication between the data storage device 102 and the host device 108.

[0021] The host device 108 can include a processor and a memory. The memory can be configured to store data and / or instructions that can be executed by the processor. The memory can be a single memory or can include one or more memories, such as one or more non-volatile memories, one or more volatile memories, or a combination thereof. The host device 108 can issue one or more commands to the data storage device 102, such as one or more requests to erase data at a memory device 104 of the data storage device 102, read data from the memory device, or write data to the memory device. For example, the host device 108 can be configured to provide data, such as user data 132, to be stored at the memory device 104 or request data 134 to be read from the memory device 104. The host device 108 can include a mobile smart phone, a music player, a video player, a game console, an electronic book reader, a personal digital assistant (PDA), a computer, such as a laptop or notebook computer, any combination thereof, or other suitable electronic device.

[0022] The host device 108 communicates with a memory interface that enables reads from and writes to the memory device 104. In some examples, the host device 108 can operate in accordance with an industry specification, such as the Universal Flash Storage (UFS) Host Controller Interface Specification. In other examples, the host device 108 can operate in accordance with one or more other specifications, such as the Secure Digital (SD) Host Controller Specification or other suitable industry specification. The host device 108 can also communicate with the memory device 104 in accordance with any other suitable communication protocol.

[0023] The memory device 104 of the data storage device 102 can include non-volatile memory (e.g., NAND, BiCS family memory, or other suitable memory). In some examples, the memory device 104 can be any type of flash memory. For example, the memory device 104 can be two-dimensional (2D) memory or three-dimensional (3D) flash memory. The memory device 104 can include one or more memory dies 103. Each of the one or more memory dies 103 can include one or more memory blocks 112 (e.g., one or more erase blocks). Each memory block 112 can include one or more sets of storage elements, such as a set of representative storage elements 107A-107N. The set of storage elements 107A-107N can be configured as a word line. The set of storage elements 107A-107N can include a plurality of storage elements (e.g., memory cells referred to herein as “strings”), such as representative storage elements 109A and 109N, respectively.

[0024] The memory device 104 can include support circuitry, such as read / write circuitry 140, to support operation of the one or more memory dies 103. Although depicted as a single component, the read / write circuitry 140 can be split into separate components of the memory device 104, such as a read circuit and a write circuit. The read / write circuitry 140 can be external to the one or more memory dies 103 of the memory device 104. Alternatively, one or more separate memory dies can include corresponding read / write circuitry that is operable to read from and / or write to storage elements within the separate memory dies independent of any other read and / or write operations at any other memory dies.

[0025] The controller 106 is coupled to the memory device 104 (e.g., one or more memory dies 103) by a bus 105, an interface (e.g., interface circuitry), another structure, or a combination thereof. For example, the bus 105 can include a plurality of different channels to enable the controller 106 to communicate with each of the one or more memory dies 103 in parallel and independent of communication with the other memory dies 103.

[0026] The controller 106 is configured to receive data and instructions from the host device 108 and send data to the host device 108. For example, the controller 106 can send data to the host device 108 using the interface 120, and the controller 106 can receive data from the host device 108 through the interface 120. The controller 106 is configured to send data and commands (e.g., memory operations 136, which can be cycling operations of memory blocks of the memory device 104) to the memory device 104 and receive data from the memory device 104. For example, the controller 106 is configured to send data and program or write commands to cause the memory device 104 to store data to a specified address of the memory device 104. The write commands can specify a physical address of a portion of the memory device 104 to be used to store the data (e.g., a physical address of a word line of the memory device 104).

[0027] The controller 106 is configured to send read commands to the memory device 104 to access data from a specified address of the memory device 104. The read commands can specify a physical address of a region of the memory device 104 (e.g., a physical address of a word line of the memory device 104). The controller 106 can also be configured to send data and commands to the memory device 104 that are associated with background scan operations, garbage collection operations, and / or wear leveling operations or other suitable memory operations.

[0028] The controller 106 can include a processor 124, a memory 126, and other associated circuitry. The memory 126 can be configured to store data and / or instructions that can be executed by the processor 124.

[0029] The controller 106 can send memory operations 136 (e.g., read commands) to the memory device 104 to cause the read / write circuitry 140 to sense data stored in the storage elements. For example, the controller 106 can send a read command to the memory device 104 in response to receiving a read access request from the host device 108. In response to receiving the read command, the memory device 104 can sense the storage elements 107A (e.g., using the read / write circuitry 140) to generate one or more sets of bits representing the stored data.

[0030] Turning now to Figure 2A cross-sectional view of a general substrate or circuit board 200 for use in a data storage device, such as data storage device 102, is provided. Circuit board 200 includes a substrate core 202, a contact finger trace 204, and a contact finger region 206. Contact finger region 206 is configured to provide an electrical connection between data storage device 102 and a host device, such as host device 108. Contact finger trace 204 is also configured to couple one or more components of data storage device 102 to contact finger region 206. Generally, contact finger trace 204 is constructed of copper (“Cu”); however, other material types are contemplated. Further, during the manufacturing process, contact finger region 206 is plated with a different material than contact finger trace 204. In one example, contact finger region 206 is plated with gold (“Au”). In another example, contact finger region 206 is plated with a nickel gold compound. In other examples, other materials suitable for a given application can be used.

[0031] During the manufacturing process, a solder mask 208 is also applied to other portions of contact finger trace 204. Solder mask 208 prevents unwanted solder connections to contact finger trace 204 and also seals portions of contact finger trace 204 from various solvents or other processes applied to data storage device 102, as described in greater detail below.

[0032] During the manufacturing process, a solvent or other cleaning solution 209 is applied to circuit board 200 prior to applying a coating to the circuit board. An example coating can include an organic solderability preservative (“OSP”), which is one or more water-based organic compounds that selectively bind to and protect the trace material (e.g., copper) until soldering is performed. An example cleaning solution 209 can be an arowana solution or arowana etch, which is typically a mixture of sulfuric acid (“H2SO4”), water (“H2O”), and hydrogen peroxide (“H2O2”). Cleaning solution 209 can be used to clean organic residue from circuit board 200.

[0033] Due to the use of different metallic materials (e.g., copper and gold) in contact finger trace 204 and contact finger region 206, a byproduct of applying cleaning solution 209 to circuit board 200 is generally known as the formation of a galvanic cell, which is referred to as the galvanic effect. Cleaning solution 209 acts as a conductive element to allow a redox reaction to occur between the dissimilar metals, in which the metals lose electrons, creating a voltage. Contact finger trace 204 includes an exposed trace portion 210, which is generally constructed of copper and has a much smaller area than contact finger region 206, which is generally constructed of gold. As Figure 2As shown, a voltage difference of approximately 1.439V is formed between the contact finger region 206 and the exposed trace portion 210. However, voltages greater than 1.439V and less than 1.439V can be generated based on the type of material used for the exposed trace portion 210 and the contact finger region 206, as well as the difference in the exposed surface area between the exposed trace portion 210 and the contact finger region 206. In some examples, the current density of a Giovanni cell can be used to determine the etching rate or speed. The current density is based on the ratio of different materials within the trace. This voltage difference causes the exposed trace portion 210 to lose material (e.g., copper), which is released into the cleaning solution 209 and / or deposited on other traces or portions of the circuit board 200. This is commonly referred to as etching.

[0034] like Figure 2 As shown, the exposed trace portion 210 along the top edge 212 of the substrate 208 should have approximately the same height as the contact finger trace 204. For example, the contact finger trace 204 has a height H1. However, due to etching caused by the Giovanni voltage difference, a significant portion of the exposed trace portion 210 is etched away, resulting in a reduced height H2 for the exposed trace portion 210. In one embodiment, etching can result in a loss of 75% of the material in the exposed trace portion 210. However, depending on the type of material used and the generated Giovanni voltage difference, a loss greater than 75% or less may occur. This can weaken the exposed trace portion 210, especially when components are soldered between the exposed trace portion 210 and another trace (such as trace 214) on the circuit board 200. Additionally, the reduced amount of material in the exposed trace portion 210 can increase the resistance within the contact finger trace 204, resulting in additional heating of the contact finger trace 204 and / or the connected components.

[0035] Go to Figure 3The diagram shows a cross-sectional area of ​​a modified circuit board 300 configured to reduce the effects of etching due to the Giaviani effect. Similar to circuit board 200, circuit board 300 includes contact traces 302, contact finger regions 304 coupled to the contact traces 302, and a substrate 306. As described above, the contact traces 302 may be constructed of copper, and the contact finger regions 304 may be constructed of gold or other suitable materials (such as nickel-gold). A first portion 308 of the contact traces 302 on a first side 310 of the substrate 306 is substantially covered by a solder mask 312. A second portion 314 of the contact traces 302 is not covered by the solder mask 312. The second portion 314 is plated with the same material (such as gold) as the contact finger regions 304 to form a first pad 315. Because the second portion 314 of the contact finger trace 302 is plated with the same material as the contact finger region 304, there is no etching, as there is no Giovanni voltage difference between the second portion 314 of the contact finger trace 302 and the contact finger region 304. Furthermore, since the second portion 314 is electrically isolated from the other traces, etching due to the Giovanni effect is reduced.

[0036] Impedance trace 316 formed of a material different from the contact finger region 304 (e.g., copper) Figure 3 As shown in the diagram, impedance trace 316 includes a plated portion and a non-plated portion 320 forming a second pad 318. The second pad 318 is plated with the same material as the second portion 314 of the contact finger trace 302 and is used to provide a connection to the second portion 314 of the contact finger trace 302. Impedance trace 316 also provides a connection from the contact finger region 304 to one or more components on the circuit board 300. The non-plated portion 320 of impedance trace 316 is typically coupled to electronic components of the data storage device 102, such as memory dies, controllers, or other components associated with the memory storage device. The non-plated portion 320 may also include a bump pad region 322 for connection to other traces or components.

[0037] When the circuit board 300 is subjected to a cleaning solution as described above, there is no etching of the contact finger trace 302 because all exposed portions of the contact finger trace 302 are plated with the same material as the contact finger region 304. Further, there is no electrical connection between the contact finger trace 302 and other traces, such as the impedance trace 316, during the cleaning process. This further prevents any etching due to the Jominy effect. Because the second pad 318 is made of a different material than the un-plated portion 320 of the impedance trace 316, the impedance trace 316 can experience slight etching. However, because the second pad 318 has a significantly smaller surface area than the un-plated portion 320, less etching occurs due to the plated portion of the second pad 318 creating a smaller Jominy voltage. In one example, the second pad 318 has approximately 75% less surface area than the un-plated portion 320. However, values greater than 75% or less than 75% are also contemplated.

[0038] As described above, a connection between the first pad 315 of the contact finger trace 302 and the second pad 318 of the impedance trace 316 is needed to connect the contact finger region 304 to components within the data storage device 102. To avoid etching due to the creation of a Jominy voltage, the connection between the first pad 315 and the second pad 318 is performed after the cleaning and subsequent OSP processes have been performed. As described in more detail below, there are various configurations that can be used to provide the connection between the first pad 315 and the second pad 318.

[0039] Turning now to Figure 4 , a circuit board 300 of Figure 3 is shown during a subsequent stage of manufacturing in which a connection is made between the first pad 315 and the second pad 318. As Figure 4 illustrates, a wire 400 is bonded between the first pad 315 and the second pad 318 to provide an electrical connection. In one embodiment, the wire 400 is a gold wire. However, other wire types suitable for a given application are also contemplated. As further illustrated in Figure 4 , a die 402 is shown coupled between the impedance trace 316 and a component trace 404, thereby showing various components coupled to the contact finger region 306 using the impedance trace 316. In one embodiment, the die 402 is a memory die, such as a NAND die. In other embodiments, the die 402 can be a controller or other component associated with the data storage device 102.

[0040] Turning now to Figure 5 , Figure 3The circuit board 300 is shown as having a component 500 that provides a connection between the first pad 315 and the second pad 318. The component 500 is generally a surface mount (SMT) component having a physical size selected based on various factors, such as the pitch between the first pad 315 and the second pad 318. The component 500 can be soldered or otherwise physically coupled to the first pad 315 and the second pad 318. In one embodiment, the component 500 is a resistor, such as a zero ohm resistor. In some embodiments, the component 500 is a resistor having a resistance value less than fifty ohms. In other embodiments, the component 500 is a capacitor. In some examples, the capacitor can have a value of 0.1 microfarad, however other capacitor values are contemplated. For example, the capacitor can have a value based on the operating frequency of the associated data storage device.

[0041] Turning now to Figure 6 A process 600 for reducing etching on a contact trace coupled to a contact finger or other external device connection point on a data storage device due to the JFET effect is described in accordance with some embodiments. The process 600 is described with reference to the circuit board 300 and the data storage device 102 described above, however it is contemplated that the process 600 is applicable to any data storage device having a contact finger constructed of a different material than an internal contact trace electrically coupled to the contact finger. The process 600 can be performed by one or more electronic processors or computing devices executing software or other computer-implemented instructions for performing the following functions.

[0042] At block 602, a ratio of a surface area of a contact finger, such as the contact finger 304, to a surface area of an exposed contact trace, such as the exposed portion 314, of a data storage device electrically connected to a contact trace, such as the contact trace 302, is calculated. In one embodiment, the exposed contact trace is a portion of the contact trace that is not encapsulated by a solder mask and exposed without any plating or coating. The contact finger is a plated portion of the contact trace configured to interface with a host device and plated with a different material than the contact trace. In some embodiments, a JFET voltage can be calculated based on the ratio of the surface area of the contact finger and the material to the surface area of the exposed contact trace.

[0043] At block 604, it is determined whether the calculated ratio exceeds a predetermined value. In some embodiments, the predetermined value can be a ratio of twenty to one. However, ratios greater than twenty to one or less than twenty to one are also contemplated. In some examples, the predetermined ratio value can be a ratio of fifteen to one. The predetermined value can vary based on the type of material associated with the contact finger and the exposed contact trace. In some embodiments, it is determined whether the calculated Janssen voltage exceeds a predetermined value based at least in part on the calculated ratio and the material of the contact finger and the exposed contact trace. For example, the predetermined Janssen voltage value can be 0.3 V. However, values greater than 0.3 V or less than 0.3 V are contemplated. In some examples, the predetermined Janssen voltage level can be determined based on a desired amount of etching caused by a Janssen voltage level that exceeds a desired amount.

[0044] At block 606, in response to determining that the ratio does not exceed the predetermined value, the contact trace is not modified. At block 608, in response to determining that the ratio does not exceed the predetermined value, the exposed contact trace is separated into a modified exposed contact trace, such as exposed portion 314, and a separate impedance trace, such as impedance trace 316. The modified exposed contact trace can be substantially smaller (e.g., have a smaller surface area) than the unmodified exposed contact trace. For example, the modified exposed contact trace can have a surface area that is approximately 20% of the unmodified exposed contact trace. However, values greater than 20% or less than 20% are also contemplated in other embodiments.

[0045] At block 610, the modified exposed contact trace and a first portion of the impedance trace are plated with the same material as the contact finger to form a pad, such as first pad 315 and second pad 318 described above. In some examples, the modified exposed contact trace and the first portion of the impedance trace are plated simultaneously and with the same material as the contact finger. In one embodiment, first pad 315 and second pad 318 have approximately the same size (e.g., have the same surface area). In other embodiments, the size of first pad 315 is set to allow for a connection between first pad 315 and second pad 318, as described in more detail below. In one embodiment, the plating material is gold. In other embodiments, the plating material is a nickel gold compound. Other plating materials suitable for a given application are contemplated. By plating the modified exposed contact trace with the same material as the contact finger, etching of first pad 315 due to the Janssen effect is reduced or eliminated. The ratio of different exposed materials on the contact finger and the contact trace can be as low as 0.3: 1. However, other ratios are contemplated. Additionally, the ratio of different exposed materials between first pad 315 and second pad 318 can be as low as 0.3: 1.

[0046] At block 612, a cleaning and pre-soldering process is performed, such as described above. For example, a cleaning solution can first be applied to the data storage device to remove any organic material, and then an OSP process can be performed to prevent contamination of the traces and other connections on the data storage device.

[0047] At block 614, a connection is made between the first pad 315 and the second pad 318. In one embodiment, the connection is made by joining a wire between the first pad 315 and the second pad 318. The wire can be a gold wire. In other embodiments, the wire is made of the same material as the plating applied to the first pad 315 and the second pad 318. In some embodiments, the connection is made by coupling a component between the modified exposed contact trace and the first portion of the impedance trace. In one example, the component is a zero ohm resistor. In other embodiments, the component is a capacitor. The component can be a surface mount device. In some examples, the physical size and package of the component is selected based on the size of the first pad 315 and the second pad 318 and the distance between the two.

[0048] At block 616, any remaining manufacturing processes are performed after the connection between the modified exposed contact trace and the first portion of the impedance trace is complete. The remaining manufacturing processes can include component placement, soldering, and applying a molding material to encapsulate the components of the data storage device.

[0049] Turning now to Figure 7 , partial substrate circuit layouts of data storage devices (such as those described above) coupled to one or more contact finger regions using different connection types are shown in accordance with some embodiments. Layout 700 shows a conventional substrate layout (as shown in Figure 2 ) in which connections to the contact finger regions are coupled directly via contact traces 702. Layout 704 shows a modified substrate layout (as shown in Figure 3 ) in which connections to the contact finger regions are facilitated by using a jumper 706 to provide an electrical connection between a contact trace 708 and an impedance trace 710 (similar to that shown in Figure 4 ). Layout 712 shows a modified substrate layout (as shown in Figure 3 ) in which connections to the contact finger regions are facilitated by using a component 714 to provide an electrical connection between a contact trace 716 and an impedance trace 718 (similar to that shown in Figure 5 ).

[0050] Figures 8A to 8C A manufacturing process for a data storage device (such as the data storage device 102 described above) is shown that uses both a conventional design 800 (e.g., the design of Figure 2 ) and a modified design 802 to reduce Janning effects on the contact traces during manufacturing (e.g., the effects shown in Figure 3design). Referring to Figure 8A Both the conventional design 800 and the modified design 802 start with a substrate core. In both designs 800, 802, the substrate drilling operation 804 and the copper plating operation 806 are performed in the same manner. During the patterning process 808, in the modified design 802, the impedance trace 809 is patterned to be separate from the contact finger trace 810, as described above.

[0051] Referring to Figure 8B A solder mask process 812 is applied to both designs 800, 802. Similarly, during a mask process 814, a mask for hard nickel gold (“Ni / Au”) plating is applied to both designs 800, 802 in the same manner. Hard Ni / Au is applied at a plating process 816 to plate at least a portion of the contact finger area, and the mask is subsequently removed for both designs 800, 802.

[0052] Referring to Figure 8C A soft Ni / Au mask process 818 applies a soft Ni / Au mask to both designs 800, 802. However, for the modified design 802, the soft Ni / Au mask is applied to allow soft Ni / Au plating on the contact finger trace 810, resulting in the formation of a first pad 820 during a soft Ni / Au plating process 824 and a second pad 822 on the impedance trace 809. An OSP process 826 is then applied to both designs 800, 802 as described above. As shown by the OSP process 826, the original design 800 experiences etching due to the Jamin effect on the contact trace coupled to the contact finger area, as detailed above. However, in the modified design 802, the contact trace does not experience etching due to the Jamin effect because the first pad 820 has the same material as the contact finger area, here Ni / Au plating. Some minor etching can occur on the impedance trace 809 due to the second pad 822, but this etching will be minor due to the relatively small surface area of the Ni / Au associated with the second pad 822.

[0053] Further manufacturing processes, such as component placement, soldering, and molding, can be performed when manufacturing the substrate. For example, during a component placement process, a wire or component can be placed between the first pad 820 and the second pad 822, such as described above in Figure 4 and Figure 5 .

[0054] For the processes, systems, methods, heuristics, etc. described herein, it should be understood that, although the steps of such processes, etc. have been described as occurring according to a certain ordered sequence, such processes could be practiced with the described steps performed in an order other than the order described herein. It further should be understood that certain steps could be performed simultaneously, that other steps could be added, or that described steps could be modified without departing from the scope of the claims. In other words, the descriptions of processes herein are provided for the purpose of illustrating certain implementations, and one skilled in the art will recognize that the processes could be practiced with the described steps performed in an order other than the order described herein, or with additional steps, or with fewer steps, without departing from the scope of the claims.

[0055] Accordingly, it is to be understood that the above description is intended to be illustrative and not restrictive. Many embodiments and applications other than the examples provided would be apparent upon reading the above description and that the scope of the claims should be determined not with reference to the above description alone, but instead should be determined in accordance with the full breadth of the claims, along with their equivalents and / or permutations. It is anticipated and intended that future developments will occur in the technologies discussed herein, and that the disclosed systems and methods will be incorporated into such future embodiments. In sum, it should be understood that the application is capable of modification and variation.

[0056] All terms used in the claims are to be given their broadest reasonable construction and ordinary meaning unless an unequivocal opposite intention of a person skilled in the art is otherwise indicated. Specifically, the use of singular articles such as "a", "the", "said", etc. should be understood to mean one or more, unless the context clearly dictates otherwise.

[0057] The Abstract is provided to allow a reader to quickly ascertain the nature of the technical disclosure. It is not intended to be used to interpret or limit the scope or the meaning of the claims. Furthermore, it is to be understood that the submission of the Abstract is not intended to limit the scope of the claims to the specific recitations in the Abstract. Moreover, the Abstract is to be interpreted to mean that the technical disclosure is concerned with the features recited in the Abstract. The Abstract is provided to allow a reader to quickly ascertain the nature of the technical disclosure. It is not intended to be used to interpret or limit the scope or the meaning of the claims. Furthermore, it is to be understood that the submission of the Abstract is not intended to limit the scope of the claims to the specific recitations in the Abstract. Moreover, the Abstract is to be interpreted to mean that the technical disclosure is concerned with the features recited in the Abstract.

Claims

1. A printed circuit board for an electronic device, the printed circuit board comprising: a substrate having a first side and a second side opposite the first side; a contact finger disposed on the first side of the substrate and configured to interface with an external electronic device; a contact trace coupled to the contact finger and extending from the first side of the substrate to the second side of the substrate, wherein the contact trace has an exposed portion disposed on the second side of the substrate; and an impedance trace disposed on the second side of the substrate and configured to be coupled to one or more components of the electronic device; wherein the contact finger and the exposed portion of the contact trace are plated with a common material to reduce Javanii etching of the contact trace; and wherein the exposed portion of the contact trace is electrically connected to the impedance trace by at least one of a component and a bond wire.

2. The printed circuit board of claim 1, wherein the exposed portion of the contact trace is electrically connected to the impedance trace by a bond wire.

3. The printed circuit board of claim 1, wherein the component is a resistor.

4. The printed circuit board of claim 1, wherein the component is a capacitor.

5. The printed circuit board of claim 1, wherein a surface area of the contact finger is up to twenty times greater than the exposed portion of the contact trace.

6. The printed circuit board of claim 1, wherein the common material is gold.

7. The printed circuit board of claim 1, wherein the common material is nickel gold.

8. The printed circuit board of claim 1, wherein the impedance trace includes a plated portion plated with the common material, and wherein the plated portion of the impedance trace is coupled to the component.

9. A method for reducing etching in a printed circuit board due to the Javanii effect, the method comprising: determining a ratio of a surface area of a contact finger to a surface area of an exposed portion of a contact trace electrically connected to the contact finger, wherein the contact finger is configured to provide an electrical connection with an external electronic device; determining whether the ratio exceeds a predetermined threshold; in response to determining that the ratio exceeds the predetermined threshold, separating the exposed portion of the contact trace into a contact trace portion and an impedance trace, wherein the contact trace portion and the impedance trace are electrically isolated; plating the contact finger and the contact trace portion with a common material to reduce Javanii etching of the contact trace; and electrically connecting the contact trace portion and the impedance trace with one of a component or a bond wire.

10. The method of claim 9, wherein the contact trace portion and the impedance trace are electrically connected with the bond wire.

11. The method of claim 9, wherein the component is a resistor having a resistance value of less than fifty ohms.

12. The method of claim 9, wherein the component is a capacitor.

13. The method of claim 9, wherein the common material is gold. ​ ​ 14. The method of claim 9, further comprising plating a first portion of the impedance trace with the common material.

15. A card-type data storage device, the card-type data storage device comprising: a substrate having a first side and a second side opposite the first side; a contact finger disposed on the first side of the substrate and configured to interface with a host device and plated with a plating material; a first trace coupled to the contact finger and extending from the first side of the substrate to the second side of the substrate, wherein the first trace has an exposed portion disposed on the second side of the substrate, the exposed portion plated with the plating material; and a second trace disposed on the second side of the substrate, wherein a portion of the second trace is plated with the plating material; and wherein the exposed portion of the first trace is electrically connected to the second trace through a connection device connected between the plated portion of the first trace and the plated portion of the second trace; and wherein the contact finger and the exposed portion of the first trace are plated with a common material to reduce Javanell etching of the first trace.

16. The card-type data storage device of claim 15, wherein the connection device is a bond wire.

17. The card-type data storage device of claim 15, wherein the connection device is a resistor.

18. The card-type data storage device of claim 15, wherein the connection device is a capacitor.

19. The card-type data storage device of claim 15, wherein a surface area of the contact finger is up to twenty times greater than the exposed portion of the first trace.

20. The card-type data storage device of claim 15, wherein the plating material is at least one of gold or nickel gold. ​ ​

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