Printed circuit boards and their manufacturing methods

Abstract

This invention discloses a printed circuit board and its manufacturing method. The inner layer of the printed circuit board includes at least one set of coaxial metallized vias, wherein each set of coaxial metallized vias includes a coaxial macro-hole and a coaxial micro-hole, with an insulating material disposed between the macro-hole and the micro-hole; in a set of coaxial metallized vias, the conductive layer at the orifice of the coaxial macro-hole is located in a different layer from the conductive layer at the orifice of the coaxial micro-hole located on the same layer of the printed circuit board; the printed circuit board also includes a coaxial macro-hole conductive structure and a coaxial micro-hole conductive structure. The conductivity of the coaxial macro-hole conductive structure and the coaxial micro-hole conductive structure is related to the alignment of the coaxial metallized vias, wherein the alignment of the coaxial metallized vias includes the deviation amount and / or offset direction of the coaxial micro-hole. The technical solution provided by this invention achieves non-destructive testing, simplifies the testing process for the alignment of coaxial holes on printed circuit boards, and reduces testing costs.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board technology, and more particularly to a printed circuit board and its preparation method. Background Technology

[0002] Coaxial via technology enables true signal impedance continuity, provides an excellent ground (GND) loop, and effectively reduces crosstalk between vias and between vias and traces. Coaxial via technology is a pre-research project for 5G high-frequency solutions, aiming to achieve better waveguide characteristics by mimicking coaxial cable design. Coaxial vias on circuit boards are used in RF coaxial cables, where the transmission loop consists of an inner conductor, an insulating medium, and an outer conductor. These three parts are concentric, meaning they share a common central axis, thus requiring high precision in the coaxial via's position.

[0003] The coaxial hole design involves drilling a large coaxial hole in the sub-board. After the large coaxial hole passes through the resin plug, a small coaxial hole is drilled in the middle of the large coaxial hole that has passed through the resin plug. Usually, the large coaxial hole and the small coaxial hole are not on the same layer, and the hole diameters differ greatly. The number of layers between them is N (N≥1).

[0004] Currently, the requirements for some electrical properties and performance indicators of coaxial holes are not clearly defined. The only known indicator is the coaxial hole alignment, which is required to be ±2 μL. The current method for measuring the alignment of coaxial holes is by slicing. Although this method can quantify the alignment data, sampling measurement will cause the substrate to be scrapped. Therefore, we are considering adopting a method that does not require slicing and directly measures the alignment of coaxial holes using tools. Summary of the Invention

[0005] This invention provides a printed circuit board and its manufacturing method to simplify the detection process of coaxial hole alignment on the printed circuit board and reduce detection costs.

[0006] According to one aspect of the present invention, a printed circuit board is provided, the printed circuit board comprising an inner layer and an outer layer, and further comprising:

[0007] The circuit board includes: an inner layer comprising at least one set of coaxial metallized vias, wherein each set of coaxial metallized vias includes a coaxial large via and a coaxial small via, an insulating material is disposed between the coaxial large via and the coaxial small via, the conductive layer of the coaxial large via includes a coaxial large via layer, the conductive layer of the coaxial small via includes a coaxial small via layer, the coaxial large via layer includes a coaxial large via orifice conductive layer and a coaxial large via internal conductive layer, and the coaxial small via layer includes a coaxial small via orifice conductive layer and a coaxial small via internal conductive layer; in a set of coaxial metallized vias, the conductive layer at the orifice of the coaxial large via is located on a different layer from the conductive layer at the orifice of the coaxial small via located on the same layer of the printed circuit board;

[0008] The printed circuit board further includes a coaxial large-hole conductive structure and a coaxial small-hole conductive structure. The coaxial large-hole conductive structure is connected to the conductive layer at the orifice of the coaxial large-hole, and the coaxial small-hole conductive structure is connected to the conductive layer at the orifice of the coaxial small-hole. The conductivity of the coaxial large-hole conductive structure and the coaxial small-hole conductive structure is related to the alignment of the coaxial metallized via. The alignment of the coaxial metallized via includes the deviation amount and / or offset direction of the coaxial small-hole.

[0009] Optionally, the printed circuit board further includes a coaxial large-hole connection pad, a connection through-hole, and a connection blind via; the coaxial large-hole connection pad and the conductive layer at the opening of the coaxial large-hole are located on the same layer, located outside the coaxial large-hole, and connected to the conductive layer at the opening of the coaxial large-hole; the orthographic projection of the connection through-hole on the printed circuit board covers at least a portion of the orthographic projection of the coaxial large-hole connection pad on the printed circuit board; the bottom pad of the connection blind via is located on the same layer as the conductive layer at the opening of the coaxial small-hole, and the orthographic projection of the bottom pad of the connection blind via on the printed circuit board at least covers the orthographic projection of the inner region of the conductive layer ring inside the coaxial large-hole on the printed circuit board, and is insulated from the connection through-hole;

[0010] The outer layer of the printed circuit board includes a coaxial small hole test pad and a coaxial large hole test pad. The coaxial large hole test pad covers at least a portion of the opening of the connecting through hole, and the coaxial small hole test pad covers at least a portion of the opening of the connecting blind hole.

[0011] The coaxial large-hole connection pad, the connection through hole, and the coaxial large-hole test pad constitute the coaxial large-hole conductive structure; the connection blind hole and the coaxial small-hole test pad constitute the coaxial small-hole conductive structure.

[0012] The continuity of the coaxial large-hole test pad and the coaxial small-hole test pad is related to the alignment of the coaxial metallized via, wherein the alignment of the coaxial metallized via includes the deviation and / or offset direction of the coaxial small hole.

[0013] Optionally, it includes n sets of coaxial metallized vias, wherein the value of n includes integers greater than or equal to 1;

[0014] The diameters of the n coaxial holes include: first diameter, second diameter, ..., nth diameter;

[0015] The diameter differences between the n coaxial small holes and the coaxial large holes include: first diameter difference, second diameter difference, ..., nth diameter difference, where, first diameter difference > second diameter difference > ... > nth diameter difference;

[0016] The diameter of the coaxial small hole in the i-th group of coaxial metallized vias is the i-th hole diameter, and the difference between the diameter of the i-th hole and the coaxial large hole is the i-th hole diameter difference. The value of i includes integers greater than or equal to 1 and less than or equal to n.

[0017] Optionally, the conductive layer inside the coaxial large hole includes at least two insulated sector rings;

[0018] The coaxial large hole connection pad includes at least two insulated sector-shaped connection pads, which are arranged around the sector-shaped ring and are connected in a one-to-one correspondence with the sector-shaped ring.

[0019] The connection vias include at least two, and the connection vias, in their orthographic projection on the printed circuit board, cover at least a portion of the orthographic projection of the fan-shaped connection pads on the printed circuit board.

[0020] The coaxial large-hole test pads include at least two, and each coaxial large-hole test pad corresponds to at least a portion of the opening of the connecting through hole.

[0021] Optionally, in each group of coaxial metallized vias, the number of spacing layers between the coaxial small via opening conductive layer and the coaxial large via opening conductive layer located on the same side of the printed circuit board is less than the number of spacing layers between the coaxial small via opening conductive layer and the outer layer.

[0022] According to another aspect of the present invention, a method for manufacturing a printed circuit board is provided, comprising:

[0023] At least one coaxial macrohole is formed in the inner layer of the printed circuit board, wherein the coaxial macrohole is a metallized via, and the conductive layer of the coaxial macrohole includes a coaxial macrohole layer, which includes a conductive layer at the orifice of the two coaxial macroholes and a conductive layer inside the coaxial macrohole.

[0024] The conductive layer at the coaxial large hole opening is laminated to the side of the printed circuit board that is away from the coaxial small hole opening.

[0025] At least one coaxial via is formed in the structure after lamination, wherein the coaxial via is a metallized via, the conductive layer of the coaxial via includes a coaxial via layer, the coaxial via layer includes a conductive layer at the via opening and a conductive layer inside the via; in a group of coaxial metallized vias, the conductive layer at the via opening of the coaxial via is located on a different layer from the coaxial via layer located on the same layer as the printed circuit board;

[0026] It also includes forming a coaxial macro-hole conductive structure and a coaxial micro-hole conductive structure. The coaxial macro-hole conductive structure is connected to the conductive layer at the orifice of the coaxial macro-hole, and the coaxial micro-hole conductive structure is connected to the conductive layer at the orifice of the coaxial micro-hole. The conductivity of the coaxial macro-hole conductive structure and the coaxial micro-hole conductive structure is related to the alignment of the coaxial metallized via. The alignment of the coaxial metallized via includes the deviation amount and / or offset direction of the coaxial micro-hole.

[0027] Optionally, the coaxial large-hole conductive structure includes a coaxial large-hole connection pad, a connection through-hole, and a coaxial large-hole test pad; the coaxial small-hole conductive structure includes a connection blind via and a coaxial small-hole test pad.

[0028] The process of laminating the conductive layer at the coaxial large hole opening on the side facing away from the printed circuit board and before reaching the conductive layer at the coaxial small hole opening includes:

[0029] A coaxial macrohole connection pad is formed, wherein the coaxial macrohole connection pad and the coaxial macrohole orifice conductive layer are located in the same layer, located outside the coaxial macrohole and connected to the coaxial macrohole orifice conductive layer;

[0030] The coaxial large hole is plugged with insulating material;

[0031] At least one coaxial via is formed in the structure after lamination, wherein the coaxial via is a metallized via, the conductive layer of the coaxial via includes a coaxial via layer, the coaxial via layer includes a conductive layer at the via opening and a conductive layer inside the via; in a group of coaxial metallized vias, the conductive layer at the via opening of the coaxial via is located on a different layer from the coaxial via layer located on the same layer as the printed circuit board;

[0032] After the laminated structure forms at least one coaxial aperture, it also includes:

[0033] A bottom pad for connecting blind vias is formed, wherein the bottom pad for connecting blind vias and the conductive layer at the orifice of the coaxial small via are located on the same layer, and the orthogonal projection of the bottom pad for connecting blind vias on the printed circuit board at least covers the orthogonal projection of the inner region of the conductive layer ring inside the coaxial large via on the printed circuit board.

[0034] The inner and outer layers of the printed circuit board are laminated to form a connecting through hole and a connecting blind hole in the printed circuit board. The orthographic projection of the connecting through hole on the printed circuit board covers at least a portion of the orthographic projection of the coaxial large hole connecting pad on the printed circuit board. The bottom pad of the connecting blind hole is insulated from the connecting through hole.

[0035] Coaxial via test pads and coaxial large via test pads are formed on the outer layer of the printed circuit board. The coaxial large via test pads cover at least a portion of the opening of the connecting via. The conductivity of the coaxial large via test pads is related to the alignment of the coaxial metallized vias. The alignment of the coaxial metallized vias includes the deviation amount and / or offset direction of the coaxial via. Optionally, forming at least one coaxial via in the structure after lamination includes:

[0036] Drill n coaxial holes of different diameters into the laminated structure;

[0037] The diameters of the n coaxial pinholes include: first diameter, second diameter, ..., nth diameter, where n is an integer greater than or equal to 1; the diameter differences between the n coaxial pinholes and the coaxial large hole include: first diameter difference, second diameter difference, ..., nth diameter difference, where first diameter difference > second diameter difference > ... > nth diameter difference; the diameter of the coaxial pinhole in the i-th group of coaxial metallized vias is the i-th diameter, and the diameter difference between the i-th diameter coaxial pinhole and the coaxial large hole is the i-th diameter difference, where i is an integer greater than or equal to 1 and less than or equal to n.

[0038] Optionally, forming at least one coaxial macrohole in the inner layer of the printed circuit board includes:

[0039] Drill at least one coaxial large hole in the inner layer of the printed circuit board.

[0040] The coaxial macrohole is formed into a metallized via through copper plating and electroplating processes. The conductive layer of the coaxial macrohole includes a coaxial macrohole layer, which includes conductive layers at the orifices of the two coaxial macroholes and a conductive layer inside the coaxial macrohole.

[0041] A plugging device is inserted into the coaxial large hole, wherein the plugging device includes an inner rigid support and a flexible outer layer, the cross-section of the inner rigid support includes a solid part and at least two fan-shaped connecting parts distributed on the edge of the solid part, and a hollow area is provided between the fan-shaped connecting parts;

[0042] Using the via plugging device as a mask, the conductive layer inside the coaxial macrohole is wet-etched to form a coaxial macrohole with at least two insulating fan-shaped rings.

[0043] Forming coaxial large-hole connection pads includes:

[0044] The surface copper of the layer containing the conductive layer of the coaxial large hole is etched to form at least two insulated fan-shaped connection pads, wherein the fan-shaped connection pads are arranged around the fan-shaped ring and are connected to the fan-shaped ring in a one-to-one correspondence. The connection vias include at least two, and the connection vias cover at least a portion of the fan-shaped connection pads located on the orthographic projection of the printed circuit board on the printed circuit board.

[0045] Optionally, in each group of coaxial metallized vias, the conductive layer at the coaxial large via opening, after lamination on the side facing away from the printed circuit board, extends to the conductive layer at the coaxial small via opening, including:

[0046] At least one layer of conductive layer is laminated to the side of the coaxial large hole opening away from the printed circuit board to the coaxial small hole opening conductive layer.

[0047] The technical solution provided in this embodiment uses a coaxial large-hole conductive structure as the first electrical signal lead-out structure for the coaxial large-hole, and a coaxial small-hole conductive structure as the second electrical signal lead-out structure for the coaxial small-hole. By detecting the conductivity of the coaxial large-hole conductive structure and the coaxial small-hole conductive structure, the deviation amount and / or offset direction of the coaxial small-hole can be determined. This eliminates the need to detect the alignment of the coaxialized metal vias in the inner layer through a slicing process, achieving non-destructive testing, simplifying the testing process, and thus saving testing costs.

[0048] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of a printed circuit board structure according to an embodiment of the present invention;

[0051] Figure 2 This is a schematic diagram of another printed circuit board structure provided according to an embodiment of the present invention;

[0052] Figure 3 This is a schematic diagram of another printed circuit board structure provided according to an embodiment of the present invention;

[0053] Figure 4 yes Figure 3Top view of the three sets of coaxial metallized vias;

[0054] Figure 5 yes Figure 3 3D view of the three sets of coaxial metallized vias;

[0055] Figure 6 yes Figure 5 Top view of the three sets of coaxial metallized vias and coaxial large hole connecting pads;

[0056] Figure 7 yes Figure 5 3D unfolded view of the three sets of coaxial metallized vias;

[0057] Figure 8 This is a top view of the coaxial small hole test pad and the coaxial large hole test pad;

[0058] Figure 9 This is a flowchart of a method for manufacturing a printed circuit board according to an embodiment of the present invention;

[0059] Figures 10-15 This is a schematic diagram of the structure corresponding to each step of a method for manufacturing a printed circuit board according to an embodiment of the present invention;

[0060] Figure 16 This is a flowchart of another method for manufacturing a printed circuit board according to an embodiment of the present invention;

[0061] Figure 17 This is a flowchart of another method for manufacturing a printed circuit board according to an embodiment of the present invention;

[0062] Figures 18-25 This is a structural diagram of each step in another method for manufacturing a printed circuit board according to an embodiment of the present invention;

[0063] Figure 26 This is a flowchart illustrating a method for testing the coaxial hole alignment of a printed circuit board, as provided in an embodiment of the present invention.

[0064] Figure 27 This is a flowchart illustrating another method for testing the coaxial hole alignment of a printed circuit board according to an embodiment of the present invention.

[0065] Figure 28 This is a flowchart illustrating another method for testing the coaxial hole alignment of a printed circuit board according to an embodiment of the present invention. Detailed Implementation

[0066] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0067] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0068] This invention provides a printed circuit board. The printed circuit board includes: an inner layer comprising at least one set of coaxial metallized vias, wherein each set of coaxial metallized vias includes a large coaxial via and a small coaxial via, an insulating material is disposed between the large and small coaxial vias, the conductive layer of the large coaxial via includes a large coaxial via layer, the conductive layer of the small coaxial via includes a small coaxial via layer, the large coaxial via layer includes a conductive layer at the large coaxial via opening and a conductive layer inside the large coaxial via, and the small coaxial via layer includes a conductive layer at the small coaxial via opening and a conductive layer inside the small coaxial via; in a set of coaxial metallized vias, the coaxial metallized vias... The conductive layer of the large-diameter hole and the conductive layer of the small-diameter hole located on the same layer of the printed circuit board are located on different layers. The printed circuit board also includes a coaxial large-diameter hole conductive structure and a coaxial small-diameter hole conductive structure. The coaxial large-diameter hole conductive structure is connected to the conductive layer of the large-diameter hole, and the coaxial small-diameter hole conductive structure is connected to the conductive layer of the small-diameter hole. The conductivity of the coaxial large-diameter hole conductive structure and the coaxial small-diameter hole conductive structure is related to the alignment of the coaxial metallized via. The alignment of the coaxial metallized via includes the deviation amount and / or offset direction of the coaxial small-diameter hole.

[0069] The technical solution provided in this embodiment uses a coaxial large-hole conductive structure as the first electrical signal lead-out structure for the coaxial large-hole, and a coaxial small-hole conductive structure as the second electrical signal lead-out structure for the coaxial small-hole. By detecting the conductivity of the coaxial large-hole conductive structure and the coaxial small-hole conductive structure, the deviation amount and / or offset direction of the coaxial small-hole can be determined. This eliminates the need to detect the alignment of the coaxialized metal vias in the inner layer through a slicing process, achieving non-destructive testing, simplifying the testing process, and thus saving testing costs.

[0070] Optionally, the printed circuit board further includes a coaxial large-hole connection pad, a connection through-hole, and a connection blind via; the coaxial large-hole connection pad and the coaxial large-hole orifice conductive layer are located on the same layer, located outside the coaxial large-hole, and connected to the coaxial large-hole orifice conductive layer; the orthogonal projection of the connection through-hole on the printed circuit board covers at least a portion of the orthogonal projection of the coaxial large-hole connection pad on the printed circuit board; the bottom pad of the connection blind via is located on the same layer as the coaxial small-hole orifice conductive layer, and the orthogonal projection of the bottom pad of the connection blind via on the printed circuit board at least covers the orthogonal projection of the inner region of the conductive layer ring inside the coaxial large-hole on the printed circuit board, and is insulated from the connection through-hole; the outer layer of the printed circuit board includes a coaxial small-hole test pad and a coaxial large-hole test pad, the coaxial large-hole test pad covering at least a portion of the orifice of the connection through-hole, and the coaxial small-hole test pad covering at least a portion of the orifice of the connection blind via. The coaxial large-hole connecting pad, connecting through-hole, and coaxial large-hole test pad constitute the coaxial large-hole conductive structure; the connecting blind via and coaxial small-hole test pad constitute the coaxial small-hole conductive structure. The conductivity of the coaxial large-hole test pad and the coaxial small-hole test pad is related to the alignment of the coaxial metallized via, where the alignment of the coaxial metallized via includes the deviation amount and / or offset direction of the coaxial small via.

[0071] Figure 1 This is a schematic diagram of a printed circuit board according to an embodiment of the present invention. Figure 2 This is a schematic diagram of another printed circuit board structure provided according to an embodiment of the present invention. For example, see [link to example diagram]. Figure 1 and Figure 2The inner layer of the printed circuit board includes three sets of coaxial metallized vias. Each set of coaxial metallized vias consists of three large coaxial vias M0, one small coaxial via M0, and one small coaxial via. The small coaxial vias include a first small coaxial via m1, a second small coaxial via m2, and a third small coaxial via m3. The conductive layer of the large coaxial via M0 includes a large coaxial via layer, and the conductive layer of the small coaxial via includes a small coaxial via layer. The large coaxial via layer includes a conductive layer Ls at the via opening and a conductive layer L01 inside the via. The small coaxial via layer includes a conductive layer Ls-q at the via opening and a conductive layer L02 inside the via, where q takes the value of an integer greater than or equal to 1. An insulating material, such as resin, is placed between the large coaxial via M0 and the small coaxial via. The printed circuit board also includes a coaxial large-hole connection pad 11, a connection through-hole 12, and a connection blind via 13; the coaxial large-hole connection pad 11, the connection through-hole 12, and the coaxial large-hole test pad 15 constitute a coaxial large-hole conductive structure; the connection blind via 13 and the coaxial small-hole test pad 16 constitute a coaxial small-hole conductive structure. The coaxial large-hole connection pad 11 and the coaxial large-hole orifice conductive layer Ls are located on the same layer and are connected to the coaxial large-hole orifice conductive layer Ls; the orthogonal projection of the connection through-hole 12 on the printed circuit board covers the portion of the orthogonal projection of the coaxial large-hole connection pad 11 on the printed circuit board; the bottom pad 14 of the connection blind via 13 is located on the same layer as the coaxial small-hole orifice conductive layer Ls-q, and the orthogonal projection of the bottom pad 14 of the connection blind via 13 on the printed circuit board covers the orthogonal projection of the area inside the conductive layer L01 ring of the coaxial large-hole on the printed circuit board, and is insulated from the connection through-hole 12. The outer layer of the printed circuit board includes a coaxial small hole test pad 16 and a coaxial large hole test pad 15. The coaxial large hole test pad 15 covers the opening of the connecting through hole 12, and the coaxial small hole test pad 16 covers the opening of the connecting blind hole 13. The conductivity of the coaxial large hole test pad 15 and the coaxial small hole test pad 16 is related to the alignment of the coaxial metallized via. The alignment of the coaxial metallized via includes the deviation amount and / or offset direction of the coaxial small hole.

[0072] Figure 1 In the diagram, the first coaxial small hole m1 is not in contact with the coaxial large hole M0, and the first coaxial small hole m1 is in an open circuit connection relative to the coaxial large hole M0. The second coaxial small hole m2 is not in contact with the coaxial large hole M0, and the second coaxial small hole m2 is in an open circuit connection relative to the coaxial large hole M0. The third coaxial small hole m3 is not in contact with the coaxial large hole M0, and the third coaxial small hole m3 is in an open circuit connection relative to the coaxial large hole M0.

[0073] Figure 2 In the diagram, the first coaxial small hole m1 is in contact with the coaxial large hole M0, and the first coaxial small hole m1 is short-circuited relative to the coaxial large hole M0. The second coaxial small hole m2 is in contact with the coaxial large hole M0, and the second coaxial small hole m2 is short-circuited relative to the coaxial large hole M0. The third coaxial small hole m3 is in contact with the coaxial large hole M0, and the third coaxial small hole m3 is short-circuited relative to the coaxial large hole M0.

[0074] Specifically, the coaxial large hole connecting pad 11 and the coaxial large hole orifice conductive layer Ls are located on the same layer and are connected to the coaxial large hole orifice conductive layer Ls. The orthogonal projection of the connecting through hole 12 on the printed circuit board covers the orthogonal projection of the coaxial large hole connecting pad 11 on the printed circuit board. The coaxial large hole test pad 15 covers the orifice of the connecting through hole 12. The coaxial large hole connecting pad 11 and the connecting through hole 12 serve as the first electrical signal lead-out structure of the coaxial large hole layer of the coaxial large hole M0, which can form a path between the coaxial large hole layer of the coaxial large hole M0 and the coaxial large hole test pad 15.

[0075] The bottom pad 14 of the blind via 13 is located on the same layer as the conductive layer Ls-q at the opening of the coaxial via. The orthographic projection of the bottom pad 14 of the blind via 13 on the printed circuit board at least covers the orthographic projection of the area inside the conductive layer L01 ring of the coaxial via on the printed circuit board, and is insulated from the through hole 12. The test pad 16 of the coaxial via covers the opening of the blind via 13. The bottom pad 14 of the blind via 13 and the blind via 13 serve as the second electrical signal lead-out structure of the coaxial via layer of the coaxial via, which can form a path between the coaxial via and the test pad 16.

[0076] Meanwhile, the coaxial large hole connection pad 11 is located outside the coaxial large hole M0, and the orthographic projection of the connection through hole 12 on the printed circuit board covers at least a portion of the orthographic projection of the coaxial large hole connection pad 11 on the printed circuit board. The connection through hole 12 and the connection blind hole 13 are insulated from each other. Therefore, if the coaxial large hole test pad 15 and the coaxial small hole test pad 16 are conductive, the coaxial small hole and the coaxial large hole M0 must be in contact, which will cause the coaxial large hole test pad 15 and the coaxial small hole test pad 16 to form a circuit and form a short circuit connection.

[0077] The technical solution provided in this embodiment uses a coaxial large-hole connecting pad and a connecting through-hole as the first electrical signal lead-out structure for the coaxial large-hole, which can form a path between the coaxial large-hole and the coaxial large-hole test pad. Similarly, the bottom pad of a connecting blind hole and the connecting blind hole serve as the second electrical signal lead-out structure for a coaxial small-hole, which can also form a path between the coaxial small-hole and the coaxial small-hole test pad. Simultaneously, the coaxial large-hole connecting pad is located outside the coaxial large-hole, and the orthographic projection of the connecting through-hole on the printed circuit board covers at least a portion of the orthographic projection of the coaxial large-hole connecting pad on the printed circuit board. The connecting through-hole and the connecting blind hole are insulated from each other. Only when the coaxial small-hole and the coaxial large-hole are in contact will the coaxial large-hole test pad and the coaxial small-hole test pad form a path, creating a short-circuit connection. Therefore, the printed circuit board provided in this embodiment determines the deviation and / or offset direction of the coaxial via by detecting the continuity of the coaxial large hole test pad and the coaxial small hole test pad. It eliminates the need to detect the alignment of the coaxial metal vias in the inner layer through a slicing process, thus achieving non-destructive testing, simplifying the testing process, and saving testing costs.

[0078] Optionally, the printed circuit board includes n sets of coaxial metallized vias, where n is an integer greater than or equal to 1; the diameters of the n coaxial vias include: first diameter, second diameter, ..., nth diameter; the diameter differences between the n coaxial vias and the coaxial large vias include: first diameter difference, second diameter difference, ..., nth diameter difference, where first diameter difference > second diameter difference > ... > nth diameter difference; the diameter of the coaxial via in the i-th set of coaxial metallized vias is the i-th diameter, and the diameter difference between the i-th diameter coaxial via and the coaxial large via is the i-th diameter difference, where i is an integer greater than or equal to 1 and less than or equal to n.

[0079] Figure 3 This is a schematic diagram of another printed circuit board structure provided according to an embodiment of the present invention. Figure 4 yes Figure 3 Top view of the three sets of coaxial metallized vias. See also, for an example, [link to example]. Figure 3 and Figure 4 There are three sets of coaxial metallized vias. The diameter of the first coaxial via m1 is the first diameter d1, the diameter of the second coaxial via m2 is the second diameter d2, and the diameter of the third coaxial via m3 is the third diameter d3. The difference between the diameter of the first coaxial via m1 and the diameter of the coaxial via M0 is the first diameter difference Δd1, the difference between the diameter of the second coaxial via m2 and the diameter of the coaxial via M0 is the second diameter difference Δd2, and the difference between the diameter of the third coaxial via m3 and the diameter of the coaxial via M0 is the third diameter difference Δd3. The first diameter difference > the second diameter difference > the third diameter difference.

[0080] Although the first and second coaxial pinholes m1 and m2 deviate from the coaxial bore M0 in a certain offset direction, they are not yet in contact. The coaxial bore test pad 15 and the coaxial pinhole test pad 16 do not form a closed circuit; they are open-circuit connections. The third coaxial pinhole m3 deviates from the coaxial bore M0 in a certain offset direction, and it is in contact with the coaxial bore M0. The coaxial bore test pad 15 and the coaxial pinhole test pad 16 form a closed circuit; they are short-circuit connections. It should be noted that it can be inferred without doubt that in other embodiments, if a fourth coaxial aperture m4 is provided, the aperture of the fourth coaxial aperture m4 is the fourth aperture d4, and the aperture difference between the fourth coaxial aperture m4 and the coaxial large aperture M0 is the fourth aperture difference Δd4, the aperture difference between the fourth coaxial aperture m4 and the coaxial large aperture M0 is greater than the aperture difference between the third coaxial aperture m3 and the coaxial large aperture M0. Therefore, the offset between the fourth coaxial aperture m4 and the coaxial large aperture M0 causes them to contact each other. The coaxial aperture test pad 16 of the fourth coaxial aperture m4 and the coaxial large aperture test pad 15 of the coaxial large aperture M0 form a path, which is a short-circuit connection. In the above example, the aperture difference between the third coaxial aperture m3 and the coaxial large aperture M0 is the deviation of the coaxial aperture.

[0081] Specifically, in multiple sets of coaxial metallized vias, by setting coaxial vias of different diameters, the difference in diameter between the smallest coaxial via and the largest coaxial via in each set of coaxial metallized vias connected to the coaxial via test pad and the coaxial via test pad is defined as the deviation of the coaxial via. The aforementioned printed circuit board can quickly and accurately obtain the deviation of the coaxial via in the coaxial metallized vias.

[0082] Optionally, the conductive layer inside the coaxial macrovia includes at least two insulating sector rings; the coaxial macrovia connection pads include at least two insulating sector connection pads, which are arranged around the sector rings and are connected to each other in a one-to-one correspondence; the connection vias include at least two, which correspond to at least a portion of the sector connection pads on the printed circuit board in their orthographic projection on the printed circuit board; and the coaxial macrovia test pads include at least two, which correspond to at least a portion of the opening of the connection via.

[0083] Figure 5 yes Figure 3 A three-dimensional view of the three sets of coaxial metallized vias. Figure 6 yes Figure 5 Top view of the three sets of coaxial metallized vias. Figure 7 yes Figure 5 Three-dimensional unfolded view of the three sets of coaxial metallized vias. Figure 8 This is a top view of the coaxial small-hole test pad and the coaxial large-hole test pad. Figure 7Each set of coaxial metallized vias is surrounded by two connecting vias. See, for an example, [link to example]. Figure 6 The coaxial large-aperture conductive layer L01 includes eight insulated sector rings, namely, sector ring A, sector ring B, sector ring C, sector ring D, sector ring E, sector ring F, sector ring G, and sector ring H; the coaxial large-aperture connection pad 11 includes eight insulated sector connection pads, namely, sector connection pad 110a, sector connection pad 110b, sector connection pad 110c, sector connection pad 110d, sector connection pad 110e, sector connection pad 110f, sector connection pad 110g, and sector connection pad 110h. The sector connection pads are arranged around the sector rings, and the sector connection pads are connected to the sector rings one-to-one; the connection through holes 12 include eight, and the orthographic projection of the connection through holes 12 on the printed circuit board corresponds to the portion of the sector connection pads on the printed circuit board. For example, Figure 8 The coaxial large-hole test pads include eight pads: the first coaxial large-hole test pad 150a, the second coaxial large-hole test pad 150b, the third coaxial large-hole test pad 150c, the fourth coaxial large-hole test pad 150d, the fifth coaxial large-hole test pad 150e, the sixth coaxial large-hole test pad 150f, the seventh coaxial large-hole test pad 150, and the eighth coaxial large-hole test pad 150h. Each coaxial large-hole test pad is electrically connected to a corresponding through-hole 12.

[0084] In this example, although the first and second coaxial vias m1 and m2 deviate from the coaxial via M0 in the direction of offset from the axis of the coaxial metallized via towards the sector ring H, the coaxial vias m1 and m2 are not in contact with each other. Neither the coaxial via test pad nor the coaxial via test pad 16 forms a closed circuit; they are open-circuit connections. The third coaxial via m3 deviates from the coaxial via M0 in the direction of offset from the axis of the coaxial metallized via towards the eighth sector ring H. The third coaxial via m3 contacts the eighth sector ring H of the coaxial via M0, and the connecting via 12 passing through the eighth sector connecting pad 110h is electrically connected to the corresponding eighth coaxial via test pad 150h. This makes the eighth coaxial via test pad 150h and the coaxial via test pad 16 form a closed circuit, which is a short-circuit connection. In the above example, it can be determined that the direction of the eighth coaxial via test pad 150h relative to the coaxial via is the offset direction of the coaxial via.

[0085] Specifically, in multiple sets of coaxial metallized vias, the continuity status of the coaxial via test pad and each coaxial via test pad is obtained. In each set of coaxial metallized vias where the coaxial via test pads and via test pads are connected, the orientation of the coaxial via test pad connected to the coaxial via test pad relative to the coaxial via test pad is the offset orientation of the coaxial via test pad. The above-mentioned printed circuit board can quickly and accurately obtain the offset orientation of the coaxial via test pad.

[0086] Optionally, in each group of coaxial metallized vias, the number of interlayers between the coaxial small via opening conductive layer and the coaxial large via opening conductive layer located on the same side of the printed circuit board is less than the number of interlayers between the coaxial small via opening conductive layer and the outer layer.

[0087] For example, see Figures 1-3 as well as Figures 5-7 The number of layers between the conductive layer Ls-q at the coaxial via opening and the outer layer is less than the number of layers between the conductive layer Ls at the coaxial macro via opening and the outer layer. This makes the conductive layer Ls-q at the coaxial via opening closer to the outer layer than the conductive layer Ls at the coaxial macro via opening. This allows the bottom pad 14 of the connecting blind via 13 to be in the same layer as the conductive layer Ls-q at the coaxial via opening, covering the opening of the coaxial via, and having the same inner diameter as the coaxial macro via M0. In this case, the connecting through hole 12 and the connecting blind via 13 are insulated. Only when the coaxial via and the coaxial macro via M0 are in contact will the coaxial macro via test pad 15 and the coaxial via test pad 16 form a circuit and a short circuit connection. Furthermore, by detecting the continuity of the coaxial large-hole test pad 15 and the coaxial small-hole test pad 16, the alignment of the coaxial metallized via can be determined. This eliminates the need to detect the alignment of the inner coaxial metallized via through a slicing process, achieving non-destructive testing, simplifying the testing process, and thus saving testing costs.

[0088] This invention also provides a method for fabricating a printed circuit board. The method includes:

[0089] S110. At least one coaxial macrohole is formed in the inner layer of the printed circuit board, wherein the coaxial macrohole is a metallized via, and the conductive layer of the coaxial macrohole includes a coaxial macrohole layer, which includes conductive layers at the openings of the two coaxial macroholes and conductive layers inside the coaxial macroholes.

[0090] S120. The conductive layer of the coaxial large hole is laminated to the side of the printed circuit board away from the conductive layer of the coaxial small hole.

[0091] S130. At least one coaxial via is formed in the structure after lamination, wherein the coaxial via is a metallized via, and the conductive layer of the coaxial via includes a coaxial via layer, which includes a conductive layer at the via opening and a conductive layer inside the via; in a group of coaxial metallized vias, the conductive layer at the via opening of the coaxial via is located on a different layer from the coaxial via layer located on the same layer as the coaxial via layer on the printed circuit board.

[0092] S140 also includes forming a coaxial macro-hole conductive structure and a coaxial micro-hole conductive structure. The coaxial macro-hole conductive structure is connected to the conductive layer at the orifice of the coaxial macro-hole, and the coaxial micro-hole conductive structure is connected to the conductive layer at the orifice of the coaxial micro-hole. The conductivity of the coaxial macro-hole conductive structure and the coaxial micro-hole conductive structure is related to the alignment of the coaxial metallized via. The alignment of the coaxial metallized via includes the deviation amount and / or offset direction of the coaxial micro-hole.

[0093] The technical solution provided in this embodiment uses a coaxial large-hole conductive structure as the first electrical signal lead-out structure for the coaxial large-hole, and a coaxial small-hole conductive structure as the second electrical signal lead-out structure for the coaxial small-hole. By detecting the conductivity of the coaxial large-hole conductive structure and the coaxial small-hole conductive structure, the deviation amount and / or offset direction of the coaxial small-hole can be determined. This eliminates the need to detect the alignment of the coaxialized metal vias in the inner layer through a slicing process, achieving non-destructive testing, simplifying the testing process, and thus saving testing costs.

[0094] Figure 9 This is a flowchart illustrating a method for fabricating a printed circuit board according to an embodiment of the present invention. See also... Figure 9 The method for manufacturing this printed circuit board includes:

[0095] S110. At least one coaxial macrohole is formed in the inner layer of the printed circuit board, wherein the coaxial macrohole is a metallized via, and the conductive layer of the coaxial macrohole includes a coaxial macrohole layer, which includes conductive layers at the openings of the two coaxial macroholes and conductive layers inside the coaxial macroholes.

[0096] See Figure 10 Three coaxial macroholes M0 are formed in the inner layer of the printed circuit board. The coaxial macroholes M0 are metallized vias. The conductive layer of the coaxial macroholes M0 includes a coaxial macrohole layer, which includes two coaxial macrohole orifice conductive layers Ls and a coaxial macrohole inner conductive layer L01.

[0097] S120. Form a coaxial macrohole connection pad, wherein the coaxial macrohole connection pad and the coaxial macrohole orifice conductive layer are located in the same layer, located outside the coaxial macrohole and connected to the coaxial macrohole orifice conductive layer.

[0098] See Figure 11A coaxial macrohole connection pad 11 is formed, wherein the coaxial macrohole connection pad 11 and the coaxial macrohole orifice conductive layer Ls are located in the same layer, located outside the coaxial macrohole M0 and connected to the coaxial macrohole orifice conductive layer Ls. The coaxial macrohole connection pad 11 serves as the electrical signal lead-out structure of the coaxial macrohole M0.

[0099] S130. The coaxial large hole is plugged with insulating material.

[0100] See Figure 11 The coaxial large hole M0 is plugged with insulating material. This ensures that an insulating material, such as resin, is placed between the coaxial large hole M0 and the coaxial small hole.

[0101] S140. The conductive layer of the coaxial large hole is laminated to the side of the printed circuit board away from the conductive layer of the coaxial small hole.

[0102] See Figure 12 The coaxial large-hole conductive layer Ls, on the side facing away from the printed circuit board, is laminated to the coaxial small-hole conductive layer Ls-q, so that the coaxial large-hole conductive layer Ls and the coaxial small-hole conductive layer Ls-q are located on different layers. The value of q includes integers greater than or equal to 1.

[0103] Optionally, in each group of coaxial metallized vias in S140, the conductive layer at the coaxial large via opening is laminated to the side facing away from the printed circuit board before reaching the conductive layer at the coaxial small via opening, including:

[0104] At least one layer is laminated to the side of the coaxial large hole conductive layer Ls away from the printed circuit board to the coaxial small hole conductive layer Ls-q.

[0105] Specifically, the number of layers between the conductive layer Ls-q at the coaxial via opening and the outer layer is less than the number of layers between the conductive layer Ls at the coaxial macro via opening and the outer layer. This makes the conductive layer Ls-q at the coaxial via opening closer to the outer layer than the conductive layer Ls at the coaxial macro via opening. This allows the bottom pad 14 of the blind via 13 to be located on the same layer as the conductive layer Ls-q at the coaxial via opening. The orthographic projection of the bottom pad 14 of the blind via 13 onto the printed circuit board at least covers the orthographic projection of the area within the conductive layer L01 ring of the coaxial macro via onto the printed circuit board. Furthermore, it is insulated from the through-hole 12. Thus, by detecting the continuity between the test pads of the coaxial macro via and the test pads of the coaxial via, the alignment of the coaxial metallized via can be determined. This eliminates the need to use a slicing process to detect the alignment of the inner coaxial metallized via, achieving non-destructive testing, simplifying the testing process, and saving testing costs.

[0106] S150. At least one coaxial via is formed in the structure after lamination, wherein the coaxial via is a metallized via, wherein the conductive layer of the coaxial via includes a coaxial via layer, the coaxial via layer includes a conductive layer at the via opening and a conductive layer inside the via; in a group of coaxial metallized vias, the conductive layers at the via openings of the two coaxial large vias corresponding to the coaxial large vias are located on different layers from the coaxial via layers located on the same layer of the printed circuit board.

[0107] See Figure 13 Three coaxial vias are formed in the conductive layer Ls-q at the orifice of the coaxial via. These coaxial vias are metallized vias, and a larger coaxial via M0 surrounds them. This results in the inner layer of the printed circuit board comprising three sets of coaxial metallized vias. A set of coaxial metallized vias consists of one larger coaxial via M0 and one smaller coaxial via, and the smaller coaxial vias include a first coaxial via m1, a second coaxial via m2, and a third coaxial via m3.

[0108] S160. Form a bottom pad for connecting blind vias, wherein the bottom pad for connecting blind vias and the conductive layer at the opening of the coaxial via are located on the same layer, and the orthographic projection of the bottom pad for connecting blind vias on the printed circuit board at least covers the orthographic projection of the area inside the conductive layer ring of the coaxial via on the printed circuit board.

[0109] See Figure 13 The bottom pad 14 of the blind via is located on the same layer as the conductive layer Ls-q at the orifice of the coaxial via. The orthogonal projection of the bottom pad 14 of the blind via 13 onto the printed circuit board at least covers the orthogonal projection of the area within the conductive layer L01 ring inside the coaxial via onto the printed circuit board, and is insulated from the connecting through hole 12. The bottom pad 14 of the blind via serves as the electrical signal lead-out structure for the first coaxial via m1, the second coaxial via m2, and the third coaxial via m3.

[0110] S170. The inner and outer layers of the printed circuit board are laminated to form a connecting through hole and a connecting blind hole in the printed circuit, wherein the orthographic projection of the connecting through hole on the printed circuit board covers at least a portion of the orthographic projection of the coaxial large hole connecting pad on the printed circuit board, and the bottom pad of the connecting blind hole is insulated from the connecting through hole.

[0111] See Figure 14 The inner and outer layers of a printed circuit board are bonded together using a lamination process. See also... Figure 15 A connecting via 12 and a connecting blind via 13 are formed in the printed circuit board. The orthographic projection of the connecting via 12 onto the printed circuit board covers at least a portion of the orthographic projection of the coaxial macrohole connecting pad 11 onto the printed circuit board. The bottom pad 14 of the connecting blind via 13 is insulated from the connecting via 12, such that the connecting via 12 is electrically connected to the coaxial macrohole M0 through the coaxial macrohole connecting pad 11.

[0112] S180. Coaxial small hole test pads and coaxial large hole test pads are formed on the outer layer of the printed circuit board, wherein the coaxial large hole test pads cover at least a portion of the opening of the connecting through hole, and the coaxial small hole test pads cover at least a portion of the opening of the connecting blind hole. The conductivity of the coaxial large hole test pads and coaxial small hole test pads is related to the alignment of the coaxial metallized vias, wherein the alignment of the coaxial metallized vias includes the deviation amount and / or offset direction of the coaxial small hole.

[0113] See Figure 1 Coaxial via test pads 16 and 15 are formed on the outer layer of the printed circuit board. The coaxial via connection pad 11 and the coaxial via opening conductive layer Ls are located on the same layer and connected to each other. The orthographic projection of the via 12 on the printed circuit board covers the orthographic projection of the coaxial via connection pad 11 on the printed circuit board. The coaxial via test pad 15 covers the opening of the via 12. The coaxial via connection pad 11 and the via 12 serve as the first electrical signal lead-out structure for the coaxial via M0, allowing the coaxial via M0 and the coaxial via test pad 15 to form a path. The bottom pad 14 of the connecting blind via 13 is located on the same layer as the conductive layer Ls-q at the opening of the coaxial via. The orthographic projection of the bottom pad 14 of the connecting blind via 13 onto the printed circuit board covers the orthographic projection of the area within the conductive layer L01 ring inside the coaxial via onto the printed circuit board, and is insulated from the connecting via 12. The test pad 16 of the coaxial via covers the opening of the connecting blind via 13. The bottom pad 14 of the connecting blind via 13 and the connecting blind via 13 serve as the second electrical signal lead-out structure for the coaxial via, allowing the coaxial via and the test pad 16 to form a circuit. Meanwhile, the connecting pad 11 of the coaxial via is located outside the coaxial via M0. The orthographic projection of the connecting via 12 onto the printed circuit board covers at least a portion of the orthographic projection of the connecting pad 15 of the coaxial via onto the printed circuit board, and the connecting via 12 and the connecting blind via 13 are insulated from each other. Therefore, if the coaxial large hole test pad 15 and the coaxial small hole test pad 16 are conductive, the coaxial small hole and the coaxial large hole M0 must be in contact, which will cause the coaxial large hole test pad 15 and the coaxial small hole test pad 16 to form a circuit and form a short circuit connection.

[0114] The technical solution provided in this embodiment uses a coaxial large-hole connecting pad and a connecting through-hole as the first electrical signal lead-out structure for the coaxial large-hole, which can form a path between the coaxial large-hole and the coaxial large-hole test pad. Similarly, the bottom pad of a connecting blind hole and the connecting blind hole serve as the second electrical signal lead-out structure for a coaxial small-hole, which can also form a path between the coaxial small-hole and the coaxial small-hole test pad. Simultaneously, the coaxial large-hole connecting pad is located outside the coaxial large-hole, and the orthographic projection of the connecting through-hole on the printed circuit board covers at least a portion of the orthographic projection of the coaxial large-hole connecting pad on the printed circuit board. The connecting through-hole and the connecting blind hole are insulated from each other. Only when the coaxial small-hole and the coaxial large-hole are in contact will the coaxial large-hole test pad and the coaxial small-hole test pad form a path, creating a short-circuit connection. Therefore, the printed circuit board provided in this embodiment determines the deviation and / or offset direction of the coaxial via by detecting the continuity of the coaxial large hole test pad and the coaxial small hole test pad. It eliminates the need to detect the alignment of the coaxial metal vias in the inner layer through a slicing process, thus achieving non-destructive testing, simplifying the testing process, and saving testing costs.

[0115] It should be noted that, Figure 2 and Figure 3 The method for fabricating the printed circuit board shown is similar to Figure 1 The preparation method is the same. The only difference is that in S150, the diameter, offset, and offset direction of the coaxial aperture are different.

[0116] Figure 16 This is a flowchart of another method for manufacturing a printed circuit board according to an embodiment of the present invention. Figure 16 and Figure 9 The difference is that further research is needed. Figure 9 S150 in the document is specified. For details, see [link to document]. Figure 16 The method for manufacturing this printed circuit board includes the following steps:

[0117] S210. At least one coaxial macrohole is formed in the inner layer of the printed circuit board, wherein the coaxial macrohole is a metallized via, and the conductive layer of the coaxial macrohole includes a coaxial macrohole layer, which includes conductive layers at the orifices of the two coaxial macroholes and conductive layers inside the coaxial macroholes.

[0118] S220. Form a coaxial macrohole connection pad, wherein the coaxial macrohole connection pad and the coaxial macrohole orifice conductive layer are located in the same layer, located outside the coaxial macrohole and connected to the coaxial macrohole orifice conductive layer.

[0119] S230. The coaxial large hole is plugged with insulating material.

[0120] S240. The conductive layer of the coaxial large hole is laminated to the side of the printed circuit board away from the conductive layer of the coaxial small hole.

[0121] It should be noted that the implementation steps and beneficial effects of S210-S240 can be implemented with reference to the implementation steps and beneficial effects of S110-S140.

[0122] S250, Drill n coaxial holes of different diameters in the structure after lamination.

[0123] The diameters of the n coaxial vias include: first diameter, second diameter, ..., nth diameter, where n is an integer greater than or equal to 1; the diameter differences between the n coaxial vias and the coaxial large vias include: first diameter difference, second diameter difference, ..., nth diameter difference, where the first diameter difference > second diameter difference > ... > nth diameter difference; the diameter of the coaxial via in the i-th group of coaxial metallized vias is the i-th diameter, and the diameter difference between the i-th diameter coaxial via and the coaxial large via is the i-th diameter difference, where i is an integer greater than or equal to 1 and less than or equal to n.

[0124] For example, see Figure 3 and Figure 4 There are three sets of coaxial metallized vias. The diameter of the first coaxial via m1 is the first diameter d1, the diameter of the second coaxial via m2 is the second diameter d2, and the diameter of the third coaxial via m3 is the third diameter d3. The difference between the diameter of the first coaxial via m1 and the diameter of the coaxial via M0 is the first diameter difference Δd1, the difference between the diameter of the second coaxial via m2 and the diameter of the coaxial via M0 is the second diameter difference Δd2, and the difference between the diameter of the third coaxial via m3 and the diameter of the coaxial via M0 is the third diameter difference Δd3. The first diameter difference > the second diameter difference > the third diameter difference.

[0125] Although the first and second coaxial pinholes m1 and m2 deviate from the coaxial bore M0 in a certain offset direction, they are not yet in contact. The coaxial bore test pad 15 and the coaxial pinhole test pad 16 do not form a closed circuit; they are open-circuit connections. The third coaxial pinhole m3 deviates from the coaxial bore M0 in a certain offset direction, and it is in contact with the coaxial bore M0. The coaxial bore test pad 15 and the coaxial pinhole test pad 16 form a closed circuit; they are short-circuit connections. It should be noted that it can be inferred without doubt that in other embodiments, if a fourth coaxial aperture m4 is provided, the aperture of the fourth coaxial aperture m4 is the fourth aperture d4, and the aperture difference between the fourth coaxial aperture m4 and the coaxial large aperture M0 is the fourth aperture difference Δd4, the aperture difference between the fourth coaxial aperture m4 and the coaxial large aperture M0 is greater than the aperture difference between the third coaxial aperture m3 and the coaxial large aperture M0. Therefore, the offset between the fourth coaxial aperture m4 and the coaxial large aperture M0 causes them to contact each other. The coaxial aperture test pad 16 of the fourth coaxial aperture m4 and the coaxial large aperture test pad 15 of the coaxial large aperture M0 form a path, which is a short-circuit connection. In the above example, the aperture difference between the third coaxial aperture m3 and the coaxial large aperture M0 is the deviation of the coaxial aperture.

[0126] S260, forming a bottom pad for connecting blind vias, wherein the bottom pad for connecting blind vias and the conductive layer at the opening of the coaxial via are located on the same layer, and the orthographic projection of the bottom pad for connecting blind vias on the printed circuit board at least covers the orthographic projection of the area inside the conductive layer ring of the coaxial via on the printed circuit board.

[0127] S270. The inner and outer layers of a printed circuit board are laminated to form a connecting via and a connecting blind via in the printed circuit, wherein the orthographic projection of the connecting via on the printed circuit board covers at least a portion of the orthographic projection of the coaxial large hole connecting pad on the printed circuit board, and the bottom pad of the connecting blind via is insulated from the connecting via.

[0128] S280. Coaxial small hole test pads and coaxial large hole test pads are formed on the outer layer of a printed circuit board, wherein the coaxial large hole test pads cover at least a portion of the opening of a connecting through hole, and the coaxial small hole test pads cover at least a portion of the opening of a connecting blind hole. The conductivity of the coaxial large hole test pads and coaxial small hole test pads is related to the alignment of the coaxial metallized vias, wherein the alignment of the coaxial metallized vias includes the deviation amount and / or offset direction of the coaxial small hole.

[0129] It should be noted that the implementation steps and beneficial effects of S260-S280 can be implemented with reference to the implementation steps and beneficial effects of S160-S180.

[0130] Specifically, based on the above technical solution, in multiple sets of coaxial metallized vias, by setting coaxial vias of different diameters, in each set of coaxial metallized vias where the coaxial via test pads and coaxial via test pads are connected, the difference in diameter between the smallest coaxial via and the largest coaxial via is the deviation of the coaxial via. The above printed circuit board can quickly and accurately obtain the deviation of the coaxial via in the coaxial metallized vias.

[0131] Figure 17 This is a flowchart illustrating another method for manufacturing a printed circuit board according to an embodiment of the present invention. Based on the above technical solution, further definitions are provided for steps S110 and S120, as well as S210 and S220. See also... Figure 17 The method for manufacturing this printed circuit board includes the following steps:

[0132] S310. Drill at least one coaxial large hole in the inner layer of the printed circuit board.

[0133] See Figure 10 At least one coaxial macrohole M0 is drilled in the conductive layer Ls at the coaxial macrohole opening of the printed circuit board.

[0134] S320. Coaxial macroholes are metallized vias by copper plating and electroplating processes. The conductive layer of the coaxial macrohole includes a coaxial macrohole layer, which includes conductive layers at the orifices of the two coaxial macroholes and conductive layers inside the coaxial macroholes.

[0135] See Figure 10 The coaxial macrohole is formed into a metallized via through copper plating and electroplating processes. The conductive layer of the coaxial macrohole M0 includes a coaxial macrohole layer, which includes a conductive layer Ls at the two coaxial macrohole openings and a conductive layer L01 inside the coaxial macrohole.

[0136] S330. Insert a plugging device into a coaxial large hole, wherein the plugging device includes an inner rigid support and a flexible outer layer, the cross-section of the inner rigid support includes a solid part and at least two fan-shaped connecting parts distributed on the edge of the solid part, and a hollow area is provided between the fan-shaped connecting parts.

[0137] See Figure 18 A plugging device 200 is inserted into the coaxial large hole M0. See also... Figure 19 and Figure 20 The plugging device 200 includes an inner rigid support 201 and a flexible outer layer 202. The cross-section of the inner rigid support 201 includes a solid portion 201a and at least two fan-shaped connecting portions 201b distributed along the edge of the solid portion 201a. A hollow area 203 is provided between the fan-shaped connecting portions 201b. For example, the plugging device 200 is a cylinder whose length is equal to the depth of the coaxial large hole M0, and whose diameter is the same as the inner diameter of the coaxial large hole M0. For example, Figure 19and Figure 20 In this design, the plugging device 200 is a cross-shaped cylindrical plugging device. The inner rigid support 201 needs to be relatively hard to provide support, facilitate insertion into the hole, and allow for free control of the insertion depth. Its material must be acid and alkali resistant, non-conductive, non-absorbent of plating solutions, and non-reactive with electroplating solutions; rigid materials such as polytetrafluoroethylene (PTFE) can be used. The flexible outer layer 202 needs to be soft, deformable, acid and alkali resistant, and non-reactive with plating solutions. It is used to completely fill the gap between the plugging device and the hole wall, preventing plating solutions from entering the material. For example, soft materials such as PVC can be used for the flexible outer layer 202.

[0138] S340. Using a plugging device as a mask, wet etching is performed on the conductive layer inside the coaxial macrohole to form a coaxial macrohole with at least two insulating fan-shaped rings.

[0139] See Figure 18 Using the via-plugging device 200 as a mask, the conductive layer L01 inside the coaxial macro-hole is wet-etched to form a coaxial macro-hole M0 with at least two insulating fan-shaped rings. The copper in the area of ​​the coaxial macro-hole M0 not blocked by the via-plugging device 200 (the cutout area 203) is etched away, while the copper in the blocked area is retained. In this way, the wall of the coaxial macro-hole M0 is vertically divided into eight locally metallized areas after etching, and these eight areas can be distinguished in eight directions: up, down, left, right, and along a 45° angle. Figure 21 and Figure 22 In the middle, the coaxial large hole M0 includes 8 insulated sector rings, namely the first sector ring A, the second sector ring B, the third sector ring C, the fourth sector ring D, the fifth sector ring E, the sixth sector ring F, the seventh sector ring G and the eighth sector ring HS120.

[0140] S350. The surface copper of the layer containing the conductive layer of the coaxial large hole is etched to form at least two insulated fan-shaped connection pads, wherein the fan-shaped connection pads are arranged around the fan-shaped ring, and the fan-shaped connection pads are connected to the fan-shaped ring in a one-to-one correspondence. The connection through holes include at least two, and the orthographic projection of the connection through holes on the printed circuit board covers at least a portion of the orthographic projection of the fan-shaped connection pads on the printed circuit board.

[0141] See Figure 18 The first region of the copper surface 301 of the layer containing the conductive layer Ls at the coaxial large hole is etched. The second region of the copper surface 300 is not etched. Since the area in the dashed line is covered by dry film, the copper surface in the area in the dashed line can form at least two insulated fan-shaped connection pads after the dry film is removed. The fan-shaped connection pads are arranged around the fan-shaped ring, and the fan-shaped connection pads are connected to the fan-shaped ring one by one. Figure 21In the middle, the coaxial large hole connection pad 11 includes 8 insulated sector-shaped connection pads, namely the first sector-shaped connection pad 110a, the second sector-shaped connection pad 110b, the third sector-shaped connection pad 110c, the fourth sector-shaped connection pad 110d, the fifth sector-shaped connection pad 110e, the sixth sector-shaped connection pad 110f, the seventh sector-shaped connection pad 110g, and the eighth sector-shaped connection pad 110h.

[0142] See Figure 5 Although the first and second coaxial vias m1 and m2 deviate from the coaxial via M0 in the direction of offset from the axis of the coaxial metallized via towards the sector ring H, they are not yet in contact. Neither the coaxial via test pad nor the coaxial via test pad 16 forms a closed circuit; they are open-circuit connections. The third coaxial via m3 deviates from the coaxial via M0 in the direction of offset from the axis of the coaxial metallized via towards the eighth sector ring H. The third coaxial via m3 contacts the eighth sector ring H of the coaxial via M0, and the connecting via 12 passing through the eighth sector connecting pad 110h is electrically connected to the corresponding eighth coaxial via test pad 150h. This creates a closed circuit between the eighth coaxial via test pad 150h and the coaxial via test pad 16, resulting in a short-circuit connection. In the above example, it can be determined that the direction of the eighth coaxial via test pad 150h relative to the coaxial via is the offset direction of the coaxial via.

[0143] S360. The coaxial large hole is plugged with insulating material.

[0144] It should be noted that the implementation steps and benefits of S360 can be implemented with reference to the implementation steps and benefits of S130.

[0145] S370, The conductive layer of the coaxial large hole is laminated to the side of the printed circuit board away from the conductive layer of the coaxial small hole.

[0146] It should be noted that the implementation steps and beneficial effects of S370 can be implemented with reference to the implementation steps and beneficial effects of S140.

[0147] S380. At least one coaxial via is formed in the structure after lamination, wherein the coaxial via is a metallized via, wherein the conductive layer of the coaxial via includes a coaxial via layer, the coaxial via layer includes a conductive layer at the via opening and a conductive layer inside the via; in a group of coaxial metallized vias, the conductive layers at the via openings of the two coaxial vias corresponding to the coaxial large vias are located on different layers from the coaxial via layers located on the same layer as the printed circuit board.

[0148] It should be noted that the implementation steps and beneficial effects of S380 can be implemented with reference to the implementation steps and beneficial effects of S150.

[0149] For example, see Figure 23 A first coaxial via m1 is formed in the coaxial via layer Ls-q. The first coaxial via m1 is a metallized via, and a coaxial large via M0 is arranged around the first coaxial via m1.

[0150] S390, forming a bottom pad for connecting blind vias, wherein the bottom pad for connecting blind vias and the conductive layer at the orifice of the coaxial via are located on the same layer, and the orthogonal projection of the bottom pad for connecting blind vias on the printed circuit board at least covers the orthogonal projection of the area inside the conductive layer ring of the coaxial via on the printed circuit board.

[0151] It should be noted that the implementation steps and beneficial effects of S390 can be implemented with reference to the implementation steps and beneficial effects of S160.

[0152] See Figure 23 A bottom pad 14 for connecting blind vias is formed on the coaxial via opening layer Ls-q. The bottom pad 14 for connecting blind vias is located on the same layer as the coaxial via opening conductive layer Ls-q. The orthographic projection of the bottom pad 14 for connecting blind vias 13 on the printed circuit board at least covers the orthographic projection of the area inside the conductive layer L01 ring of the coaxial via on the printed circuit board, and is insulated from the connecting through hole 12. The bottom pad 14 for connecting blind vias serves as the electrical signal lead-out structure for the first coaxial via m1.

[0153] S391. The inner and outer layers of a printed circuit board are laminated to form a connecting through hole and a connecting blind hole in the printed circuit, wherein the orthographic projection of the connecting through hole on the printed circuit board covers at least a portion of the orthographic projection of the coaxial large hole connecting pad on the printed circuit board, and the bottom pad of the connecting blind hole is insulated from the connecting through hole.

[0154] It should be noted that the implementation steps and beneficial effects of S391 can be implemented with reference to the implementation steps and beneficial effects of S170.

[0155] See Figure 24 and Figure 25 The inner and outer layers of the printed circuit board are laminated together using a lamination process. This forms connection vias 12 and connection blind vias 13 in the printed circuit. The eight connection vias 12 are positioned one-to-one within the projection of the fan-shaped connection pads onto the printed circuit board, allowing the connection vias 12 to be electrically connected to the coaxial large hole M0 via the coaxial large hole connection pad 11.

[0156] S392. A coaxial small hole test pad and at least two coaxial large hole test pads are formed on the outer layer of a printed circuit board. The coaxial large hole test pads cover at least a portion of the opening of a connecting through hole, and the coaxial small hole test pads cover at least a portion of the opening of a connecting blind hole. The conductivity of the coaxial large hole test pads and the coaxial small hole test pads is related to the alignment of the coaxial metallized vias. The alignment of the coaxial metallized vias includes the deviation amount and / or offset direction of the coaxial small hole.

[0157] See Figure 25 Coaxial small hole test pads 16 and coaxial large hole test pads 15 are formed on the outer layer of the printed circuit board. There are 8 coaxial large hole test pads 15, and each coaxial large hole test pad 15 is electrically connected to a corresponding through hole 12.

[0158] See Figure 5 The coaxial large hole M0 includes eight insulated sector-shaped rings, namely, sector ring A, sector ring B, sector ring C, sector ring D, sector ring E, sector ring F, sector ring G, and sector ring H; the coaxial large hole connection pad 11 includes eight insulated sector-shaped connection pads, namely, sector-shaped connection pad 110a, sector-shaped connection pad 110b, sector-shaped connection pad 110c, sector-shaped connection pad 110d, sector-shaped connection pad 110e, sector-shaped connection pad 110f, sector-shaped connection pad 110g, and sector-shaped connection pad 110h. The sector-shaped connection pads are arranged around the sector-shaped rings, and the sector-shaped connection pads are connected to the sector-shaped rings one-to-one; the connection through holes 12 include eight, and the orthographic projection of the connection through holes 12 on the printed circuit board is located one-to-one within the orthographic projection of the sector-shaped connection pads on the printed circuit board. For example, Figure 8 The coaxial large-hole test pads include eight pads: the first coaxial large-hole test pad 150a, the second coaxial large-hole test pad 150b, the third coaxial large-hole test pad 150c, the fourth coaxial large-hole test pad 150d, the fifth coaxial large-hole test pad 150e, the sixth coaxial large-hole test pad 150f, the seventh coaxial large-hole test pad 150, and the eighth coaxial large-hole test pad 150h. Each coaxial large-hole test pad is electrically connected to a corresponding through-hole 12.

[0159] Specifically, in multiple sets of coaxial metallized vias, the continuity status of the coaxial via test pad and each coaxial via test pad is obtained; in each set of coaxial metallized vias where the coaxial via test pad and the coaxial via test pad are connected, the orientation of the coaxial via test pad relative to the coaxial via test pad is the offset orientation of the coaxial via test pad.

[0160] The present invention also provides a flowchart illustrating a method for testing the alignment of coaxial holes on a printed circuit board.

[0161] S410. Obtain the conductivity status of the coaxial large-hole conductive structure and the coaxial small-hole conductive structure.

[0162] S410. Determine the alignment of the coaxial metallized via based on the conductivity of the coaxial large-hole conductive structure and the coaxial small-hole conductive structure, wherein the alignment of the coaxial metallized via includes the deviation amount and / or offset direction of the coaxial small hole.

[0163] The technical solution provided in this embodiment uses a coaxial large-hole conductive structure as the first electrical signal lead-out structure for the coaxial large-hole, and a coaxial small-hole conductive structure as the second electrical signal lead-out structure for the coaxial small-hole. By detecting the conductivity of the coaxial large-hole conductive structure and the coaxial small-hole conductive structure, the deviation amount and / or offset direction of the coaxial small-hole can be determined. This eliminates the need to detect the alignment of the coaxialized metal vias in the inner layer through a slicing process, achieving non-destructive testing, simplifying the testing process, and thus saving testing costs.

[0164] Figure 26 This is a schematic flowchart illustrating a method for testing the coaxial hole alignment of a printed circuit board according to an embodiment of the present invention. See also... Figure 26 The test method for the coaxial hole alignment of this type of printed circuit board includes the following steps:

[0165] S410. Obtain the continuity status of the coaxial large hole test pad and the coaxial small hole test pad in each group of coaxial metallized vias.

[0166] S420. Based on the conductivity of the coaxial large hole test pad and the coaxial small hole test pad in each group of coaxial metallized vias, determine the alignment of the coaxial metallized vias. The alignment of the coaxial metallized vias includes the deviation amount and / or offset direction of the coaxial small hole.

[0167] against Figures 1-3 The printed circuit board has a coaxial large hole connection pad 11 and a coaxial large hole orifice conductive layer Ls located on the same layer and connected to the coaxial large hole orifice conductive layer Ls. The orthogonal projection of the connecting through hole 12 on the printed circuit board covers the orthogonal projection of the coaxial large hole connection pad 11 on the printed circuit board. The coaxial large hole test pad 15 covers the orifice of the connecting through hole 12. The coaxial large hole connection pad 11 and the connecting through hole 12 serve as the first electrical signal lead-out structure of the coaxial large hole layer of the coaxial large hole M0, which can form a path between the coaxial large hole layer of the coaxial large hole M0 and the coaxial large hole test pad 15.

[0168] The bottom pad 14 of the blind via 13 is located on the same layer as the conductive layer Ls-q at the opening of the coaxial via. The orthographic projection of the bottom pad 14 of the blind via 13 on the printed circuit board at least covers the orthographic projection of the area inside the conductive layer L01 ring of the coaxial via on the printed circuit board, and is insulated from the through hole 12. The test pad 16 of the coaxial via covers the opening of the blind via 13. The bottom pad 14 of the blind via 13 and the blind via 13 serve as the second electrical signal lead-out structure of the coaxial via layer of the coaxial via, which can form a path between the coaxial via and the test pad 16.

[0169] Meanwhile, the coaxial large hole connection pad 11 is located outside the coaxial large hole M0, and the orthographic projection of the connection through hole 12 on the printed circuit board covers at least a portion of the orthographic projection of the coaxial large hole connection pad 11 on the printed circuit board. The connection through hole 12 and the connection blind hole 13 are insulated from each other. Therefore, if the coaxial large hole test pad 15 and the coaxial small hole test pad 16 are conductive, the coaxial small hole and the coaxial large hole M0 must be in contact, which will cause the coaxial large hole test pad 15 and the coaxial small hole test pad 16 to form a circuit and form a short circuit connection.

[0170] The technical solution provided in this embodiment uses a coaxial large-hole connecting pad and a connecting through-hole as the first electrical signal lead-out structure for the coaxial large-hole, which can form a path between the coaxial large-hole and the coaxial large-hole test pad. Similarly, the bottom pad of a connecting blind via and the connecting blind via serve as the second electrical signal lead-out structure for a coaxial small-hole, which can also form a path between the coaxial small-hole and the coaxial small-hole test pad. Simultaneously, the coaxial large-hole connecting pad is located outside the coaxial large-hole, and the orthographic projection of the connecting through-hole on the printed circuit board covers at least a portion of the orthographic projection of the coaxial large-hole connecting pad on the printed circuit board. The connecting through-hole and the connecting blind via are insulated from each other. Only when the coaxial small-hole and the coaxial large-hole are in contact will the coaxial large-hole test pad and the coaxial small-hole test pad form a path, creating a short-circuit connection. Therefore, the printed circuit board provided in this embodiment determines the deviation and / or offset direction of the coaxial via by detecting the continuity of the coaxial large hole test pad and the coaxial small hole test pad. It eliminates the need to detect the alignment of the coaxial metal vias in the inner layer through a slicing process, thus achieving non-destructive testing, simplifying the testing process, and saving testing costs.

[0171] Figure 27 This is a flowchart illustrating another method for testing the coaxial hole alignment of a printed circuit board, provided by an embodiment of the present invention. Figure 27 for Figure 26 The S420 in the document is further specified. See also Figure 27 The test method for the coaxial hole alignment of the printed circuit board includes the following steps:

[0172] S510. Obtain the continuity status of the coaxial large hole test pad and the coaxial small hole test pad in each group of coaxial metallized vias.

[0173] Among the coaxial metallized vias connected to the S520, coaxial small hole test pad, and coaxial large hole test pad, the difference in diameter between the smallest coaxial small hole and the smallest coaxial large hole is the deviation of the coaxial small hole.

[0174] against Figure 3 The printed circuit board shown includes three sets of coaxial metallized vias. The diameter of the first coaxial via m1 is a first diameter d1, the diameter of the second coaxial via m2 is a second diameter d2, and the diameter of the third coaxial via m3 is a third diameter d3. The difference between the diameter of the first coaxial via m1 and the diameter of the coaxial via M0 is a first diameter difference Δd1, the difference between the diameter of the second coaxial via m2 and the diameter of the coaxial via M0 is a second diameter difference Δd2, and the difference between the diameter of the third coaxial via m3 and the diameter of the coaxial via M0 is a third diameter difference Δd3. The first diameter difference > the second diameter difference > the third diameter difference.

[0175] Although the first and second coaxial pinholes m1 and m2 deviate from the coaxial bore M0 in a certain offset direction, they are not yet in contact. The coaxial bore test pad 15 and the coaxial pinhole test pad 16 do not form a closed circuit; they are open-circuit connections. The third coaxial pinhole m3 deviates from the coaxial bore M0 in a certain offset direction, and it is in contact with the coaxial bore M0. The coaxial bore test pad 15 and the coaxial pinhole test pad 16 form a closed circuit; they are short-circuit connections. It should be noted that it can be inferred without doubt that in other embodiments, if a fourth coaxial aperture m4 is provided, the aperture of the fourth coaxial aperture m4 is the fourth aperture d4, and the aperture difference between the fourth coaxial aperture m4 and the coaxial large aperture M0 is the fourth aperture difference Δd4, the aperture difference between the fourth coaxial aperture m4 and the coaxial large aperture M0 is greater than the aperture difference between the third coaxial aperture m3 and the coaxial large aperture M0. Therefore, the offset between the fourth coaxial aperture m4 and the coaxial large aperture M0 causes them to contact each other. The coaxial aperture test pad 16 of the fourth coaxial aperture m4 and the coaxial large aperture test pad 15 of the coaxial large aperture M0 form a path, which is a short-circuit connection. In the above example, the aperture difference between the third coaxial aperture m3 and the coaxial large aperture M0 is the deviation of the coaxial aperture.

[0176] Specifically, in multiple sets of coaxial metallized vias, by setting coaxial vias of different diameters, the difference in diameter between the smallest coaxial via and the largest coaxial via in each set of coaxial metallized vias connected to the coaxial via test pad and the coaxial via test pad is defined as the deviation of the coaxial via. The aforementioned printed circuit board can quickly and accurately obtain the deviation of the coaxial via in the coaxial metallized vias.

[0177] Figure 28 This is a flowchart illustrating another method for testing the coaxial hole alignment of a printed circuit board according to an embodiment of the present invention. Figure 28 for Figure 26 S410 and S420 in the document are further defined. See also Figure 28 The test method for the coaxial hole alignment of the printed circuit board includes the following steps:

[0178] S610. Obtain the continuity status of the coaxial small hole test pad and each coaxial large hole test pad in each group of coaxial metallized vias.

[0179] In each group of coaxial metallized vias connected to the S620 coaxial small hole test pad and the coaxial large hole test pad, the orientation of the coaxial large hole test pad connected to the coaxial small hole test pad relative to the coaxial small hole pad is the offset orientation of the coaxial small hole.

[0180] against Figure 5 The printed circuit board shown includes a coaxial large hole M0 comprising eight insulated sector rings: a first sector ring A, a second sector ring B, a third sector ring C, a fourth sector ring D, a fifth sector ring E, a sixth sector ring F, a seventh sector ring G, and an eighth sector ring H. The coaxial large hole connection pad 11 comprises eight insulated sector connection pads: a first sector connection pad 110a, a second sector connection pad 110b, a third sector connection pad 110c, a fourth sector connection pad 110d, a fifth sector connection pad 110e, a sixth sector connection pad 110f, a seventh sector connection pad 110g, and an eighth sector connection pad 110h. The sector connection pads surround the sector rings, and each sector connection pad is connected to a corresponding sector ring. There are eight connecting through holes 12, and each of the eight through holes 12 is located within the orthographic projection of the sector connection pads on the printed circuit board. For example, Figure 8 The coaxial large-hole test pads include eight pads: the first coaxial large-hole test pad 150a, the second coaxial large-hole test pad 150b, the third coaxial large-hole test pad 150c, the fourth coaxial large-hole test pad 150d, the fifth coaxial large-hole test pad 150e, the sixth coaxial large-hole test pad 150f, the seventh coaxial large-hole test pad 150, and the eighth coaxial large-hole test pad 150h. Each coaxial large-hole test pad is electrically connected to a corresponding through-hole 12.

[0181] In this example, although the first and second coaxial vias m1 and m2 deviate from the coaxial via M0 in the direction of offset from the axis of the coaxial metallized via towards the sector ring H, the coaxial vias m1 and m2 are not in contact with each other. Neither the coaxial via test pad nor the coaxial via test pad 16 forms a closed circuit; they are open-circuit connections. The third coaxial via m3 deviates from the coaxial via M0 in the direction of offset from the axis of the coaxial metallized via towards the eighth sector ring H. The third coaxial via m3 contacts the eighth sector ring H of the coaxial via M0, and the connecting via 12 passing through the eighth sector connecting pad 110h is electrically connected to the corresponding eighth coaxial via test pad 150h. This makes the eighth coaxial via test pad 150h and the coaxial via test pad 16 form a closed circuit, which is a short-circuit connection. In the above example, it can be determined that the direction of the eighth coaxial via test pad 150h relative to the coaxial via is the offset direction of the coaxial via.

[0182] Specifically, in multiple sets of coaxial metallized vias, the continuity status of the coaxial via test pad and each coaxial via test pad is obtained. In each set of coaxial metallized vias where the coaxial via test pads and via test pads are connected, the orientation of the coaxial via test pad connected to the coaxial via test pad relative to the coaxial via test pad is the offset orientation of the coaxial via test pad. The above-mentioned printed circuit board can quickly and accurately obtain the offset orientation of the coaxial via test pad.

[0183] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0184] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A printed circuit board, the printed circuit board comprising an inner layer and an outer layer, characterized in that, include: The inner layer of the printed circuit board includes at least one set of coaxial metallized vias, wherein each set of coaxial metallized vias includes a coaxial large via and a coaxial small via, and an insulating material is disposed between the coaxial large via and the coaxial small via. The conductive layer of the coaxial large via includes a coaxial large via layer, and the conductive layer of the coaxial small via includes a coaxial small via layer. The coaxial large via layer includes a conductive layer at the opening of the coaxial large via and a conductive layer inside the coaxial large via. The coaxial small via layer includes a conductive layer at the opening of the coaxial small via and a conductive layer inside the coaxial small via. In a set of coaxial metallized vias, the conductive layer at the opening of the coaxial large via is located on a different layer from the conductive layer at the opening of the coaxial small via located on the same layer of the printed circuit board. The printed circuit board further includes a coaxial large-hole conductive structure and a coaxial small-hole conductive structure. The coaxial large-hole conductive structure is connected to the conductive layer at the orifice of the coaxial large-hole, and the coaxial small-hole conductive structure is connected to the conductive layer at the orifice of the coaxial small-hole. The conductivity of the coaxial large-hole conductive structure and the coaxial small-hole conductive structure is related to the alignment of the coaxial metallized via. The alignment of the coaxial metallized via includes the deviation amount and / or offset direction of the coaxial small-hole. When determining the alignment of the coaxial metallized via, the deviation amount of the coaxial small-hole is determined by the difference in aperture between the coaxial small-hole and the coaxial large-hole forming the path, and the offset direction of the coaxial small-hole is determined by the orientation of the test pad of the coaxial large-hole forming the path relative to the coaxial small-hole.

2. The printed circuit board according to claim 1, characterized in that, The printed circuit board further includes a coaxial large-hole connection pad, a connection through-hole, and a connection blind via; the coaxial large-hole connection pad and the conductive layer at the opening of the coaxial large-hole are located on the same layer, located outside the coaxial large-hole, and connected to the conductive layer at the opening of the coaxial large-hole; the orthographic projection of the connection through-hole on the printed circuit board covers at least a portion of the orthographic projection of the coaxial large-hole connection pad on the printed circuit board; the bottom pad of the connection blind via is located on the same layer as the conductive layer at the opening of the coaxial small-hole, and the orthographic projection of the bottom pad of the connection blind via on the printed circuit board at least covers the orthographic projection of the inner region of the conductive layer ring inside the coaxial large-hole on the printed circuit board, and is insulated from the connection through-hole; The outer layer of the printed circuit board includes a coaxial small hole test pad and a coaxial large hole test pad. The coaxial large hole test pad covers at least a portion of the opening of the connecting through hole, and the coaxial small hole test pad covers at least a portion of the opening of the connecting blind hole. The coaxial large-hole connection pad, the connection through hole, and the coaxial large-hole test pad constitute the coaxial large-hole conductive structure; the connection blind hole and the coaxial small-hole test pad constitute the coaxial small-hole conductive structure. The continuity between the coaxial large-hole test pad and the coaxial small-hole test pad is related to the alignment of the coaxial metallized via, wherein the alignment of the coaxial metallized via includes the deviation amount and / or offset direction of the coaxial small hole.

3. The printed circuit board according to claim 1, characterized in that, It includes n sets of coaxial metallized vias, wherein the value of n includes integers greater than or equal to 1; The diameters of the n coaxial holes include: first diameter, second diameter, ..., nth diameter; The diameter differences between the n coaxial small holes and the coaxial large holes include: first diameter difference, second diameter difference, ..., nth diameter difference, where, first diameter difference > second diameter difference > ... > nth diameter difference; The diameter of the coaxial small hole in the i-th group of coaxial metallized vias is the i-th hole diameter, and the difference between the diameter of the i-th hole and the coaxial large hole is the i-th hole diameter difference. The value of i includes integers greater than or equal to 1 and less than or equal to n.

4. The printed circuit board according to claim 2, characterized in that, The conductive layer inside the coaxial large hole includes at least two insulating sector rings. The coaxial large hole connection pad includes at least two insulated sector-shaped connection pads, which are arranged around the sector-shaped ring and are connected in a one-to-one correspondence with the sector-shaped ring. The connection vias include at least two, and the connection vias, in their orthographic projection on the printed circuit board, cover at least a portion of the orthographic projection of the fan-shaped connection pads on the printed circuit board. The coaxial large-hole test pads include at least two, and each coaxial large-hole test pad corresponds to at least a portion of the opening of the connecting through hole.

5. The printed circuit board according to claim 1, characterized in that, In each group of coaxial metallized vias, the number of spacing layers between the coaxial small via opening conductive layer and the coaxial large via opening conductive layer located on the same side of the printed circuit board is less than the number of spacing layers between the coaxial small via opening conductive layer and the outer layer.

6. A method for manufacturing a printed circuit board, characterized in that, include: At least one coaxial macrohole is formed in the inner layer of the printed circuit board, wherein the coaxial macrohole is a metallized via, and the conductive layer of the coaxial macrohole includes a coaxial macrohole layer, which includes a conductive layer at the orifice of the two coaxial macroholes and a conductive layer inside the coaxial macrohole. The conductive layer at the coaxial large hole opening is laminated to the side of the printed circuit board that is away from the coaxial small hole opening. At least one coaxial via is formed in the structure after lamination, wherein the coaxial via is a metallized via, the conductive layer of the coaxial via includes a coaxial via layer, the coaxial via layer includes a conductive layer at the via opening and a conductive layer inside the via; in a group of coaxial metallized vias, the conductive layer at the via opening of the coaxial via is located on a different layer from the coaxial via layer located on the same layer as the printed circuit board; It also includes forming a coaxial macro-hole conductive structure and a coaxial micro-hole conductive structure. The coaxial macro-hole conductive structure is connected to the conductive layer at the orifice of the coaxial macro-hole, and the coaxial micro-hole conductive structure is connected to the conductive layer at the orifice of the coaxial micro-hole. The conductivity of the coaxial macro-hole conductive structure and the coaxial micro-hole conductive structure is related to the alignment of the coaxial metallized via. The alignment of the coaxial metallized via includes the deviation amount and / or offset direction of the coaxial micro-hole. When determining the alignment of coaxial metallized vias, the deviation of the coaxial via is determined by the difference in diameter between the coaxial via and the coaxial through hole forming the path, and the offset direction of the coaxial via is determined by the orientation of the test pad of the coaxial through hole forming the path relative to the coaxial via.

7. The method for manufacturing a printed circuit board according to claim 6, characterized in that, The coaxial large-hole conductive structure includes a coaxial large-hole connection pad, a connection through hole, and a coaxial large-hole test pad; the coaxial small-hole conductive structure includes a connection blind hole and a coaxial small-hole test pad. The process of laminating the conductive layer at the coaxial large hole opening on the side facing away from the printed circuit board and before reaching the conductive layer at the coaxial small hole opening includes: A coaxial macrohole connection pad is formed, wherein the coaxial macrohole connection pad and the coaxial macrohole orifice conductive layer are located in the same layer, located outside the coaxial macrohole and connected to the coaxial macrohole orifice conductive layer; The coaxial large hole is plugged with insulating material; At least one coaxial via is formed in the structure after lamination, wherein the coaxial via is a metallized via, the conductive layer of the coaxial via includes a coaxial via layer, the coaxial via layer includes a conductive layer at the via opening and a conductive layer inside the via; in a group of coaxial metallized vias, the conductive layer at the via opening of the coaxial via is located on a different layer from the coaxial via layer located on the same layer as the printed circuit board; After the laminated structure forms at least one coaxial aperture, it also includes: A bottom pad for connecting blind vias is formed, wherein the bottom pad for connecting blind vias and the conductive layer at the orifice of the coaxial small via are located on the same layer, and the orthogonal projection of the bottom pad for connecting blind vias on the printed circuit board at least covers the orthogonal projection of the inner region of the conductive layer ring inside the coaxial large via on the printed circuit board. The inner and outer layers of the printed circuit board are laminated to form a connecting through hole and a connecting blind hole in the printed circuit board. The orthographic projection of the connecting through hole on the printed circuit board covers at least a portion of the orthographic projection of the coaxial large hole connecting pad on the printed circuit board. The bottom pad of the connecting blind hole is insulated from the connecting through hole. Coaxial small hole test pads and coaxial large hole test pads are formed on the outer layer of the printed circuit board. The coaxial large hole test pads cover at least a portion of the opening of the connecting via. The continuity between the coaxial large hole test pads and the coaxial small hole test pads is related to the alignment of the coaxial metallized vias. The alignment of the coaxial metallized vias includes the deviation amount and / or offset direction of the coaxial small hole.

8. The method for manufacturing a printed circuit board according to claim 6, characterized in that, The formation of at least one coaxial aperture in the structure after lamination includes: Drill n coaxial holes of different diameters into the laminated structure; The diameters of the n coaxial pinholes include: first diameter, second diameter, ..., nth diameter, where n is an integer greater than or equal to 1; the diameter differences between the n coaxial pinholes and the coaxial large hole include: first diameter difference, second diameter difference, ..., nth diameter difference, where first diameter difference > second diameter difference > ... > nth diameter difference; the diameter of the coaxial pinhole in the i-th group of coaxial metallized vias is the i-th diameter, and the diameter difference between the i-th diameter coaxial pinhole and the coaxial large hole is the i-th diameter difference, where i is an integer greater than or equal to 1 and less than or equal to n.

9. The method for manufacturing a printed circuit board according to claim 6, characterized in that, Forming at least one coaxial macrohole in the inner layer of a printed circuit board includes: Drill at least one coaxial large hole in the inner layer of the printed circuit board. The coaxial macrohole is formed into a metallized via through copper plating and electroplating processes. The conductive layer of the coaxial macrohole includes a coaxial macrohole layer, which includes conductive layers at the orifices of the two coaxial macroholes and a conductive layer inside the coaxial macrohole. A plugging device is inserted into the coaxial large hole, wherein the plugging device includes an inner rigid support and a flexible outer layer, the cross-section of the inner rigid support includes a solid part and at least two fan-shaped connecting parts distributed on the edge of the solid part, and a hollow area is provided between the fan-shaped connecting parts; Using the via plugging device as a mask, the conductive layer inside the coaxial macrohole is wet-etched to form a coaxial macrohole with at least two insulating fan-shaped rings. Forming coaxial large-hole connection pads includes: The surface copper of the layer containing the conductive layer of the coaxial large hole is etched to form at least two insulated fan-shaped connection pads, wherein the fan-shaped connection pads are arranged around the fan-shaped ring and are connected to the fan-shaped ring in a one-to-one correspondence. There are at least two connection vias, and the connection vias cover at least a portion of the fan-shaped connection pads located on the orthographic projection of the printed circuit board on the printed circuit board.

10. The method for preparing a printed circuit board according to claim 6, characterized in that, In each group of coaxial metallized vias, the conductive layer at the opening of the large coaxial via is laminated to the side facing away from the printed circuit board, and then extends to the conductive layer at the opening of the small coaxial via, including: At least one layer of conductive layer is laminated to the side of the coaxial large hole opening away from the printed circuit board to the coaxial small hole opening conductive layer.

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