Imaging circuit and imaging device

Abstract

[Problem] To provide an imaging circuit and an imaging device capable of switching output types while reducing circuit scale. [Solution] An imaging circuit according to the present disclosure includes: a photoelectric conversion element that converts incident light into a photocurrent; a first transistor that converts the photocurrent into a voltage signal; a second transistor that amplifies the voltage signal; a third transistor that controls the current to be supplied to the first transistor; and a fourth transistor connected to the second transistor.

Description

Technical Field

[0001] The present disclosure relates to an imaging circuit and an imaging device. Background Art

[0002] In typical imaging devices, synchronous imaging elements are often used to capture image data (frames) at the timing of a synchronization signal. However, synchronous imaging elements can only obtain image data during the cycle time of the synchronization signal (for example, every 1 / 60 second) and are not suitable for applications that require high-speed image data acquisition. Therefore, asynchronous imaging elements have been proposed. The pixels of asynchronous imaging elements have event detection circuits that can detect events in which the amount of light exceeds a threshold value for each address in real time.

[0003] [Citation List]

[0004] [Patent Document]

[0005] [Patent Document 1]

[0006] JP 2016-533140 T Summary of the Invention

[0007] [Technical Issues]

[0008] Asynchronous solid-state imaging elements can generate and output data at higher speeds than synchronous solid-state imaging elements. For example, their use can improve safety in traffic environments by enabling faster image recognition of people and obstacles. However, there is a problem: providing both an address event detection circuit and a synchronous detection circuit in each pixel can increase the mounting area.

[0009] The present disclosure provides an imaging circuit and an imaging device capable of switching output types while reducing the circuit scale.

[0010] [Solution to the problem]

[0011] Aspects of an imaging circuit according to the present invention may include: a photoelectric conversion element that converts incident light into photocurrent; a first transistor that converts the photocurrent into a voltage signal; a second transistor that amplifies the voltage signal; a third transistor that controls the current to be supplied to the first transistor; and a fourth transistor that is connected to the second transistor.

[0012] The imaging circuit may further include a fifth transistor connected between a first node and a first reference potential, the first node coupling the control electrode of the first transistor to the first terminal of the second transistor.

[0013] A buffer, a subtractor, and a quantizer may be further connected to the stage subsequent to the first node.

[0014] It may further include a control unit configured to enable switching between a first mode and a second mode, wherein in the first mode, the third transistor and the fourth transistor are turned on and the fifth transistor is used as a current source, and in the second mode, a pulse voltage is applied to the control electrode of the third transistor, the fourth transistor is turned on and the fifth transistor is turned off.

[0015] The control unit may be configured to implement switching between the first mode and the second mode according to the measured amount of light.

[0016] A sixth transistor may further be included, the sixth transistor being connected between the photoelectric conversion element and a second node, the second node coupling the first terminal of the first transistor to the control electrode of the second transistor.

[0017] The first transistor and the second transistor may be included in a multi-stage logarithmic conversion circuit.

[0018] The circuit may further include a sixth transistor connected between a third node and a second reference potential, wherein the third node is coupled to the second terminal of the second transistor and the second terminal of the fourth transistor.

[0019] It may also include a control unit configured to enable switching between a first mode and a second mode, wherein in the first mode, the third transistor is turned on, the fourth transistor is turned off, the fifth transistor is used as a current source, and the sixth transistor is turned on, and in the second mode, a pulse voltage is applied to the control electrode of the third transistor, the fourth transistor is turned on, the fifth transistor is turned off, and the sixth transistor is turned off.

[0020] It may further include a first switch and a second switch, the front stage of the first switch is connected to the control electrode of the first transistor and the first terminal of the second transistor, the front stage of the second switch is connected to the second terminal of the second transistor and the first terminal of the fourth transistor, and the fourth transistor may be connected between the second transistor and the second reference potential.

[0021] A buffer, a subtractor, and a quantizer may be connected to the stage following the first switch, and an analog-to-digital converter may be connected to the stage following the second switch.

[0022] It may also include a control unit configured to enable switching between a first mode and a second mode, wherein in the first mode, the third transistor and the fourth transistor are turned on, the fifth transistor is used as a current source, the first switch is turned on and the second switch is turned off, and in the second mode, a pulse voltage is applied to the control electrode of the third transistor, the fourth transistor is turned on, the fifth transistor is turned off, the first switch is turned off and the second switch is turned on.

[0023] The photoelectric conversion element and the fifth transistor may be mounted on different chips or substrates.

[0024] An imaging device according to an aspect of the present disclosure may include: an analog-to-digital converter; and a plurality of imaging circuits, wherein in each imaging circuit, a first terminal of the fourth transistor may be connected to the analog-to-digital converter via a signal line.

[0025] A third switch, a fourth switch, and a current source may be further included. The third switch may be connected between the signal line and the second reference potential, and the fourth switch and the current source may be connected in series between the signal line and the second reference potential.

[0026] It may also include a control unit configured to enable switching between a first mode and a second mode, wherein in the first mode, the third transistor and the fourth transistor are turned on, the fifth transistor is used as a current source, the third switch is turned on, and the fourth switch is turned off, and in the second mode, a pulse voltage is applied to the control electrode of the third transistor, the fourth transistor is turned on, the fifth transistor is turned off, the third switch is turned on, and the fourth switch is turned off.

[0027] The control unit may be configured to implement switching between the first mode and the second mode according to the measured amount of light.

[0028] The floating diffusion layers of at least two imaging circuits may be connected via a seventh transistor.

[0029] The second terminals of the first transistors in at least two imaging circuits may be connected via an eighth transistor.

[0030] The photoelectric conversion elements, the first transistor, the second transistor, the third transistor, and the fourth transistor of the plurality of imaging circuits may be mounted on the same chip or substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a block diagram showing a configuration example of an imaging device according to the present disclosure.

[0032] Figure 2 is a diagram illustrating an example of a laminated structure of an imaging element.

[0033] Figure 3 is a plan view illustrating an example of a light receiving chip according to the present disclosure.

[0034] Figure 4 is a plan view showing an example of a detection chip according to the present disclosure.

[0035] Figure 5 is a plan view showing an example of an address event detection unit.

[0036] Figure 6 is a block diagram showing a configuration example of an address event detection circuit.

[0037] Figure 7is a circuit diagram illustrating an example of an address event detection circuit.

[0038] Figure 8 is a circuit diagram illustrating an example of an imaging circuit according to the present disclosure.

[0039] Figure 9 It shows Figure 8 Table of example circuit setups.

[0040] Figure 10 is a circuit diagram showing an example of an imaging circuit according to a first modification.

[0041] Figure 11 It shows Figure 10 Table of example circuit setups.

[0042] Figure 12 is a flowchart illustrating an example of a process for switching between logarithmic reading and linear reading.

[0043] Figure 13 is a flowchart illustrating an example of a process for switching between logarithmic reading and linear reading.

[0044] Figure 14 is a circuit diagram illustrating an example of an imaging circuit according to a second modification.

[0045] Figure 15 is a circuit diagram illustrating an example of an imaging circuit according to a third modification.

[0046] Figure 16 is a circuit diagram illustrating an example of an imaging circuit according to a fourth modification.

[0047] Figure 17 is a circuit diagram illustrating an example of an imaging circuit according to a fifth modification.

[0048] Figure 18 is a circuit diagram illustrating an example of an imaging circuit according to a sixth modification.

[0049] Figure 19 is a circuit diagram illustrating an example of an imaging circuit according to a seventh modification.

[0050] Figure 20 is a circuit diagram illustrating an example of an imaging circuit according to an eighth modification.

[0051] Figure 21 is a circuit diagram illustrating an example of an imaging circuit according to a ninth modification.

[0052] Figure 22 is a circuit diagram illustrating an example of an imaging element according to a tenth modification.

[0053] Figure 23 is a circuit diagram illustrating an example of an imaging circuit according to an eleventh modification.

[0054] Figure 24 It shows Figure 23 Table of example circuit setups.

[0055] Figure 25 is a circuit diagram illustrating an example of an imaging circuit according to a twelfth modification.

[0056] Figure 26 is a circuit diagram illustrating an example of an imaging circuit according to a thirteenth modification.

[0057] Figure 27 is a circuit diagram illustrating an example of an imaging circuit according to a fourteenth modification.

[0058] Figure 28 is a circuit diagram illustrating an example of an imaging circuit according to a fifteenth modification.

[0059] Figure 29 is a diagram showing a first embodiment of an imaging circuit.

[0060] Figure 30 is a diagram showing a second embodiment of an imaging circuit.

[0061] Figure 31 is a diagram showing a third embodiment of an imaging circuit.

[0062] Figure 32 is a diagram showing a fourth embodiment of an imaging circuit.

[0063] Figure 33 is a diagram showing a fifth embodiment of an imaging circuit.

[0064] Figure 34 is a diagram showing a sixth embodiment of an imaging circuit.

[0065] Figure 35 A diagram showing a seventh embodiment of the imaging circuit.

[0066] Figure 36 A diagram showing an eighth embodiment of the imaging circuit.

[0067] Figure 37 is a diagram showing a first embodiment of a detection circuit.

[0068] Figure 38 is a diagram showing a second embodiment of a detection circuit.

[0069] Figure 39is a diagram showing a third embodiment of a detection circuit.

[0070] Figure 40 is a diagram showing a fourth embodiment of a detection circuit.

[0071] Figure 41 is a diagram showing a fifth embodiment of a detection circuit.

[0072] Figure 42 is a diagram showing a sixth embodiment of a detection circuit.

[0073] Figure 43 is a block diagram showing a schematic configuration example of a vehicle control system.

[0074] Figure 44 : is a diagram showing an example of positions where the imaging unit and the vehicle exterior information detection unit are installed. DETAILED DESCRIPTION

[0075] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, in this specification and the accompanying drawings, components having substantially the same functional configuration will be denoted by the same reference numerals, and thus repeated description thereof will be omitted.

[0076] [Configuration Example of Imaging Device]

[0077] Figure 1 is a block diagram illustrating a configuration example of an imaging device according to the present disclosure. Figure 1 The imaging device 100 in FIG. 1 includes an imaging lens 110, an imaging element 200, a storage unit 120, and a control unit 130. The imaging device 100 is, for example, a camera mounted in a wearable device or a vehicle-mounted camera.

[0078] The imaging lens 110 collects incident light onto the imaging element 200 .

[0079] The imaging element 200 includes a plurality of pixels. Each of the plurality of pixels generates an address event when the absolute value of the brightness change exceeds a threshold value. The address event includes, for example, an ON event and an OFF event. Here, the ON event indicates that the detected brightness has exceeded a first threshold value. The OFF event indicates that the detected brightness has dropped below a second threshold value. For example, a value greater than a reference value can be used as the first threshold value. In addition, a value less than the reference value can be used as the second threshold value. However, the method of setting the first threshold value and the second threshold value is not limited.

[0080] Each pixel of the imaging element 200 outputs a detection signal indicating the result of detecting an address event. Each detection signal includes, for example, an ON event detection signal VCH indicating the presence or absence of an ON event and an OFF event detection signal VCL indicating the presence or absence of an OFF event. Note that the pixels in the imaging element 200 can detect both ON and OFF events as targets, or can detect either of these events as targets.

[0081] The imaging element 200 can generate image data from the detection signal. In addition, the imaging element 200 performs predetermined processing such as recognition processing on the image data. Then, the imaging element 200 outputs the processed data to the storage unit 120 via the signal line 209.

[0082] The storage unit 120 is adapted to record data output from the imaging element 200. The control unit 130 controls the imaging element 200 and enables capturing of image data at a desired timing.

[0083] [Configuration Example of Imaging Element]

[0084] Figure 2 An example of a laminated structure of the imaging element 200 is shown. Figure 2 The imaging element 200 in FIG. 1 includes a detection chip 202 and a light receiving chip 201 stacked on the detection chip 202. Electrical connection can be established between these chips via a connection portion such as a via. The electrical connection is not limited to vias and can be achieved by Cu-Cu bonding or bumps.

[0085] Figure 3 is a plan view illustrating an example of a light receiving chip 201. Light receiving chip 201 is provided with a light receiving unit 220. Multiple photodiodes 221 are arranged in a two-dimensional grid in light receiving unit 220. Photodiodes 221 are configured to perform photoelectric conversion on incident light to generate photocurrent. A pixel address, including a row address and a column address, is assigned to each of these photodiodes 221. Therefore, various controls can be performed by specifying a row address, a column address, or a pixel address.

[0086] Figure 4 is a plan view showing an example of the detection chip 202 . Figure 4 The detection chip 202 includes a signal processing circuit 230 , a row driving circuit 251 , a column driving circuit 252 , an address holding unit 253 and an address event detection unit 260 .

[0087] The address event detection unit 260 generates an address event when the absolute value of the luminance change of each of the plurality of photodiodes 221 (pixels) exceeds a predetermined threshold. The address event detection unit 260 then generates a detection signal indicating the result of detecting the address event for each pixel. The address event detection unit 260 then inputs the detection signal based on the enable signal to the signal processing circuit 230.

[0088] Here, the enable signal is a signal that specifies whether to activate the output of a detection signal for each pixel. When the enable signal has a waveform that activates the output, the detection signal is output from the corresponding pixel. On the other hand, when the enable signal has a waveform that deactivates the output, the detection signal is not output from the corresponding pixel.

[0089] The row driving circuit 251 is used to select a row address and output a detection signal corresponding to the row address to the address event detection unit 260 .

[0090] The column driving circuit 252 is configured to select a column address and cause a detection signal corresponding to the column address to be output to the address event detection unit 260 .

[0091] The address holding unit 253 is configured to hold the pixel address of the defective pixel where the abnormality occurs.

[0092] The signal processing circuit 230 is adapted to perform predetermined signal processing on the detection signal from the address event detection unit 260. The signal processing circuit 230 arranges the detection signal as pixel signals in a two-dimensional grid shape and acquires image data. The signal processing circuit 230 then performs signal processing such as image recognition processing on the image data.

[0093] Furthermore, the signal processing circuit 230 may have a function of obtaining the frequency of address event detection for each pixel and identifying defective pixels based on the statistics of this detection frequency. In this case, the signal processing circuit 230 stores the pixel address of the defective pixel in the address holding unit 253. Furthermore, the signal processing circuit 230 generates an enable signal for each pixel and provides the enable signal to the address event detection unit 260. As the enable signal corresponding to the defective pixel, an enable signal having a waveform that disables the output is output.

[0094] Figure 5 is an example of a plan view of the address event detection unit 260. Figure 5 In the address event detection unit 260, a plurality of address event detection circuits 300 are arranged in a two-dimensional grid shape. A pixel address is assigned to each address event detection circuit 300. In addition, the address event detection circuit 300 is connected to the photodiode 221 having the same address or a corresponding address.

[0095] The address event detection circuit 300 is configured to quantize a voltage signal according to a photocurrent from the corresponding photodiode 221. Furthermore, the address event detection circuit 300 is configured to output a voltage signal quantized according to the enable signal as a detection signal.

[0096] [Configuration Example of Address Event Detection Circuit]

[0097] Figure 6 is a block diagram showing a configuration example of each address event detection circuit 300 . Figure 6 The address event detection circuit 300 in FIG. 3 includes a current-voltage conversion circuit 310 , a buffer 320 , a subtractor 430 , a quantizer 340 , a transfer circuit 350 , and N-type transistors 361 and 362 .

[0098] The current-voltage conversion circuit 310 is configured to convert the current signal from the corresponding photodiode 221 into a voltage signal. In addition, the current-voltage conversion circuit 310 provides the voltage signal to the buffer 320.

[0099] The buffer 320 is used to output the input voltage signal to the subtractor 430. The use of the buffer 320 can increase the power of driving the circuit in the subsequent stage. In addition, the buffer 320 can ensure isolation of noise accompanying the switching operation of the subsequent stage.

[0100] The subtractor 430 is configured to obtain the variation of the correction signal by performing a subtraction process, and supplies the variation as a differential signal to the quantizer 340 of the subsequent stage.

[0101] Quantizer 340 is configured to compare the differential signal with a predetermined threshold value and convert the analog differential signal into a digital detection signal. This process corresponds to quantization. For example, quantizer 340 compares the differential signal with a first threshold value and a second threshold value and provides the comparison result as a 2-bit detection signal to transmission circuit 350. Note that quantizer 340 is an example of a comparator.

[0102] The N-type transistors 361 and 362 can turn on and off the power to be supplied to the current-voltage conversion circuit 310, the buffer 320, the subtractor 430, the quantizer 340, and the transmission circuit 350 according to the enable signal. As these N-type transistors, metal oxide semiconductor (MOS) transistors can be used. The N-type transistors 361 and 362 are connected in series between the power supply terminal and the power supply line 363, and the enable signals ENx and ENy provided from the signal processing circuit 230 are input to their gates. The power supply line 363 is connected to each power supply terminal of the current-voltage conversion circuit 310, the buffer 320, the subtractor 430, and the quantizer 340. Note that the N-type transistors 361 and 362 are examples of transistors.

[0103] Here, the enable signals ENx and ENy are signals for providing instructions on whether to activate the output of the pixel with the pixel address (x, y). For example, when the output is to be activated, both the enable signals ENx and ENy are set to a high level. In addition, when the output is to be deactivated, at least one of the enable signals ENx and ENy is set to a low level.

[0104] The transmission circuit 350 is configured to transmit the detection signal to the signal processing circuit 230 according to the column driving signal from the column driving circuit 252 .

[0105] Figure 7 1 is a circuit diagram showing an example of a general address event detection circuit. Here, the address event circuit is an example of an imaging circuit. Figure 7 In the figure, it is shown in detail with Figure 6 The photodiode 221, the current-voltage conversion circuit 310, the buffer 320, the subtractor 430, the quantizer 340 and the transmission circuit 350 correspond to the parts.

[0106] Figure 7 The address event detection circuit in includes a photodiode PD, a current-voltage conversion circuit 2, a buffer 3, a subtractor 4, a quantizer 5 and a logic circuit 6.

[0107] The anode of the photodiode PD is grounded. As the ground, for example, a reference potential of the circuit or a reference potential of the substrate can be used. However, the type of reference potential used as the ground is not limited.

[0108] Figure 7 The current-voltage conversion circuit 2 in FIG. 1 is a detection circuit that performs general logarithmic output. The current-voltage conversion circuit 2 includes a transistor 20, a transistor 21, and a transistor 23. Transistors 20 and 21 can be, for example, NMOS transistors. Furthermore, transistor 23 can be, for example, a PMOS transistor. A bias voltage PBias is applied to the gate terminal of transistor 23. Depending on the value of bias voltage PBias, transistor 23 can function as a current source transistor.

[0109] The source of transistor 20 is connected to the cathode of photodiode PD. The drain of transistor 20 is connected to a power supply potential. The gate of transistor 20 is connected to the source of transistor 21. Furthermore, the source of transistor 23 is connected to power supply potential VDD. Furthermore, the drain of transistor 23 is connected to the gate of transistor 20 and the source of transistor 21. Furthermore, the gate of transistor 21 is connected to the source of transistor 20 and the cathode of photodiode PD. The drain of transistor 21 is grounded.

[0110] The current-voltage conversion circuit 2 converts the current flowing through the photodiode PD into a voltage value which is outputted logarithmically. Figure 7 The current-voltage conversion circuit 2 in FIG. 1 is a source-grounded logarithmic conversion circuit, but this configuration is merely an example. Therefore, a circuit having another configuration for converting current into voltage may be used. For example, a diode-type circuit, a gate-grounded circuit, or a gain-boosted (multi-stage) logarithmic conversion circuit may be used as the current-voltage conversion circuit 2.

[0111] The buffer 3 includes a transistor 30 and a current source S1. As the transistor 30, an NMOS transistor can be used, for example. As the current source S1, a PMOS transistor can be used, for example. The source of the transistor 30 is connected to the power supply potential. Moreover, the gate of the transistor 30 is connected to the current-voltage conversion circuit 2 (at Figure 7 In the example of FIG, a node between the drain of transistor 23 and the source of transistor 21 . A current source S1 is connected between the drain of transistor 30 and ground.

[0112] The buffer 3 is a source follower circuit that performs impedance conversion. By using a source follower circuit, high input impedance and low output impedance can be maintained regardless of the amplification of the voltage signal output from the current-voltage conversion circuit 2.

[0113] The subtractor 4 includes a capacitor C1, a capacitor C2, a transistor 31, a transistor 32, and a current source S2. For example, PMOS transistors can be used as the transistor 31 and the transistor 32. For example, an NMOS transistor can be used as the current source S2.

[0114] The source of transistor 32 is connected to a power supply potential. Current source S2 is connected between the drain of transistor 32 and ground. Furthermore, capacitor C1 and capacitor C2 are connected in series between a node coupling the drain of transistor 32 to current source S2 and a node coupling the drain of transistor 30 to current source S1. The gate of transistor 32 and the source of transistor 31 are both connected to the node coupling capacitor C1 to capacitor C2. The drain of transistor 31 is connected to a node coupling the drain of transistor 32 to current source S2.

[0115] Transistor 32 and current source S2 form an inverter, wherein the gate of transistor 32 serves as the input side and the node where the drain of transistor 32 is coupled to current source S2 serves as the output side. The inverter is configured to invert the input voltage and output the inverted input voltage. Capacitor C2 is connected in parallel with the inverter. The gate voltage of transistor 31 is controlled by the row drive signal. Therefore, the source and drain of transistor 31 are turned on and off according to the row drive signal.

[0116] If a conduction state is established between the source and drain of the transistor 31, the voltage signal V init is input to the buffer 3 side (input side) of capacitor C1, the opposite side of capacitor C1 serves as a virtual ground terminal. Assuming that the potential of the virtual ground terminal is zero and the electrostatic capacitance of capacitor C1 is c1, the potential Q accumulated in capacitor C1 is init It is expressed by the following equation (1).

[0117] Q init =c1×V init (1)

[0118] On the other hand, since both ends of the capacitor C2 are short-circuited at this time, the accumulated charge of the capacitor C2 is substantially zero.

[0119] Next, the operation when a non-conductive state is established between the source and drain of the transistor 31 will be described. In this case, the voltage on the buffer 3 side (input side) of the capacitor C1 changes to V after In this case, the charge Q accumulated in capacitor C1 is after It is expressed by the following equation (2).

[0120] Q after =c1×V after (2)

[0121] On the other hand, assuming the output voltage is V out And the electrostatic capacitance of the capacitor C2 is c2, and the charge Q2 accumulated in the capacitor C2 at this time is expressed by the following equation (3).

[0122] Q2=-c2×V out (3)

[0123] Since the total amount of charge in the capacitor C1 and the capacitor C2 does not change regardless of the conduction state between the source and the drain of the transistor 31 , the following equation (4) is established.

[0124] Q init =Q after +Q2 (4)

[0125] If equations (1) to (3) are substituted into equation (4), the following equation (5) can be obtained.

[0126]

[0127] Equation (5) represents the subtraction operation of the voltage signal. The gain of the subtraction operation is c1 / c2. In order to maximize the gain, a design can be adopted to obtain a large c1 value and a small c2 value. However, if the c2 value is set to be too small, the kTC noise increases, which affects the performance. Therefore, it is necessary to adopt a design that takes into account the trade-off between gain and noise. Note that since the address event detection circuit including the subtractor 4 is installed for each pixel, there is a limit on the area of ​​the capacitor C1 and the capacitor C2.

[0128] The quantizer 5 includes transistors 33 to 36. PMOS transistors, for example, can be used as the transistors 33 and 34. NMOS transistors, for example, can be used as the transistors 35 and 36.

[0129] The source of transistor 33 is connected to the power supply potential. In addition, the drain of transistor 33 is connected to the source of transistor 35. The drain of transistor 35 is grounded. The source of transistor 34 is connected to the power supply potential. In addition, the drain of transistor 34 is connected to the source of transistor 36. The drain of transistor 36 is connected to ground. Quantizer 5 is connected to the node (subtractor 4) between the drain of transistor 32 and current source S2 via an input terminal. In addition, the input terminal of quantizer 5 is connected to the gate of transistor 33 and the gate of transistor 34.

[0130] A bias voltage Vbon is applied to the gate of transistor 35. On the other hand, a bias voltage Vboff is applied to the gate of transistor 36. Here, bias voltage Vbon corresponds to a first threshold value, and bias voltage Vboff corresponds to a second threshold value. Furthermore, one of the output terminals of quantizer 5 is connected to a node coupling the drain of transistor 33 to the source of transistor 35. The voltage of the output terminal corresponds to the ON event detection signal VCH. The other output terminal of quantizer 5 is connected to a node coupling the drain of transistor 34 to the source of transistor 36. The voltage of the output terminal corresponds to the OFF event detection signal VCL.

[0131] In other words, the quantizer 5 is configured to output the ON event detection signal VCH at a high level if the differential signal exceeds the first threshold, and output the OFF event detection signal VCL at a low level if the differential signal is below the second threshold.

[0132] The logic circuit 6 corresponds to the above-mentioned signal processing circuit 230. In other words, the logic circuit 6 can perform various signal processing based on the ON event detection signal VCH and the OFF event detection signal VCL input from the quantizer 5. The logic circuit 6 can be connected not only to Figure 7The address event detection circuit (pixel) shown can also be connected to other address event detection circuits. The logic circuit 6 can thus arrange the detection signals, which serve as pixel signals, into a two-dimensional grid and acquire image data. Furthermore, the logic circuit 6 can perform signal processing, such as image recognition processing, on the image data.

[0133] Figure 7 The address event detection circuit shown is suitable for performing logarithmic output. However, in recent years, address event detection circuits capable of performing linear output in addition to logarithmic output have also been developed. However, in order to provide the function of switching between logarithmic and linear outputs, the circuit scale increases, making it difficult to achieve power saving and size reduction.

[0134] Therefore, the present disclosure provides an imaging circuit and an imaging device capable of switching between logarithmic output and linear output while reducing the circuit scale.

[0135] Figure 8 The circuit diagram in shows an example of a circuit capable of switching between logarithmic output and linear output. Figure 8 The address event detection circuits for two pixels are included. However, the number of pixels included in the imaging device according to the present disclosure may be greater than this. Each address event detection circuit includes a detection circuit 2D, a buffer 3, a subtractor 4, and a quantizer 5. Figure 8 The configuration of the buffer 3, subtractor 4 and quantizer 5 in Figure 7 Although not shown, the logic circuit 6 may be connected to the stage after the quantizer 5.

[0136] The detection circuit 2D includes a photodiode PD, a transistor 20, a transistor 21, a transistor 22, a transistor 23, a transistor 25, and a transistor 26. For example, NMOS transistors can be used as the transistor 20, the transistor 21, the transistor 22, the transistor 25, and the transistor 26. For example, a PMOS transistor can be used as the transistor 23.

[0137] The anode of the photodiode PD is grounded. As the ground, for example, a reference potential of the circuit or a reference potential of the substrate can be used. However, the type of reference potential used as the ground is not limited.

[0138] The cathode of photodiode PD is connected to the drain of transistor 25. On the other hand, the source of transistor 25 is connected to the gate of transistor 21. At least a portion of the electrical connection between the source of transistor 25 and the gate of transistor 21 may be formed by a floating diffusion layer (FD) 47. In addition, the source of transistor 20 is connected to the source of transistor 25 and the gate of transistor 21. The drain of transistor 20 is connected to the drain of transistor 22. The source of transistor 22 is connected to the power supply potential. A bias voltage RST is applied to the gate of transistor 22. Bias voltage RST is controlled according to the setting of the address event detection circuit.

[0139] The gate of transistor 20 is connected to the node that couples the source of transistor 21 to the drain of transistor 23. The node that couples the source of transistor 21 to the drain of transistor 23 is connected to the input side of buffer 3 (the gate of transistor 30) via signal line Hout. Here, signal line Hout corresponds to the first output terminal of detection circuit 2D. The source of transistor 23 is connected to the power supply potential VDD. On the other hand, bias voltage PBias is applied to the gate of transistor 23. Transistor 23 can be used as a current source transistor, and a non-conductive state is established between the source and drain of transistor 23 according to bias voltage PBias.

[0140] The drain of transistor 21 is connected to the drain of transistor 26. The bias voltage applied to the gate of transistor 26 can be controlled. The source of transistor 26 is connected to the signal line Vout. The source of transistor 26 corresponds to the second output terminal of detection circuit 2D. Signal line Vout is an example of a vertical signal line. Figure 8 As shown, the second output terminals of the plurality of detection circuits 2D may be connected to the signal line Vout. Note that the signal line Vout may be a signal line provided separately from the signal line for controlling the gate voltage of the transistor 31.

[0141] The signal line Vout is connected to the analog-to-digital converter 43. The signal line Vout is grounded via the switch 40. A switch 41 and a current source 42 are connected in series between the signal line Vout and the ground. For example, field effect transistors (FETs) can be used as the switches 40, 41, and 42.

[0142] In this way, the detection circuit 2D corresponds to a circuit formed by adding the transistor 22, the transistor 25, and the transistor 26 to the Figure 7 The circuit is obtained by using the current-voltage conversion circuit 2 in FIG. Among them, transistors 22 and 26 correspond to transistors added to achieve switching between logarithmic output and linear output. On the other hand, transistor 25 is an optional switch for correlated double sampling (CDS). As will be described later, a circuit having a configuration in which transistor 25 is omitted can be used.

[0143] Figure 8 The transistor 21 in FIG. 1 corresponds to an amplifier transistor. Figure 8 In the circuit, the source and drain of the amplifier transistor are connected to different signal processing circuits. Figure 8 In the case of a circuit of, for example, the source side of the amplifier transistor is connected to the logic circuit 6 (DVS circuit), and the drain side of the amplifier transistor is connected to the analog-to-digital converter 43. However, the type of signal processing circuit to which the source side / drain side of the amplifier transistor is connected may be different from Figure 8 Those in the examples in .

[0144] In addition, the type of analog-to-digital converter 43, which is the connection destination of the signal line Vout, is not particularly limited. For example, the analog-to-digital converter 43 may be a column ADC. In this case, one or more column ADCs are prepared for one column or multiple columns. The column ADC may be shared by multiple columns. In addition, the analog-to-digital converter 43 may be a regional ADC or an ADC prepared for each pixel. In addition, the location where the analog-to-digital converter 43 is installed is not particularly limited. For example, the analog-to-digital converter 43 may be mounted on a different chip from the photodiode PD.

[0145] In the following, reference will be made to Figure 9 Table description in Figure 8 In the operation of the circuit. Figure 8 In the circuit, logarithmic output or linear output can be switched for each group (row or column) of detection circuits 2D connected to the same signal line Vout.

[0146] First, the setting in the case of performing logarithmic output will be described. In this case, the bias voltage RST of the gate of transistor 22 is set to the power supply potential. Moreover, the bias voltage PBias of the gate of transistor 23 is set to a voltage for causing transistor 23 to operate as a current source. In addition, the bias voltage of the gate of transistor 26 is set to a voltage for establishing conduction between the source and drain of transistor 26. Switch 40 is set to be on and switch 41 is set to be off. Note that during the time period when detection based on logarithmic output is performed, a conduction setting is performed between the source and drain of transistor 25. Therefore, in the case of performing logarithmic output, the signal line Vout is grounded. In addition, when transistor 25 is turned on, the photocurrent of the photodiode PD is converted into a voltage signal, which is output to the circuit (buffer 3) of the subsequent stage via the first output terminal (signal line Hout) of the detection circuit 2D.

[0147] Next, the settings for performing linear output will be described. In this case, a pulsed voltage signal is applied to the bias voltage RST of the gate of transistor 22. In addition, the bias voltage PBias of the gate of transistor 23 is set to ground potential. In addition, the bias voltage of the gate of transistor 26 is set to a voltage for establishing conduction between the source and drain of transistor 26. Switch 40 is set to off, and switch 41 is set to on. Note that conduction is set between the source and drain of transistor 25 during the period when detection based on linear output is performed and the period when reset processing is performed. Therefore, when performing linear output, current is supplied from current source 42 to signal line Vout. Then, when transistor 25 is turned on, the photocurrent of photodiode PD is converted into a voltage signal and output to signal line Vout via the second output terminal of detection circuit 2D. The analog-to-digital converter 43 is capable of converting the voltage signal into a digital signal.

[0148] Note that you can use the inversion Figure 8 In this case, the cathode of the photodiode PD is connected to the reference potential instead of the anode. Figure 8 In the example, it is only necessary to replace the PMOS transistor with an NMOS transistor and the NMOS transistor with a PMOS transistor. In other words, the polarity of the circuit can be reversed by reversing the connection relationship of the terminals of the photoelectric conversion element and the conductivity type of the transistor. Similarly, the polarity of multiple circuits can be reversed, which will be described below. In addition, both the ground potential and the power supply potential are examples of reference potentials, and any potential can be used depending on the polarity.

[0149] Figure 8 The circuit shown in is merely an example of a circuit that can switch between logarithmic output and linear output. Therefore, a circuit having a configuration different from this can be used to switch between logarithmic output and linear output.

[0150] An imaging circuit according to the present disclosure may include a photoelectric conversion element, a first transistor, a second transistor, a third transistor, and a fourth transistor. The photoelectric conversion element converts incident light into a photocurrent. The first transistor converts the photocurrent into a voltage signal. The second transistor amplifies the voltage signal. The third transistor controls the current to be supplied to the first transistor. The fourth transistor is connected to the second transistor. The above-mentioned transistor 20 is an example of a first transistor. The transistor 21 is an example of a second transistor. A transistor (e.g., transistor 22) having a gate to which a bias voltage RST is applied is an example of a third transistor. The transistor 26 is an example of a fourth transistor. The photodiode PD is an example of a photoelectric conversion element.

[0151] Furthermore, the imaging circuit according to the present disclosure may further include a fifth transistor connected between a first node coupling the control electrode of the first transistor to the first terminal of the second transistor and the first reference potential. Here, the gate of a MOS transistor is an example of a control electrode of a transistor. The source of a MOS transistor is an example of a first terminal of a transistor. The power supply potential VDD is an example of a first reference potential. Transistor 23 is an example of a fifth transistor. However, when implementing a circuit having a different polarity, the correspondence between the first terminal and the first reference potential may differ from the above-described correspondence.

[0152] Furthermore, the imaging circuit according to the present disclosure may further include a sixth transistor connected between the photoelectric conversion element and a second node, the second node coupling the first terminal of the first transistor to the control electrode of the second transistor. Transistor 25 is an example of the sixth transistor.

[0153] In addition, a buffer, a subtractor, and a quantizer may be connected to a stage after the first node in the imaging circuit according to the present invention. A node coupling the transistor 23 to the transistor 21 is an example of a first node.

[0154] The imaging circuit according to the present disclosure may further include a control unit. The control unit is configured to enable switching between a first mode and a second mode. In the first mode, the third transistor and the fourth transistor may be turned on, and the fifth transistor may function as a current source. In the second mode, a pulse voltage may be applied to the control electrode of the third transistor, the fourth transistor may be turned on, and the fifth transistor may be turned off.

[0155] The imaging device according to the present disclosure may include an analog-to-digital converter and multiple imaging circuits. The first terminal of the fourth transistor in each imaging element may be connected to the analog-to-digital converter via a signal line. Furthermore, the imaging device according to the present disclosure may further include a third switch, a fourth switch, and a current source. The third switch is connected between the signal line and a second reference potential. The fourth switch and the current source are connected in series between the signal line and the second reference potential.

[0156] Figure 10 The circuit diagram in shows an example of an imaging circuit according to the first modification. Figure 10 The address event circuit in FIG includes a detection circuit 2A, a buffer 3, a subtractor 4, a quantizer 5, and a logic circuit 6. The configuration of the buffer 3, the subtractor 4, the quantizer 5, and the logic circuit 6 is similar to that of FIG. Figure 7Configuration of the address event circuit in . Detection circuit 2A includes a photodiode PD, transistors 20, 21, 22, 23, 24, a switch LogEN, and a switch LinEN. Transistors 20, 21, 22, and 24 can be, for example, NMOS transistors. Transistor 23 can be, for example, a PMOS transistor.

[0157] The anode of the photodiode PD is grounded. As the ground, for example, a reference potential of the circuit or a reference potential of the substrate can be used. However, the type of reference potential used as the ground is not limited.

[0158] The cathode of photodiode PD is connected to the source of transistor 20 and the gate of transistor 21. The drain of transistor 20 is connected to the drain of transistor 22. The source of transistor 22 is connected to the power supply potential. Furthermore, bias voltage RST is applied to the gate of transistor 22. Meanwhile, the gate of transistor 20 is connected to the source of transistor 21, the drain of transistor 23, and switch LogEN. The source of transistor 23 is connected to the power supply potential VDD. Bias voltage PBias is applied to the gate of transistor 23.

[0159] The drain of transistor 21 is connected to switch LinEN and the source of transistor 24. Bias voltage NBias is applied to the gate of transistor 24. Furthermore, the drain of transistor 24 is grounded. Switch LogEN is connected between the node coupling the drain of transistor 23 to the source of transistor 21 and the output terminal of detection circuit 2A. On the other hand, switch LinEN is connected between the node coupling the drain of transistor 21 to the source of transistor 24 and the output terminal of detection circuit 2A. The output terminal of detection circuit 2A is connected to the input side of buffer 3 (the gate of transistor 30).

[0160] In the following, reference will be made to Figure 11 Table description in Figure 10 in the operation of the circuit.

[0161] First, the configuration for logarithmic output will be described. In this case, the bias voltage RST of the gate of transistor 22 is set to the power supply potential. Furthermore, the bias voltage PBias of the gate of transistor 23 is set to a voltage for causing transistor 23 to operate as a current source. The bias voltage of the gate of transistor 24 is set to the power supply potential. Switch LogEN is set to on, and switch LinEN is set to off. When performing logarithmic output, the photocurrent of photodiode PD is converted into a voltage signal and output to the subsequent circuit (buffer 3) via the output terminal of detection circuit 2A.

[0162] Next, we will describe the configuration for linear output. In this case, a pulsed voltage signal is applied to the bias voltage RST of the gate of transistor 22. Furthermore, the bias voltage PBias of the gate of transistor 23 is set to ground potential. Furthermore, the bias voltage of the gate of transistor 24 is set to a voltage that causes transistor 24 to function as a current source. Switch LogEN is set to off, and switch LinEN is set to on. The photocurrent of photodiode PD is converted into a voltage signal and, even when performing linear output, is output to the subsequent circuit (buffer 3) via the output terminal of detection circuit 2A.

[0163] exist Figure 10 In the circuit, the logic circuit 6 may be provided for each pixel or may be shared by a plurality of pixels. In addition, the logic circuit 6 may be mounted on the same chip as the photodiode PD or on a different chip from the photodiode PD.

[0164] exist Figure 10 In the circuit in FIG. 1 , different switches are connected to the source and drain of the amplifier transistor (transistor 21). Even when the switch LinEN or the switch LogEN is turned on, the detection signal is supplied to the logic circuit 6 (DVS circuit) or the circuit of the preceding stage. Therefore, a circuit capable of switching the mode according to the state of the switch LinEN and the switch LogEN can be used as Figure 10 Logic circuit 6 in FIG. For example, when switch LogEN is on, logic circuit 6 can operate in a first mode corresponding to logarithmic output. Furthermore, when switch LinEN is on, logic circuit 6 can operate in a second mode corresponding to linear output. For example, the aforementioned modes of logic circuit 6 can be switched based on the amount of light. Light amount can be measured using dedicated pixels or an external sensor. For example, pixels with adjusted exposure time or analog gain can be used to measure light amount.

[0165] The imaging circuit according to the present disclosure may further include a first switch and a second switch, wherein the first switch has a front end connected to the control electrode of the first transistor and the first terminal of the second transistor, and the second switch has a front end connected to the second terminal of the second transistor and the first terminal of the fourth transistor. In this case, the fourth transistor may be connected between the second transistor and the second reference potential. Figure 10 Transistor 24 in FIG is an example of a fourth transistor. Switch LogEN is an example of a first switch. Switch LinEN is an example of a second switch. Ground is an example of a second reference potential. A buffer, a subtractor, and a quantizer may be connected to the stage following the first switch, and an analog-to-digital converter may be connected to the stage following the second switch.

[0166] Figure 12is a flowchart showing an example of a process for switching between logarithmic reading and linear reading. Figure 10 In the case of the circuit in FIG. 1 , the first mode corresponds to logarithmic reading, and the second mode corresponds to linear reading. The switching of the modes may be performed for the entire pixel array or may be performed for a portion of the pixel array. Figure 12 The flowchart in describes the processing.

[0167] First, the imaging circuit performs logarithmic reading for a predetermined time period (step S10). Next, the amount of light in the environment is measured (step S11). Then, it is determined whether the measured amount of light is less than a threshold value (step S12). In the case where the measured amount of light is less than the threshold value (yes in step S12), the imaging circuit switches from logarithmic reading to linear reading (step S13). Next, the imaging circuit performs linear reading for a predetermined time period (step S14). Then, after a specific time period has passed, the imaging circuit is switched to logarithmic reading (step S15). For example, a timer circuit can be used to measure time in step S15. On the other hand, in the case where the measured amount of light is equal to or greater than the threshold value (no in step S12), the imaging circuit performs logarithmic reading for a predetermined time period (step S10).

[0168] Figure 12 An example of a process of switching to linear reading when the amount of light is relatively small is shown. However, the conditions for switching the reading method may be different from this. For example, a process of switching to linear reading when the amount of light is relatively large may be employed, such as Figure 13 In the following, reference will be made to the flowchart in Figure 13 The flowchart in describes the processing.

[0169] First, the imaging circuit performs logarithmic reading for a predetermined time period (step S20). Next, the amount of light in the environment is measured (step S21). Then, it is determined whether the measured amount of light is equal to or greater than a threshold value (step S22). In the case where the measured amount of light is equal to or greater than the threshold value ("Yes" in step S22), the imaging circuit switches from logarithmic reading to linear reading (step S23). Next, the imaging circuit performs linear reading for a predetermined time period (step S24). Then, after a specific time period has passed, the imaging circuit is switched to logarithmic reading (step S25). For example, a timer circuit can be used to measure time in step S25. On the other hand, in the case where the measured amount of light is less than the threshold value ("No" in step S22), the imaging circuit performs logarithmic reading for a predetermined time period (step S20).

[0170] In this way, the control unit may be configured to implement switching between the first mode and the second mode depending on the measured amount of light.

[0171] Figure 14An example of an imaging circuit according to a second modification is shown. Figure 14 The address event circuit in FIG includes a detection circuit 2C, a buffer 3, a subtractor 4, a quantizer 5, and a logic circuit 6. The configuration of the buffer 3, the subtractor 4, the quantizer 5, and the logic circuit 6 is similar to that of FIG. Figure 7 The configuration of the address event circuit in the detection circuit 2C is the same as Figure 10 The configuration of the detection circuit 2A in FIG is similar, except that the transistor 25 is provided between the cathode of the photodiode PD and the node that couples the source of the transistor 20 to the gate of the transistor 21. In other words, the drain of the transistor 25 is connected to the cathode of the photodiode PD. In addition, the source of the transistor 25 is connected to the source of the transistor 20 and the gate of the transistor 21.

[0172] The source and drain of the transistor 25 may be conductive during the period when detection based on logarithmic output is performed. Furthermore, the source and drain of the transistor 25 may be conductive during the period when detection based on linear output is performed and during the period when reset processing is performed.

[0173] You can also Figure 14 The logic circuit 6 is used in a circuit in a first mode (logarithmic reading) or a second mode (linear reading). For example, the logic circuit 6 can detect the motion of an object in the first mode based on whether the contrast of the measured light amounts exceeds a threshold. Furthermore, the logic circuit 6 can detect the motion of an object in the second mode based on whether the difference in the measured light amounts exceeds a threshold. However, the logic circuit 6 can detect the motion of an object based on other criteria.

[0174] Figure 15 An example of an imaging circuit according to a third modification is shown. Figure 15 The address event circuit in FIG includes a detection circuit 2B, a buffer 3, a subtractor 4, a quantizer 5, and a logic circuit 6. The configuration of the buffer 3, the subtractor 4, the quantizer 5, and the logic circuit 6 is similar to that of FIG. Figure 7 On the other hand, the configuration of the detection circuit 2B is the same as that of the address event circuit in the switch LinEN except for the connection destination on the output side. Figure 10 The configuration of the detection circuit 2A in FIG. 1 is similar. In other words, the output side of the switch LinEN is connected to the signal line Vout instead of the buffer 3. In this way, the logarithmic output signal and the linear output signal can be output to different circuits.

[0175] Figure 16 An example of an imaging circuit according to a fourth modification is shown. Figure 16 In the embodiment, a plurality of detection circuits 2d are connected to the signal line Vout. Each detection circuit 2d is connected to the signal line Vout. Figure 8 Corresponding to the detection circuit 2D in Figure 8The transistor 25 is omitted.

[0176] In each detection circuit 2d, the drain of the amplifying transistor (transistor 21) is connected to the signal line Vout via the transistor 26. Specifically, the drain of the transistor 21 is connected to the drain of the transistor 26, and the source of the transistor 26 is connected to the signal line Vout. Moreover, the switch 40 may be provided between the signal line Vout and the ground, as shown in FIG. Figure 16 Here, the switch 40 may be installed outside the pixel array.

[0177] Figure 17 An example of an imaging circuit according to a fifth modification is shown. Figure 17 The circuit in corresponds to the circuit in which the switch 41 and the current source 42 are added to the Figure 16 The switch 41 and the current source 42 are connected in series between the signal line Vout and the ground. When viewed from the switch 40, the switch 41 and the current source 42 are connected in parallel. In which the switch 40 is off, the switch 41 is on, and Figure 17 In the case where the detection circuit 2d in the configuration performs linear output, the grayscale signal can be read through the signal line Vout.

[0178] Figure 18 An example of an imaging circuit according to a sixth modification is shown. Figure 18 The circuit in corresponds to the circuit in Figure 17 The circuit is obtained by adding a transistor 25 between the cathode of the photodiode PD and the floating diffusion layer 47 in each imaging circuit. In other words, the drain of the transistor 25 is connected to the cathode of the photodiode PD. On the other hand, the source of the transistor 25 is connected to the floating diffusion layer 47.

[0179] It should be noted that in the imaging circuit according to the present disclosure, the capacity of the floating diffusion layer 47 can be variable. In addition, multiple photodiodes PD can share a single floating diffusion layer. In addition, the capacity of the conversion transistor (transistor 20) on the side opposite to the photodiode PD can be variable.

[0180] Figure 19 An example of an imaging circuit according to a seventh modification is shown. Figure 19 The detection circuit 2E in FIG. 1 includes a photodiode PD, a transistor 20, a transistor 21, a transistor 22, a transistor 23, a transistor 24, and a transistor 25. The transistor 20, the transistor 21, the transistor 22, the transistor 24, and the transistor 25 are NMOS transistors. On the other hand, the transistor 23 is a PMOS transistor.

[0181] The anode of the photodiode PD is grounded. The cathode of the photodiode PD is connected to the drain of the transistor 25. The source of the transistor 25 is connected to the source of the transistor 20 and the gate of the transistor 21. The gate of the transistor 20 is connected to the source of the transistor 21, the drain of the transistor 23, and the signal line Hout (first output terminal). The drain of the transistor 20 is connected to the drain of the transistor 22. In addition, the source of the transistor 22 is connected to the power supply potential. A bias voltage RST is applied to the gate of the transistor 22. The source of the transistor 23 is connected to the power supply potential VDD. Furthermore, a bias voltage PBias is applied to the gate of the transistor 23.

[0182] The drain of the transistor 21 and the source of the transistor 24 are connected to the signal line Vout via the second output terminal. The drain of the transistor 24 is grounded. In addition, a bias voltage NBias is applied to the gate of the transistor 24.

[0183] Figure 19 The operation of the detection circuit 2E is similar to Figure 14 The operation of the detection circuit 2C in FIG. 1 is similar, except that the switch LinEN and the switch LogEN are not included.

[0184] Figure 20 An example of an imaging circuit according to an eighth modification is shown. Figure 20 The detection circuit 2F in FIG. 2 corresponds to a circuit obtained by adding a transistor 27 to the detection circuit 2D. In other words, the source of the transistor 27 is connected to the drain of the transistor 22 and the drain of the transistor 20. On the other hand, the drain of the transistor 27 is connected to the drain of the transistor 27 of the other detection circuit 2F.

[0185] In this manner, in the imaging circuit according to the present disclosure, the node of the first transistor (the drain of the transistor 20) on the side opposite to the photodiode PD can be connected to the corresponding node of another pixel via one or more transistors. The first transistor refers to a transistor that converts photocurrent into a voltage signal.

[0186] Figure 21 An example of an imaging circuit according to a ninth modification is shown. Figure 21 In the detection circuit 2G, the power supply potential VR connected to the source of transistor 22 (logarithmic conversion side) and the power supply potential VDD connected to the source of transistor 23 (amplifier side) are different. For example, different power supplies can be used as the power supply potential VR and the power supply potential VDD. In addition, different potentials can be generated by voltage division from the same power supply circuit. In this case, the switch in the detection circuit (pixel) can be omitted. In addition, the imaging circuit can be configured so that a complete transfer can be performed between the photodiode PD and the floating diffusion layer 47.

[0187] Figure 22 An example of an imaging circuit according to a tenth modification is shown. Figure 22 The detection circuit 2H includes a photodiode PD, a transistor 20, a transistor 21, a transistor 22, a transistor 23, a transistor 25, a transistor 26, a transistor 28, and a transistor 29. For example, NMOS transistors can be used as the transistor 20, the transistor 21, the transistor 22, the transistor 25, the transistor 26, the transistor 28, and the transistor 29. For example, a PMOS transistor can be used as the transistor 23.

[0188] The anode of photodiode PD is grounded. On the other hand, the cathode of photodiode PD is connected to the drain of transistor 25. The source of transistor 25 is connected to the gate of transistor 21 and the source of transistor 20. The source of transistor 21 is connected to the drain of transistor 29 and the gate of transistor 20. The drain of transistor 21 is connected to the drain of transistor 26. The bias voltage applied to the gate of transistor 26 can be controlled. The source of transistor 26 corresponds to the second output terminal of detection circuit 2H and is connected to signal line Vout.

[0189] The drain of transistor 20 is connected to the gate of transistor 29 and the source of transistor 28. The gate of transistor 28 is connected to the source of transistor 29, the drain of transistor 23, and the signal line Hout. Signal line Hout corresponds to the first output terminal of the detection circuit and is connected to buffer 3 (the gate of transistor 30). The drain of transistor 28 is connected to the drain of transistor 22. Bias voltage RST is applied to the gate of transistor 22. The source of transistor 22 is connected to the power supply potential. On the other hand, bias voltage PBias is applied to the gate of transistor 23. The source of transistor 23 is connected to the power supply potential.

[0190] Figure 22 The detection circuit in the embodiment is a gain-boost circuit comprising two logarithmic conversion circuits. By using a gain-boost circuit, the sensitivity of the detection circuit can be improved and the gain of the current-to-voltage conversion can be increased. In this manner, the configuration of the current-to-voltage conversion circuit that can be used in the imaging circuit according to the present disclosure is not limited. Furthermore, current-to-voltage conversion circuits having different configurations can be implemented depending on the pixels in the pixel array.

[0191] Figure 23 An imaging circuit according to an eleventh modification is shown. Figure 23The detection circuit 21 in FIG. 1 includes a photodiode PD, a transistor 20, a transistor 21, a transistor 22, a transistor 23, a transistor 25, a transistor 26, and a transistor 44. For example, NMOS transistors can be used as the transistor 20, the transistor 21, the transistor 22, the transistor 25, the transistor 26, and the transistor 44. For example, a PMOS NMOS transistor can be used as the transistor 23.

[0192] The anode of photodiode PD is grounded. The cathode of photodiode PD is connected to the drain of transistor 25. The source of transistor 25 is connected to the source of transistor 20 and the gate of transistor 21. The gate of transistor 20 is connected to the source of transistor 21, the drain of transistor 23, and signal line Hout. Signal line Hout corresponds to the first output terminal of detection circuit 2I. The drain of transistor 20 is connected to the drain of transistor 22. A bias voltage RSTx (x=0, 1, 2, ...) is applied to the gate of transistor 22. The source of transistor 22 is connected to the power supply potential. A bias voltage PBias is applied to the gate of transistor 23. The source of transistor 23 is connected to the power supply potential VDD.

[0193] On the other hand, the drain of transistor 21 is connected to the drain of transistor 26 and the source of transistor 44. A bias voltage SWxD (x=0, 1, 2, ...) is applied to the gate of transistor 44. The drain of transistor 44 is grounded. A bias voltage SWxL (x=0, 1, 2, ...) is applied to the gate of transistor 26. The source of transistor 26 corresponds to the second output terminal of detection circuit 2I and is connected to signal line Vout.

[0194] Note that the structures of the buffer 3, the subtractor 4, and the quantizer 5 are the same as those in the above-described figures. Although not shown, it is assumed that a logic circuit 6 is connected to the stage after the quantizer 5.

[0195] The imaging circuit according to the present disclosure may further include a sixth transistor connected between a third node coupling the second terminal of the second transistor to the second terminal of the fourth transistor and the second reference potential. The drain of the MOS transistor is an example of a second terminal of the transistor. The node coupling transistor 21 to transistor 26 is an example of a third node. Transistor 44 is an example of a sixth transistor. Ground is an example of a second reference potential. However, depending on the polarity of the circuit, the correspondence between the second terminal of the transistor and the second reference potential may differ from the above-described correspondence.

[0196] In the following, reference will be made to Figure 24 Table description in Figure 23 in the operation of the circuit.

[0197] First, the setting in the case of performing logarithmic output will be described. In this case, the bias voltage RSTx applied to the gate of transistor 22 is set to the power supply potential. In addition, the bias voltage PBias applied to the gate of transistor 23 is set to a voltage for causing transistor 23 to operate as a current source. The bias voltage SWxL applied to the gate of transistor 26 is low. In this way, a non-conducting state is achieved between the source and drain of transistor 26. The bias voltage SWxD applied to the gate of transistor 44 is high. In this way, a conducting state is achieved between the source and drain of transistor 44. Switch 40 is set to off and switch 41 is set to on. In the case of performing logarithmic output, the photocurrent of the photodiode PD is converted into a voltage signal and output to the circuit (buffer 3) of the subsequent stage via the output terminal of the detection circuit 2A.

[0198] Next, the setting in the case of performing linear output will be described. In this case, a pulse-shaped voltage signal is applied to the bias voltage RSTx, which is applied to the gate of transistor 22. In addition, the bias voltage PBias applied to the gate of transistor 23 is set to ground potential. The bias voltage SWxL applied to the gate of transistor 26 is high. In this way, a conductive state is achieved between the source and drain of transistor 26. The bias voltage SWxD applied to the gate of transistor 44 is low. In this way, a non-conductive state is achieved between the source and drain of transistor 44. Switch 40 is set to be on, and switch 41 is set to be off. The photocurrent of the photodiode PD is converted into a voltage signal and output to the circuit (buffer 3) of the subsequent stage via the output terminal of the detection circuit 2A even in the case of linear output.

[0199] An imaging circuit according to the present disclosure may include a control unit. The control unit is configured to enable switching between a first mode and a second mode. In the first mode, the third transistor may be turned on, the fourth transistor may be turned off, the fifth transistor may function as a current source, and the sixth transistor may be turned on. In the second mode, a pulse voltage may be applied to a control electrode of the third transistor, the fourth transistor may be turned on, the fifth transistor may be turned off, and the sixth transistor may be turned off.

[0200] Furthermore, in the first mode, the third and fourth transistors may be turned on, the fifth transistor may function as a current source, the first switch may be turned on, and the second switch may be turned off. In this case, in the second mode, a pulse voltage may be applied to the control electrode of the third transistor, the fourth transistor may be turned on, the fifth transistor may be turned off, the first switch may be turned off, and the second switch may be turned on.

[0201] Furthermore, in the first mode, the third and fourth transistors may be turned on, the fifth transistor may function as a current source, the third switch may be turned on, and the fourth switch may be turned off. In the second mode, a pulse voltage may be applied to the control electrode of the third transistor, the fourth transistor may be turned on, the fifth transistor may be turned off, the third switch may be turned on, and the fourth switch may be turned off.

[0202] Figure 25 An example of an imaging circuit according to a twelfth modification is shown. Figure 25 , the floating diffusion layer 47 of the detection circuit 2D is connected via the transistor 45. That is, the source of the transistor 45 is connected to the floating diffusion layer 47 of one detection circuit 2D. In addition, the gate of the transistor 45 is connected to the floating diffusion layer 47 of another detection circuit 2D. The transistor 45 is, for example, an NMOS transistor. In this way, in the imaging circuit according to the present disclosure, the floating diffusion layers of a plurality of detection circuits can be connected via at least one transistor. In this way, the sum signal (FD sum signal) of the floating diffusion layer can be output to the subsequent circuit and the object can be detected. In addition, the influence of noise is reduced, and the voltage output by the detection circuit is stabilized. In other words, the floating diffusion layers of at least two imaging circuits can be connected via the seventh transistor. The transistor 45 is an example of the seventh transistor.

[0203] Figure 26 An example of an imaging circuit according to a thirteenth modification is shown. Figure 26 The detection circuit 2J in corresponds to a circuit obtained by adding a transistor 46 to the above-mentioned detection circuit 2D. Transistor 46 is, for example, an NMOS transistor. The source of transistor 46 is connected to a node that couples the drain of transistor 22 to the drain of transistor 20. On the other hand, the drain of transistor 46 is connected to the drain of transistor 46 of another detection circuit 2J. In this way, in the imaging circuit according to the present disclosure, the sources of the reset transistors (transistor 22) in different detection circuits can be connected via at least one transistor. In this way, the influence of noise can be reduced and the voltage output by the detection circuit can be stabilized. In other words, the second terminals of the first transistors in at least two imaging circuits can be connected via an eighth transistor. Transistor 46 is an example of an eighth transistor.

[0204] Figure 27 An example of an imaging circuit according to a fourteenth modification is shown. Figure 27 The detection circuit 2K in FIG. 1 includes a photodiode PD, a transistor 20, a transistor 21, a transistor 22A, a transistor 23, and a transistor 24. The transistor 20, the transistor 21, the transistor 22A, and the transistor 24 are, for example, NMOS transistors. The transistor 23 is, for example, a PMOS transistor.

[0205] The anode of the photodiode PD is grounded. On the other hand, the cathode of the photodiode PD is connected to the drain of the transistor 25. The source of the transistor 25 is connected to the gate of the transistor 21 and the source of the transistor 22A. Moreover, the drain of the transistor 22A is connected to the source of the transistor 20. The bias voltage RST is applied to the gate of the transistor 22A. The gate of the transistor 20 is connected to the drain of the transistor 23, the source of the transistor 21, and the signal line Hout. Among them, the signal line Hout corresponds to the first output terminal of the detection circuit 2K. The above-mentioned buffer 3 is connected to the first output terminal, for example. The drain of the transistor 20 is connected to the power supply potential.

[0206] Bias voltage PBias is applied to the gate of transistor 23. Furthermore, the source of transistor 23 is connected to power supply potential VDD. The drain of transistor 21 is connected to signal line Vout via the second output terminal. Furthermore, the drain of transistor 21 is connected to the source of transistor 24. Bias voltage NBias is applied to the gate of transistor 24. Furthermore, the drain of transistor 24 is grounded.

[0207] The transistor 20 corresponds to a conversion transistor, and the transistor 21 corresponds to an amplification transistor. On the other hand, the transistor 22A corresponds to a reset transistor (reset switch) for detecting a voltage in the circuit. Figure 27 As shown, the reset transistor can be connected between the conversion transistor and the floating diffusion layer, rather than between the power supply potential and the conversion transistor. In this way, the position of the reset transistor connection is not limited in the imaging circuit according to the present disclosure.

[0208] Figure 28 An example of an imaging circuit according to a fifteenth modification is shown. Figure 28 The detection circuit 2L includes a photodiode PD, a transistor 20, a transistor 21, a transistor 22A, a transistor 23, a transistor 24, a transistor 28, and a transistor 29. The transistor 20, the transistor 21, the transistor 22A, the transistor 24, the transistor 28, and the transistor 29 are, for example, NMOS transistors. The transistor 23 is, for example, a PMOS transistor.

[0209] The anode of the photodiode PD is grounded. On the other hand, the cathode of the photodiode PD is connected to the drain of the transistor 25. The source of the transistor 25 is connected to the source of the transistor 22A and the gate of the transistor 21. A bias voltage RST is applied to the gate of the transistor 22A. The drain of the transistor 22A is connected to the source of the transistor 20. The gate of the transistor 20 is connected to the drain of the transistor 29 and the source of the transistor 21.

[0210] Furthermore, the drain of transistor 20 is connected to the source of transistor 28 and the gate of transistor 29. The gate of transistor 28 is connected to the drain of transistor 23, the source of transistor 29, and the signal line Hout. Here, signal line Hout corresponds to the first output terminal of detection circuit 2L. For example, the first output terminal is connected to the aforementioned buffer 3. The drain of transistor 28 is connected to the power supply potential. Bias voltage PBias is applied to the gate of transistor 23. Furthermore, the source of transistor 23 is connected to the power supply potential VDD.

[0211] The detection circuit 2L includes a gain-up current-voltage conversion circuit in which a logarithmic conversion circuit is included in multiple stages. Even when a gain-up current-voltage conversion circuit is employed, a reset transistor (reset switch) may be provided between the conversion transistor and the floating diffusion layer.

[0212] In the imaging circuit according to the present disclosure, the first transistor and the second transistor may be included in a multi-stage logarithmic conversion circuit.

[0213] The imaging circuit according to the present disclosure can be implemented in various aspects. Figures 29 to 42 In the figure, components mounted on the same chip or substrate are surrounded by thick lines. Figures 29 to 36 Embodiments of imaging circuits according to the present disclosure are described.

[0214] like Figure 29 As shown, the photodiode PD can be mounted on a different chip or substrate from the other components of the detection circuit. Figure 29 In the case of the implementation in FIG. 1 , the transistor 25 (transmission gate) may be a transistor that does not perform full transmission. In addition, the transistor 25 may be omitted. In addition, as Figure 30 As shown, the photodiode PD and the transistor 25 (transmission gate) can be mounted on a different chip or substrate from other components of the detection circuit. In other words, in the imaging circuit according to the present disclosure, the photoelectric conversion element and the fifth transistor can be mounted on a different chip or substrate.

[0215] like Figure 31 As shown, the photodiode PD, transistor 20, transistor 21, transistor 22, transistor 25 and floating diffusion layer 47 can be mounted on different chips or substrates from other components of the detection circuit. Figure 31 In the case of the embodiment in which the chip or substrate has electrical connections at multiple locations. Figure 31In the embodiment of the present invention, the transistor 26 corresponding to the switch between the detection circuit and the signal line Vout is not mounted on the same chip or substrate as the chip or substrate of the photodiode PD. In addition, the transistor 23, which is a PMOS transistor, is not mounted on the same chip or substrate as the photodiode PD. Since the PMOS transistor, which has a conductivity type different from that of the other transistors in the detection circuit, requires good isolation, it occupies a large area. Therefore, there is a case where it is preferably mounted on a chip or substrate different from the photodiode PD and the NMOS transistor. In the case of using a transistor with the same conductivity type as the photodiode PD, the transistor 23 is not mounted on the same chip or substrate as the photodiode PD. Figure 31 In the case of a circuit with opposite polarity, a transistor having a different conductivity type may be mounted on a chip or substrate different from that of the photodiode.

[0216] like Figure 32 As shown, the components in the detection circuit except the transistor 23 (PMOS transistor) with different conductivity types can be mounted on the same chip or substrate. Figure 32 In the case of the embodiment in FIG. 1 , the transistor 26 corresponding to the switch between the detection circuit and the signal line Vout is mounted on the same chip or substrate as the chip or substrate of the photodiode PD. Figure 32 In this case, the signal line Vout and the circuits in the subsequent stage are mounted on different chips or substrates from the detection circuit.

[0217] like Figure 33 As shown in FIG, in a plurality of detection circuits, components other than the transistor 23 (PMOS transistor) having a different conductivity type and the signal line Vout can be mounted on the same chip or substrate as the photodiode PD. In this way, the photoelectric conversion element, the first transistor, the second transistor, the third transistor, and the fourth transistor in a plurality of imaging circuits can be mounted on the same chip or substrate. Furthermore, as Figure 34 As shown in , in multiple detection circuits, elements other than the transistor 23 (PMOS transistor) with a different conductivity type, the signal line Vout, the switch 40, and the wiring from the switch 40 to the ground (reference potential) can be mounted on the same chip or substrate as the photodiode PD.

[0218] like Figure 35 As shown, in multiple detection circuits, elements other than the transistor 23 (PMOS transistor) having a different conductivity type, the signal line Vout, the switch 40, the wiring from the switch 40 to the ground (reference potential), the switch 41, the current source 42, and the wiring from the current source 42 to the ground (reference potential) can be mounted on the same chip or substrate as the photodiode PD.

[0219] exist Figure 36In FIG. 1 , the buffer 3 including the transistor 30 and the current source S1 is surrounded by a thick line. The buffer 3 can be mounted on the same chip or substrate as the photodiode PD of the detection circuit. Alternatively, the buffer 3 and the photodiode PD of the detection circuit can be mounted on different chips or substrates.

[0220] In the following, reference will be made to Figures 37 to 42 An example implementation of an imaging circuit is described.

[0221] like Figure 37 As shown, the photodiode PD can be mounted on a chip or substrate different from the other components of the detection circuit. Figure 38 As shown, the photodiode PD and the transistor 25 can be mounted on a chip or substrate different from the other components of the detection circuit. Figure 39 As shown, the transistor 20 , the transistor 21 , the transistor 22 , the transistor 25 and the floating diffusion layer 47 in the detection circuit may be mounted on the same chip or substrate as the photodiode PD.

[0222] like Figure 40 As shown, the photodiode PD, the transistor 20, the transistor 21, the transistor 22, the transistor 24, the transistor 25 and the floating diffusion layer 47 can be mounted on the same chip or substrate. Figure 40 In the embodiment, the transistor 23 having a conductivity type different from that of the other transistors in the detection circuit is mounted on a different chip or substrate from the photodiode PD. Therefore, good separation can be achieved and the overall size of the embodiment can be reduced.

[0223] like Figure 41 As shown, the photodiode PD, the transistor 20, the transistor 21, the transistor 22, the transistor 24, the transistor 25, the floating diffusion layer 47 and the switch LinEN can be mounted on the same chip or substrate. In the case where the switch LinEN is a MOS transistor and the transistors 20, the transistor 21, the transistor 22, the transistor 24 and the transistor 25 are of the same conductivity type, for example, Figure 41 However, the implementation scheme of the switch LinEN and the switch LogEN is not limited.

[0224] In addition, if Figure 42 As shown, the photodiode PD, transistor 20, transistor 21, transistor 22, transistor 24, transistor 25, floating diffusion layer 47, switch LinEN and switch LogEN can be mounted on the same chip or substrate. For example, when switch LinEN and switch LogEN are MOS transistors and transistor 20, transistor 21, transistor 22, transistor 24 and transistor 25 are of the same conductivity type, a Figure 42 The implementation method in .

[0225] Using the imaging circuit of the present disclosure, an address event circuit capable of switching between logarithmic and linear outputs while reducing the number of transistors can be implemented. Consequently, events can be read at high speed by switching the output type to be used depending on the imaging circuit's application or environment. This enables the implementation of an asynchronous imaging element capable of generating and outputting data at high speed while reducing circuit size. For example, image recognition of people or obstacles can be performed at high speed, improving safety in the transportation sector.

[0226] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile object (such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, an unmanned aerial vehicle, a ship, and a robot).

[0227] Figure 43 : is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0228] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 43 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0229] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a drive force generating device (e.g., an internal combustion engine or a drive motor) that generates the vehicle's drive force, a drive force transmission mechanism that transmits the drive force to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a control device (e.g., a brake device) that generates the vehicle's braking force.

[0230] The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as the headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a portable device that replaces the key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door locks, power windows, lights, and other functions.

[0231] The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receive the captured images. Furthermore, the vehicle exterior information detection unit 12030 can also perform object detection and distance detection on people, vehicles, obstacles, signs, text, and the like on the road based on the received images.

[0232] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can also output the electrical signal as an image and ranging information. The light received by imaging unit 12031 can be visible light or invisible light such as infrared light.

[0233] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration based on the detection information input from the driver state detection unit 12041, or can determine whether the driver is dozing off.

[0234] The microcomputer 12051 can calculate control target values ​​of the driving force generation device, the steering mechanism, or the braking device based on the vehicle interior and exterior information acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to implement functions of an advanced driver assistance system (ADAS), including vehicle collision avoidance, impact mitigation, driving based on vehicle-to-vehicle distance, speed maintenance driving, vehicle collision warning, vehicle lane departure warning, and the like.

[0235] In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on the information around the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby enabling coordinated control for automatic driving for autonomous driving without relying on the driver's operation.

[0236] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the vehicle exterior information acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control for preventing glare, such as switching from high beam to low beam, by controlling the headlights according to the position of a preceding vehicle or an oncoming vehicle detected by the external vehicle information detection unit 12030.

[0237] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the occupants of the vehicle or the outside of the vehicle of information. Figure 43 In the example shown, audio speakers 12061, a display unit 12062, and an instrument panel 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0238] Figure 44 is a diagram showing an example of the installation position of the imaging unit 12031.

[0239] exist Figure 44 In the figure, the vehicle 12100 includes imaging units 12101 , 12102 , 12103 , 12104 , and 12105 as the imaging unit 12031 .

[0240] Imaging units 12101, 12102, 12103, 12104, and 12105 are disposed at locations within the vehicle interior of vehicle 12100, such as the front nose, side-view mirrors, rear bumper, rear door, and upper portion of the windshield. Imaging unit 12101 disposed within the vehicle interior and imaging unit 12105 disposed within the upper portion of the windshield primarily capture images in front of vehicle 12100. Imaging units 12102 and 12103 disposed on the side-view mirrors primarily capture images to the sides of vehicle 12100. Imaging unit 12104 disposed on the rear bumper or rear door primarily captures images behind vehicle 12100. The front-view images captured by imaging units 12101 and 12105 are primarily used to detect leading vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0241] Please note that Figure 44The figure shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101, which is located at the front nose. Imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103, respectively, which are located at the side mirrors. Imaging range 12114 indicates the imaging range of imaging unit 12104, which is located at the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 can be obtained.

[0242] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera configured by a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0243] For example, microcomputer 12051 can extract the closest three-dimensional object on the path of vehicle 12100, specifically a three-dimensional object traveling at a predetermined speed (e.g., 0 km / h or higher) in the same direction as vehicle 12100, as the preceding vehicle by obtaining the distance to each three-dimensional object within imaging ranges 12111 to 12114 and the temporal change in that distance (relative speed to vehicle 12100) based on distance information obtained from imaging units 12101 to 12104. Furthermore, microcomputer 12051 can set a predetermined inter-vehicle distance to be maintained ahead of the preceding vehicle and execute automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control). Thus, for example, cooperative control can be implemented for autonomous driving purposes, where the vehicle travels autonomously without requiring driver input.

[0244] For example, microcomputer 12051 can classify and extract three-dimensional object data related to three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects (such as utility poles) based on the distance information obtained from imaging units 12101 to 12104, and use this three-dimensional object data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles near vehicle 12100 as obstacles that the driver of vehicle 12100 can visually identify and obstacles that are difficult to visually identify. In addition, microcomputer 12051 determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is greater than a set value and there is a possibility of collision, a warning is output to the driver via audio speaker 12061 or display unit 12062, and forced deceleration or evasive steering is performed via drive system control unit 12010, thereby enabling driving assistance for collision avoidance.

[0245] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify pedestrians by determining whether a pedestrian exists in images captured by the imaging units 12101 to 12104. This pedestrian identification is performed by, for example, extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, performing pattern matching on a series of feature points indicating the outline of an object, and determining whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to display the identified pedestrian with a square outline for emphasis. Furthermore, the audio / image output unit 12052 may control the display unit 12062 to display an icon indicating a pedestrian, etc., at a desired location.

[0246] Thus far, examples of vehicle control systems to which the technology of the present disclosure can be applied have been described. The technology of the present disclosure can be applied to, for example, the imaging unit 12031 in the above-described configuration. Specifically, the distance measuring device 90 including the aforementioned imaging circuit and light source 91 can be mounted on the imaging unit 12031. By applying the technology of the present disclosure to the imaging unit 12031, accurate distance information can be obtained, and the functionality and safety of the vehicle 12100 can be enhanced in environments with a wide dynamic range of brightness.

[0247] It should be noted that the present technology can also have the following configurations.

[0248] (1) An imaging circuit includes: a photoelectric conversion element that converts incident light into a photocurrent; a first transistor that converts the photocurrent into a voltage signal; a second transistor that amplifies the voltage signal; a third transistor that controls a current to be supplied to the first transistor; and a fourth transistor connected to the second transistor.

[0249] (2) The imaging circuit according to claim 1, further comprising: a fifth transistor connected between a first node coupling the control electrode of the first transistor to the first terminal of the second transistor and the first reference potential.

[0250] (3) The imaging circuit according to (2), wherein the buffer, the subtractor, and the quantizer are connected to a stage subsequent to the first node.

[0251] (4) The imaging circuit according to (2) or (3), further comprising: a control unit configured to enable switching between a first mode and a second mode, wherein in the first mode, the third transistor and the fourth transistor are turned on and the fifth transistor is used as a current source, and in the second mode, a pulse voltage is applied to the control electrode of the third transistor, the fourth transistor is turned on, and the fifth transistor is turned off.

[0252] (5) The imaging circuit according to (4), wherein the control unit is configured to implement switching between the first mode and the second mode according to the measured light amount.

[0253] (6) The imaging circuit according to any one of (1) to (5), further including: a sixth transistor connected between the photoelectric conversion element and a second node, the second node coupling the first terminal of the first transistor to the control electrode of the second transistor.

[0254] (7) The imaging circuit according to any one of (1) to (6), wherein the first transistor and the second transistor are included in a multi-stage logarithmic conversion circuit.

[0255] (8) The imaging circuit according to any one of (2) to (5), further including: a sixth transistor connected between a third node coupling the second terminal of the second transistor to the second terminal of the fourth transistor and the second reference potential.

[0256] (9) The imaging circuit according to (8) further includes: a control unit configured to enable switching between a first mode and a second mode, in which the third transistor is turned on, the fourth transistor is turned off, the fifth transistor is used as a current source, and the sixth transistor is turned on, and in the second mode, a pulse voltage is applied to the control electrode of the third transistor, the fourth transistor is turned on, the fifth transistor is turned off, and the sixth transistor is turned off.

[0257] (10) The imaging circuit according to any one of (2) to (4) further includes a first switch and a second switch, wherein the front stage of the first switch is connected to the control electrode of the first transistor and the first terminal of the second transistor, and the front stage of the second switch is connected to the second terminal of the second transistor and the first terminal of the fourth transistor, wherein the fourth transistor is connected between the second transistor and the second reference potential.

[0258] (11) The imaging circuit according to (10), wherein the buffer, the subtractor, and the quantizer are connected to a stage subsequent to the first switch, and the analog-to-digital converter is connected to a stage subsequent to the second switch.

[0259] (12) The imaging circuit according to (11) further includes: a control unit configured to enable switching between a first mode and a second mode, wherein in the first mode, the third transistor and the fourth transistor are turned on, the fifth transistor is used as a current source, the first switch is turned on, and the second switch is turned off, and in the second mode, a pulse voltage is applied to the control electrode of the third transistor, the fourth transistor is turned on, the fifth transistor is turned off, the first switch is turned off, and the second switch is turned on.

[0260] (13) The imaging circuit according to any one of (2) to (4), wherein the photoelectric conversion element and the fifth transistor are mounted on different chips or substrates.

[0261] (14) An imaging device comprising: an analog-to-digital converter; and a plurality of imaging circuits according to any one of claims 1 to 5, wherein the first terminal of the fourth transistor in each imaging circuit is connected to the analog-to-digital converter via a signal line.

[0262] (15) The imaging device according to (14), further comprising: a third switch, a fourth switch and a current source, wherein the third switch is connected between the signal line and the second reference potential, and the fourth switch and the current source are connected in series between the signal line and the second reference potential.

[0263] (16) The imaging device according to (15) further includes: a control unit configured to enable switching between a first mode and a second mode, in which, in the first mode, the third transistor and the fourth transistor are turned on; the fifth transistor is used as a current source, the third switch is turned on, and the fourth switch is turned off, and in the second mode, a pulse voltage is applied to the control electrode of the third transistor, the fourth transistor is turned on, the fifth transistor is turned off, the third switch is turned on, and the fourth switch is turned off.

[0264] (17) The imaging device according to (16), wherein the control unit is configured to switch between the first mode and the second mode according to the measured light amount.

[0265] (18) The imaging device according to (14) or (15), wherein the floating diffusion layers in at least two imaging circuits are connected via a seventh transistor.

[0266] (19) The imaging device according to (14) or (15), wherein the second terminals of the first transistors in at least two imaging circuits are connected via an eighth transistor.

[0267] (20) The imaging device according to (14), wherein the photoelectric conversion elements, the first transistor, the second transistor, the third transistor, and the fourth transistor of the plurality of imaging circuits are mounted on the same chip or substrate.

[0268] The various aspects of the present disclosure are not limited to the aforementioned embodiments and include various modifications that can be implemented by those skilled in the art, and the effects of the present disclosure are not limited to the above details. In other words, various additions, modifications, and partial deletions can be made without departing from the conceptual concept and gist of the present disclosure, and the conceptual concept and gist of the present disclosure can be derived from the details defined in the claims and their equivalents.

[0269] [Reference Number List]

[0270] Hout, Vout signal lines

[0271] PD Photodiode

[0272] S1, S2, 42 current source

[0273] 2 Logarithmic Transformation Circuit

[0274] 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2d detection circuit

[0275] 3,320 buffers

[0276] 4,330 subtractors

[0277] 5,340 quantizers

[0278] 6 Logic Circuits

[0279] 40,41 switch

[0280] 42 Current Source

[0281] 43 Analog-to-digital converter (ADC)

[0282] 100 Imaging Device

[0283] 300 Address event detection circuit

[0284] 310 Current-Voltage Conversion Circuit

[0285] 350 Transmission Circuit

Claims

1. An imaging circuit, comprising: Photoelectric conversion element, which converts incident light into photocurrent; a first transistor, converting the photocurrent into a voltage signal; a second transistor, amplifying the voltage signal; a third transistor controlling a current to be supplied to the first transistor; a fourth transistor, connected to the second transistor, a fifth transistor connected between a first node coupling the control electrode of the first transistor to the first terminal of the second transistor and a first reference potential, and A control unit is configured to enable switching between a first mode and a second mode, wherein in the first mode, the third transistor and the fourth transistor are turned on and the fifth transistor is used as a current source, and in the second mode, a pulse voltage is applied to the control electrode of the third transistor, the fourth transistor is turned on and the fifth transistor is turned off.

2. The imaging circuit according to claim 1, wherein: A buffer, a subtractor, and a quantizer are connected to the stage subsequent to the first node.

3. The imaging circuit according to claim 1, wherein: The control unit is configured to implement switching between the first mode and the second mode according to the measured amount of light.

4. The imaging circuit according to claim 1 , further comprising: A sixth transistor is connected between the photoelectric conversion element and a second node, wherein the second node couples the first terminal of the first transistor to the control electrode of the second transistor.

5. The imaging circuit according to claim 1, wherein: The first transistor and the second transistor are included in a multi-stage logarithmic conversion circuit.

6. The imaging circuit according to claim 1, further comprising: a first switch, a front stage of the first switch being connected to the control electrode of the first transistor and the first terminal of the second transistor; as well as a second switch, a front stage of the second switch being connected to the second terminal of the second transistor and the first terminal of the fourth transistor; The fourth transistor is connected between the second transistor and a second reference potential.

7. The imaging circuit according to claim 6, wherein: A buffer, a subtractor, and a quantizer are connected to the stage following the first switch, and an analog-to-digital converter is connected to the stage following the second switch.

8. The imaging circuit according to claim 7, wherein: In the first mode, the first switch is turned on and the second switch is turned off. In the second mode, the first switch is turned off and the second switch is turned on.

9. The imaging circuit according to claim 1, wherein: The photoelectric conversion element and the fifth transistor are mounted on different chips or substrates.

10. An imaging circuit, comprising: Photoelectric conversion element, which converts incident light into photocurrent; a first transistor, converting the photocurrent into a voltage signal; a second transistor, amplifying the voltage signal; a third transistor controlling a current to be supplied to the first transistor; a fourth transistor, connected to the second transistor, a fifth transistor connected between a first node and a first reference potential, the first node coupling the control electrode of the first transistor to the first terminal of the second transistor, a sixth transistor connected between a third node and a second reference potential, the third node coupling the second terminal of the second transistor to the second terminal of the fourth transistor; as well as A control unit is configured to enable switching between a first mode and a second mode, wherein in the first mode, the third transistor is turned on, the fourth transistor is turned off, the fifth transistor is used as a current source, and the sixth transistor is turned on, and in the second mode, a pulse voltage is applied to the control electrode of the third transistor, the fourth transistor is turned on, the fifth transistor is turned off, and the sixth transistor is turned off.

11. An imaging device comprising: analog-to-digital converters; as well as A plurality of imaging circuits according to any one of claims 1 to 3; The first terminal of the fourth transistor in each of the imaging circuits is connected to the analog-to-digital converter via a signal line.

12. The imaging device according to claim 11, further comprising: Third switch; Fourth switch; as well as Current source; Wherein, the third switch is connected between the signal line and the second reference potential; and The fourth switch and the current source are connected in series between the signal line and the second reference potential.

13. The imaging device according to claim 12, wherein: In the first mode, the third switch is turned on and the fourth switch is turned off, and in the second mode, the third switch is turned on and the fourth switch is turned off.

14. The imaging device according to claim 13, wherein The control unit is configured to implement switching between the first mode and the second mode according to the measured amount of light.

15. The imaging device according to claim 11, wherein The floating diffusion layers in at least two imaging circuits are connected via a seventh transistor.

16. The imaging device according to claim 11, wherein The second terminals of the first transistors in at least two of the imaging circuits are connected via an eighth transistor.

17. The imaging device according to claim 11, wherein The photoelectric conversion elements, the first transistor, the second transistor, the third transistor, and the fourth transistor of the plurality of imaging circuits are mounted on the same chip or substrate.

Images