Error handling flow management in memory devices

Abstract

The present disclosure relates to error handling flow management in memory devices. Systems and methods including a memory device and a processing device operatively coupled to the memory device are disclosed. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset interval, determining an ordered set of error handling operations to be performed on the data, determining a most recently performed error handling operation associated with the voltage offset interval; adjusting an order of the set of error handling operations by positioning the most recently performed error handling operation within a predetermined position in the order of error handling operation set; and performing one or more error handling operations in the set of error handling operations in the adjusted order until data associated with the read error is recovered.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to error handling flow management in memory devices. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] In one aspect, this disclosure provides a system comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations including: detecting read errors relating to data residing in a block of the memory device, wherein the block is associated with a voltage offset interval; determining an ordered set of error handling operations to be performed on the data; determining the most recently executed error handling operation associated with the voltage offset interval, wherein the most recently executed error handling operation is an error handling operation that has successfully recovered data associated with a previous read error occurring on the block associated with the voltage offset interval; adjusting the order of the set of error handling operations by positioning the most recently executed error handling operation within a predetermined position according to the order of the set of error handling operations; and performing one or more error handling operations in the adjusted order of the set of error handling operations until the data associated with the read error is recovered.

[0004] In another aspect, this disclosure further provides a method comprising: detecting a read error relating to data residing in a block of a memory device; determining an ordered set of error handling operations to be performed on the data; determining the most recently executed error handling operation, wherein the most recently executed error handling operation is an error handling operation that has successfully recovered data associated with a previous read error; and executing the most recently executed error handling operation as a first error handling operation in an error handling stream.

[0005] In another aspect, this disclosure further provides a non-transitory computer-readable storage medium including instructions that, when executed by a processing means operatively coupled to a memory, perform operations including: detecting read errors with respect to data residing in a block of the memory means, wherein the block is associated with a voltage offset interval; determining an ordered set of error handling operations to be performed on the data; determining the most recently executed error handling operation associated with the voltage offset interval, wherein the most recently executed error handling operation is an error handling operation that has successfully recovered data associated with a previous read error occurring on the block associated with the voltage offset interval; adjusting the order of the set of error handling operations by positioning the most recently executed error handling operation within a predetermined location according to the order of the set of error handling operations; and performing one or more error handling operations in the set of error handling operations in the adjusted order until the data associated with the read error is recovered. Attached Figure Description

[0006] This disclosure will be more fully understood from the embodiments given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 The illustration schematically depicts a time-voltage shift of a three-level memory cell, according to some embodiments of the present disclosure, capable of storing three data bits by programming the memory cell into eight charge states, the eight charge states differing in the amount of charge on the floating gate of the cell.

[0009] Figure 3 Example graphs depicting the correlation between threshold voltage offset and programming time (i.e., the time elapsed since the block was programmed) according to some embodiments of the present disclosure.

[0010] Figure 4 This describes the instance metadata maintained by the memory subsystem controller according to aspects of this disclosure.

[0011] Figure 5 This is a flowchart of an example method for error handling flow management performed according to some embodiments of the present disclosure.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0013] This disclosure relates to various aspects of error handling flow management in memory devices. The memory subsystem may be a memory device, a memory module, or a mixture of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request retrieval of data from the memory subsystem.

[0014] The memory subsystem can utilize one or more memory devices (including any combination of different types of non-volatile memory devices and / or volatile memory devices) to store data provided by the host system. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. Each memory device may contain one or more arrays of memory cells. A memory cell (“cell”) is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states associated with the number of bits stored. Logical states may be represented by binary values ​​(such as “0” and “1”) or combinations of such values.

[0015] Various data operations can be performed by the memory subsystem. Data operations can be host-initiated. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on a memory device at the memory subsystem and to read data from a memory device at the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., error correction code (ECC) codeword parity data), data version (e.g., to distinguish between new and old data being written), a valid bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0016] A memory device comprises multiple memory cells capable of storing one or more bits of information, depending on the type of memory cell. A memory cell can be programmed (written into the memory cell) by applying a voltage to it, causing a charge to be held within the cell; this voltage is called the "threshold voltage" and is denoted as Vt.

[0017] Memory devices can have a distribution that is narrower than the operating range of the control voltages allowed for each cell of the device. Therefore, multiple distributions (with "valleys" between them) can be precisely placed within an operating voltage window that allows each cell to store and reliably detect multiple bits, such as for a TLC. 3 = 8 distributions (7 valleys), 2 for MLC 2 = 4 distributions (3 valleys), etc. Voltage intervals (valley margins) are interspersed between the distributions, in which the memory cells of the device have no (or very few) their threshold voltages. Therefore, these valley margins can be used to separate various charge states by applying a read voltage corresponding to each valley, and the logic state of the cell can be determined by detection during a read operation. This effectively allows a single memory cell to store multiple bits of information: in 2... N A memory cell operating under a distribution (also known as a hierarchy) can store N bits of information. During a read operation, a 2 N -1 reading voltage to distinguish 2 N A distribution. Specifically, this can be achieved by displaying the measured threshold voltage V of the memory cell. T A read operation is performed by comparing the voltage level with one or more reference voltage levels corresponding to a known valley (e.g., the valley center) of the memory device.

[0018] Due to a phenomenon known as slow charge loss (SCL), the threshold voltage V of a memory cell decreases as the cell's charge diminishes. T This can vary over time, and the process is sometimes referred to as "time-to-voltage shift" (TVS). Since a typical cell stores negatively charged particles (electrons), the loss of electrons causes the voltage threshold to shift along the voltage axis towards a lower voltage threshold V. T Shifting. The threshold voltage can be changed rapidly initially (immediately after the memory cell is programmed), while simultaneously changing in a roughly logarithmic linear or power-law manner relative to the time t elapsed since the cell programming event (ΔV). T (t)=-C*t b The voltage can be slowed down over a longer period of time. In some embodiments of this disclosure, this can be achieved by maintaining a track of the time elapsed since the programming event and environmental conditions such as temperature for a particular memory partition (block, plane, etc.), and by offsetting the voltage of each valley value to be used during a read operation by ΔV. T Correlation to mitigate TVS, where the standard "baseline read level" threshold voltage V T (Immediately displayed by the cell after programming) The change is a voltage offset: V T →V T +ΔV T , where ΔV T It is negative due to charge loss. Although TVS is a continuous process and is related to ΔV TThe compensation for (t) can change over time, but in some embodiments, a discrete number of offset "intervals" can be used to achieve sufficient accuracy of the offset. Blocks can be associated with intervals using metadata (e.g., programmed within a specified time window and under similar environmental conditions, such as temperature). Since the time elapsed since programming and the temperature conditions are among the major factors affecting the amount of TVS, it can be inferred that blocks associated with the same interval will exhibit a similar distribution of threshold voltages for their memory cells, and therefore the same voltage offset will need to be applied to the base read level for read operations.

[0019] The memory subsystem controller may periodically perform a calibration process to associate blocks with one of intervals. Each interval may in turn be associated with a set of voltage offsets to be applied for read operations. The block-to-interval association is referred to herein as Auxiliary Read Metadata (ARM), which represents a portion of the broader state metric of the memory device. The state metric may also include the number of abandoned physical memory blocks (or other partitions), the number of times various physical blocks have been erased, the configuration type of cells in various memory partitions (e.g., single-level cells vs. multi-level cells), or any other type of information indicating the state of the memory device. The ARM may be stored in a metadata table maintained by the memory subsystem controller.

[0020] According to embodiments of this disclosure, TVS can be selectively tracked for programmed partitions grouped into families. Each family may contain one or more blocks programmed within a specified time window and / or a specified temperature window. Based on the partition-to-family grouping, an appropriate interval-specific read (voltage) offset is applied to a base read (voltage) level during a read operation. The base read level may also be stored in the metadata of the memory device. Upon receiving a read command, the memory subsystem controller may identify the family associated with the memory partition identified by the logical address specified in the read command and identify the current interval associated with the identified family. The memory subsystem controller may then determine a set of read offsets for the identified interval and calculate a new read voltage by superimposing the read offsets associated with the identified intervals onto the base read level. The memory subsystem controller may then perform a read operation using the new read voltage, as described in more detail below.

[0021] A "read error" refers to the memory subsystem's failure to verify one or more data items retrieved from the memory device in response to a read command. Read errors can be associated with host-initiated read operations or system-initiated scan operations and can occur due to reasons such as: the measured threshold voltage V exhibited by the memory cell. TRead errors can occur due to TVS (Transient Voltage Surge) causing a mismatch between the read voltage level and the requested data, or due to noise or interference. In a read error, a bit error in the read data exceeds the bit error that the underlying ECC (Electronic Code Correction) can correct, causing ECC failure and consequently a read error. In response to a read error, the memory subsystem can execute an error handling stream to attempt data recovery. The error handling stream may contain one or more error handling operations for data items retrieved from the memory device. Error handling operations may include one or more read retries using different parameters (e.g., variations in read voltage) compared to the initial read operation performed on the memory cell. Error handling operations may also include "deep error handling techniques," such as forward error correction (FEC) with various versions of reliability information, Hybrid Automatic Repeat Request (HARQ), etc.

[0022] In some implementations, the memory subsystem controller may use a default (e.g., static) error handling flow, where the order of error handling operations performed during the error handling flow remains the same for all blocks of the memory device. For example, upon entering the error handling flow, the memory subsystem controller may first perform a set of relatively low-latency operations, such as performing a predetermined number of read retries using different, relatively small (e.g., not exceeding a predefined threshold) read offsets applied to the base read level. In response to a low-latency step that successfully recovers data, the memory subsystem controller may exit the error handling flow to restart read and write operations. In response to a low-latency step that fails to recover data, the memory subsystem controller may perform the next error handling operation specified in the error handling flow. For example, the memory subsystem controller may perform a higher-latency step, such as applying a larger read offset compared to the read offset used in the low-latency step, or using deep error handling techniques (e.g., FEC, HARQ, etc.) to recover data.

[0023] In some implementations, in response to a sudden, systematic change to the memory subsystem, the memory subsystem controller can adjust the order of error handling operations performed during the error handling stream by implementing state-of-the-art error handling techniques. Systematic changes include parameter changes occurring throughout the memory subsystem, such as a sudden change in operating temperature (e.g., an increase of 20 degrees Celsius in operating temperature within seconds), power-on of the memory subsystem from an extended power-off period, etc. State-of-the-art error handling techniques may include executing the last successful error handling operation in the error handling stream as the first error handling operation in response to a new read error.

[0024] However, error handling operations can be time-consuming and impact the performance of the memory subsystem, leading to increased read times and / or performance degradation as observed by the host system. Therefore, due to TVS, implementing state-of-the-art error handling techniques for all blocks regardless of their associated intervals can increase the latency of the error handling stream executed by the memory subsystem. This is because, due to the different read offsets associated with different intervals, performing error handling operations that successfully recover data for blocks allocated to one interval can be ineffective for blocks allocated to different intervals.

[0025] This disclosure improves the efficiency of error handling operations by implementing a memory subsystem controller capable of adjusting the order of error handling operations in an error handling stream within a memory device based on the last error handling operation. Specifically, the memory subsystem controller can implement different error handling streams for different intervals and maintain an indication of the last error handling operation performed for each interval and / or each error handling stream. The last error handling operation may be an error handling operation performed during a previous error handling stream that successfully recovered data. The memory subsystem controller can maintain an indication of the last error handling operation for each interval and / or each error handling stream in a metadata table. Furthermore, the memory subsystem controller can maintain an indication of the position within the sequence of error handling operations in each error handling stream, where a corresponding last error handling operation will be performed during a subsequent error handling stream for each interval. Specifically, the last error handling position may instruct the memory subsystem controller to perform the last error handling operation as a first error handling operation in a subsequent error handling stream for a specific interval, as a second error handling operation in a subsequent error handling stream for a specific interval, etc. Therefore, based on the last error handling operation and the last error handling position, the memory subsystem controller can adjust the operation order of the corresponding error handling stream for each interval to perform the last error handling operation at the indicated last error handling position.

[0026] In an illustrative example, in response to a read error on a block associated with a specific range, the range's default error handling flow may instruct the memory subsystem controller to perform error handling operation 1, followed by error handling operation 2, and then error handling operation 3. In response to performing error handling operation 2, the memory subsystem controller may successfully recover the data associated with the read error. The memory subsystem controller may then register error handling operation 2 as the last successful error handling operation in the metadata table. In response to another read error, the memory subsystem controller may look up the last error handling operation (i.e., error handling operation 2) and the last error handling position (e.g., the first position) for the range in the metadata table. The memory subsystem controller may then execute error handling operation 2 as the first error handling operation in subsequent error handling flows for the range.

[0027] The advantages of this disclosure include, but are not limited to, improving the performance of the memory subsystem by reducing the latency of the error handling stream performed by the memory subsystem. This can result in improved performance and reduced power consumption of the memory subsystem. Furthermore, it can increase the lifespan of the memory subsystem. Although embodiments are described using memory cells of NAND flash memory, aspects of this disclosure can be applied to other types of memory subsystems.

[0028] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0029] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0030] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing power.

[0031] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without intermediate components), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0032] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0033] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple independent communication connections, and / or combinations of communication connections.

[0034] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0035] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0036] Each memory device 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), store multiple bits per cell. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0037] While non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0038] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0039] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0040] In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing operations that control the memory subsystem 110, including various processes, operations, logical flows, and routines for handling communication between the memory subsystem 110 and the host system 120.

[0041] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0043] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0044] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes a raw memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0045] Memory subsystem 110 includes an error handling flow management component 113 that can be used to implement error handling strategies according to embodiments of the present disclosure. In some embodiments, memory subsystem controller 115 includes at least a portion of the error handling flow management component 113. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, error handling flow management component 113 is part of host system 120, an application, or an operating system. Error handling flow management component 113 may manage block families associated with memory device 130, as described in more detail below.

[0046] Figure 2 This illustration schematically demonstrates how, according to some embodiments of the present disclosure, memory cells can be programmed into eight charge states Q. k (Also known as a hierarchy) The time-voltage shift (TVS) of a three-level memory cell (TLC) that stores three data bits differs in the amount of charge on the cell's storage gate among the eight charge states. Threshold voltage P (V T Q k The distribution of ) and the 7 valley margins VM n Separate. Programmed as the k-th charge state (Q) k Each cell can store a specific combination of 3 bits. For example, the charge state Q k It can store binary combinations of 101, as depicted. Other mappings from Qk to 3 bits are also possible. This charge state Q k Valley margin VM can be detected during read operations. k Internal control gate voltage V CG Sufficient to open the cell to source-drain current while maintaining the previous valley margin VM k-1 The control gate voltage is insufficient to open the cell to the source-drain current. Memory cells can be configured to store N=1 bits (SLC), N=2 bits (MLC), N=3 bits (TLC), N=4 bits (QLC), etc., depending on how much distribution can be fitted within the operating range of the control gate voltage (and with a sufficiently large valley margin). Even Figure 2 While TLC is described, the operations described in this disclosure can be applied to any N-bit memory cell.

[0047] Memory cells are typically joined by word lines (wires electrically connected to the cell's control gate) and, in one configuration (by selecting consecutive bit lines connected to the cell's source and drain electrodes), are programmed together as memory pages (e.g., 16KB or 32KB pages). As an example, Figure 2This illustrates a scenario where 3 bits are programmed in 3 passes. Other programming sequences can also be used, such as 1-pass and 2-pass programming. For Figure 2 In the example shown, during a read operation, the memory controller 115 can determine the control gate voltage V applied within the sixth valley margin VM6. CG The control gate voltage within the seventh valley margin VM7 is sufficient to open the cell to the source-drain current, and thus sufficient to open the cell. Therefore, the memory controller 115 can determine that the cell is in charge state Q7 corresponding to logic state 010 (i.e., XP:0,UP:1,LP:0).

[0048] use Figure 2 The solid line in the diagram depicts the distribution of threshold voltages that the memory cells have immediately after programming. Over time, due to slow charge loss, the distribution shifts (typically towards V). T The lower values), as shown by the shifted valley values ​​indicated by dashed lines. Therefore, the threshold voltage of various memory cells is shifted by a certain value ΔV. T The value may depend on the time elapsed since programming, environmental conditions (e.g., ambient temperature), etc. For optimal read operation, controller 115 (or error handling flow management component 113) can therefore utilize a corresponding offset V that is the same (or approximately the same) as the time voltage shift. R →V R +ΔV (where ΔV is typically less than zero) is used to adjust the base read level. In one embodiment, the offset can be determined (or estimated) as the difference between the center of the valley margin immediately following programming (e.g., center 202 of VM7) and the same-but shifted-center of the valley margin at a later point in time (e.g., new center 204). Figure 2 The diagram illustrates that TVS with different distributions (valleys) and valley margins can differ from each other. Figure 2 In the typical scenario described, TVS is large for larger charges Q and small for smaller charges.

[0049] like Figure 2As shown, TVS in the memory device is a continuous process. However, in some embodiments, sufficient accuracy of the voltage offset can be achieved using a set of discrete intervals and a corresponding set of discrete voltage offsets ΔV. In such embodiments, TVS can be addressed by setting several discrete intervals (e.g., five, eight, twenty, etc.) associated with various memory partitions. As an example, suppose that for valley 7, the desired optimal read position shift is 500 mV. In the case of six intervals, the offset of valley 7 can be defined as equally spaced, for example, 0 mV, N mV, 2N mV, 3N mV, 4N mV, 5N mV. Similarly, offsets for other valley values ​​can be defined. Interval offsets can be defined as not equally spaced but following different intervals. Interval-related data can be stored in metadata table 210. The associations of various memory partitions (grouped into families, as described in more detail below) with intervals can be stored in family-interval association 212; family-interval associations can change dynamically over time. For example, as memory cells continue to lose charge over time, due to temperature changes and program / erase cycles (PECs), corresponding memory partitions (groups into families) can be moved sequentially from lower-level partitions to higher-level partitions with larger voltage offset values. The partition-offset association 214 may also be stored in the metadata table 210. In some embodiments, the partition-offset association 214 may be static, but the family-partition association 212 may be adjusted (based on memory partition calibration) to account for the actual charge loss of the memory cells in the corresponding partition. In some embodiments, the family-partition association 212 may store the logical address of the memory partition, such as the LBA of the corresponding block, while the association between the LBA and the corresponding physical block address (PBA) may be stored outside the metadata table 210, for example, separately within a memory translation table stored in local memory 119 or one of the memory devices 130, 140. However, in some embodiments, the family-partition association 212 may additionally include LBA-to-PBA translations or store direct PBA-to-partition associations. Figure 2 The number of intervals, interval-offset correlation 214, and partition-interval correlation are schematically depicted using curved arrows. These can be based on the calibration of the memory device (or a similar type of memory device, for example, during design and manufacturing) to maximize performance and minimize read errors during read operations.

[0050] Threshold voltage offset depends on the time after programming (TAP). TAP is the time elapsed since the cell was written and is the first-level driver of the TVS. TAP can be estimated (e.g., inferred from data state metrics) or measured directly (e.g., from the controller clock). Cells, blocks, pages, block families, etc., are new (or relatively new) with (relatively) small TAPs and old (or relatively old) with (relatively) large TAPs. A time slice is the duration between two TAP points during which measurements can be performed (e.g., performing a reference calibration 8 to 12 minutes after programming). A time slice can be referenced by its center point (e.g., 10 minutes).

[0051] Memory devices can be grouped into block families, such that each block family contains one or more blocks programmed within a specified time window and possibly a specified temperature window. As mentioned above, since the elapsed time and temperature after programming are the main factors affecting time-voltage shift, it is presumed that all blocks and / or partitions within a single block family will exhibit similar threshold voltage distributions in the memory cells and therefore will require the same voltage offset for read operations. TVS also depends on the program erase cycle; however, for wear leveling, all blocks will have similar PECs, and therefore PEC is not a differentiating factor for TVS among blocks within a block family.

[0052] Block families can be created asynchronously relative to block programming events. In an illustrative example, whenever a specified time period Δt (e.g., a predetermined number of minutes) has elapsed since the creation of the last block family, or whenever the reference temperature of a memory cell (which is updated at specified time intervals) has changed by more than a specified threshold temperature ΔΘ since the creation of the current block family, then... Figure 1 The memory subsystem controller 115 can create (“enable”) new block families. Similarly, a family can be “deactivated” (and a new family can be created) after a time period Δt has elapsed since the family was created or when the reference temperature (in either direction) has changed by more than ΔΘ. The memory subsystem controller 115 can maintain identifiers for active block families associated with one or more blocks when they are programmed.

[0053] The newly created block families can be associated with interval 0. Subsequently, the memory subsystem controller can periodically perform a calibration process to offset each die of each block family against a predefined threshold voltage offset interval (within...). Figure 3 In the illustrative example, for a single valley value in the range 0-9, where the offset becomes more negative downwards along the y-axis (e.g., the offset of range 9 would have a higher magnitude compared to range 2, and both offsets are negative), it is associated with one of these values, and subsequently with the voltage offset to be applied for the read operation. The association between blocks and block families, as well as between block families and dies, and the threshold voltage offset range can be stored in the corresponding metadata tables maintained by the memory subsystem controller.

[0054] The voltage distribution is attributed to the temporal change in slow charge loss (SCL), which causes a drift in the threshold voltage level. According to various embodiments of this disclosure, time-varying voltage shifts are selectively tracked for programmed blocks grouped by block family, and an appropriate voltage offset based on the block affiliation of a particular block family is applied to the base read level to perform a read operation.

[0055] Figure 3 This illustration schematically depicts a set of predefined threshold voltage offset intervals (intervals 0 to 9) for a specific valley value according to embodiments of the present disclosure. Figure 3 As schematically shown, the threshold voltage offset curve can be subdivided into multiple threshold voltage offset intervals, such that each interval corresponds to a predetermined range of threshold voltage offset. Although Figure 3 The illustrative example defines ten intervals (0-9), but in other implementations, various other numbers of intervals may be used (e.g., 64 intervals). Based on a periodically performed calibration process, the memory subsystem controller associates each die of each block family with a threshold voltage offset interval, which defines a set of threshold voltage offsets that will be applied to the base voltage read level to perform a read operation, as described in more detail below.

[0056] Figure 4 The instance metadata maintained by the memory subsystem controller according to aspects of this disclosure is illustrated schematically. In some embodiments, the error handling flow management component 113 may maintain error handling metadata table 410 and error handling metadata table 420. In some embodiments, error handling metadata tables 410 and 420 may be stored in the memory of the memory subsystem (e.g., at memory devices 130, 140, local memory 119, etc.) and may be referenced by the error handling flow management component 113 to determine the error handling flow associated with a particular offset range. Error handling metadata tables 410 and 420 may be two separate metadata tables or combined into a single metadata table.

[0057] As illustrated in Error Handling Metadata Table 410, each interval may be associated with a corresponding error handling stream (e.g., F0, F1...F5). As illustrated in Error Handling Metadata Table 420, each error handling stream may be associated with a specific set of error handling operations to be executed in a particular order (e.g., operation order), parameter values ​​(e.g., read level adjustment values) for each error handling operation in each error handling stream (e.g., OP1 parameters, OP2 parameters, OP3 parameters, etc.), an indication of the last error handling operation performed, and the position of the last error handling operation to be performed within the operation order during subsequent error handling streams. The last error handling operation may be an error handling operation performed during a previous error handling stream that successfully recovered data.

[0058] The intervals associated with newer block families (i.e., recently created block families experiencing larger TVS due to the log-linear nature of SCL, where charge loss changes faster over time after programming compared to later times) can be associated with error handling streams, where error handling operations involve relatively large read level adjustments (e.g., applying a read offset greater than a predetermined threshold to the base read level). This is because compared to older block families (e.g., Figure 3 Blocks in block families 6-9 in the interval (in the block family), and newer block families (e.g., Figure 3 Blocks in the block family (within intervals 0-3) may experience significant shifts in threshold voltage over time (e.g., the threshold voltage changes rapidly immediately after a memory cell is programmed). Therefore, by performing a relatively wide read level adjustment exceeding the threshold criterion, the error handling stream management component 113 can increase the probability that the initial error handling operation using the error handling stream will successfully recover data. Thus, in some embodiments, each interval may be assigned a different set of error handling operations to be executed in a predetermined order. For example, relatively older intervals (e.g., intervals with relatively large TVS, such as...) Figure 3 Intervals 6-9 in the diagram can be specified as having an error handling flow, wherein the error handling operation includes the error handling flow management component 113 first performing a low-latency error handling step. In response to the low-latency error handling step failing to recover the desired data, the error handling flow management component 113 can then perform a deep error handling technique with higher latency and a higher success rate, such as HARQ and / or FEC with reliability (soft) information. In other embodiments, the error handling operations and / or the order of the error handling operations in the error handling flow may be the same for each interval.

[0059] Error handling flow management component 113 can perform error handling operations associated with an interval to a block of the same interval's block family. In some embodiments, the association between an interval and a corresponding error handling flow can be determined and set during the manufacture of memory subsystem 110 or during the programming and / or calibration of memory subsystem 110. Thus, each interval can be associated with an error handling flow having a specific set of error handling operations performed in a particular order.

[0060] In some embodiments, the memory subsystem controller 115 may adjust the error handling stream for each interval by reordering the error handling stream so that the last error handling operation of each corresponding interval is moved to a predetermined position within the operation order of the default error handling stream. The predetermined position may be set during the programming and / or calibration of the memory subsystem 110. The default error handling stream may refer to the set of error handling streams for each block of the memory subsystem during the programming and / or calibration of the memory subsystem 110, and / or to the error handling stream initially associated with each interval (e.g., F0, F1...F5). For example, the default error handling stream for error handling stream F0 may include performing error handling operation 1 (OP1), followed by error handling operation 2 (OP2), and then error handling operation 3 (OP3). By maintaining a record of each interval of error handling operations that successfully recovered data during the most recently executed error handling stream, the error handling stream management component 113 may track the last error handling operation of each most recently executed error handling stream via metadata table 420. The order of error handling operations for a given interval can be adjusted based on the last error handling operation (the error handling operation that successfully recovered data and was performed by the error handling flow management component 113 during the most recent error handling flow). Specifically, the error handling flow management component 113 can perform the last error handling operation at the position indicated in the operation order as shown in the metadata table 420 during subsequent error handling flows.

[0061] The error handling final position can indicate to the error handling flow management component 113 at which location within the operation sequence for a corresponding interval and during subsequent error handling flows assigned to said interval, the error handling final operation is performed. The error handling final position can be set during the programming and / or calibration of the memory subsystem 110. Specifically, each error handling final position for each error handling flow and / or interval can be selected and set during the programming and / or calibration of the memory subsystem 110. In some embodiments, the error handling final position can be set as a first position within the error handling flow. Thus, the error handling final operation can be performed first in subsequent processing flows. In some embodiments, the error handling final position can be set as a second position within the error handling flow. For example, the first error handling operation may include a read retry operation, and the second error handling operation may include the error handling final operation. In other embodiments, the error handling final position can be any position within the error handling flow. For example, in response to an error handling last position indication that the last error handling operation will be performed in a second order during a subsequent error handling stream, the error handling stream management component 113 may perform a first error handling operation of the error handling stream during the subsequent error handling stream, then perform a last error handling operation in response to the first error handling operation failing to recover data, and subsequently perform the remaining error handling operations in the error handling stream until the data is successfully recovered. In some embodiments, the error handling stream management component 113 may perform the last error handling operation first in a subsequent processing stream, rather than looking up the last error handling position in the metadata table. Specifically, during each error handling stream, the error handling stream management component 113 may determine the last error handling operation, perform the last error handling operation as the first error handling operation in the error handling stream, and perform the remaining error handling operations in the error handling stream in response to the last error handling operation failing to recover data until the data is recovered.

[0062] In an illustrative example, in response to a read error on a block associated with a range (e.g., range 0 (F0)), the default error handling flow for range 0 may instruct the error handling flow management component 113 to perform error handling operation 1, followed by error handling operation 2, and then error handling operation 3. In response to performing error handling operation 2, the error handling flow management component 113 may successfully recover the data associated with the read error. The error handling flow management component 113 may then register error handling operation 2 as the last error handling operation in the metadata table 420. In response to another read error, the error handling flow management component 113 may look up the last error handling operation (i.e., error handling operation 2) and the last error handling position (e.g., first) in the metadata table 420. The error handling flow management component 113 may then execute error handling operation 2 as the first operation in a subsequent error handling flow.

[0063] In response to the failure of error handling operation 2 to recover data, error handling flow management component 113 may execute the remaining error handling operations specified by the error handling flow (e.g., execute error handling operation 1, then execute error handling operation 3). In response to the recovery of data by an error handling operation, error handling flow management component 113 may update metadata table 420 to indicate which error handling operation successfully recovered data. In response to the successful recovery of data by error handling operation 2, error handling flow management component 113 may terminate the execution of any other operations specified by the error handling flow and maintain error handling operation 2 as the last error handling operation in metadata table 420.

[0064] As discussed above, each error handling stream (e.g., F0, F1...F5) may contain different error handling operations that will be executed by the error handling stream management component 113 in a predetermined order until the desired data of the read operation is successfully recovered. Error handling operations may include one or more read retries using different parameters, such as applying different read offsets to the base read level, or deep error handling techniques such as FEC and HARQ. In some embodiments, one error handling operation may include a first set of read retries applying a set of read offsets to the base read level, and another error handling operation may include a second set of read retries applying different sets of read offsets (with different values) to the base read level. One or more error handling operations in one error handling stream may not be included in another error handling stream, and vice versa. In some embodiments, multiple intervals may be associated with the same error handling stream.

[0065] Figure 5 This is a flowchart of an example method 500 for error handling flow management implemented by a memory subsystem controller operating according to some embodiments of the present disclosure. Method 500 may be performed by processing logic that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The error handling flow management component 113 is executed. Although shown in a specific order or sequence, the order of operations may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated operations may be executed in different orders, and some operations may be executed in parallel. In addition, in some embodiments, one or more operations may be omitted. Therefore, not all of the illustrated operations are required in every embodiment, and other process flows are possible.

[0066] At operation 510, the processing logic detects read errors regarding data in a block residing in the memory device. In some embodiments, the block may be part of a block family associated with a voltage offset range.

[0067] At operation 520, the processing logic determines an ordered set of error handling operations to be executed to recover data associated with the read error. For example, the processing logic may use metadata tables (e.g., metadata tables 410 and / or 420) to determine which error handling stream is associated with the voltage offset range and the order of the error handling operations (along with their parameters) specified by the error handling stream.

[0068] At operation 530, the processing logic determines the last error handling operation associated with the voltage offset interval. The last error handling operation may be an error handling operation that successfully recovered data during the processing logic's execution of a recent error handling stream (e.g., a recently executed error handling operation) on the block associated with the voltage offset interval. The processing logic can maintain an indication of the last error handling operation in a metadata table.

[0069] At operation 540, the processing logic adjusts the order of the error handling operation set by positioning the last error handling operation within a predetermined position according to the order of the error handling operation set. The predetermined position indicates to the processing logic at which location within the operation order of the corresponding interval to execute the last error handling operation in the error handling operation order. The processing logic may maintain the indication of the predetermined position in the metadata table. The predetermined position may be set during at least one of the programming or calibration of the memory device.

[0070] At operation 550, the processing logic executes one or more error handling operations from the set of error handling operations in an adjusted order until the data associated with the read error is recovered. In response to the adjusted order of the error handling operations among the multiple error handling operations recovering the data associated with the read error, the processing logic can update the metadata table by replacing the last error handling operation of the previous error handling operation with the last operation of the current error handling operation.

[0071] Figure 6 An example machine of computer system 600 is shown, wherein a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., run an operating system to execute commands corresponding to the controller). Figure 1(Operation of the error handling flow management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0072] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network device, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is shown, it should also be understood that the term "machine" includes any collection of machines that individually or collectively execute a set (or more) of instructions to perform any one or more of the methods discussed herein.

[0073] The example computer system 600 includes processing devices 602 communicating with each other via a bus 630, main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage system 618. Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 to perform the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 for communicating via the network 620.

[0074] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) on which one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein are stored. The instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0075] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 1 The error handling flow management component 113 provides functional instructions. While machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine to cause a machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0076] Some parts of the previously described algorithms and symbolic representations of operations on data bits in computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, considered as a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for common use, it has proven convenient sometimes to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0077] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of a computer system into other data representing physical quantities similarly represented in the memory or registers or other such information storage systems of a computer system.

[0078] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0079] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to execute the methods. Structures for various such systems will be presented as described below. Furthermore, embodiments of this disclosure are described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0080] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0081] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A memory system, comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations including: detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset interval; determining an ordered set of error handling operations to be performed on the data based on a metadata table; determining a most recently performed error handling operation associated with the voltage offset interval, wherein the most recently performed error handling operation is an error handling operation that has successfully recovered data associated with a previous read error that occurred on a block associated with the voltage offset interval; adjusting an order of the set of error handling operations by positioning the most recently performed error handling operation within a predetermined position in the order of the set of error handling operations; and performing one or more error handling operations of the set of error handling operations in the adjusted order until data associated with the read error is recovered.

2. The memory system of claim 1, wherein the ordered set of error handling operations is based on the voltage offset interval associated with the block.

3. The memory system of claim 1, wherein the processing device is to perform further operations including: maintaining a record in the metadata table indicating an error handling operation that successfully recovered data.

4. The memory system of claim 1, wherein the processing device is to perform further operations including: maintaining an indication in the metadata table of a location of the predetermined position in an error handling flow.

5. The memory system of claim 1, wherein the processing device is to perform further operations including: in response to an error handling operation of a plurality of error handling operations recovering data associated with the read error in the adjusted order, updating the metadata table by replacing a most recently performed error handling operation with the error handling operation.

6. The memory system of claim 1, wherein the predetermined position is set during at least one of a program or calibration of the memory device.

7. The memory system of claim 1, wherein the order is specified in the metadata table.

8. A method for memory operations, comprising: detecting a read error with respect to data residing in a block of a memory device, wherein the block is associated with a voltage offset interval; determining an ordered set of error handling operations to be performed on the data based on a metadata table, determining a most recently performed error handling operation associated with the voltage offset interval, wherein the most recently performed error handling operation is an error handling operation that has successfully recovered data associated with a previous read error that occurred on a block associated with the voltage offset interval; adjusting an order of the set of error handling operations by positioning the most recently performed error handling operation within a predetermined position in the order of the set of error handling operations; and performing one or more error handling operations of the set of error handling operations in the adjusted order until data associated with the read error is recovered. ​ performing one or more error handling operations of a set of error handling operations in an adjusted order until data associated with the read error is recovered.

9. The method of claim 8, wherein the ordered set of error handling operations is based on the voltage offset bin associated with the block.

10. The method of claim 8, further comprising: maintaining, in the metadata table, a record indicating an error handling operation that successfully recovered data.

11. The method of claim 8, further comprising: updating the metadata table by replacing the most recently performed error handling operation with an error handling operation in response to the error handling operation recovering data associated with the read error in an adjusted order.

12. The method of claim 8, further comprising: maintaining, in the metadata table, an indication that the most recently performed error handling operation is to be performed first in a subsequent error handling flow.

13. The method of claim 8, wherein the order of the set of error handling operations is specified in the metadata table.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device operatively coupled to a memory, perform operations comprising: detecting a read error with respect to data residing in a block of a memory device, wherein the block is associated with a voltage offset bin; determining, based on a metadata table, an ordered set of error handling operations to be performed on the data, determining a most recently performed error handling operation associated with the voltage offset bin, wherein the most recently performed error handling operation is an error handling operation that has successfully recovered data associated with a previous read error that occurred on a block associated with the voltage offset bin; adjusting the order of a set of error handling operations by positioning the most recently performed error handling operation within a predetermined position in the order of the set of error handling operations; and performing one or more error handling operations of the set of error handling operations in the adjusted order until data associated with the read error is recovered.

15. The non-transitory computer-readable storage medium of claim 14, wherein the ordered set of error handling operations is based on the voltage offset bin associated with the block.

16. The non-transitory computer-readable storage medium of claim 14, wherein the processing device performs further operations comprising: maintaining, in the metadata table, a record indicating an error handling operation that successfully recovered data.

17. The non-transitory computer-readable storage medium of claim 14, wherein the processing device performs further operations comprising: maintaining, in the metadata table, an indication of a location of the predetermined position in an error handling flow.

18. The non-transitory computer-readable storage medium of claim 14, wherein the processing device will perform further operations comprising: ​ In response to an error handling operation of the plurality of error handling operations recovering data associated with the read error in the adjusted order, updating the metadata table by replacing a most recently performed error handling operation with the error handling operation.

19. The non-transitory computer readable storage medium of claim 14, wherein the predetermined location is set during at least one of programming or calibration of the memory device.

20. The non-transitory computer readable storage medium of claim 14, wherein the order is specified in the metadata table.

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