Output circuit, display driver, and display device

Abstract

The present application aims to provide an output circuit, a display driver including the output circuit, and a display device, which are capable of realizing a high-reliability operation and achieving a small area. The present application includes: a PMOS transistor switch that outputs a positive voltage signal from an output terminal in an on state; an NMOS transistor switch that outputs a negative voltage signal from the output terminal in an on state; and a voltage control circuit that supplies, to a back gate of the PMOS transistor switch, a voltage obtained by performing level shifting on a voltage of a source or a drain of the PMOS transistor switch in the on state to a high potential side, and supplies, to a back gate of the NMOS transistor switch, a voltage obtained by performing level shifting on a voltage of a source or a drain of the NMOS transistor switch in the on state to a low potential side.

Description

Technical Field

[0001] This invention relates to an output circuit that outputs positive and negative voltages, a display driver that drives a display panel, and a display device. Background Technology

[0002] Currently, as the main display device, liquid crystal display devices that use liquid crystal panels driven by an active matrix are commonly known.

[0003] The liquid crystal panel has multiple data lines and multiple gate lines arranged in a crisscross pattern. The data lines extend vertically along the two-dimensional image, and the gate lines extend horizontally along the two-dimensional image. Furthermore, a pixel portion connected to the data lines and gate lines is formed at each intersection of the data lines and gate lines. The liquid crystal display device includes both the liquid crystal panel and a data driver. The data driver supplies grayscale data signals (also called grayscale voltage signals) with analog voltage values ​​corresponding to the brightness levels of each pixel to the data lines using a unit data pulse during a horizontal scan period. To prevent degradation of the liquid crystal panel, the data driver performs polarity reversal driving, that is, it alternately supplies positive and negative grayscale data signals to the liquid crystal panel during each predetermined frame period.

[0004] As an output circuit for performing this polarity reversal drive, the following output circuit is proposed: a switch group is provided, which receives a positive polarity driving voltage and a negative polarity driving voltage corresponding to the grayscale data signal, and alternately selects one of the two to output to the liquid crystal panel (for example, see Patent Document 1). Figures 9-11 (SW1~SW12).

[0005] In the output circuit described in Patent Document 1, a positive drive voltage (5V) is output from the positive output pad OUT1 by using switches SW1 to SW12 (as described in the document). Figure 9 The state is switched to the state where the output pad OUT1 outputs a negative polarity drive voltage (-5V) (as described in the literature). Figure 11 (state). Furthermore, during this polarity switch, in the output circuit described in Patent Document 1, as in the document... Figure 10 The diagram shows the process of temporarily setting one end of each switch to 0V before switching to the state described in the document. Figure 11 The state shown. Therefore, the withstand voltage of each switch can be constructed using low-voltage components that are half the range of the liquid crystal driving voltage.

[0006] [Existing Technical Documents]

[0007] [Patent Literature]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-102211 SUMMARY

[0009] [Problems to be Solved by the Invention]

[0010] In Patent Document 1 (the document Figures 9-11 ), the output selection switches (SW5, SW6, SW7, SW8) connected to OUT1, OUT2 can be configured with low-voltage elements having a withstand voltage of one-half of the liquid crystal drive voltage range, but in the case where the switches are configured with low-voltage transistor switches having a withstand voltage of one-half of the liquid crystal drive voltage range, it is not suitable to use a complementary switch in which a P-channel type and an N-channel type are combined, and it is necessary to configure the switches with a single-conductivity-type transistor switch. The reason for this will be described below.

[0011] For example, the range of voltage values of a positive polarity drive voltage (gray scale voltage signal) is set to VGND (0 V) to VDDH (5 V), and the range of voltage values of a negative polarity drive voltage (gray scale voltage signal) is set to VDDL (-5 V) to VGND (0 V).

[0012] Here, first, a case where the output selection switch SW5 of the output positive polarity drive voltage shown in Patent Document 1 (the document Figures 9-11 ) is configured with an N-channel type transistor switch will be considered.

[0013] The N-channel type transistor switch SW5 outputs a positive polarity drive voltage supplied to the first terminal, and therefore the control terminal thereof is supplied with a positive power supply voltage VDDH at maximum. Here, when the output terminal OUT1 connected to the second terminal of the N-channel type transistor switch SW5 is driven to a reference power supply voltage VGND due to a polarity inversion from the negative polarity to the positive polarity, if the output terminal OUT1 does not sufficiently approach the reference power supply voltage VGND from the drive voltage of the negative polarity, there is a risk that the voltage difference between the control terminal of the N-channel type transistor switch SW5 and the output terminal OUT1 connected to the second terminal exceeds the withstand voltage. In order to avoid this risk, it is necessary to sufficiently ensure the drive time of the reference power supply voltage VGND to the output terminal OUT1 at the time of polarity inversion, and it is difficult to achieve high-speed drive under the operation condition of a short output period. In addition, in the case where the voltage value of the positive polarity drive voltage approaches the positive power supply voltage VDDH, even if the positive power supply voltage VDDH is supplied to the control terminal of the N-channel type transistor switch SW5, it is not possible to output a voltage range from the positive power supply voltage VDDH to the threshold voltage of the N-channel type transistor.

[0014] Next, a case where the output selection switch SW5 is configured with a P-channel type transistor switch will be considered.

[0015] The P-channel transistor switch SW5 outputs a drive voltage of positive polarity supplied to the first terminal, and thus controls in a manner that a voltage within a withstand voltage on the low voltage side with respect to the drive voltage of positive polarity is supplied to the control terminal thereof. In this case, there is no risk that the voltage difference between the control terminal of the P-channel transistor switch SW5 and the output terminal OUT1 connected to the second terminal exceeds the withstand voltage. In addition, as long as the supply voltage of the control terminal of the P-channel transistor switch SW5 is appropriately controlled with respect to the drive voltage of positive polarity, an arbitrary drive voltage of positive polarity can be output by the P-channel transistor switch SW5.

[0016] Therefore, the output selection switch that outputs a drive voltage of positive polarity is most suitable to be constituted by a P-channel transistor switch alone. Similarly, the output selection switch that outputs a drive voltage of negative polarity is most suitable to be constituted by an N-channel transistor switch alone.

[0017] Incidentally, a data driver of a display device generally includes a Metal Oxide Semiconductor (MOS) transistor circuit on a Large Scale Integrated Circuit (LSI) of silicon, and an output circuit including the output selection switch also includes a MOS transistor circuit. Since the output selection switch of the MOS transistor has a back gate, the withstand voltage between the back gate terminal and the other terminal also has to be set to one-half of the liquid crystal drive voltage. As for the supply voltage supplied to the back gate terminal, generally, in a P-type Metal Oxide Semiconductor (PMOS) transistor, the voltage on the upper limit side of the voltage range of the source terminal or a power supply voltage commonly connected to the source terminal, and in an N-type Metal Oxide Semiconductor (NMOS) transistor, the voltage on the lower limit side of the voltage range of the source terminal or a power supply voltage commonly connected to the source terminal.

[0018] Here, a case in which the output selection switch that outputs a drive voltage of positive polarity is constituted by a PMOS transistor switch alone is considered.

[0019] In a case in which the voltage applied to the back gate of the PMOS transistor switch is a positive power supply voltage VDDH on the upper limit side of the voltage range of the source terminal, and the gate terminal of the PMOS transistor switch takes a voltage lower than a reference power supply voltage VGND, there is a risk that the voltage difference between the back gate terminal and the gate terminal exceeds the withstand voltage.

[0020] On the other hand, in the case where the back gate terminal of the PMOS transistor switch is commonly connected with the source terminal, there is no risk of exceeding the withstand voltage. Also, in the case where the output selection switch of the drive voltage of the negative polarity is constituted by the NMOS transistor switch alone, when the back gate terminal of the NMOS transistor switch is commonly connected with the source terminal, there is also no risk of exceeding the withstand voltage.

[0021] However, in the case where the PMOS transistor switch is provided as a single conductivity type MOS transistor switch with the source terminal commonly connected with the back gate terminal, there is a mode in which current flows outside the transistor due to the action of the parasitic bipolar transistor.

[0022] This will be described. Further, for the sake of convenience of description, it is assumed that the output circuit is formed on a P-type semiconductor substrate.

[0023] Figure 1 is a cross-sectional view showing a PMOS transistor Qs as an output selection switch and a parasitic bipolar transistor formed in the PMOS transistor Qs.

[0024] The PMOS transistor Qs is formed in an N-type well NW formed on the surface of a P-type semiconductor substrate PS, for example. The gate G of the PMOS transistor Qs is constituted by a gate insulating film Go and a gate electrode Gp stacked on the P-type semiconductor substrate PS. The drain D and the source S are constituted by a high-concentration P-type diffusion region Rd and a P-type diffusion region Rs disposed apart from each other by a gate length in the N-type well NW. In the vicinity of the source in the N-type well NW, a high-concentration N-type diffusion region BG as a back gate terminal for applying a potential to the back gate of the PMOS transistor Qs is formed. The back gate terminal and the source S are commonly connected to the output terminal of a positive amplifier AMP which generates a drive voltage of the positive polarity and outputs, via a wiring. The drain D is connected to a data line load LOD which is a capacitive load of a liquid crystal panel, for example, via a wiring. Further, around the N-type well NW in the surface of the P-type semiconductor substrate PS, a high-concentration P-type diffusion region Rc for applying a negative power supply voltage VDDL to the P-type semiconductor substrate PS is formed.

[0025] Hereinafter, as shown in Figure 1 , the action in the case where the output selection switch includes a single conductivity type MOS transistor with the source S (Rs) and the back gate terminal (BG) commonly connected will be described. Further, the driving of the liquid crystal panel will be described taking column inversion driving as an example. In the column inversion driving, a drive voltage of the same polarity is supplied during the data period in one frame.

[0026] For example, when the data line load LOD discharges under positive voltage, the low-voltage driving voltage is supplied to the data line load LOD from the positive amplifier AMP via the PMOS transistor Qs. This results in low voltages at the drain (D), source (S), and back gate of the PMOS transistor Qs on the output terminal side. Therefore, if the PMOS transistor Qs is in the on state, then... Figure 1 As shown by the thick arrow, current flows from the data line load LOD to the positive amplifier AMP side.

[0027] However, at this time, such as Figure 1 As shown, the parasitic bipolar transistor PaB formed between the P-type diffused regions Rd and Rc of the drain D of the PMOS transistor Qs becomes conductive. Therefore, as Figure 1 As shown by the thick arrow, current flows from the data line load LOD through the P-type diffusion region Rd, the N-type well NW, the P-type semiconductor substrate PS, and the P-type diffusion region Rc.

[0028] That is, such as Figure 1 As shown, a parasitic PNP transistor PaB is formed, which uses the P-type diffusion region Rd of the PMOS transistor Qs on the LOD side of the data line load as the emitter, the P-type semiconductor substrate PS supplied with the negative power supply voltage VDDL as the collector, and the N-type well NM connected to the P-type diffusion region Rc that serves as the back gate terminal of the PMOS transistor Qs as the base.

[0029] Therefore, when the voltage difference between the drive voltage output from the positive amplifier AMP and the voltage of the data line load LOD exceeds the threshold voltage (absolute value) of the parasitic bipolar transistor PaB, for example, when the change in drive voltage is large and its rate of change is fast, a parasitic bipolar current IR temporarily flows from the data line load LOD independently of the current flowing in the PMOS transistor Qs. Particularly in data drivers, this parasitic bipolar current IR can be generated simultaneously in multiple output circuits, thus causing adverse effects on the operation of surrounding circuits, operational malfunctions such as discharge operations due to circuit design deviations, and in the worst case, concerns about inducing latch-up. Furthermore, the same problem occurs in NMOS transistors that act as output selection switches when driven by a negative voltage, similar to that of the PMOS transistor Qs.

[0030] Therefore, the object of the present invention is to provide an output circuit, a display driver and a display device including the output circuit, wherein the output circuit, as an output circuit that selectively outputs one of a positive and a negative voltage signal, can achieve highly reliable operation and save area.

[0031] [Technical means to solve the problem]

[0032] The output circuit of the present invention comprises: a positive voltage signal supply circuit, which supplies a positive voltage signal, which is higher than the reference power supply voltage, to a first node or cuts off the supply of the positive voltage signal to the first node; a negative voltage signal supply circuit, which supplies a negative voltage signal, which is lower than the reference power supply voltage, to a second node or cuts off the supply of the negative voltage signal to the second node; a first output terminal; a first switch, including a first PMOS transistor switch with its source connected to the first node and its drain connected to the first output terminal, which connects the first output terminal and the first node in a conducting state and disconnects the connection between the first output terminal and the first node in a de-conducting state; a second switch, including a first NMOS transistor switch with its source connected to the second node and its drain connected to the first output terminal, which connects the first output terminal and the second node in a conducting state and disconnects the connection between the first output terminal and the second node in a de-conducting state; a third switch, which applies the reference power supply voltage to the first node in a conducting state and stops the application of the reference power supply voltage to the first node in a de-conducting state; and a fourth switch, which applies the reference power supply voltage to the second node in a conducting state. The circuit comprises: a reference power supply voltage, wherein the application of the reference power supply voltage to the second node is stopped when the switch is in the off state; a first voltage control circuit, connected to the gate of the first switch, controls the first switch to be in the on state; a second voltage control circuit, connected to the gate of the second switch, controls the second switch to be in the on state; a first control unit, connected to the gate of the first switch, controls the first switch to be in the off state; a second control unit, connected to the gate of the second switch, controls the second switch to be in the off state; a third voltage control circuit, which uses the voltage of the source or drain of the first PMOS transistor switch as a first voltage and supplies a second voltage, after level shifting the first voltage to a high potential side, to the back gate of the first PMOS transistor switch, or supplies the reference power supply voltage to the back gate of the first PMOS transistor switch; and a fourth voltage control circuit, which uses the voltage of the source or drain of the first NMOS transistor switch as a third voltage and supplies a fourth voltage, after level shifting the third voltage to a low potential side, to the back gate of the first NMOS transistor switch, or supplies the reference power supply voltage to the back gate of the first NMOS transistor switch.

[0033] The display driver of the present invention includes a plurality of output circuits, from which a plurality of grayscale voltage signals having positive or negative voltage values ​​are output for driving a plurality of data lines of a liquid crystal display panel.

[0034] The display device of the present application has a display driver including a plurality of the output circuit, outputs a plurality of gray scale voltage signals having a voltage value of positive polarity or negative polarity from the plurality of output circuits, and a liquid crystal display panel having a plurality of data lines that receive the plurality of gray scale voltage signals.

[0035] [Effects of the Invention]

[0036] According to the present application, even if a single conductivity type MOS transistor is used as an output selection switch that selectively outputs one of voltage signals of positive polarity and negative polarity to a capacitive load, generation of a parasitic bipolar transistor parasitic to the MOS transistor is suppressed, and the MOS transistor is low-voltage withstanding.

[0037] Thus, according to the present application, an output circuit that is area-saving and highly reliable when selectively outputting one of voltage signals of positive polarity and negative polarity can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 is a cross-sectional view of a semiconductor substrate of a PMOS transistor and a parasitic bipolar transistor parasitic to the PMOS transistor.

[0039] Figure 2 is a circuit diagram showing an example of the structure of the output circuit 100.

[0040] Figure 3A is a waveform chart showing a waveform of the back gate voltage Vbg11 generated by the voltage control circuit 55 in response to the positive voltage signal Vp.

[0041] Figure 3B is a waveform chart showing a waveform of the back gate voltage Vbg21 generated by the voltage control circuit 65 in response to the negative voltage signal Vn.

[0042] Figure 4 is a timing chart showing an example of the control signal S12 to the control signal S14, the control signal S22 to the control signal S24 generated by the control section 101.

[0043] Figure 5 is a circuit diagram showing a voltage control circuit 55-1 as a first embodiment of the voltage control circuit 55.

[0044] Figure 6 is a circuit diagram showing a voltage control circuit 55-2 as a second embodiment of the voltage control circuit 55.

[0045] Figure 7 is a circuit diagram showing a voltage control circuit 55-3 as a third embodiment of the voltage control circuit 55.

[0046] Figure 8 is a circuit diagram showing a voltage control circuit 55-4 as a fourth embodiment of the voltage control circuit 55.

[0047] Figure 9 is a circuit diagram showing a voltage control circuit 65-1 as a first embodiment of the voltage control circuit 65.

[0048] Figure 10 is a circuit diagram showing a voltage control circuit 50-1 as a first embodiment of the voltage control circuit 50.

[0049] Figure 11 is a circuit diagram showing a voltage control circuit 50-2 as a second embodiment of the voltage control circuit 50.

[0050] Figure 12 is a circuit diagram showing a voltage control circuit 60-1 as a first embodiment of the voltage control circuit 60.

[0051] Figure 13 is a circuit diagram showing a voltage control circuit 60-2 as a second embodiment of the voltage control circuit 60.

[0052] Figure 14 is a circuit diagram showing a structure of an output circuit 200 as a second embodiment of the output circuit of the present application.

[0053] Figure 15 is a block diagram showing a structure of a display device 400 having a data driver 73 including the output circuit of the present application.

[0054] Figure 16 is a block diagram showing an internal structure of the data driver 73.

[0055] [Explanation of symbols]

[0056] 10A: positive voltage signal supply circuit

[0057] 11, 21: output selection switch

[0058] 12 to 14, 22 to 24: switch

[0059] 20A: negative voltage signal supply circuit

[0060] 50, 55, 60, 65: voltage control circuit

[0061] 73: data driver

[0062] 100, 200: output circuit

[0063] 400: display device DETAILED DESCRIPTION

[0064] [Example 1]

[0065] Figure 2 is a circuit diagram showing the configuration of an output circuit 100 as an example of the output circuit of the present application.

[0066] First, the kinds of power supply voltages supplied to the output circuit 100 and the relationship between the power supply voltages and the element withstand voltage will be described.

[0067] As the power supply to the output circuit 100, at least three power supplies having the following magnitude relationship, a reference power supply voltage VGND, a positive power supply voltage VDDH, and a negative power supply voltage VDDL are included.

[0068] VDDL < VGND < VDDH

[0069] Here, a voltage higher than the reference power supply voltage VGND is described as a positive voltage, and a voltage lower than the reference power supply voltage VGND is described as a negative voltage.

[0070] In this regard, the withstand voltage VDDT is set to as low a value as possible in order to seek reduction in circuit area (cost reduction) accompanying low withstand voltage, although it is larger than the voltage difference a: (VDDH-VGND) and the voltage difference b: (|VDDL-VGND|) and does not exceed the voltage difference c: (VDDH-VDDL).

[0071] Further, as the power supply voltages supplied to the output circuit 100, in addition to the reference power supply voltage VGND, the positive power supply voltage VDDH, and the negative power supply voltage VDDL, a positive-side low power supply voltage VCCH and a negative-side low power supply voltage VCCL represented by the following magnitude relationship can be included.

[0072] VDDL < VCCL < VGND < VCCH < VDDH

[0073] The output circuit 100 receives a signal having a higher potential than the reference power supply voltage VGND as a positive voltage signal Vpi, and receives a signal having a potential lower than the reference power supply voltage VGND as a negative voltage signal Vni. Then, the output circuit 100 alternately selects one of a positive voltage signal Vp and a negative voltage signal Vn amplified from the positive voltage signal Vpi and the negative voltage signal Vni, respectively, at a prescribed timing, and outputs to one capacitive load (for example, a data line of a liquid crystal display device). Thus, the output circuit 100 drives (polarity inversion drives) the capacitive load.

[0074] As Figure 2As shown, the output circuit 100 includes: output terminals DL1, nodes Nsll and Ns21 connected to a capacitive load, a positive voltage signal supply circuit 10A, a negative voltage signal supply circuit 20A, output selection switches 11 and 21, first to fourth voltage control circuits (50, 60, 55, 65), switches 12 and 22, first and second control units (13, 23), and a control section 101.

[0075] The positive voltage signal supply circuit 10A controls supply and cutoff of an arbitrary positive voltage signal Vp (VGND < Vp < VDDH) having a voltage value on the high potential side with respect to the reference power supply voltage VGND to the node Nsll. The negative voltage signal supply circuit 20A controls supply and cutoff of an arbitrary negative voltage signal Vn (VGND > Vn > VDDL) having a voltage value on the low potential side with respect to the reference power supply voltage VGND to the node Ns21.

[0076] The output selection switch 11 includes a PMOS transistor switch that outputs the voltage Vll of the node Nsll to the output terminal DLl by connecting the node Nsll and the output terminal DLl when turned on. Hereinafter, the output selection switch 11 will also be referred to as a PMOS transistor switch 11. In the PMOS transistor switch 11, a first terminal (hereinafter referred to as a source) is connected to the node Nsll, a second terminal (hereinafter referred to as a drain) is connected to the output terminal DLl, and a control terminal (hereinafter referred to as a gate) is commonly connected to the first voltage control circuit 50 and the first control unit 13.

[0077] The output selection switch 21 includes an NMOS transistor switch that outputs the voltage V21 of the node Ns21 to the output terminal DLl by connecting the node Ns21 and the output terminal DLl when turned on. Hereinafter, the output selection switch 21 will also be referred to as an NMOS transistor switch 21. In the NMOS transistor switch 21, the source is connected to the node Ns21, the drain is connected to the output terminal DLl, and the gate is commonly connected to the second control circuit 60 and the second control unit 23.

[0078] The switch 12 includes, for example, an NMOS transistor switch connected between the node Nsll and a reference power supply terminal that receives the reference power supply voltage VGND. The switch 12 applies the reference power supply voltage VGND to the node Nsll when turned on, and stops the application of the reference power supply voltage VGND to the node Nsll when turned off.

[0079] Switch 22 includes, for example, a PMOS transistor switch connected between node Ns21 and a reference power supply terminal. When switch 22 is turned on, it applies a reference power supply voltage VGND to node Ns21, and when it is turned off, it stops applying the reference power supply voltage VGND to node Ns21.

[0080] The first control unit 13 includes, for example, a PMOS transistor switch 13 (hereinafter simply referred to as switch 13) connected between the gate of the PMOS transistor switch 11 and the reference power supply terminal. The first control unit 13 is controlled in conjunction with the control of the on-state of switch 12. When it is on together with switch 12, the reference power supply voltage VGND is supplied to the gate of the PMOS transistor switch 11, thereby controlling the PMOS transistor switch 11 to be off-state. Alternatively, switch 13 can also be disposed between the gate of the PMOS transistor switch 11 and node Ns11.

[0081] The second control unit 23 includes, for example, an NMOS transistor switch 23 (hereinafter simply referred to as switch 23) connected between the gate of the NMOS transistor switch 21 and the reference power supply terminal. The second control unit 23 is controlled in conjunction with the control of the on-state of switch 22. When it is on together with switch 22, the reference power supply voltage VGND is supplied to the gate of the NMOS transistor switch 21, thereby controlling the NMOS transistor switch 21 to be off-state. Alternatively, switch 23 can also be disposed between the gate of the NMOS transistor switch 21 and node Ns21.

[0082] In addition, Figure 2 In one example shown, the first control unit 13 and the second control unit 23 are represented as switches, respectively. Here, when a pair of switches 12 and 13 and a pair of switches 22 and 23 output a positive or negative voltage signal (Vp or Vn) to the output terminal DL1, one of them is controlled to be turned on and the other is controlled to be turned off.

[0083] The first voltage control circuit 50 is connected to the gate of the PMOS transistor switch 11 and becomes active when the first control unit 13 is in a disabled state (switch 13 is open). When active, the first voltage control circuit 50 generates a gate voltage Vg11 that keeps the PMOS transistor switch 11 on and supplies it to the gate of the PMOS transistor switch 11. Furthermore, when the first control unit 13 is active (switch 13 is on), the first voltage control circuit 50 becomes disabled.

[0084] The second voltage control circuit 60 is connected to the gate of the NMOS transistor switch 21 and becomes active when the second control unit 23 is inactive (the switch 23 is off). The second voltage control circuit 60 generates, as a gate voltage Vg21, a voltage that maintains the NMOS transistor switch 21 in an on state and supplies it to the gate of the NMOS transistor switch 21 when it is active. In addition, the second voltage control circuit 60 becomes inactive when the second control unit 23 is active (the switch 23 is on).

[0085] The third voltage control circuit 55 operates in conjunction with the first voltage control circuit 50 and supplies a voltage Vbg11 that controls the back gate of the PMOS transistor switch 11. Specifically, when the first voltage control circuit 50 is made inactive and the PMOS transistor switch 11 is controlled to be off, the third voltage control circuit 55 supplies the reference power supply voltage VGND as the back gate voltage Vbg11 to the back gate of the PMOS transistor switch 11.

[0086] On the other hand, when the first voltage control circuit 50 is made active and the PMOS transistor switch 11 is controlled to be on, the third voltage control circuit 55 takes the voltage (V11) of the source (Ns11) or the voltage (VDL1) of the drain (output terminal DL1) of the PMOS transistor switch 11 as a first reference voltage and supplies, as the back gate voltage Vbg11, a voltage that is level-shifted to the high potential side to the back gate of the PMOS transistor switch 11.

[0087] The fourth voltage control circuit 65 operates in conjunction with the second voltage control circuit 60 and supplies a voltage Vbg21 that controls the back gate of the NMOS transistor switch 21. Specifically, when the second voltage control circuit 60 is made inactive and the NMOS transistor switch 21 is controlled to be off, the fourth voltage control circuit 65 supplies the reference power supply voltage VGND as the back gate voltage Vbg21 to the back gate of the NMOS transistor switch 21.

[0088] On the other hand, when the second voltage control circuit 60 is made active and the NMOS transistor switch 21 is controlled to be on, the fourth voltage control circuit 65 takes the voltage (V21) of the source (Ns21) or the voltage (VDL1) of the drain (output terminal DL1) of the NMOS transistor switch 21 as a second reference voltage and supplies, as the back gate voltage Vbg21, a voltage that is level-shifted to the low potential side to the back gate of the NMOS transistor switch 21.

[0089] Here, the third voltage control circuit 55 in the on state of the PMOS transistor switch 11 functions to control the back gate voltage Vbgll of the PMOS transistor switch 11 to a voltage higher than the positive electrode voltage signal Vp supplied to the source and drain of the PMOS transistor switch 11 when the PMOS transistor switch 11 passes the positive electrode voltage signal Vp. Thus, the threshold voltage (absolute value) of the PMOS transistor switch 11 increases by the back gate effect, and the generation of a PNP parasitic bipolar transistor (e.g. PaB) at the time of voltage change in the discharge operation or the charge operation of the capacitive load accompanying the positive electrode voltage signal Vp can be suppressed. Figure 1

[0090] However, at this time, if the voltage difference between the back gate voltage Vbgll and the voltage (Vp) of the source or drain of the PMOS transistor switch 11 is too large, the threshold voltage (absolute value) of the PMOS transistor switch 11 greatly increases, and the on resistance of the PMOS transistor switch 11 increases accordingly. Therefore, the level shift amount is controlled in the voltage control circuit 55 to form a small voltage difference that minimizes the increase in the on resistance of the PMOS transistor switch 11 and suppresses the generation of the PNP parasitic bipolar transistor.

[0091] Similarly, the fourth voltage control circuit 65 in the on state of the NMOS transistor switch 21 functions to control the back gate voltage Vbg21 of the NMOS transistor switch 21 to a voltage lower than the negative electrode voltage signal Vn supplied to the source and drain of the NMOS transistor switch 21 when the NMOS transistor switch 21 passes the negative electrode voltage signal Vn. Thus, the threshold voltage of the NMOS transistor switch 21 increases by the back gate effect, and the generation of an NPN parasitic bipolar transistor at the time of voltage change in the charge operation or the discharge operation of the capacitive load accompanying the negative electrode voltage signal Vn can be suppressed.

[0092] However, at this time, if the voltage difference between the back gate voltage Vbg21 and the voltage (Vn) of the source or drain of the NMOS transistor switch 21 is too large, the threshold voltage of the NMOS transistor switch 21 greatly increases, and the on resistance of the NMOS transistor switch 21 increases accordingly. Therefore, the level shift amount is controlled in the voltage control circuit 65 to form a small voltage difference that minimizes the increase in the on resistance of the NMOS transistor switch 21 and suppresses the generation of the NPN parasitic bipolar transistor.

[0093] The positive electrode voltage signal supply circuit 10A includes an amplification circuit 10 that outputs the positive electrode voltage signal Vp and a switch 14 that controls the supply and cutoff of the positive electrode voltage signal Vp to the node Nsll.

[0094] ​To handle a wide-range positive voltage signal Vp, switch 14 includes a complementary metal-oxide-semiconductor (CMOS) switch with both PMOS and NMOS transistors. Since the two ends of switch 14 have the same positive voltage range, it can be easily configured as a CMOS switch. Alternatively, amplifier circuit 10 can be configured to internally incorporate the function of switch 14; in this case, the output node of amplifier circuit 10 becomes node Ns11. Furthermore, in... Figure 2 In this context, the amplifier circuit 10 is not limited to a voltage follower that amplifies and outputs a positive voltage signal Vp that is the same as the input voltage signal Vpi; it can also be an amplifier circuit where the input voltage signal Vpi and the output voltage signal Vp are different. Furthermore, the voltage signal supplied from the positive voltage signal supply circuit 10A to node Ns11 will henceforth be denoted as Vp.

[0095] The negative voltage signal supply circuit 20A includes: an amplifier circuit 20 that outputs a negative voltage signal Vn; and a switch 24 that controls the supply and disconnection of the negative voltage signal Vn to node Ns21. To handle negative voltage signals over a wide voltage range, the switch 24 includes a CMOS switch. Alternatively, the amplifier circuit 20 may be configured to internally incorporate the function of the switch 24; in this case, the output node of the amplifier circuit 20 becomes node Ns21.

[0096] In addition, Figure 2 In this circuit, amplifier circuit 20 is not limited to a voltage follower that amplifies and outputs a negative voltage signal Vn that is the same as the input voltage signal Vni; it can also be an amplifier circuit where the input voltage signal Vni and the output voltage signal Vn are different. Furthermore, the voltage signal supplied from negative voltage signal supply circuit 20A to node Ns21 will henceforth be denoted as Vn.

[0097] Switches 12-14 and 22-24 are respectively controlled to be turned on and off by control signals S12-S14 and S22-S24 output from the self-control unit 101. Furthermore, when the first to fourth voltage control circuits (50, 60, 55, 65) are controlled by control signals, the self-control unit 101 supplies the control signals.

[0098] Next, for Figure 2 The voltage withstand ratings of the components in the output circuit 100 are explained below. Each component in the output circuit 100 is constructed with a voltage withstand rating VDDT lower than the output voltage range, with the minimum withstand voltage set to approximately half of the output voltage range.

[0099] Specifically, in order to keep the node Nsll from the positive voltage signal supply circuit 10A within the range from the reference power supply voltage VGND to the positive power supply voltage VDDH, the amplification circuit 10 and the switch 14 can be configured by a transistor having a lower withstand voltage VDDT than the output voltage range. Similarly, in order to keep the node Ns21 from the negative voltage signal supply circuit 20A within the range from the reference power supply voltage VGND to the negative power supply voltage VDDL, the amplification circuit 20 and the switch 24 can be configured by a transistor having a lower withstand voltage VDDT than the output voltage range.

[0100] Next, the element withstand voltage of the PMOS transistor switch 11 as the output selection switch will be described.

[0101] For example, when the positive voltage signal Vp is output to the output terminal DLl, both the switch 12 and the switch 13 are turned off, and the PMOS transistor switch 11 is controlled to be in the on state by the first voltage control circuit 50. At this time, the voltages of the source and the drain of the PMOS transistor switch 11 become within the positive voltage range of VGND to VDDH. Thus, the gate-source voltage difference of the PMOS transistor switch 11 is controlled to be within the lower withstand voltage VDDT than the output voltage range. In addition, the voltage difference between the gate and the back gate of the PMOS transistor switch 11 is also controlled to be within the withstand voltage VDDT by the first voltage control circuit 50 and the third voltage control circuit 55.

[0102] On the other hand, when the negative voltage signal Vn is output to the output terminal DLl, the reference power supply voltage VGND is supplied to the gate and the source by the switch 12 and the switch 13, and the PMOS transistor switch 11 is controlled to be in the off state. Therefore, even if the negative voltage signal Vn is output to the output terminal DLl to which the drain of the PMOS transistor switch 11 is connected, the voltage between each of the terminals of the source, the drain, the gate, and the back gate of the PMOS transistor switch 11 is controlled to be within the lower withstand voltage VDDT than the output voltage range.

[0103] Further, when the output terminal DLl is switched from the positive voltage signal Vp to the negative voltage signal Vn, for example, the switch 13 is controlled to be off while the switch 12 is kept in the on state, and thus the first voltage control circuit 50 is operated, and thereby the output terminal DLl is temporarily driven from the positive voltage to the reference power supply voltage VGND. Thereafter, the output operation is switched to the negative voltage signal Vn. Thus, the voltage difference between each of the terminals of the PMOS transistor switch 11 can be kept within the lower withstand voltage VDDT.

[0104] Next, the element withstand voltage of the NMOS transistor switch 21 as the output selection switch will be described.

[0105] For example, when the negative voltage signal Vn is output to the output terminal DLl, both the switch 22 and the switch 23 are turned off, and the NMOS transistor switch 21 is controlled to be in the on state by the second voltage control circuit 60. At this time, each voltage of the source and the drain of the NMOS transistor switch 21 becomes within the negative voltage range of VGND ~ VDDL. The gate-source voltage difference of the NMOS transistor switch 21 is controlled to be within the withstand voltage VDDT. In addition, the gate-backgate voltage difference of the NMOS transistor switch 21 is also controlled to be within the withstand voltage VDDT by the second voltage control circuit 60 and the fourth voltage control circuit 65.

[0106] On the other hand, when the positive voltage signal Vp is output to the output terminal DLl, the NMOS transistor switch 21 is controlled to be in the off state by supplying the gate and the source with the reference power supply voltage VGND through the switch 22 and the switch 23. Therefore, even if the output terminal DLl to which the drain is connected is the positive voltage signal Vp, each terminal voltage of the source, the drain, the gate, and the backgate of the NMOS transistor switch 21 is controlled to be within the withstand voltage VDDT. Furthermore, when the output terminal DLl is switched from the negative voltage signal Vn to the positive voltage signal Vp, for example, the switch 23 is controlled to be off while the switch 22 is kept in the on state, thereby causing the second voltage control circuit 60 to operate, and thus the output terminal DLl is temporarily driven from the negative voltage to the reference power supply voltage VGND. Thereafter, the output operation to the positive voltage signal Vp is switched. Thus, each terminal voltage difference of the NMOS transistor switch 21 can be kept within the withstand voltage VDDT which is lower than the output voltage range.

[0107] As described above, Figure 2 The output circuit 100 shown in FIG. 1 includes the output selection switch 11 and the output selection switch 21, and can be configured with transistors having a withstand voltage VDDT which is lower than the output voltage range.

[0108] Next, the operation of the third voltage control circuit 55 and the fourth voltage control circuit 65 will be described with reference to Figure 3A and Figure 3B

[0109] Figure 3A A signal waveform of the positive voltage signal Vp supplied to the source side or the drain side of the PMOS transistor switch 11 when the positive voltage signal Vp is continuously output, and a backgate voltage Vbgll of the PMOS transistor switch 11 controlled by the third voltage control circuit 55 are shown. In addition, the positive voltage signal Vp supplied to the source side of the PMOS transistor switch 11 is the voltage signal Vll on the node Nsll, and the positive voltage signal Vp supplied to the drain side of the PMOS transistor switch 11 is the output signal VDLl on the output terminal DLl.

[0110] In​Figure 3A In one example, the voltage signal Vp (V11 or VDL1) supplied to the source or drain side of the PMOS transistor switch 11 changes from a positive voltage near the reference power supply voltage VGND to a positive voltage near the positive power supply voltage VDDH at time t1, and then changes again to a positive voltage near the reference power supply voltage VGND at time t2. At this time, as shown... Figure 3A As shown, the back gate voltage Vbg11 of the PMOS transistor switch 11 is maintained at a voltage that has been level-shifted to the positive side relative to the voltage signal Vp by a predetermined voltage difference LSp, and operates in accordance with the voltage signal Vp. The predetermined voltage difference LSp is controlled to minimize the increase in the on-resistance of the PMOS transistor switch 11 and to suppress the generation of PNP parasitic bipolar transistors (e.g., PNPs). Figure 1 The relatively small voltage difference of PaB.

[0111] In addition, Figure 3A In the process, when the positive voltage signal Vp (V11 or VDL1) is near the positive power supply voltage VDDH, the back gate voltage Vbg11 is below the positive power supply voltage VDDH, and the voltage difference between it and the voltage signal Vp decreases.

[0112] Figure 3B The diagram shows the negative voltage signal Vn supplied to the source or drain side of the NMOS transistor switch 21 when a negative voltage signal Vn is continuously output, and the signal waveforms of the back gate voltage Vbg21 of the NMOS transistor switch 21 controlled by the fourth voltage control circuit 65. Furthermore, the negative voltage signal Vn supplied to the source side of the NMOS transistor switch 21 is the voltage signal V21 at node Ns21, and the negative voltage signal Vn supplied to the drain side of the NMOS transistor switch 21 is the output signal VDL1 at the output terminal DL1.

[0113] exist Figure 3B In one example, the voltage signal Vn (V21 or VDL1) supplied to the source or drain side of the NMOS transistor switch 21 changes from a negative voltage near the reference power supply voltage VGND to a negative voltage near the negative power supply voltage VDDL at time t1, and then changes again to a negative voltage near the reference power supply voltage VGND at time t2. At this time, the back gate voltage Vbg21 of the NMOS transistor switch 21 maintains a predetermined voltage difference LSn that is level-shifted negatively relative to the voltage signal Vn, and operates in accordance with the voltage signal Vn. This predetermined voltage difference LSn is controlled to minimize the increase in the on-resistance of the NMOS transistor switch 21 and to suppress the generation of a parasitic NPN bipolar transistor. Figure 3BIn the process, when the negative voltage signal Vn (V21 or VDL1) is near the negative power supply voltage VDDL, the back gate voltage Vbg21 is above the negative power supply voltage VDDL, and the voltage difference between it and the voltage signal Vn decreases.

[0114] As described above, by controlling the back gate voltage of the PMOS transistor switch 11 through the third voltage control circuit 55, the generation of parasitic bipolar transistors in the PMOS transistor switch 11 can be suppressed. Similarly, by controlling the back gate voltage of the NMOS transistor switch 21 through the fourth voltage control circuit 65, the generation of parasitic bipolar transistors in the NMOS transistor switch 21 can be suppressed.

[0115] and then, Figure 2 The output circuit 100 shown can also be constructed with components within a voltage rating VDDT that is lower than the output voltage range (VDDL~VDDH), thus achieving area saving (cost reduction).

[0116] Therefore, according to the present invention, the output circuit, which selectively outputs one of the positive and negative voltage signals, can improve the reliability of its operation and reduce the area required.

[0117] Next, refer to Figure 4 illustrate Figure 2 Example of control of output circuit 100 shown.

[0118] Figure 4 It means Figure 2 The timing diagram shows an example of the control states of control signals S12-S14 and S22-S24 generated by the control unit 101.

[0119] also, Figure 4 The diagram shows an example of the control signal generated by the control unit 101 when the output circuit 100 periodically alternates between outputting positive voltage signal Vp and negative voltage signal Vn, a so-called polarity reversal drive. Additionally, Figure 4 The diagram shows the operation during each period of the positive drive of the output positive voltage signal Vp and the negative drive of the output negative voltage signal Vn. Figure 2 The diagram shows the on / off control of each switch and the voltage waveforms of the positive voltage signal V11 at node Ns11, the negative voltage signal V21 at node Ns21, and the output voltage VDL1 at output terminal DL1. At this time, the positive voltage signal Vp and the negative voltage signal Vn can be single or multiple step signals within the voltage range corresponding to their respective polarities.

[0120] In addition, Figure 4In the example shown, switching periods T1 and T3 are provided between the positive electrode driving period T2 and the negative electrode driving period T4, respectively, and during the switching periods, in order to prevent the element from exceeding the withstand voltage, the output terminal DL1 is temporarily driven to the reference power supply voltage VGND. Further, with respect to the positive electrode driving period T2 and the negative electrode driving period T4, it is also possible to divide into a plurality of periods that sequentially output a plurality of voltage signals of the same polarity.

[0121] Here, in the case where the driving is performed Figure 4 In the driving shown, for example, the switch 12 and the switch 23 are provided as NMOS transistor switches, the switch 13 and the switch 22 are provided as PMOS transistor switches, and the switch 14 and the switch 24 are provided as CMOS transistor switches. The control signals S12 to S14 and the control signals S22 to S24 that control the respective switches are supplied with power supply voltages corresponding to the voltage polarities of the respective switches that they control.

[0122] Further, in the case where the driving is performed Figure 4 In the case where the driving is performed, with respect to the CMOS transistor switch 14 and the CMOS transistor switch 24, the state of turning on / off is shown by the voltage supplied to one of the NMOS transistor switches in the CMOS switch structure.

[0123] Further, in the case where the driving is performed Figure 4 In the case where the driving is performed, the state immediately before the switching period T1 (initial state) is set to the state in which the negative electrode voltage signal Vn generated in the negative electrode voltage signal supply circuit 20A is supplied to the output terminal DL1 via the NMOS transistor switch 21, that is, the operation state within the negative electrode driving period T4.

[0124] In the case where the driving is performed Figure 4In the switching period T1, first, the voltage signals from the positive voltage signal supply circuit 10A and the negative voltage signal supply circuit 20A are cut off by making the switches 14 and 24 both into the off state by the control signals S14 and S24. Also, the reference power supply voltage VGND is supplied to the gate and source of the PMOS transistor switch 11 (the node Nsll) by making the switches 12 and 13 both into the on state by the control signals S12 and S13. Thus, the voltage control circuit 50 is made into the inactive state, the PMOS transistor switch 11 is made into the off state, and the voltage Vll of the node Nsll becomes the reference power supply voltage VGND. At this time, the reference power supply voltage VGND is supplied to the back gate of the PMOS transistor switch 11 from the voltage control circuit 55. Also, the reference power supply voltage VGND is supplied to the source of the NMOS transistor switch 21 (the node Ns21) by making the switch 22 into the on state by the control signal S22. Also, the voltage control circuit 60 is made into the active state and the NMOS transistor switch 21 is made into the on state by making the switch 23 into the off state by the control signal S23. At this time, the voltage which is level-shifted to the negative side by the voltage difference LSn from the voltage (VGND) of the source or drain of the NMOS transistor switch 21 is supplied to the back gate of the NMOS transistor switch 21 from the voltage control circuit 65.

[0125] Thus, as shown in FIG. 6, in the switching period T1, the voltage V21 of the node Ns21 is raised to the reference power supply voltage VGND, and the output voltage VDL1 of the output terminal DL1 is also raised to the reference power supply voltage VGND via the NMOS transistor switch 21. Figure 4

[0126] Next, in the positive electrode drive period T2, the supply of the voltage signal from the negative voltage signal supply circuit 20A is continued to be cut off by making the switch 24 into the off state by the control signal S24. On the other hand, the positive electrode voltage signal Vp is supplied to the node Nsll from the positive voltage signal supply circuit 10A by making the switch 14 into the on state by the control signal S14. Also, the reference power supply voltage VGND is supplied to the gate and source of the NMOS transistor switch 21 (the node Ns21) by making the switches 22 and 23 both into the on state by the control signals S22 and S23. Thus, the voltage control circuit 60 is made into the inactive state, the NMOS transistor switch 21 is made into the off state, and the voltage V21 of the node Ns21 continues to be the reference power supply voltage VGND. At this time, the reference power supply voltage VGND is supplied to the back gate of the NMOS transistor switch 21 from the voltage control circuit 65. Further, the voltage control circuit 50 is made active and the PMOS transistor switch 11 is made into the on state by making the switches 12 and 13 both into the off state by the control signals S12 and S13. Then, as shown in FIG. 6, in the positive electrode drive period T2, the voltage Vll of the node Nsll is raised to the positive electrode voltage signal Vp, and the output voltage VDL1 of the output terminal DL1 is also raised to the positive electrode voltage signal Vp via the PMOS transistor switch 11.​Figure 4 As shown, the output voltage VDL1 of the output terminal DL1 is raised to the positive voltage signal Vp via the on-state of the PMOS transistor switch 11. At this time, to the back gate of the PMOS transistor switch 11, a voltage that is level-shifted to the positive side by a voltage difference LSp from the voltage (Vp) of the source or drain of the PMOS transistor switch 11 is supplied from the voltage control circuit 55. Further, during the positive electrode drive period T2, even if the positive voltage signal Vp output from the positive electrode voltage signal supply circuit 10A is changed, since the on-state of the PMOS transistor switch 11 can be maintained by the voltage control circuit 50, the output voltage VDL1 also changes in accordance with the positive voltage signal Vp. In addition, even in the case where the positive voltage signal Vp is greatly changed to the negative side, since a voltage that is higher than the positive voltage signal Vp by the voltage difference LSp is supplied to the back gate of the PMOS transistor switch 11 from the voltage control circuit 55, generation of a parasitic bipolar transistor can also be suppressed.

[0127] Next, during the switching period T3, the supply of the voltage signal from the positive electrode voltage signal supply circuit 10A and the negative electrode voltage signal supply circuit 20A is cut off by making the switches 14 and 24 both into the off-state by the control signal S14 and the control signal S24. In addition, the gate and the source (the node Ns21) of the NMOS transistor switch 21 are supplied with the reference power supply voltage VGND by continuing to make the switches 22 and 23 both into the on-state by the control signal S22 and the control signal S23. Thus, the voltage control circuit 60 is continued to be in the inactive state, and the NMOS transistor switch 21 is continued to be in the off-state, as shown in FIG. 6B. Figure 4 As shown, the voltage V21 of the node Ns21 is also maintained at the reference power supply voltage VGND. At this time, to the back gate of the NMOS transistor switch 21, the reference power supply voltage VGND is supplied from the voltage control circuit 65. In addition, the source (the node Nsll) of the PMOS transistor switch 11 is supplied with the reference power supply voltage VGND by making the switch 12 into the on-state by the control signal S12. In addition, the voltage control circuit 50 is maintained in the active state by making the switch 13 continue to be in the off-state, and the PMOS transistor switch 11 is maintained in the on-state. At this time, to the back gate of the PMOS transistor switch 11, a voltage that is level-shifted to the positive side by the voltage difference LSp from the voltage (VGND) of the source or drain of the PMOS transistor switch 11 is continued to be supplied from the voltage control circuit 55. Thus, during the switching period T3, the voltage Vll of the node Nsll is lowered to the reference power supply voltage VGND, and the output voltage VDL1 of the output terminal DL1 is also lowered to the reference power supply voltage VGND via the PMOS transistor switch 11.

[0128] Next, during the negative electrode drive period T4, the switch 14 is made into an off state by the control signal S14, and the supply of the voltage signal from the positive electrode voltage signal supply circuit 10A is continued to be cut off. On the other hand, the switch 24 is made into an on state by the control signal S24, and the negative electrode voltage signal Vn is supplied from the negative electrode voltage signal supply circuit 20A to the node Ns21. Further, the switch 12 and the switch 13 are both made into on states by the control signal S12 and the control signal S13, and the reference power supply voltage VGND is supplied to the gate and the source (the node Nsll) of the PMOS transistor switch 11. Thereby, the voltage control circuit 50 is made into an inactive state, the PMOS transistor switch 11 is made into an off state, and the voltage Vll of the node Nsll is maintained as the reference power supply voltage VGND. At this time, the reference power supply voltage VGND is supplied from the voltage control circuit 55 to the back gate of the PMOS transistor switch 11. Further, the switch 22 and the switch 23 are both made into off states by the control signal S22 and the control signal S23, the voltage control circuit 60 is made into an active state, and the NMOS transistor switch 21 is made into an on state. Also, as shown in FIG. 6, the output voltage VDLl of the output terminal DLl is lowered to the negative electrode voltage signal Vn via the on state of the NMOS transistor switch 21. At this time, the voltage which is level-shifted to the negative side by the voltage difference LSn with respect to the voltage (Vn) of the source or the drain of the NMOS transistor switch 21 is supplied from the voltage control circuit 65 to the back gate of the NMOS transistor switch 21. Further, even if the voltage value of the negative electrode voltage signal Vn output from the negative electrode voltage signal supply circuit 20A is changed during the negative electrode drive period T4, the on state of the NMOS transistor switch 21 is maintained by the voltage control circuit 60, and therefore the output voltage VDLl is changed in accordance with the voltage value of the negative electrode voltage signal Vn. Also, even in the case where the negative electrode voltage signal Vn is greatly changed to the positive side, since the voltage which is lower than the negative electrode voltage signal Vn by the voltage difference LSn is supplied from the voltage control circuit 65 to the back gate of the NMOS transistor switch 21, the generation of the parasitic bipolar transistor can be suppressed. Figure 4

[0129] Further, in the case where the output voltage VDLl is changed to the positive side, the voltage control circuit 60 is made into an active state by the control signal S22 and the control signal S23, and the NMOS transistor switch 21 is made into an on state. Also, as shown in FIG. 6, the output voltage VDLl of the output terminal DLl is lowered to the negative electrode voltage signal Vn via the on state of the NMOS transistor switch 21. At this time, the voltage which is level-shifted to the negative side by the voltage difference LSn with respect to the voltage (Vn) of the source or the drain of the NMOS transistor switch 21 is supplied from the voltage control circuit 65 to the back gate of the NMOS transistor switch 21. Further, even if the voltage value of the negative electrode voltage signal Vn output from the negative electrode voltage signal supply circuit 20A is changed during the negative electrode drive period T4, the on state of the NMOS transistor switch 21 is maintained by the voltage control circuit 60, and therefore the output voltage VDLl is changed in accordance with the voltage value of the negative electrode voltage signal Vn. Also, even in the case where the negative electrode voltage signal Vn is greatly changed to the positive side, since the voltage which is lower than the negative electrode voltage signal Vn by the voltage difference LSn is supplied from the voltage control circuit 65 to the back gate of the NMOS transistor switch 21, the generation of the parasitic bipolar transistor can be suppressed. Figure 4 ​In the example shown, a driving control example in which the positive electrode driving period and the negative electrode driving period are switched alternately is explained, but at the time of power-on or power-off, control corresponding to the rise or fall of the power supply voltage is performed. For example, at the time of rise or fall of the power supply voltage, the capacitive load connected to the output terminal DL1 is driven to the reference power supply voltage VGND, and therefore, for example, the supply of the voltage signal of the positive electrode voltage signal supply circuit 10A and the negative electrode voltage signal supply circuit 20A is cut off (switches 14 and 24 are turned off), the switches 12 and 22 are controlled to be both on, and the switches 13 and 23 are controlled to be both off. At this time, the voltage control circuit 50 and the voltage control circuit 60 can also be controlled to be both in the active state and the transistors 11 and 21 can also be controlled to be both on. In addition, the voltage control circuit 55 can also be controlled in conjunction with the active state of the voltage control circuit 50 to supply a voltage, which is level-shifted to the positive side with respect to the reference power supply voltage VGND, to the back gate of the PMOS transistor switch 11. Similarly, the voltage control circuit 65 can also be controlled in conjunction with the active state of the voltage control circuit 60 to supply a voltage, which is level-shifted to the negative side with respect to the reference power supply voltage VGND, to the back gate of the NMOS transistor switch 21.

[0130] Next, the output circuit 100 will be described. Figure 2 The third voltage control circuit 55 included in the output circuit 100 shown in FIG. 1 will be described.

[0131] Figure 5 is a circuit diagram showing the structure of the voltage control circuit 55-1 as the first embodiment of the voltage control circuit 55.

[0132] Figure 5 The voltage control circuit 55-1 shown controls the voltage supplied to the back gate of the PMOS transistor switch 11. When the PMOS transistor switch 11 is in the on state, the voltage control circuit 55-1 supplies, as the back gate voltage, a voltage, which is level-shifted to the high voltage side with a prescribed voltage difference LSp with respect to the voltage (the positive electrode voltage signal Vp or the reference power supply voltage VGND) supplied to the source (Ns11) or the drain (DL1) of the PMOS transistor switch 11, to the back gate of the PMOS transistor switch 11. In addition, when the PMOS transistor switch 11 is in the off state, the voltage control circuit 55-1 supplies the reference power supply voltage VGND to the back gate of the PMOS transistor switch 11. Further, in Figure 5 the example shown in FIG. 1, the positive electrode voltage signal Vp is supplied as the voltage supplied to the source (Ns11) or the drain (DL1) of the PMOS transistor switch 11. As for Figure 5 the same applies to each of the embodiments of the voltage control circuit 55 described later.

[0133] Figure 5 The voltage control circuit 55-1 shown includes a load element 56 connected at one end to the back gate of the PMOS transistor switch 11, and a current source 58 that sets the current value flowing to the load element 56.

[0134] When the PMOS transistor switch 11 is in the on state, the load element 56 receives the voltage supplied to the source (Ns11) or drain (DL1) of the PMOS transistor switch 11 at one end, and supplies a voltage Vbg11 having a prescribed voltage difference LSp to the positive side with respect to the positive voltage signal Vp to the back gate of the PMOS transistor switch 11 via the other end. The voltage Vbg11 is controlled to be a voltage higher than the positive voltage signal Vp and below the positive power supply voltage VDDH. The voltage difference LSp between the positive voltage signal Vp and the back gate of the PMOS transistor switch 11 is set in accordance with the voltage value of the positive voltage signal Vp and the current value flowing to the load element 56 by the current source 58. The load element 56 can include a resistive element, a diode-connected MOS transistor, a source follower MOS transistor, and the like.

[0135] Further, during the switching period T3 of the negative drive period T4, Figure 4 the reference power supply voltage VGND is supplied to the source (Ns11) or drain (DL1) of the PMOS transistor switch 11 instead of the positive voltage signal Vp, and a voltage Vbg11 having a prescribed voltage difference LSp to the positive side with respect to the reference power supply voltage VGND is supplied to the back gate of the PMOS transistor switch 11.

[0136] Further, the voltage control circuit 55-1 includes a switch 59 that, when on, supplies the reference power supply voltage VGND to the back gate of the PMOS transistor switch 11.

[0137] When the PMOS transistor switch 11 is in the on state, the switch 59 is controlled to be off, and when the PMOS transistor switch 11 is in the off state, the switch 59 is controlled to be on. Thus, during the negative drive period T4 of the output of the negative voltage signal Vn to the output terminal DL1, Figure 4 the element withstand voltage exceeding prevention function operates to prevent the voltage difference between the drain (DL1) and the back gate of the PMOS transistor switch 11 from exceeding the element withstand voltage when the negative voltage signal is output.

[0138] During the negative drive period T4 of the output of the negative voltage signal Vn to the output terminal DL1, Figure 4 In the timing chart shown, the switch 59 is made to be on during the entire period of T4 and T1 in which the voltage control circuit 50 is in the inactive state and the PMOS transistor switch is off, and is made to be off during the period of T2 and T3 in which the voltage control circuit 50 is in the active state and the PMOS transistor switch is on. The switch 59, for example, includes an NMOS transistor switch, and can be controlled by a signal from the voltage control circuit 50.Figure 2 The control signal S23 of the control section 101 shown is controlled by a complementary signal.

[0139] The back gate voltage Vbgll of the PMOS transistor switch 11 is maintained at a higher potential than the voltage supplied to the source (Nsll) or drain (DLl) by the voltage control circuit 55-1. Thus, with respect to the charge and discharge operation of the data line load when the PMOS transistor switch 11 is turned on, the generation of a parasitic bipolar transistor can be suppressed.

[0140] Further, the back gate voltage Vbgll varies in response to the anode voltage signal Vp. Furthermore, by controlling the voltage difference between the back gate voltage Vbgll and the anode voltage signal Vp to be relatively small, the on resistance of the PMOS transistor switch 11 can be maintained low.

[0141] Figure 6 is a circuit diagram showing the structure of a voltage control circuit 55-2 as a second embodiment of the voltage control circuit 55.

[0142] In the voltage control circuit 55-2, Figure 5 The load element 56 shown includes a PMOS transistor 56a of a diode connection structure, and the other structure is the same as that of the voltage control circuit shown in Figure 5 .

[0143] The drain and gate of the PMOS transistor 56a itself are connected to the node Nsll or the output terminal DLl, and the source and back gate thereof are connected to the back gate of the PMOS transistor switch 11. The connection structure of the current source 58 and the switch 59 is the same as that of the voltage control circuit shown in Figure 5 .

[0144] The voltage difference LSp between the voltage supplied to the source (Nsll) or drain (DLl) of the PMOS transistor switch 11 (for example, the anode voltage signal Vp) and the back gate voltage Vbgll is set in accordance with the size of the PMOS transistor 56a and the current value flowing to the PMOS transistor 56a by the current source 58. In accordance with the current value of the current source 58, the voltage difference LSp is set to a value capable of suppressing the generation of a parasitic bipolar transistor. In addition, the PMOS transistor switch 11 and the PMOS transistor 56a are of the same conductivity type, and by connecting the back gates of each other, the influence of the variation in characteristics due to the manufacturing variation of the transistor can be suppressed, and thus the on resistance of the PMOS transistor switch 11 can be set constant.

[0145] Further, as the load element 56, an NMOS transistor of a diode connection structure can also be included instead of the PMOS transistor 56a as shown in Figure 6A PMOS transistor 56a of a diode connection structure is shown. In this case, it is possible to generate some influence of characteristic variation caused by manufacturing deviation of the transistor.

[0146] Figure 7 is a circuit diagram showing a structure of a voltage control circuit 55-3 as a third embodiment of the voltage control circuit 55.

[0147] In the voltage control circuit 55-3, Figure 5 A load element 56 shown includes a PMOS transistor 56b of a source follower structure, and other structures are the same as those of the voltage control circuit shown in Figure 5

[0148] The drain of the PMOS transistor 56b is connected to a reference power supply voltage VGND terminal, and the gate thereof is connected to a node Nsll or an output terminal DLl. Further, the source and the back gate of the PMOS transistor 56b are connected to the back gate of the PMOS transistor switch 11.

[0149] The PMOS transistor 56b supplies a source follower output following a voltage (for example, a positive voltage signal Vp) supplied to the source (Nsll) or the drain (DLl) of the PMOS transistor switch 11 as a back gate voltage Vbgll to the back gate of the PMOS transistor switch 11. A voltage difference LSp of the positive voltage signal Vp and the back gate voltage Vbgll is set according to the size of the PMOS transistor 56b and the current value flowing to the PMOS transistor 56b by the current source 58. According to the current value of the current source 58, the voltage difference LSp is set to a value capable of suppressing generation of a parasitic bipolar transistor.

[0150] In addition, the PMOS transistor switch 11 and the PMOS transistor 56b are of the same conductivity type, and by connecting the back gates thereof to each other in common, it is possible to suppress the influence of characteristic variation caused by manufacturing deviation of the transistor, and thus it is possible to set the on resistance of the PMOS transistor switch 11 to be constant.

[0151] Figure 8 is a circuit diagram showing a structure of a voltage control circuit 55-4 as a fourth embodiment of the voltage control circuit 55.

[0152] In the voltage control circuit 55-4, a PMOS transistor 56c and a PMOS transistor 56d are adopted instead of Figure 6 the diode connection type PMOS transistor 56a in the voltage control circuit 55-2 shown, and other structures are the same as those of the voltage control circuit shown in Figure 6

[0153] ​​The drain of PMOS transistor 56c is connected to the output terminal DL1, the gate is connected to node Ns11, and the source and back gate are connected to the back gate of PMOS transistor switch 11.

[0154] The drain of PMOS transistor 56d is connected to node Ns11, the gate is connected to the output terminal DL1, and the source and back gate are connected to the back gate of PMOS transistor switch 11. The connection structure between current source 58 and switch 59 is similar to... Figure 6 same.

[0155] PMOS transistor switch 11, PMOS transistor 56c, and PMOS transistor 56d are of the same conductivity type. By connecting their back gates together, the influence of characteristic variations caused by manufacturing deviations of the transistors can be suppressed, thereby allowing the on-resistance of PMOS transistor switch 11 to be set to a constant.

[0156] Next, an explanation Figure 8 The function of the voltage control circuit 55-4 shown.

[0157] exist Figure 8 In this context, the transient node Ns11 and the output terminal DL1 are set to Vpa and Vpb, respectively, when the voltage of the positive voltage signal Vp changes. Then, when the voltage of the output terminal DL1 stabilizes, i.e., its value becomes constant, it becomes...

[0158] Vpa = Vpb = Vp.

[0159] For example, when the positive voltage signal Vp changes rapidly and significantly, and the voltages Vpa and Vpb are transiently different, more current flows to one of the PMOS transistors 56c or 56d, i.e., the PMOS transistor whose gate receives the lower of Vpa and Vpb. At this time, the drain voltage of the other PMOS transistor 56c or 56d becomes the higher of Vpa and Vpb. Therefore, the back gate voltage Vbg11 of the PMOS transistor switch 11 is controlled to be higher than both the source and drain voltages Vpa and Vpb. Thus, even with rapid voltage changes relative to the positive voltage signal Vp, the operation of the parasitic bipolar transistor can be reliably suppressed.

[0160] Next, for Figure 2 An embodiment of the fourth voltage control circuit 65 of the output circuit 100 shown will be described.

[0161] Figure 9 This is a circuit diagram showing the structure of voltage control circuit 65-1 as a first embodiment of voltage control circuit 65.

[0162] Figure 9 The voltage control circuit 65-1 shown controls the voltage supplied to the back gate of the NMOS transistor switch 21. When the NMOS transistor switch 21 is in the on state, the voltage control circuit 65-1 supplies, as the back gate voltage Vbg21 of the NMOS transistor switch 21, a voltage that has been level-shifted to the low voltage side by a prescribed voltage difference LSn with respect to the voltage (negative electrode voltage signal Vn or reference power supply voltage VGND) supplied to the source (Ns21) or drain (DL1) of the NMOS transistor switch 21.

[0163] Figure 9 The voltage control circuit 65-1 shown includes a load element 66, one end of which is connected to the back gate of the NMOS transistor switch 21, and a current source 68 that sets the current value flowing to the load element 66.

[0164] When the NMOS transistor switch 21 is in the on state, the load element 66 receives, at one end thereof, the voltage (for example, the negative electrode voltage signal Vn) supplied to the source (Ns21) or drain (DL1) of the NMOS transistor switch 21, and supplies, at the other end thereof, the back gate voltage Vbg21 that has been level-shifted to the negative side by a prescribed voltage difference LSn with respect to the negative electrode voltage signal Vn to the back gate of the NMOS transistor switch 21. Figure 3B The back gate voltage Vbg21 shown, which has been level-shifted to the negative side by a prescribed voltage difference LSn with respect to the negative electrode voltage signal Vn, is supplied to the back gate of the NMOS transistor switch 21 via the other end thereof.

[0165] Furthermore, the voltage value of the back gate voltage Vbg21 is controlled to be lower than the negative electrode voltage signal Vn and to be equal to or higher than the negative power supply voltage VDDL. The voltage difference LSn between the negative electrode voltage signal Vn and the back gate of the NMOS transistor switch 21 is set in accordance with the negative electrode voltage signal Vn and the current value flowing to the load element 66 by the current source 68. The load element 66 can include a resistance element, a diode-connected MOS transistor, a source follower MOS transistor, or the like.

[0166] Furthermore, during the switching period T1 of Figure 4 the reference power supply voltage VGND is supplied to the source (Ns21) or drain (DL1) of the NMOS transistor switch 21 instead of the negative electrode voltage signal Vn, and the voltage Vbg21 having a prescribed voltage difference LSn to the negative side with respect to the reference power supply voltage VGND is supplied to the back gate of the NMOS transistor switch 21.

[0167] Further, the voltage control circuit 65-1 includes a switch 69 that, when on, supplies the reference power supply voltage VGND to the back gate of the NMOS transistor switch 21.

[0168] When NMOS transistor switch 21 is in the ON state, switch 69 is controlled to OFF; when NMOS transistor switch 21 is in the OFF state, switch 69 is controlled to ON. Therefore, the positive voltage signal Vp is output from the output terminal DL1. Figure 4 During the positive drive period T2, the device overvoltage protection function is activated to prevent the voltage difference between the drain (DL1) and back gate of the NMOS transistor switch 21 from exceeding the device withstand voltage when the positive voltage signal is output.

[0169] Here, in Figure 4 In the timing diagram shown, switch 69 is turned off during the entire periods T4 and T1 when voltage control circuit 60 is in a failed state and NMOS transistor switch 21 is turned on, and turned on during the entire periods T2 and T3 when voltage control circuit 60 is in a failed state and NMOS transistor switch 21 is turned off. Switch 69 may include, for example, a PMOS transistor switch, which can be utilized Figure 2 The control unit 101 shown controls the complementary signal of the control signal S13.

[0170] The voltage control circuit 65-1 maintains the back gate voltage Vbg21 supplied to the back gate of the NMOS transistor switch 21 at a potential lower than the voltage supplied to the source (Ns21) or drain (DL1). Therefore, the generation of parasitic bipolar transistors can be suppressed relative to the charging and discharging operation of the data line load when the NMOS transistor switch 21 is turned on.

[0171] Furthermore, the back gate voltage Vbg21 varies with the negative electrode voltage signal Vn, but by keeping the voltage difference between the back gate voltage Vbg21 and the negative electrode voltage signal Vn relatively small, the on-resistance of the NMOS transistor switch 21 can be kept low. Additionally, the load element 66 of the voltage control circuit 65-1 and... Figure 5 Specific examples or application examples of the load element 56 of the voltage control circuit 55-1 shown, for example... Figure 6-8 Similarly, the load elements 56a, 56b, 56c, and 56d shown may include resistor elements, diode-connected MOS transistors, or source follower MOS transistors, etc.

[0172] Next, regarding Figure 2 An embodiment of the first voltage control circuit 50 of the output circuit 100 shown will be described.

[0173] Figure 10 This is a circuit diagram showing the structure of voltage control circuit 50-1 as a first embodiment of voltage control circuit 50.

[0174] The voltage control circuit 50-1 supplies the gate voltage of the PMOS transistor switch 11 with the voltage V11 received by the source of the PMOS transistor switch 11 via node Ns11 after level shifting to the low voltage side.

[0175] like Figure 10 As shown, the voltage control circuit 50-1 includes: a load element (or load circuit) 51, one end of which is connected to the gate of the PMOS transistor switch 11; and a current source 52, which sets the current value flowing to the load element 51. The load element 51 receives the voltage V11 supplied to the source of the PMOS transistor switch 11 at node Ns11, and generates a voltage Vg11 that is lower than the voltage V11 by a predetermined voltage difference, which is then supplied to the gate of the PMOS transistor switch 11. The potential difference across the load element 51, i.e., the voltage difference between the source (node ​​Ns11) and the gate of the PMOS transistor switch 11, is set according to the on-resistance of the load element 51 and the current value of the current source 52. That is, the voltage difference is set to be greater than the threshold voltage (absolute value) of the PMOS transistor switch 11, i.e., a voltage difference that keeps the PMOS transistor switch 11 in the on state.

[0176] Furthermore, the load element 51 may include a resistor or a diode-connected MOS transistor connected between node Ns11 and the gate of the PMOS transistor switch 11. Alternatively, the load element 51 may also include a source follower NMOS transistor, which receives a gate voltage V11, has its source connected to the gate of the PMOS transistor switch 11, and its drain connected to a predetermined power supply voltage terminal. Additionally, a current source 52 may be connected, for example, between the negative power supply voltage VDDL and the gate of the PMOS transistor switch 11. Alternatively, a lower negative power supply voltage VCCL may be used instead of the negative power supply voltage VDDL.

[0177] The voltage between the terminals of each component in the voltage control circuit 50-1 is set to a minimum withstand voltage VDDT. The gate voltage Vg11 is lower than the voltage V11 at node Ns11, and the voltage difference between the gate voltage Vg11 and the voltage V11 is controlled to a minimum withstand voltage VDDT.

[0178] Figure 11 This is a circuit diagram showing the structure of voltage control circuit 50-2, which is a second embodiment of voltage control circuit 50.

[0179] The voltage control circuit 50-2 supplies a prescribed power supply voltage as the gate voltage Vgl l to the gate of the PMOS transistor switch 11 in accordance with the voltage Vl l received by the source of the PMOS transistor switch 11. The voltage control circuit 50-2 includes a switch 53 and a switch 54 that selectively supply one of the reference power supply voltage VGND and the negative-side low power supply voltage VCCL to the gate of the PMOS transistor switch 11. Each of the switches 53 and 54 is turned on / off by a control signal S50 generated by the control section 101, for example.

[0180] The control signal S50 can be controlled, for example, on the basis of the logic value (0, 1) of a prescribed bit of digital data corresponding to the positive voltage signal Vp (= Vl l) supplied to the source of the PMOS transistor switch 11. For example, when the voltage value of the positive voltage signal Vp becomes a value on the positive power supply voltage VDDH side, the switches 53 and 54 are made to be on and off, respectively, by the control signal S50. Thereby, the gate voltage Vgl l having the reference power supply voltage VGND is supplied to the gate of the PMOS transistor switch 11. On the other hand, when the voltage value of the positive voltage signal Vp becomes a value on the reference power supply voltage VGND side, the switches 53 and 54 are made to be off and on, respectively, by the control signal S50. Thereby, the gate voltage Vgl l having the negative-side low power supply voltage VCCL is supplied to the gate of the PMOS transistor switch 11.

[0181] Further, as a specific circuit example of the voltage control circuit 50 (50-1, 50-2), there are shown in Figure 10 and Figure 11 , but it is not limited to such a circuit structure. In general, as the voltage control circuit 50, as long as it can be constituted without exceeding the low withstand voltage VDDT, and can maintain the PMOS transistor switch 11 in the on state at the time of failure of the first control section 13 (switch 13 off) shown in Figure 2 , there is no limitation to the circuit form.

[0182] Next, an embodiment of the second voltage control circuit 60 of the output circuit 100 shown in Figure 2 will be described.

[0183] Figure 12 is a circuit diagram showing the structure of the voltage control circuit 60-1 as a first embodiment of the voltage control circuit 60.

[0184] The voltage control circuit 60-1 supplies, as the gate voltage Vg21, to the gate of the NMOS transistor switch 21, a voltage obtained by level-shifting the voltage V21 received by the source of the NMOS transistor switch 21 via the node Ns21 to the high voltage side.

[0185] AsFigure 12 As shown, the voltage control circuit 60-1 includes a load element (or load circuit) 61 connected at one end to the gate of the NMOS transistor switch 21, and a current source 62 that sets the current value flowing to the load element 61. The load element 61 receives the voltage V21 of the node Ns21 supplied to the source of the NMOS transistor switch 21, and generates a voltage that is higher than the voltage V21 by a prescribed voltage difference as the gate voltage Vg21, which is supplied to the gate of the NMOS transistor switch 21.

[0186] The potential difference across the load element 61, i.e., the voltage difference between the source (node Ns21) and the gate of the NMOS transistor switch 21, is set in accordance with the on-resistance of the load element 61 and the current value of the current source 62. That is, the voltage difference is set to a voltage difference that is greater than the threshold voltage of the NMOS transistor switch 21, i.e., a voltage difference that will cause the NMOS transistor switch 21 to remain in the on state.

[0187] In addition, the load element 61 can include a resistive element or a diode-connected MOS transistor connected between the node Ns21 and the gate of the NMOS transistor switch 21. In addition, the load element 61 can also include a source follower PMOS transistor that receives the voltage V21 at the gate, has the source connected to the gate of the NMOS transistor switch 21, and has the drain connected to a prescribed power supply voltage terminal. In addition, the current source 62 is connected, for example, between the positive power supply voltage VDDH and the gate of the NMOS transistor switch 21. In addition, a positive-side low power supply voltage VCCH can also be used instead of the positive power supply voltage VDDH.

[0188] The voltage across the terminals of each element of the voltage control circuit 60-1 is set to be less than the withstand voltage VDDT, the gate voltage Vg21 is a high voltage compared to the voltage V21 of the node Ns21, and the voltage difference from the voltage V21 is controlled to be less than the withstand voltage VDDT.

[0189] Figure 13 FIG. 6B is a circuit diagram showing the structure of a voltage control circuit 60-2 that is a second embodiment of the voltage control circuit 60.

[0190] The voltage control circuit 60-2 supplies a prescribed power supply voltage as the gate voltage Vg21 to the gate of the NMOS transistor switch 21 in accordance with the voltage V21 received at the source of the NMOS transistor switch 21.

[0191] The voltage control circuit 60-2 includes switches 63 and 64 that selectively supply one of the reference power supply voltage VGND and the positive-side low power supply voltage VCCH to the gate of the NMOS transistor switch 21. Each of the switches 63 and 64 is turned on / off by a control signal S60 generated by the control section 101, for example.

[0192] The control signal S60 can be controlled, for example, based on the logic value (0, 1) of a prescribed bit of digital data corresponding to the negative voltage signal Vn (= V21) supplied to the source of the NMOS transistor switch 21. For example, when the voltage value of the negative voltage signal Vn becomes a value on the negative power supply voltage VDDL side, the switches 63 and 64 are caused to be turned on and off, respectively, by the control signal S60. Thereby, the gate voltage Vg21 having the reference power supply voltage VGND is supplied to the gate of the NMOS transistor switch 21. On the other hand, when the voltage value of the negative voltage signal Vn becomes a value on the reference power supply voltage VGND side, the switches 63 and 64 are caused to be turned off and on, respectively, by the control signal S60. Thereby, the positive-side low power supply voltage VCCH is supplied to the gate of the NMOS transistor switch 21.

[0193] Further, in Figure 12 and Figure 13 , an example (60-1, 60-2) of a specific circuit of the voltage control circuit 60 is shown, but it is not limited to this kind of circuit structure. In any case, as the voltage control circuit 60, as long as it can be constituted without exceeding the withstand voltage VDDT, and can maintain the NMOS transistor switch 21 in the on state at the time of failure of the second control unit 23 (switch 23 off) shown in Figure 2 , there is no limitation on the circuit form.

[0194] [Embodiment 2]

[0195] Figure 14 is a circuit diagram showing the structure of an output circuit 200 that is another example of the output circuit of the present application.

[0196] Figure 2 The output circuit 100 shown in Figure 14 The output circuit 200 shown in

[0197] Further, in the output circuit 200 shown in Figure 14 , the positive voltage signal supply circuit 10B is employed instead of the Figure 2The positive voltage signal supply circuit 10A shown, the negative voltage signal supply circuit 20B instead of the negative voltage signal supply circuit 20A, using the control unit 201 instead of the control unit 101. Further, in Figure 14 In the output circuit 200 shown, the output terminal DL2, the switch 32, the switch 34, the switch 42 and the switch 44, the control unit 33, the control unit 43, the output selection switch 31 and the output selection switch 41, the voltage control circuit 50A, the voltage control circuit 60A, the voltage control circuit 55A and the voltage control circuit 65A are newly provided, and other structures are the same as Figure 2 the output circuit shown.

[0198] In Figure 14 , the positive voltage signal supply circuit 10B controls the supply and cut-off of the positive voltage signal Vp (VGND < Vp < VDDH) to the node Ns11 or the node Ns31 of the two systems. The negative voltage signal supply circuit 20B controls the supply and cut-off of the negative voltage signal Vn (VGND > Vn > VDDL) to the node Ns21 or the node Ns41 of the two systems.

[0199] The output selection switch 31 includes a PMOS transistor switch, the source of which (hereinafter referred to as the PMOS transistor switch 31) is connected to the node Ns31, and the drain is connected to the output terminal DL2.

[0200] The output selection switch 41 includes an NMOS transistor switch, the source of which (hereinafter referred to as the NMOS transistor switch 41) is connected to the node Ns41, and the drain is connected to the output terminal DL2.

[0201] The switch 32 includes, for example, an NMOS transistor switch connected between the node Ns31 and the reference power supply terminal which supplies the reference power supply voltage VGND. The switch 42 includes, for example, a PMOS transistor switch connected between the node Ns41 and the reference power supply terminal.

[0202] The control unit 33 includes, for example, a PMOS transistor switch 33 (hereinafter also referred to simply as switch 33) connected between the gate of the PMOS transistor switch 31 and the reference power supply terminal. The control unit 33 is controlled in cooperation with the control of the on state of the switch 32, and when it becomes the on state together with the switch 32, the reference power supply voltage VGND is supplied to the gate of the PMOS transistor switch 31, and the PMOS transistor switch 31 is controlled to the off state. The control unit 34 includes, for example, an NMOS transistor switch 43 (hereinafter also referred to simply as switch 43) connected between the gate of the NMOS transistor switch 41 and the reference power supply terminal. The control unit 34 is controlled in cooperation with the control of the on state of the switch 42, and when it becomes the on state together with the switch 42, the reference power supply voltage VGND is supplied to the gate of the NMOS transistor switch 41, and the NMOS transistor switch 41 is controlled to the off state.

[0203] Further, in Figure 14 , an example in which the control unit 33 and the control unit 34 are constituted by switches is shown.

[0204] The voltage control circuit 50A is connected to the gate of the PMOS transistor switch 31, and like the voltage control circuit 50, it becomes the active state when the control unit 33 is the inactive state (the switch 33 is off), and controls the PMOS transistor switch 31 to the on state. Further, when the control unit 33 is the active state (the switch 33 is on), the voltage control circuit 50A is made the inactive state. The voltage control circuit 60A is connected to the gate of the NMOS transistor switch 41, and like the voltage control circuit 60, it becomes the active state when the control unit 43 is the inactive state (the switch 43 is off), and controls the NMOS transistor switch 41 to the on state. Further, when the control unit 43 is the active state (the switch 43 is on), the voltage control circuit 60A is made the inactive state.

[0205] The voltage control circuit 55A is connected to the back gate of the PMOS transistor switch 31, and like the voltage control circuit 55, it controls the back gate voltage of the PMOS transistor switch 31 to suppress the operation of the parasitic bipolar transistor. The voltage control circuit 65A is connected to the back gate of the NMOS transistor switch 41, and like the voltage control circuit 65, it controls the back gate voltage of the NMOS transistor switch 41 to suppress the operation of the parasitic bipolar transistor.

[0206] In Figure 14 , the circuit 202 included between the node Ns11 and the node Ns21 and the output terminal DL1 and the circuit 203 included between the node Ns31 and the node Ns41 and the output terminal DL2 have the same function as each other, and when one of them performs the output operation of the positive voltage signal, the other performs the output operation of the negative voltage signal.

[0207] Figure 14 The positive voltage signal supply circuit 10B shown is in Figure 2 The positive voltage signal supply circuit 10A shown is formed by adding a switch 34, which controls the supply and cutoff of the positive voltage signal Vp to node Ns31. Since switch 34 also passes through the positive voltage signal Vp with a wide voltage range, it includes a CMOS switch similar to switch 14. Furthermore, the amplifier circuit 10 included in the positive voltage signal supply circuit 10B can also be configured to internally include the functions of switches 14 and 34.

[0208] The negative voltage signal supply circuit 20B is in Figure 2 The negative voltage signal supply circuit 20A shown is formed by adding a switch 44, which controls the supply and cutoff of the negative voltage signal Vn to node Ns41. Since switch 44 also passes through the negative voltage signal Vn with a wide voltage range, it includes a CMOS switch similar to switch 24. Furthermore, the amplifier circuit 20 included in the negative voltage signal supply circuit 20B can also be configured to internally include the functions of switches 24 and 44.

[0209] exist Figure 14 In the output circuit 200 shown, when a positive voltage signal Vp is output to the output terminal DL1, the switches 12-14 and 22-24 that control the output to the output terminal DL1 are connected to the circuit. Figure 4 The positive drive period T2 (including the switching periods before and after) is controlled in the same way as the positive drive period T4 (including the switching periods before and after). At this time, the switches 32-34 and 42-44 that control the output to the output terminal DL2 are controlled in the same way as the negative drive period T4 (including the switching periods before and after) of switches 12-14 and 22-24, and output a negative voltage signal Vn to the output terminal DL2.

[0210] Additionally, when a negative voltage signal Vn is output to the output terminal DL1, the switches 12-14 and 22-24 that control the output to the output terminal DL1 are engaged with... Figure 4 The negative drive period T4 (including the switching periods before and after) is controlled in the same way as the positive drive period T2 (including the switching periods before and after). At this time, the switches 32-34 and 42-44 that control the output to the output terminal DL2 are controlled in the same way as the switches 12-14 and 22-24 that control the positive drive period T2 (including the switching periods before and after), and output a positive voltage signal Vp to the output terminal DL2.

[0211] and Figure 2 Similarly, the control unit 201, as shown in the control unit 101, is in accordance with...Figure 4 The timing shown generates the control signals Sll-S13, S22-S24. Further, the control section 201 generates the control signals S32-S34, S42-S44 of the signal patterns. Furthermore, in the case where the switches 14, 24, 34, 44 each include a complementary switch, the respective complementary signals of S14, S24, S34, S44 are also generated by the control section 201. In addition, although the generation of the control signals by the control section 201 is omitted in Figure 14 the voltage control circuits 55 and 65, and the respective switches included in the voltage control circuits 55A and 65A, and the control signals required for the control of the respective voltage control circuits 50, 60, 50A, 60A are also generated by the control section 201.

[0212] Thus, in the output circuit 200 shown in Figure 14 the same manner as the output circuit 100, the drive control shown in Figure 4 is performed. However, with respect to the drive control of the output terminal DL2, the supply period of the positive voltage signal Vp and the supply period of the negative voltage signal Vn are exchanged in the drive control shown in Figure 4 . That is, when the positive voltage signal Vp is supplied to the output terminal DLl, the negative voltage signal Vn is supplied to the output terminal DL2, and when the negative voltage signal Vn is supplied to the output terminal DLl, the positive voltage signal Vp is supplied to the output terminal DL2.

[0213] Further, in the output circuit 200 shown in Figure 14 the same manner as the output circuit 100, each element can be constituted by a low voltage withstanding element, and thus the area saving and the cost reduction of the output circuit can be sought.

[0214] Figure 15 is a block diagram showing the outline structure of a liquid crystal display device 400 including a data driver 73 having the output circuit of the present application.

[0215] In the output circuit 200 shown in Figure 15In the active matrix type display panel 71 including a liquid crystal display device, m (m is a natural number of 2 or more) horizontal scan lines S1 to Sm extending in the horizontal direction of a two-dimensional picture and n (n is a natural number of 2 or more) data lines D1 to Dn extending in the vertical direction of the two-dimensional picture are formed in each pixel unit. A display cell functioning as a pixel is formed at each intersection of the horizontal scan lines and the data lines. The display cell includes at least a switching element and a pixel electrode, and when the switching element becomes in an on state in accordance with a scan pulse of the horizontal scan line, a gray scale voltage signal of the data line is applied to the pixel electrode via the switching element, and the brightness of the liquid crystal display device is controlled in accordance with the gray scale voltage applied to the pixel electrode. Further, in the display panel 71, a plurality of display cells are arranged in a matrix form, and a display screen is formed by the display cells. Figure 15 In the display panel 71, the structure of the display cell is omitted from the description.

[0216] The drive control section 74 receives an image signal VD in which a control signal and the like are integrated, generates a timing signal based on a horizontal synchronization signal from the image signal VD, and supplies the timing signal to the scan driver 72. In addition, the drive control section 74 generates various control signal groups and a sequence of pixel data PD indicating the gradation of the brightness of each pixel in, for example, 8-bit luminance gray scale, based on the image signal VD, and supplies the sequence to the data driver 73.

[0217] The scan driver 72 sequentially applies a horizontal scan pulse to each of the horizontal scan lines S1 to Sm of the display panel 71 based on the timing signal supplied from the drive control section 74.

[0218] The data driver 73 is formed on, for example, a semiconductor device such as a Large Scale Integrated Circuit (LSI). The data driver 73 converts the pixel data PD supplied from the drive control section 74 into gray scale voltage signals G1 to Gn having a gray scale voltage corresponding to each of the pixel data PD for each of n in one horizontal scan line. Then, the data driver 73 applies the gray scale voltage signals G1 to Gn to the data lines D1 to Dn of the display panel 71. Further, a part or all of the circuit of the scan driver 72 or the data driver 73 can be integrally formed with the display panel. In addition, the data driver 73 can include a plurality of LSIs.

[0219] Figure 16 is a block diagram showing the internal structure of the data driver 73.

[0220] As Figure 16As shown, the data driver 73 includes a shift register 600, a data register latch circuit 700, a level shift circuit 800, a level voltage generation circuit 500, a decoder circuit 900, and an output amplification circuit 2000. In addition, an interface circuit (not shown) is included which receives a control signal or an image digital signal supplied from the drive control section 74, generates a clock signal or a control signal required inside the driver, and outputs a signal group which has been subjected to timing adjustment with the image digital signal. Figure 15 In the drawing, the details of the interface circuit are omitted for the sake of explanation. Figure 16

[0221] Further, with respect to the power supply voltage, the shift register 600 and the data register latch circuit 700 are supplied with at least a reference power supply voltage VGND and a positive-side low power supply voltage VCCH, and the block which generates the negative-side signal is further supplied with a negative-side low power supply voltage VCCL. The level shift circuit 800, the level voltage generation circuit 500, the decoder circuit 900, and the output amplification circuit 2000 are supplied with at least the reference power supply voltage VGND, a positive power supply voltage VDDH, and a negative power supply voltage VDDL.

[0222] The shift register 600 generates a plurality of latch timing signals for selection which are used to perform latching in synchronization with the clock signal CLK in accordance with a start pulse, and supplies the data register latch circuit 700.

[0223] The data register latch circuit 700 receives an image digital signal, a polarity inversion signal (POL), a timing control signal, and the like, imports the image digital signal by every predetermined number in accordance with each of the latch timing signals supplied from the shift register 600, and supplies the predetermined number of image digital signals to the level shift circuit 800 in accordance with the latch timing.

[0224] Further, the data register latch circuit 700 selects the output of the image digital signal to the level shifter 80P or the level shifter 80N corresponding to the positive or the negative based on the polarity inversion signal (POL).

[0225] ​The level shifting circuit 800 includes a positive level shifter 80P and a negative level shifter 80N. The positive level shifter 80P converts low-amplitude (VGND / VCCH) image digital signals into positive image digital signals with analog voltage amplitude (VGND / VDDH). The negative level shifter 80N converts low-amplitude (VGND / VCCL) image digital signals into negative image digital signals with analog voltage amplitude (VGND / VDDL). A predetermined number of image digital data signals supplied from the data register latch circuit 700 are sent to the positive level shifter 80P or the negative level shifter 80N according to a polarity reversal signal (POL), widened to an analog voltage amplitude corresponding to each polarity, and then sent to the positive decoder 90P or the negative decoder 90N.

[0226] The decoder circuit 900 includes a positive decoder 90P and a negative decoder 90N in every two outputs. Furthermore, the arrangement order of the decoders 90P and 90N of each polarity within the decoder circuit 900 can be changed.

[0227] The voltage level generator circuit 500 generates multiple voltage levels with different values ​​for the positive and negative terminals, and supplies them to the decoder 90P and decoder 90N respectively.

[0228] The decoder circuit 900 selects a level voltage corresponding to the image digital signal after level shifting from the plurality of level voltages, using the two outputs of a set of positive decoder 90P and negative decoder 90N as units, and supplies the level voltage selected according to each polarity to the output amplifier circuit 2000.

[0229] The output amplifier circuit 2000 includes, for example, the following: Figure 14 The output circuit 2000 receives the polarity inversion signal (POL) and a switching control signal group, performs operational amplification on the voltage level of each polarity selected by the decoder circuit 900, and outputs a positive voltage signal (Vp) to one of the two output terminals of the data driver and a negative voltage signal (Vn) to the other, according to the polarity inversion signal (POL). Furthermore, in the output amplifier circuit 2000, the polarity inversion signal (POL) is used to control, for example... Figure 14 The output circuit 200 provides control signals S12, S13, S14, S22, S23, S24, S32, S33, S34, S42, S43, and S44, thereby controlling the on / off states of switches 12, 13, 14, 22, 23, 24, 32, 33, 34, 42, 43, and 44. Furthermore,Figure 14 The control section 201 that generates each control signal can also be provided in common for a plurality of output circuits 200 of the output amplification circuit 2000.

[0230] In Figure 16 In the block diagram of the data driver, the blocks having a voltage range of the analog voltage amplitude are the level shift circuit 800, the decoder circuit 900, the output amplification circuit 2000, and the level voltage generation circuit 500.

[0231] Further, the level voltage generation circuit 500 can be divided into a positive analog voltage range (VGND ~ VDDH) and a negative analog voltage range (VGND ~ VDDL) to constitute. The output amplification circuit 2000 can also include elements of a voltage resistance of each of the positive analog voltage range (VGND ~ VDDH) and the negative analog voltage range (VGND ~ VDDL).

[0232] That is, Figure 16 In the data driver, the liquid crystal drive voltage signal of the voltage range of VDDL ~ VDDH is output to the output terminal as the negative voltage signal and the positive voltage signal, but the elements constituting the data driver can include a low voltage resistance VDDT element capable of operating in the positive analog voltage range (VGND ~ VDDH) or the negative analog voltage range (VGND ~ VDDL) of about one-half of the liquid crystal drive voltage range. In the case of a transistor of the low voltage resistance VDDT, for example, the gate insulating film can be thinned, and the output circuit including the transistor can be implemented in a space-saving manner. Further, since the voltage resistance is reduced, the element spacing can also be narrowed. Thus, Figure 16 The data driver can be constituted in a space-saving manner, and thus the price can be reduced.

Claims

1. An output circuit characterized by comprising: has: a positive voltage signal supply circuit that supplies a positive voltage signal that is a high voltage compared to a reference power supply voltage to a first node or cuts off supply of the positive voltage signal to the first node; a negative voltage signal supply circuit that supplies a negative voltage signal that is a low voltage compared to the reference power supply voltage to a second node or cuts off supply of the negative voltage signal to the second node; a first output terminal; a first switch including a first P-type metal oxide semiconductor transistor switch having a source connected to the first node and a drain connected to the first output terminal, which connects the first output terminal and the first node in an on state and cuts off connection of the first output terminal and the first node in an off state; a second switch including a first N-type metal oxide semiconductor transistor switch having a source connected to the second node and a drain connected to the first output terminal, which connects the first output terminal and the second node in an on state and cuts off connection of the first output terminal and the second node in an off state; a third switch that applies the reference power supply voltage to the first node in an on state and stops application of the reference power supply voltage to the first node in an off state; a fourth switch that applies the reference power supply voltage to the second node in an on state and stops application of the reference power supply voltage to the second node in an off state; a first voltage control circuit connected to a gate of the first switch, which controls the first switch to be in the on state; a second voltage control circuit connected to a gate of the second switch, which controls the second switch to be in the on state; a first control unit connected to the gate of the first switch, which controls the first switch to be in the off state; a second control unit connected to the gate of the second switch, which controls the second switch to be in the off state; a third voltage control circuit that takes a voltage of a source or a drain of the first P-type metal oxide semiconductor transistor switch as a first voltage and supplies a second voltage that is a result of level shifting the first voltage to a high potential side to a back gate of the first P-type metal oxide semiconductor transistor switch or supplies the reference power supply voltage to the back gate of the first P-type metal oxide semiconductor transistor switch; and a fourth voltage control circuit that takes a voltage of a source or a drain of the first N-type metal oxide semiconductor transistor switch as a third voltage and supplies a fourth voltage that is a result of level shifting the third voltage to a low potential side to a back gate of the first N-type metal oxide semiconductor transistor switch or supplies the reference power supply voltage to the back gate of the first N-type metal oxide semiconductor transistor switch. the first output terminal has an output voltage range between a maximum value of the positive voltage signal and a minimum value of the positive voltage signal, 2. The output circuit according to claim 1, characterized by at least the first switch and the second switch are composed of transistors having a lower withstand voltage than the output voltage range. ​ 3. The output circuit according to claim 1, characterized by When the first P-type metal oxide semiconductor transistor switch is controlled to be in the on state, the third voltage control circuit supplies, as a first voltage, a voltage of a source or a drain of the first P-type metal oxide semiconductor transistor switch, and supplies, as a second voltage, a voltage obtained by performing level shifting on the first voltage to a high potential side, to a back gate of the first P-type metal oxide semiconductor transistor switch, and when the first P-type metal oxide semiconductor transistor switch is controlled to be in the off state, the third voltage control circuit supplies the reference power supply voltage to the back gate of the first P-type metal oxide semiconductor transistor switch, When the first N-type metal oxide semiconductor transistor switch is controlled to be in the on state, the fourth voltage control circuit supplies, as a third voltage, a voltage of a source or a drain of the first N-type metal oxide semiconductor transistor switch, and supplies, as a fourth voltage, a voltage obtained by performing level shifting on the third voltage to a low potential side, to a back gate of the first N-type metal oxide semiconductor transistor switch, and when the first N-type metal oxide semiconductor transistor switch is controlled to be in the off state, the fourth voltage control circuit supplies the reference power supply voltage to the back gate of the first N-type metal oxide semiconductor transistor switch.

4. The output circuit according to claim 1 or 2, characterized by The third voltage control circuit includes: a first load element connected between the source or the drain of the first P-type metal oxide semiconductor transistor switch and the back gate of the first P-type metal oxide semiconductor transistor switch; a first current source that sets a current value flowing to the first load element; and a first back gate control switch that, in an on state, applies the reference power supply voltage to the back gate of the first P-type metal oxide semiconductor transistor switch, and, in an off state, stops the application of the reference power supply voltage to the back gate of the first P-type metal oxide semiconductor transistor switch, When the first P-type metal oxide semiconductor transistor switch is controlled to be in the on state, the first load element receives, as the first voltage, a voltage of the source or the drain of the first P-type metal oxide semiconductor transistor switch, and outputs, as the second voltage, a voltage obtained by performing level shifting on the first voltage by a voltage difference based on the current value flowing to the first load element, to the back gate of the first P-type metal oxide semiconductor transistor switch, When the first P-type metal oxide semiconductor transistor switch is controlled to be in the off state, the first back gate control switch is made to be in the on state, and the reference power supply voltage is supplied to the back gate of the first P-type metal oxide semiconductor transistor switch.

5. The output circuit according to any one of claims 1 to 3, characterized by, The fourth voltage control circuit includes: a second load element connected between the source or the drain of the first N-type metal oxide semiconductor transistor switch and the back gate of the first N-type metal oxide semiconductor transistor switch; a second current source that sets a current value flowing to the second load element; and a second back gate control switch that, in an on state, applies the reference power supply voltage to the back gate of the first N-type metal oxide semiconductor transistor switch, and, in an off state, stops the application of the reference power supply voltage to the back gate of the first N-type metal oxide semiconductor transistor switch. a second back gate control switch which applies the reference power supply voltage to the back gate of the first N-type metal oxide semiconductor transistor switch in an on state, and stops the application of the reference power supply voltage to the back gate of the first N-type metal oxide semiconductor transistor switch in an off state, when the first N-type metal oxide semiconductor transistor switch is controlled to be in the on state, the second load element receives the voltage of the source or drain of the first N-type metal oxide semiconductor transistor switch as the third voltage, and outputs the third voltage which is level-shifted by a voltage difference based on the current value flowing to the second load element as the fourth voltage to the back gate of the first N-type metal oxide semiconductor transistor switch, when the first N-type metal oxide semiconductor transistor switch is controlled to be in the off state, the second back gate control switch is made to be in the on state, and the reference power supply voltage is supplied to the back gate of the first N-type metal oxide semiconductor transistor switch.

6. The output circuit according to claim 4, characterized by the first current source is connected between the back gate of the first P-type metal oxide semiconductor transistor switch and a positive power supply voltage terminal which receives a positive power supply voltage, the first back gate control switch is connected between the back gate of the first P-type metal oxide semiconductor transistor switch and a reference power supply voltage terminal which receives the reference power supply voltage, the first load element includes: a diode-connected metal oxide semiconductor transistor which is connected between the source or drain of the first P-type metal oxide semiconductor transistor switch and the back gate of the first P-type metal oxide semiconductor transistor switch; or a P-type metal oxide semiconductor source follower transistor which receives the voltage of the source or drain of the first P-type metal oxide semiconductor transistor switch as the first voltage from the gate, and is connected to the back gate of the first P-type metal oxide semiconductor transistor switch from the source.

7. The output circuit according to claim 5, characterized by the second current source is connected between the back gate of the first N-type metal oxide semiconductor transistor switch and a negative power supply voltage terminal which receives a negative power supply voltage, the second back gate control switch is connected between the back gate of the first N-type metal oxide semiconductor transistor switch and a reference power supply voltage terminal which receives the reference power supply voltage, the second load element includes: a diode-connected metal oxide semiconductor transistor which is connected between the source or drain of the first N-type metal oxide semiconductor transistor switch and the back gate of the first N-type metal oxide semiconductor transistor switch; or an N-type metal oxide semiconductor source follower transistor which receives the voltage of the source or drain of the first N-type metal oxide semiconductor transistor switch as the third voltage from the gate, and is connected to the back gate of the first N-type metal oxide semiconductor transistor switch from the source.

8. The output circuit according to claim 4, characterized by the first current source is connected between the back gate of the first P-type metal oxide semiconductor transistor switch and a positive power supply voltage terminal which receives a positive power supply voltage, the first back gate control switch is connected between the back gate of the first P-type metal oxide semiconductor transistor switch and a reference power supply voltage terminal that receives the reference power supply voltage, the first load element includes: a first P-type metal oxide semiconductor transistor whose drain is connected to one of the source and the drain of the first P-type metal oxide semiconductor transistor switch, whose gate is connected to the other of the source and the drain of the first P-type metal oxide semiconductor transistor switch, and whose source is connected to the back gate of the first P-type metal oxide semiconductor transistor switch; and a second P-type metal oxide semiconductor transistor whose drain is connected to the other of the source and the drain of the first P-type metal oxide semiconductor transistor switch, whose gate is connected to the one of the source and the drain of the first P-type metal oxide semiconductor transistor switch, and whose source is connected to the back gate of the first P-type metal oxide semiconductor transistor switch.

9. The output circuit according to claim 5, characterized by the second current source is connected between the back gate of the first N-type metal oxide semiconductor transistor switch and a negative power supply voltage terminal that receives a negative power supply voltage, the second back gate control switch is connected between the back gate of the first N-type metal oxide semiconductor transistor switch and the reference power supply voltage terminal that receives the reference power supply voltage, the second load element includes: a first N-type metal oxide semiconductor transistor whose drain is connected to one of the source and the drain of the first N-type metal oxide semiconductor transistor switch, whose gate is connected to the other of the source and the drain of the first N-type metal oxide semiconductor transistor switch, and whose source is connected to the back gate of the first N-type metal oxide semiconductor transistor switch; and a second N-type metal oxide semiconductor transistor whose drain is connected to the other of the source and the drain of the first N-type metal oxide semiconductor transistor switch, whose source is connected to the one of the source and the drain of the first N-type metal oxide semiconductor transistor switch, and whose source is connected to the back gate of the first N-type metal oxide semiconductor transistor switch.

10. The output circuit according to any one of claims 1 to 3, characterized by, a control section that performs the following in conjunction: the enable / disable control of the first and second control units; the on / off control of the third and fourth switches; the enable / disable control of the first and second voltage control circuits; the control of the voltage supplied to the back gate of the first P-type metal oxide semiconductor transistor switch by the third voltage control circuit; the control of the voltage supplied to the back gate of the first N-type metal oxide semiconductor transistor switch by the fourth voltage control circuit; and the voltage supply / cut-off control of the positive and negative voltage signal supply circuits to switch the positive and negative voltage signals at a prescribed timing and output from the first output terminal.

11. The output circuit according to claim 10, wherein The control section sets a first period as a transition period for switching from the negative electrode voltage signal to the positive electrode voltage signal output from the first output terminal, a second period for outputting the positive electrode voltage signal from the first output terminal, a third period as a transition period for switching from the positive electrode voltage signal to the negative electrode voltage signal output from the first output terminal, and a fourth period for outputting the negative electrode voltage signal from the first output terminal, During the first period, the supply of the positive electrode voltage signal from the positive electrode voltage signal supply circuit is cut off, the supply of the negative electrode voltage signal from the negative electrode voltage signal supply circuit is cut off, both the third switch and the fourth switch are brought to an on state, the first control unit and the second control unit are brought to an active state and an inactive state, respectively, the first voltage control circuit and the second voltage control circuit are brought to an inactive state and an active state, respectively, and the third voltage control circuit is controlled to supply the reference power supply voltage to the back gate of the first P-type metal oxide semiconductor transistor switch, and the fourth voltage control circuit is controlled to supply a voltage obtained by level-shifting the voltage of the source or drain of the first P-type metal oxide semiconductor transistor switch to the back gate of the first N-type metal oxide semiconductor transistor switch, whereby the first P-type metal oxide semiconductor transistor switch is brought to an off state, and the first N-type metal oxide semiconductor transistor switch is brought to an on state, so that the reference power supply voltage is supplied to the first node and the second node and the first output terminal, During the second period, the supply of the negative electrode voltage signal from the negative electrode voltage signal supply circuit is continued to be cut off, the positive electrode voltage signal is supplied from the positive electrode voltage signal supply circuit to the first node, the third switch and the fourth switch are brought to an off state and an on state, respectively, the first control unit and the second control unit are brought to an inactive state and an active state, respectively, the first voltage control circuit and the second voltage control circuit are brought to an active state and an inactive state, respectively, and the third voltage control circuit is controlled to supply a voltage obtained by level-shifting the voltage of the source or drain of the first P-type metal oxide semiconductor transistor switch to the back gate of the first P-type metal oxide semiconductor transistor switch, and the fourth voltage control circuit is controlled to supply the reference power supply voltage to the back gate of the first N-type metal oxide semiconductor transistor switch, whereby the first P-type metal oxide semiconductor transistor switch is brought to an on state, and the first N-type metal oxide semiconductor transistor switch is brought to an off state, so that the positive electrode voltage signal is supplied to the first output terminal via the first P-type metal oxide semiconductor transistor switch, and the reference power supply voltage is supplied to the second node via the fourth switch, During the third period, the supply of the negative voltage signal from the negative voltage signal supply circuit is continued to be cut off, the supply of the positive voltage signal from the positive voltage signal supply circuit is cut off, both the third switch and the fourth switch are made to be in the on state, the first control unit and the second control unit are continued to be made to be in the invalid state and the valid state respectively, the first voltage control circuit and the second voltage control circuit are continued to be made to be in the valid state and the invalid state respectively, and the third voltage control circuit is controlled to continue to supply the voltage after the voltage of the source or the drain of the first P-type metal oxide semiconductor transistor switch is level-shifted to the back gate of the first P-type metal oxide semiconductor transistor switch, and the fourth voltage control circuit is controlled to continue to supply the reference power supply voltage to the back gate of the first N-type metal oxide semiconductor transistor switch, so that the first P-type metal oxide semiconductor transistor switch is made to be in the on state, the first N-type metal oxide semiconductor transistor switch is made to be in the off state, the reference power supply voltage is supplied to the first node and the second node and the first output terminal, During the fourth period, the supply of the positive voltage signal from the positive voltage signal supply circuit is continued to be cut off, on the other hand, the negative voltage signal is supplied from the negative voltage signal supply circuit to the second node, the third switch and the fourth switch are made to be in the on state and the off state respectively, the first control unit and the second control unit are made to be in the valid state and the invalid state respectively, the first voltage control circuit and the second voltage control circuit are made to be in the invalid state and the valid state respectively, and the third voltage control circuit is controlled to supply the reference power supply voltage to the back gate of the first P-type metal oxide semiconductor transistor switch, and the fourth voltage control circuit is controlled to supply the voltage after the voltage of the source or the drain of the first N-type metal oxide semiconductor transistor switch is level-shifted to the back gate of the first N-type metal oxide semiconductor transistor switch, so that the first P-type metal oxide semiconductor transistor switch is made to be in the off state, the first N-type metal oxide semiconductor transistor switch is made to be in the on state, thereby the negative voltage signal is supplied to the first output terminal through the first N-type metal oxide semiconductor transistor switch, and the reference power supply voltage is supplied to the first node through the third switch.

12. The output circuit according to any one of claims 1 to 3, characterized by, Comprise: a second output terminal; a third node and a fourth node; a fifth switch comprising a second P-type metal oxide semiconductor transistor switch with a source connected to the third node and a drain connected to the second output terminal, which connects the second output terminal and the third node when in the on state, and cuts off the connection between the second output terminal and the third node when in the off state; a sixth switch including a second N-type metal oxide semiconductor transistor switch whose source is connected to the fourth node and whose drain is connected to the second output terminal, which connects the second output terminal and the fourth node in an on state and cuts the connection between the second output terminal and the fourth node in an off state; a seventh switch which applies the reference power supply voltage to the third node in an on state and stops the application of the reference power supply voltage to the third node in an off state; an eighth switch which applies the reference power supply voltage to the fourth node in an on state and stops the application of the reference power supply voltage to the fourth node in an off state; a fifth voltage control circuit connected to the gate of the fifth switch and controlling the fifth switch to be in an on state; a sixth voltage control circuit connected to the gate of the sixth switch and controlling the sixth switch to be in an on state; a third control unit connected to the gate of the fifth switch and controlling the fifth switch to be in an off state; a fourth control unit connected to the gate of the sixth switch and controlling the sixth switch to be in an off state; a seventh voltage control circuit which supplies, as a fifth voltage, the voltage of the source or the drain of the second P-type metal oxide semiconductor transistor switch to the back gate of the second P-type metal oxide semiconductor transistor switch after level-shifting the fifth voltage to the high potential side or supplies the reference power supply voltage to the back gate of the second P-type metal oxide semiconductor transistor switch; and a eighth voltage control circuit which supplies, as a seventh voltage, the voltage of the source or the drain of the second N-type metal oxide semiconductor transistor switch to the back gate of the second N-type metal oxide semiconductor transistor switch after level-shifting the seventh voltage to the low potential side or supplies the reference power supply voltage to the back gate of the second N-type metal oxide semiconductor transistor switch, the positive electrode voltage signal supply circuit controls the supply or cut-off of the positive electrode voltage signal to the first node or the third node, the negative electrode voltage signal supply circuit controls the supply or cut-off of the negative electrode voltage signal to the second node or the fourth node. Further comprising a control section which performs the following in conjunction:

13. The output circuit according to claim 12, characterized by the enable / disable control of the first to fourth control units; the enable / disable control of the first to sixth voltage control circuits, respectively; ​ on / off control of the third switch, the fourth switch, the seventh switch, and the eighth switch; control of the third voltage control circuit and the seventh voltage control circuit over voltage supplied to the back gate of the first P-type metal oxide semiconductor transistor switch and the second P-type metal oxide semiconductor transistor switch; control of the fourth voltage control circuit and the eighth voltage control circuit over voltage supplied to the back gate of the first N-type metal oxide semiconductor transistor switch and the second N-type metal oxide semiconductor transistor switch; and voltage supply / cutoff control of the positive voltage signal supply circuit and the negative voltage signal supply circuit, respectively, to output one of the positive voltage signal and the negative voltage signal from the first output terminal and the other of the positive voltage signal and the negative voltage signal from the second output terminal, and to switch the polarity of the voltage signal output from the first output terminal and the second output terminal at a prescribed timing.

14. The output circuit according to any one of claims 1 to 3, wherein the first voltage control circuit receives a voltage of the first node and supplies a voltage obtained by level-shifting the voltage of the first node to a low voltage side to a gate of the first P-type metal oxide semiconductor transistor switch, the second voltage control circuit receives a voltage of the second node and supplies a voltage obtained by level-shifting the voltage of the second node to a high voltage side to a gate of the first N-type metal oxide semiconductor transistor switch.

15. The output circuit according to claim 14, characterized by the first voltage control circuit includes: a third load element connected between the first node and the gate of the first P-type metal oxide semiconductor transistor switch; and a third current source that sets a current value flowing to the third load element, when the first P-type metal oxide semiconductor transistor switch is controlled to be in an on state, the third load element supplies a voltage obtained by level-shifting a voltage with respect to the first node by a voltage difference based on the current value flowing to the third load element to the gate of the first P-type metal oxide semiconductor transistor switch.

16. The output circuit of claim 14, wherein the second voltage control circuit includes: a fourth load element connected between the second node and the gate of the first N-type metal oxide semiconductor transistor switch; and a fourth current source that sets a current value flowing to the fourth load element, when the first N-type metal oxide semiconductor transistor switch is controlled to be in an on state, the fourth load element supplies a voltage obtained by level-shifting a voltage with respect to the second node by a voltage difference based on the current value flowing to the fourth load element to the gate of the first N-type metal oxide semiconductor transistor switch.

17. The output circuit according to any one of claims 1 to 3, characterized by, the positive voltage signal has a voltage value higher than the reference power supply voltage and lower than a prescribed positive power supply voltage, and the negative voltage signal has a voltage value lower than the reference power supply voltage and higher than a prescribed negative power supply voltage, The first voltage control circuit receives the reference power supply voltage and a negative-side low power supply voltage having a voltage value lower than the reference power supply voltage and higher than the negative power supply voltage, and selects one of the reference power supply voltage and the negative-side low power supply voltage to supply to a gate of the first P-type metal oxide semiconductor transistor switch based on a voltage value of the positive voltage signal.

18. The output circuit according to any one of claims 1 to 3, characterized by, The positive voltage signal has a voltage value higher than the reference power supply voltage and lower than a prescribed positive power supply voltage, and the negative voltage signal has a voltage value lower than the reference power supply voltage and higher than a prescribed negative power supply voltage, The second voltage control circuit receives the reference power supply voltage and a positive-side low power supply voltage having a voltage value lower than the reference power supply voltage and lower than the positive power supply voltage, and selects one of the reference power supply voltage and the positive-side low power supply voltage to supply to a gate of the first N-type metal oxide semiconductor transistor switch based on a voltage value of the negative voltage signal.

19. A display driver, comprising: An output circuit according to any one of claims 1 to 17, 20. A display device comprising: A display driver including a plurality of output circuits according to any one of claims 1 to 17, and outputting a plurality of gray scale voltage signals having voltage values of positive polarity or negative polarity from the plurality of output circuits; and A liquid crystal display panel having a plurality of data lines that receive the plurality of gray scale voltage signals.

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