Managing the selection of voltage ranges for blocks used in memory devices

Abstract

This disclosure relates to managing voltage range selection for blocks in a memory device. A processing apparatus of a memory subsystem is configured to: sort a plurality of blocks of the memory device; divide the sorted plurality of blocks into a plurality of block segments; scan a first block at a first boundary of a first block segment in the plurality of block segments; scan a second block at a second boundary of the first block segment; identify a first voltage range associated with the first block based on the scan result of the first block; identify a second voltage range associated with the second block based on a second scan result of the second block; and, in response to determining that the first voltage range matches the second voltage range, assign the first voltage range to each block in a subset of the plurality of blocks assigned to the first block segment.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to managing voltage range selection for blocks of memory devices. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] This disclosure relates to a system comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations including: sorting a plurality of blocks of the memory device; dividing the sorted plurality of blocks into a plurality of block segments; identifying a first voltage interval associated with a first block by scanning a first block at a first boundary of a first block segment among the plurality of block segments; identifying a second voltage interval associated with a second block by scanning a second block at a second boundary of the first block segment; and assigning the first voltage interval to each block in the first block segment in response to determining that the first voltage interval matches the second voltage interval.

[0004] Another aspect of this disclosure relates to a method comprising: sorting a plurality of blocks of a memory device by a processing means; identifying a first voltage interval associated with the first block by scanning a first block at a first boundary of the plurality of sorted blocks; identifying a second voltage interval associated with the second block by scanning a second block at a predetermined position of the plurality of sorted blocks; and assigning the first voltage interval to each block located between the first boundary of the plurality of sorted blocks and the predetermined position of the plurality of sorted blocks in response to determining that the first voltage interval matches the second voltage interval.

[0005] Another aspect of this disclosure is directed to a non-transitory computer-readable storage medium comprising instructions which, when executed by a processing means, cause the processing means to perform operations including: sorting a plurality of blocks of a memory means; dividing the sorted plurality of blocks into a plurality of block segments; identifying a first voltage interval associated with a first block by scanning a first block at a first boundary of a first block segment; identifying a second voltage interval associated with a second block by scanning a second block at a second boundary of the first block segment; and assigning the first voltage interval to each block in the first block segment in response to determining that the first voltage interval matches the second voltage interval. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of some embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 A block diagram illustrating an example method of assigning voltage ranges to blocks of a memory device using a segmented bipartite search technique according to one or more aspects of this disclosure.

[0009] Figure 3 A block diagram illustrating an example method of assigning voltage ranges to blocks of a memory device using a bipartite search technique according to one or more aspects of this disclosure.

[0010] Figure 4 This is a flowchart of an example method for assigning voltage ranges to blocks of a memory device using a segmented bipartite search according to some embodiments of this disclosure.

[0011] Figure 5 This is a flowchart of an example method for assigning voltage ranges to blocks of a memory device by dividing blocks into segments based on post-programming time, according to some embodiments of the present disclosure.

[0012] Figure 6 This is a flowchart of an example method for assigning voltage ranges to blocks of a memory device by dividing blocks into segments based on the number of blocks in each segment, according to some embodiments of the present disclosure.

[0013] Figure 7 An example machine of a computer system is described, within which a set of instructions can be executed to cause the machine to perform any or more of the methods discussed herein. Detailed Implementation

[0014] Embodiments of this disclosure are directed to managing voltage range assignments to blocks of a memory device. The memory subsystem may be a memory device, a memory module, or a hybrid of a memory device and a memory module. The following description, in conjunction with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem containing one or more memory devices, such as those for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0015] The memory subsystem may utilize one or more memory devices (including any combination of different types of non-volatile memory devices and / or volatile memory devices) to store data provided by the host system. In some embodiments, the non-volatile memory devices may be provided by NAND type flash memory devices. The following is combined with... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be grouped into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. A “block” will be referred to herein as a set of contiguous or non-contiguous memory pages. An example of a “block” is an “erasable block,” which is the smallest erasable unit of memory, while a “page” is the smallest writable unit of memory. Each page contains a set of memory cells. A memory cell is an electronic circuit that stores information.

[0016] Data operations can be performed by the memory subsystem. Data operations can be initiated by the host. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on a memory device at the memory subsystem and to read data from a memory device at the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) of the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., ECC codeword, parity check code), data version (e.g., age used to distinguish the data being written), valid bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0017] A memory device comprises multiple memory cells, each of which may store one or more bits of information, depending on the type of memory cell. A memory cell can be programmed (written to) by applying a voltage to it, which causes the memory cell to retain a charge, thus allowing modulation of the voltage distribution generated by the memory cell. Furthermore, precise control over the amount of charge stored in a memory cell allows the establishment of multiple threshold voltage levels corresponding to different logic levels, thus effectively allowing a single memory cell to store multiple bits of information: in 2... nA memory cell operating at different threshold voltage levels can store n bits of information. Therefore, a read operation can be performed by comparing the measured voltage exhibited by the memory cell with one or more reference read voltage levels to distinguish between two logic levels for a single-level cell and multiple logic levels for a multi-level cell.

[0018] Due to a phenomenon known as slow charge loss, the threshold voltage of a memory cell changes in real time as the cell's charge degrades; this is called "time voltage shift" (because the degradation charge causes the voltage distribution to shift along the voltage axis towards a lower voltage level). The threshold voltage changes rapidly at first (immediately after the memory cell is programmed), and then slows down approximately logarithmically with respect to the time elapsed since the cell programming event. Therefore, failure to mitigate the time voltage shift caused by slow charge loss can lead to an increased bit error rate in read operations.

[0019] However, various common implementations fail to adequately address time-voltage shift or employ inefficient strategies that result in high bit error rates and / or exhibit other drawbacks. Embodiments of this disclosure address these and other drawbacks by implementing a memory subsystem employing a set of read threshold voltage intervals (hereinafter referred to as voltage intervals) and assigning one voltage from a voltage interval to each block stored at the memory device of the memory subsystem based on the post-programming time of each block. A voltage interval represents a set of read level threshold voltages that can be used to perform a read operation at a given block, such that each read level threshold voltage corresponds to a valley value, where each valley value is the distance between two adjacent data states of the block to be read. For example, for a 3-bit TLC block, there may be 8 data states (i.e., levels) and 7 valley values. Therefore, each voltage interval for a TLC block has 7 read voltages, and each valley value has one read voltage. In some implementations, reads may be associated with pages, and each page type corresponds to certain valley values. For page reads, the appropriate read voltage is read from the interval assigned to the block containing the page. One or more valley values ​​for each page type are determined by Gray code used to represent the levels. Gray code refers to a binary digit system where two consecutive valley values ​​differ by only one bit (e.g., binary digits). On a TLC block, some portions of the block can store either a multi-level cell (MLC) with 2 bits per memory cell (generating 4 data states) or a single-level cell (SLC) with 1 bit per memory cell. For the MLC and SLC portions, there can be 3 and 1 read voltages, respectively. The block's association with the die and voltage ranges can be stored in a corresponding metadata table maintained by the memory subsystem controller.

[0020] While assigning voltage ranges to blocks within the memory subsystem solves the problem of time-based voltage shift, an efficient method for calculating the relative age of each block may be required. For example, when the memory subsystem is powered down for an extended period, the system cannot track the downtime. When the memory subsystem is powered back on, it is desirable to identify the voltage range of each block within a short timeframe by performing a small number of operations and scanning a small number of blocks. Therefore, bipartite search and segmented bipartite search algorithms enable the assignment of voltage ranges to blocks without having to scan every single block.

[0021] In some embodiments, voltage range selection techniques can use bipartite search and segmented bipartite search of blocks stored in the memory device of the memory subsystem, thus significantly improving the performance and accuracy of the voltage range selection process for blocks in the memory subsystem. According to embodiments of this disclosure, blocks of the memory device can be sorted by the age of each block from youngest to oldest. In one embodiment, the age of a block can refer to the time elapsed since the block was last programmed. The age of a block can be an absolute age or a relative age (e.g., relative to other blocks in the memory device). In one embodiment, one or more voltage range selection techniques can be used to select a voltage range for each block of the memory device, thereby optimizing the voltage range selection process for performance and accuracy.

[0022] In one embodiment, voltage range selection for each block of the memory device can be performed by performing a bipartite search algorithm on a sorted list of blocks of the memory device to determine a small subset of blocks to be scanned for voltage range determination. In one embodiment, scanning a block of the memory device may refer to performing a read operation on the block using a read level voltage offset associated with a given voltage range, and subsequently determining one or more reliability statistics based on the block's read operations, such that voltage ranges associated with high reliability indicators can be selected and assigned to blocks, as explained in more detail below. In one embodiment, when a voltage range is selected for each of the scanned subsets of blocks, each of the remaining unscanned blocks may have a voltage range assigned based on the voltage range selection for the scanned blocks. In some embodiments, the subset of blocks to be scanned may include a first block at the top of the list of sorted blocks, a second block in the middle of the list of sorted blocks, and a third block at the end of the list of sorted blocks.

[0023] After scanning a subset of blocks, the voltage range assigned to the first block can be compared with the voltage range assigned to the second block. Since voltage range assignment is proportional to the age of the blocks, if the first and second blocks are assigned to the same voltage range, the set of blocks between the first and second blocks in the sorted block list can also be assigned to the same voltage range as the first block. Therefore, if the voltage range of the first block matches the voltage range of the second block (e.g., the same voltage range), the blocks between the top and middle of the sorted list can be assigned to the same voltage range as the first and second blocks. Given that the sorted list is sorted by block age, blocks between the first and second blocks in the sorted list can be assigned to the same voltage range as the first and / or second blocks without scanning those blocks. The blocks between the first and second blocks can then be assigned the voltage range of the first block in the list. Similarly, the voltage range assigned to the second block can be compared with the voltage range assigned to the third block. If the voltage range of the second block matches the voltage range of the third block (e.g., the same voltage range), then the block between the middle and the bottom of the sorted list can be assigned the voltage range of the second block in the list. In this case, the complete list of blocks can have assigned voltage ranges based on the scan results of several blocks in the list, thus significantly improving the performance of the scan memory device.

[0024] On the other hand, if the voltage range assigned to the first block does not match the voltage range assigned to the second block, a new iteration of bipartite search and scan can be performed on the blocks in the sorted list between the first and second blocks to identify the voltage range to be assigned to each block between the first and second blocks. In this case, the fourth block, located in the middle between the first and second blocks, can be identified, scanned, and the fourth voltage range can be assigned to the fourth block based on the scan result. If the voltage range of the first block matches the voltage range of the fourth block, the blocks in the sorted list between the first and fourth blocks can be assigned the voltage range of the first block. Similarly, if the voltage range assigned to the second block does not match the voltage range assigned to the third block, a new iteration of bipartite search and scan can be performed on the blocks in the sorted list between the second and third blocks to identify which voltage range to be assigned to each block between the second and third blocks. In an embodiment, the process of comparing the voltage ranges of the scanned blocks and performing a new iteration of bipartite search and scan of the blocks can be repeated until the voltage range is assigned to each block of the memory device.

[0025] In one embodiment, voltage range selection for blocks of a memory device can be performed by executing a segmented bipartite search algorithm on a sorted list of blocks of the memory device, such that a finite subset of blocks is scanned for voltage range determination. In one embodiment, the blocks of the memory device may be sorted by age of each block, and the list of sorted blocks may be divided into several segments. In an embodiment, dividing the sorted blocks into segments (e.g., where each segment has an equal number of blocks) and then performing a bipartite search on each segment can improve the accuracy of voltage range assignment. As an example, the effect of block-to-block variation is that the selected voltage range may be limited to the blocks within the same segment, since the bipartite search for assigning voltage ranges to blocks is performed on one segment at a time. The bipartite search algorithm can be performed separately for each segment to identify a subset of blocks in the segment to be scanned for voltage range determination. Blocks in each segment can then be assigned to voltage ranges based on the scan results of the blocks in the corresponding segment, as described herein. Figure 4 To explain in more detail. In an illustrative example, for a given segment, a subset of three blocks may be selected for scanning, the blocks comprising a first block at the top of a list of sorted blocks in the segment, a second block in the middle of a list of sorted blocks in the segment, and a third block at the end of a list of sorted blocks in the segment. In an embodiment, a subset of blocks in the segment may be scanned, and voltage ranges may be assigned to each block in the subset of blocks based on the scan results, as explained in more detail above herein.

[0026] The voltage range assigned to the first block and the voltage range assigned to the second block can then be compared to determine if the two voltage ranges match. If the voltage range of the first block matches the voltage range of the second block, it can be determined that the block between the top of the sorted list and the middle of the sorted list of the segment has the same voltage range as the first and second blocks, since voltage range assignment is proportional to the age of the block. Therefore, the block between the first and second blocks in the sorted list of the segment can be projected to have the same voltage range assigned as the first and / or second blocks without having to scan the block. The block between the first and second blocks can then be assigned the voltage range of the first block in the sorted list of the segment. Similarly, the voltage range assigned to the second block can be compared with the voltage range of the third block in a subset of the blocks in the segment. If the voltage range of the second block matches the voltage range of the third block, then the block between the middle and the bottom of the sorted list of the segment can be assigned the voltage range of the second block in the list.

[0027] On the other hand, if the voltage range assigned to the first block in the segment does not match the voltage range assigned to the second block in the segment, a second iteration of bipartite search and scanning can be performed on the blocks between the first and second blocks in the sorted list of the segment to identify which voltage range should be assigned to each block between the first and second blocks in the segment. In this case, the fourth block at the intermediate position between the first and second blocks can be identified and scanned, and the fourth voltage range can be assigned to the fourth block based on the scan result. If the voltage range of the first block matches the voltage range of the fourth block, then the blocks between the first and fourth blocks in the sorted list of the segment can be assigned the voltage range of the first block. Similarly, if the voltage range assigned to the second block does not match the voltage range assigned to the third block, a new iteration of bipartite search and scanning can be performed on the blocks between the second and third blocks in the sorted list of the segment to identify which voltage range should be assigned to each block between the second and third blocks. In one embodiment, the process of comparing voltage intervals of scanned blocks within a segment and performing new iterations of the block bipartite search and scan can be repeated until a voltage interval is assigned to each block within the segment. In another embodiment, the bipartite search and scan for voltage interval selection can be performed for each segment in a group of segments comprising blocks of memory devices, such that when a voltage interval selection is determined for each segment in the group of segments, each block of the memory device is assigned a voltage interval. In one embodiment, blocks of the memory device can be equally divided into segments such that each segment may have approximately the same number of blocks. In another embodiment, blocks of the memory device can be divided into segments based on the post-programming time of the blocks, as explained in more detail below.

[0028] Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, optimizing the voltage range selection process so that each block of the memory subsystem is accurately assigned a voltage range while minimizing performance overhead on the memory subsystem. Because the voltage range selection process supports performing a bipartite search to select only a subset of blocks to be scanned for voltage range determination, while projecting voltage range assignments to the remaining blocks based on the scan results, the performance of performing voltage range determination for blocks is optimized. Furthermore, since the voltage range selection process also supports performing a segmented bipartite search on blocks, the impact of block-to-block variations is limited to the specific range of blocks within a segment, thus improving the accuracy of voltage range selection for blocks in the memory subsystem.

[0029] Figure 1This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0030] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0031] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a networked commercially available device), or such a computing device containing memory and processing means (e.g., a processor).

[0032] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0033] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0034] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0035] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0036] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on changes in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0037] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, and an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0038] While non-volatile memory devices, such as 3D cross-point non-volatile memory cell arrays and NAND-type memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0039] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0040] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0041] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including controller 115, but in another embodiment of the present disclosure, memory subsystem 110 does not include controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0043] In some implementations, the memory subsystem 110 may use a striping scheme in which each data payload (e.g., user data) utilizes multiple dies of the memory device 130 (e.g., a NAND-type flash memory device), such that the payload is distributed across a subset of the dies, while the remaining one or more dies are used to store error correction information (e.g., parity bits). Therefore, the set of blocks distributed across the set of dies of the memory device using a striping scheme is referred to herein as a “superblock.”

[0044] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the controller 115 and decode the addresses to access the memory device 130.

[0045] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0046] According to embodiments of this disclosure, the memory subsystem 110 includes a voltage range assignment component 113, which can be used to implement techniques for assigning voltage ranges to blocks of memory devices 130-140 by performing a bipartite search and a segmented bipartite search. In one embodiment, the voltage range assignment component 113 can sort the blocks of memory devices 130-140 from the youngest block to the oldest block according to the age of each block. In one embodiment, the age of a block can refer to the time elapsed since the block was last programmed. In other embodiments, the age of a block can refer to the relative age of the block based on the sequence (serial number) of the blocks programmed or the power-on timestamp of the blocks programmed. Since the memory devices cannot track power-off times, the accumulated power-on time can be accumulated and tracked by the memory subsystem and written to non-volatile memory before a power-off, reloaded after a power-off and restored from the previous value, and updated on the non-volatile memory, thus achieving a monotonically increasing accumulated power-on time that can be used to timestamp each block when it is programmed. Voltage range assignment component 113 can perform voltage range selection for each block of memory devices 130-140 by performing a bipartite search algorithm on a sorted list of blocks of memory devices 130-140 to determine a small subset of blocks to be scanned for voltage range determination.

[0047] In one embodiment, scanning a block of the memory device may refer to performing read operations on the block using a read level voltage offset associated with a given voltage range and subsequently determining one or more reliability statistics based on the read operations on the block. An example of a reliability statistic is the Raw Bit Error Rate (RBER). RBER corresponds to the number of bit errors per codeword encountered by data stored at the block. A codeword may refer to the minimum permissible read unit. Voltage range assignment component 113 may perform a second set of read operations using a read level voltage offset associated with a second voltage range and determine a corresponding second RBER based on the second set of read operations. In this case, voltage range assignment component 113 may select a voltage range associated with the minimum RBER and may assign the selected range to the block. In some embodiments, when a voltage range is selected for each of the scanned subsets of a block, voltage range assignment component 113 may assign the voltage range to each of the remaining unscanned blocks based on the voltage range selection for the scanned block. Voltage range assignment component 113 can select a first block at the top of the sorted block list, a second block in the middle of the sorted block list, and a third block at the end of the sorted block list to be included in a subset of the blocks to be scanned for voltage range determination.

[0048] While a subset of blocks is being scanned, voltage range assignment component 113 can compare the voltage range assigned to the first block with the voltage range assigned to the second block to determine whether the two voltage ranges refer to the same range value. If the voltage range of the first block matches the voltage range of the second block (e.g., the same voltage range), then voltage range assignment component 113 can determine that the blocks between the top and middle of the sorted list have the same characteristics and can be assigned the same voltage range as the first and second blocks. Therefore, given that the sorted list of blocks is sorted by block age, the blocks between the first and second blocks in the sorted list can be projected to have the same voltage range as the first and / or second blocks without having to scan the blocks. Voltage range assignment component 113 then assigns the voltage range of the first block in the list to the blocks between the first and second blocks. In one embodiment, voltage range assignment component 113 may also compare the voltage range assigned to the second block with the voltage range assigned to the third block, and if the voltage range of the second block matches the voltage range of the third block (e.g., the same voltage range), then the voltage range assignment component 113 may assign the voltage range of the second block in the sorted list to the block between the middle of the sorted list and the bottom of the assignable sorted list.

[0049] If the voltage range assigned to the first block does not match the voltage range assigned to the second block, the voltage range assignment component 113 may initiate a second iteration of bipartite search and scanning to identify which voltage range should be assigned to each block between the first and second blocks. In this case, the voltage range assignment component 113 may identify a fourth block located at an intermediate position between the first and second blocks. The voltage range assignment component 113 may scan the fourth block and may assign the fourth voltage range to the fourth block based on the scan results. The voltage range assignment component 113 may compare the voltage range of the first block with the voltage range of the fourth block. If the voltage ranges match, the voltage range assignment component 113 may assign the voltage range of the first block to a block between the first and fourth blocks in the sorted list. In an embodiment, the voltage range assignment component 113 may repeat the process of comparing the voltage ranges of the scanned blocks and performing a new iteration of bipartite search and scanning of the blocks until the voltage range is assigned to each block of the memory devices 130-140.

[0050] In some implementations, voltage range assignment component 113 may perform a segmented bipartite search algorithm on a sorted list of blocks of memory devices 130-140 to perform voltage range selection for the blocks of memory devices 130-140. In one implementation, voltage range assignment component 113 may sort the blocks of the memory device by age of each block and may divide the list of sorted blocks into several segments. Voltage range assignment component 113 may then perform a bipartite search algorithm on each segment to determine a subset of blocks in the segment to be scanned for voltage range determination. Voltage range assignment component 113 may assign voltage ranges to blocks in each segment based on the scan results of the blocks in the corresponding segment. In an illustrative example, for a given segment, voltage range assignment component 113 may select a subset of three blocks for scanning, the blocks comprising a first block at the top of the list of sorted blocks in the segment, a second block in the middle of the list of sorted blocks in the segment, and a third block at the end of the list of sorted blocks in the segment. In one implementation, voltage range assignment component 113 can scan a subset of blocks within a segment and assign voltage ranges to each block within that subset based on the scan results, as explained in more detail above. In another implementation, voltage range assignment component 113 can repeat the bipartite search and scan process for voltage range selection for each segment in a group of segments comprising blocks of memory devices 130-140, such that when voltage range selection is determined for each segment in the group of segments, each block of memory devices 130-140 is assigned a voltage range.

[0051] In one embodiment, voltage range assignment component 113 may divide blocks of memory devices 130-140 into equal segments, such that each segment may have approximately the same number of blocks. In another embodiment, voltage range assignment component 113 may divide blocks of memory devices 130-140 into segments based on the post-programming time of the blocks. As an example, if a first set of blocks of the memory device has a significantly higher post-programming time than a second set of blocks (e.g., the first set was programmed three months ago), voltage range assignment component 113 may assign the first set of blocks to a separate segment. Voltage range assignment component 113 may subsequently assign the second set of blocks to additional segments based on the post-programming time of the blocks or based on satisfying a threshold number of blocks per segment.

[0052] Figure 2 This diagram illustrates an example method 200 for assigning voltage ranges to blocks of a memory device using a segmented bipartite search technique, according to one or more aspects of this disclosure. Method 200 can be executed by processing logic comprising hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions running on a processor to perform hardware emulation), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1 The voltage range is assigned to component 113 for execution.

[0053] Method 200 begins at operation 205. At operation 205, processing logic sorts the blocks of the memory device according to the age of each block to produce sorted blocks 210. In an embodiment, the age of a block may refer to the time elapsed since the block was last programmed. As an example, the age of a block may be represented by a block version field that assigns a value specific to each block of the memory device. The sorted blocks 210 may then be divided into segments 230-232, such that segment 230 may contain blocks between indices 206 and 207 of the sorted blocks 210, segment 231 may contain blocks between indices 207 and 208 of the sorted blocks 210, and segment 232 may contain blocks between indices 208 and 209 of the sorted blocks 210. Indices 206-209 may have any number of blocks between them and cannot be interpreted as indicating neighboring indices of the corresponding segments. In this case, the block at index 207 can be assigned to segment 230 as the last block in the segment, and also to segment 231 as the first block in the segment. In another embodiment, the block at index 207 can be assigned to segment 230 as the last block in the segment, and the second block at index 207+1 can be assigned to segment 231 as the first block in the segment.

[0054] At operation 215, the block at index 206 is processed to determine the voltage range to which the block to be assigned is located. In an implementation, the block can be scanned by performing multiple read operations using read level voltages associated with multiple voltage ranges and selecting the voltage range that produces the minimum RBER from among the multiple voltage ranges based on the read operations, as explained in more detail herein. After the block at index 206 of segment 230 is scanned, voltage range 211 can be determined based on the scan results and can be assigned to the block at index 206. Similarly, the block at index 207 of segment 230 is processed to determine the voltage range to which the block to be assigned is located. Voltage range 212 can be determined based on the scan results of the block at index 207, and voltage range 212 can be assigned to the block at index 207. Voltage range 211 and voltage range 212 can then be compared to determine whether voltage range 211(x) and voltage range 212(y) refer to the same voltage range.

[0055] At operation 236, the processing logic determines that voltage interval 211 matches voltage interval 212, and further determines that the block between indices 206 and 207 of segment 230 can be projected to have the same voltage interval assignment as the block at index 206, without having to scan other blocks within segment 230. The processing logic then assigns interval 211 to each block between indices 206 and 207 of the block interval assignment list 220. The processing logic can then proceed to process segment 231.

[0056] At operation 216, the processing logic scans the block at index 208 to determine the voltage range to be assigned to the block at index 208. Based on the scan results of the block at index 208 in segment 231, voltage range 213 can be determined and assigned to the block at index 208. Given that the block at index 207 already has voltage range 212 assigned at operation 215, the processing logic can continue to compare voltage range 212 with voltage range 213 to determine how to perform voltage range assignment on the block of segment 231.

[0057] At operation 237, the processing logic determines that voltage intervals 212 and 213 do not match, and further determines that the block between indices 207 and 208 of segment 231 cannot be projected to have the same voltage interval assignment as the block at index 207. The processing logic then determines that each block between indices 207 and 208 of segment 231 is scannable and that voltage interval determination can be performed based on the scan results of each block between indices 207 and 208. The processing logic then performs a scan operation on the block between indices 207 and 208, and assigns the corresponding voltage interval to each block based on the scan results of each block, as explained in more detail herein.

[0058] At operation 217, the processing logic processes segment 232 by scanning the block at index 209 to determine the voltage range to be assigned to the block at index 209. Based on the scan results of the block at index 209 of segment 232, voltage range 214 can be determined and assigned to the block at index 209. Given that the block at index 208 already has voltage range 213 assigned at operation 216, the processing logic can continue to compare voltage range 213 with voltage range 214 to determine how to perform voltage range assignment on the block of segment 232.

[0059] At operation 238, the processing logic determines that voltage interval 213 matches voltage interval 214, and further determines that the block between indices 208 and 209 of segment 232 can be projected to have the same voltage interval assignment as the block at index 208, without having to scan other blocks within segment 232, since the blocks in segment 232 are sorted by block age. The processing logic then assigns interval 213 to each block between indices 208 and 209 of block interval assignment list 220. In some embodiments, the processing logic may repeat the operation of method 200 based on a predetermined schedule to adjust and / or update the interval determination of the memory device blocks as the age of each block changes over time.

[0060] Figure 3 This diagram illustrates an example method 300 for assigning voltage ranges to blocks of a memory device using a bipartite search technique according to one or more aspects of this disclosure. Method 300 can be executed by processing logic comprising hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions running on a processor to perform hardware emulation), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The voltage range is assigned to component 113 for execution.

[0061] Method 300 begins at operation 305. At operation 305, processing logic sorts the blocks of the memory device by the age of each block to produce sorted blocks 310. In an embodiment, the age of a block may refer to the time elapsed since the block was last programmed and may be represented by a block version field that assigns a value specific to each block of the memory device. In an illustrative example, a block with version number 5000 was programmed before another block with version number 5001, and so on. The processing logic may perform iteration 1 to scan the blocks at the top of the sorted list 310 (i.e., the block at index 306), the blocks in the middle of the sorted list 310 (i.e., the block at index 307), and the blocks at the bottom of the sorted list 310 (i.e., the block at index 309). In an embodiment, the processing logic scans the blocks at indices 306, 307, and 309 to assign voltage ranges to the blocks at indices 306, 307, and 309 and to determine how to assign voltage ranges to the remaining blocks in the sorted list 310.

[0062] At operation 315, the block at index 306 is processed to determine the voltage range to which the block to be assigned is located. In an implementation, the block can be scanned by performing multiple read operations using read level voltages associated with multiple voltage ranges and selecting the voltage range that produces the minimum RBER from among the multiple voltage ranges based on the read operations, as explained in more detail herein. After scanning the block at index 306, voltage range 311 can be determined based on the scan results and can be assigned to the block at index 306. Similarly, the block at index 307 is processed to determine the voltage range to which the block to be assigned is located. Voltage range 312 can be determined based on the scan results of the block at index 307, and voltage range 312 can be assigned to the block at index 307. Voltage range 311 and voltage range 312 can then be compared to determine whether voltage range 311(x) and voltage range 312(y) refer to the same voltage range.

[0063] At operation 322, the processing logic determines that voltage interval 311 matches voltage interval 312, and further determines that the block between index 306 and index 307 can be projected to have the same voltage interval assignment as the block at index 306, without having to scan every block between index 306 and index 307. The processing logic then assigns interval 311 to every block between index 306 and index 307 in the block interval assignment list 320. The processing logic can then continue to scan the block at index 309.

[0064] At operation 316, the processing logic scans the block at index 309 to determine the voltage range to be assigned to the block at index 309. Based on the scan results of the block at index 309, voltage range 313 can be determined and assigned to the block at index 309. Given that the block at index 307 already has the voltage range 312 assigned at operation 315, the processing logic can continue to compare voltage range 312 with voltage range 313 to determine how to perform voltage range assignment for the block between indices 307 and 309.

[0065] At operation 324, the processing logic determines that voltage intervals 312 and 313 do not match, and further determines that the block between indices 307 and 308 cannot be projected to have the same voltage interval assignment as the block at index 307. The processing logic then proceeds to iteration 2 to perform a new bipartite search on the block between the block at index 307 and the block at index 309. To perform the bipartite search, the processing logic determines the block at index 308, which represents the intermediate position between the block at index 307 and the block at index 309, and performs a scan operation on the block at index 308. Based on the scan result of the block at index 309, the processing logic determines that voltage interval 314 is suitable for the block at index 309 and assigns voltage interval 314 to the block at index 209.

[0066] At operation 326, the processing logic compares voltage interval 312 with voltage interval 314 to determine whether voltage interval 312(x) and voltage interval 314(y) refer to the same voltage interval. The processing logic then determines that voltage interval 312 matches voltage interval 314, and further determines that the block between index 307 and index 308 can be projected to have the same voltage interval assignment as the block at index 307, without having to scan every block between index 307 and index 308. At operation 332, the processing logic assigns interval 312 to every block between index 307 and index 308 in the block interval assignment list 320.

[0067] At operation 328, the processing logic compares voltage interval 314 with voltage interval 313 to determine how to perform voltage interval assignment on the blocks between indices 308 and 309 of the sorted block list 310. At operation 334, the processing logic determines that voltage interval 314 and voltage interval 313 do not match, and further determines that the blocks between indices 308 and 309 cannot be projected to have the same voltage interval assignment as the block at index 308. The processing logic then proceeds to iteration 3 to perform a new bipartite search on the blocks between the blocks at index 308 and index 309, as explained in more detail above at operation 324.

[0068] Figure 4This is a flowchart illustrating an example method of assigning voltage ranges to blocks of a memory device using a segmented bipartite search according to some embodiments of this disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The voltage range is assigned to component 113 for execution. Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. In addition, in some embodiments, one or more operations may be omitted. Therefore, not all illustrated operations are required in every embodiment, and other process flows are possible.

[0069] At operation 410, the processing logic sorts the set of blocks of the memory device based on the age of each block. In an implementation, the age of a block may be represented by the block version field of the block, which is updated whenever a block is programmed, as explained in more detail above.

[0070] At operation 420, the processing logic divides the sorted block set into block segments. In one embodiment, blocks of the memory device can be divided into block segments equally. In another embodiment, blocks of the memory device can be divided into block segments based on the age of the blocks, as explained in more detail herein.

[0071] At operation 430, the first block at the first boundary of the first block segment in the processing logic scans the first block segment and the second block at the second boundary of the first block segment. In one embodiment, the block at the first boundary may be the youngest block among the blocks in the block segment, and the block at the second boundary may be the oldest block among the blocks in the block segment.

[0072] At operation 440, the processing logic identifies a first voltage range associated with the first block based on the scan results of the first block, and identifies a second voltage range associated with the second block based on the second scan results of the second block. In an embodiment, the first voltage range and the second voltage range contain read-level voltages that can be used to perform read operations on data stored in the corresponding blocks, as explained in more detail above herein.

[0073] At operation 450, the processing logic determines whether a first voltage range of the first block matches a second voltage range of the second block. When the processing logic determines that the first voltage range matches the second voltage range (e.g., the first and second voltage ranges refer to the same range), the processing logic determines that the remaining unscanned blocks in the block segment can be projected to have ranges identical to any boundary of the segment. The processing logic then continues to assign the first voltage range to each block within the first block segment.

[0074] Figure 5 This is a flowchart illustrating an example method for assigning voltage ranges to blocks of a memory device by dividing blocks into segments based on block-based post-programming time, according to some embodiments of this disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The voltage range is assigned to component 113 for execution. Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. In addition, in some embodiments, one or more operations may be omitted. Therefore, not all illustrated operations are required in every embodiment, and other process flows are possible.

[0075] At operation 510, the processing logic sorts the set of blocks of the memory device based on the age of each block. At operation 520, the processing logic assigns a subset 1 of the sorted blocks to segment 1 based on the post-programming time value of each block. In an embodiment, the processing logic may determine that subset 1 of the blocks represents a high percentage (e.g., 60%) of the blocks of the memory device with a post-programming time of three months or more. The processing logic may further determine that the remaining blocks of the memory device represented by subset 2 have a post-programming time of several hours (e.g., the blocks have been programmed within the past 10 hours). The processing logic may then determine that subset 1 of the sorted blocks is assigned to a separate segment different from subset 2 of the sorted blocks.

[0076] Therefore, at operation 520, based on the relative age of each block in subset 1, the processing logic assigns subset 1 of sorted blocks to segment 1, and at operation 530, the processing logic assigns subset 2 of sorted blocks to one or more segments. Since the blocks in subset 2 have significantly younger ages compared to the blocks in subset 1, the processing logic can equally split the blocks in subset 2 between segment 2 and segment 3.

[0077] At operation 540, the processing logic scans the blocks at the boundaries of each of segments 1, 2, and 3, and determines the associated voltage range for each scanned block, as explained in more detail above. At operation 550, the processing logic begins a loop to determine whether the voltage ranges assigned to the blocks at the boundaries of each segment match each other. If the voltage ranges assigned to the blocks at the boundaries of segment 1 match, the processing logic continues to operation 590. At operation 590, the processing logic assigns the voltage range of the block at the first boundary of segment 1 to each block within segment 1. The processing logic can then continue to operation 540 to process the next segment.

[0078] On the other hand, if the processing logic determines that the voltage ranges of the blocks assigned to the boundary of segment 1 do not match, the processing logic may proceed to operation 570. At operation 570, the processing logic scans each block within the segment to determine the corresponding voltage range for each block. In other embodiments, the processing logic may perform a new bipartite search on a subset of the blocks in segment 1 and determine the corresponding voltage range based on the bipartite search. At operation 580, the processing logic assigns the determined voltage ranges to blocks in segment 1 based on the scan results, as explained in more detail above. The processing logic may then proceed to operation 540 to process the next segment.

[0079] Figure 6 This is a flowchart illustrating an example method, according to some embodiments of the present disclosure, for assigning voltage ranges to blocks of a memory device by dividing blocks into segments based on the number of blocks at each segment. Method 600 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, specialized logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 600 is performed by… Figure 1 The voltage range is assigned to component 113 for execution. Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. In addition, in some embodiments, one or more operations may be omitted. Therefore, not all illustrated operations are required in every embodiment, and other process flows are possible.

[0080] At operation 610, the processing logic sorts the set of blocks of the memory device based on the age of each block. At operation 620, the processing logic assigns a percentage of the total number of sorted blocks to each segment in the segment set, such that each subset may have approximately the same number of blocks. As an example, the processing logic may assign 25% of the blocks to each segment in the set of four segments. The processing logic may then determine the blocks at each boundary of each segment for scan and voltage range determination, as explained in more detail above.

[0081] At operation 630, the processing logic scans the blocks at the boundaries of each segment in the segment set and determines the associated voltage range for each scanned block, as explained in more detail above. At operation 650, the processing logic begins a loop to determine whether the voltage ranges assigned to the blocks at the boundaries of each segment match each other. If the voltage ranges assigned to the blocks at the boundaries of a given segment match, the processing logic continues to operation 690. At operation 690, the processing logic assigns the voltage range of the block at the first boundary of the segment to each block within the segment. The processing logic can then continue to operation 630 to process the next segment.

[0082] On the other hand, if the processing logic determines that the voltage ranges of the blocks assigned to the boundaries of a given segment do not match, the processing logic may proceed to operation 670. At operation 670, the processing logic performs a bipartite search to select a subset of blocks to be scanned, as explained in more detail herein. The processing logic further scans the selected subset of blocks within the given segment. At operation 680, the processing logic determines the voltage range for each block within the segment based on the scan results of the selected subset of blocks, as explained in more detail herein. Figure 2 For a more detailed explanation, the processing logic can then proceed to operation 630 to process the next segment.

[0083] Figure 7 This describes an example machine of computer system 700, within which an instruction set for causing the machine to perform any or more of the methods discussed herein can be executed. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to execute commands corresponding to...). Figure 1(Operation of voltage range assignment component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, with the capabilities of a server or client machine in a client-server network environment.

[0084] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any or more of the methods discussed herein.

[0085] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0086] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 communicating via network 720.

[0087] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which one or more instruction sets 726 or software embodying any or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, the main memory 704 and processing device 702 also constituting the machine-readable storage medium. The machine-readable storage medium 724, the data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0088] In one embodiment, instruction 726 includes instructions for implementing the corresponding Figure 1 The voltage range is assigned to the functional instructions of component 113. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0089] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented as a way for those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm here and generally is considered a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0090] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system, or other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0091] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0092] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices for performing the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0093] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0094] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: Memory devices; as well as A processing device, operatively coupled to the memory device, to perform operations including: Sort the multiple blocks of the memory device; The sorted blocks are divided into multiple block segments; A first voltage range associated with the first block is identified by scanning the first block at the first boundary of the first block segment among the plurality of block segments, wherein the first voltage range is a first set of read level threshold voltages for performing a read operation at the first block; A second voltage range associated with the second block is identified by scanning the second block at the second boundary of the first block segment, wherein the second voltage range is a second set of read level threshold voltages for performing a read operation at the second block; as well as In response to determining that the first voltage range matches the second voltage range, the first voltage range is assigned to each block in the first block segment.

2. The system of claim 1, wherein the sorting of the plurality of blocks is performed based on the age of each of the plurality of blocks.

3. The system of claim 1, wherein each of the plurality of block segments comprises a corresponding subset of the blocks of the plurality of blocks of the memory device.

4. The system of claim 1, wherein each of the plurality of block segments comprises a corresponding subset of blocks in the plurality of blocks, wherein the corresponding subset of blocks is determined based on the age of each block in the corresponding subset of blocks.

5. The system of claim 1, wherein the processing device further performs operations including the following: In response to determining that the first voltage range and the second voltage range do not match: Scan each block in the subset of the plurality of blocks assigned to the first block segment; and The corresponding interval associated with the corresponding block is identified based on the corresponding scan results of the corresponding block.

6. The system of claim 1, wherein the processing device further performs operations including: In response to determining that the first voltage range and the second voltage range do not match: Scan the third block at the predetermined location within the first block segment; A third voltage range associated with the third block is identified based on the third scan result of the third block, wherein the third voltage range is a third set of read level threshold voltages for performing a read operation at the third block; and In response to determining that the first voltage range matches the third voltage range, the first voltage range is assigned to each block in a second subset of the sorted plurality of blocks, wherein the second subset of the blocks is located between the first boundary of the first block segment and the predetermined position within the first block segment.

7. The system of claim 1, wherein the processing device further performs operations including: For each of the plurality of block segments: A third voltage interval associated with the third block is identified by scanning the third block at the corresponding first boundary of the respective block segment in the plurality of block segments, wherein the third voltage interval is a third set of read level threshold voltages for performing a read operation at the third block; A fourth voltage interval associated with the fourth block is identified by scanning the fourth block at the corresponding second boundary of the respective block segments among the plurality of block segments, wherein the fourth voltage interval is a fourth set of read level threshold voltages for performing a read operation at the fourth block; and In response to determining that the third voltage range matches the fourth voltage range, the third voltage range is assigned to each block in the corresponding block segment.

8. A method comprising: The processing device sorts multiple blocks of the memory device; A first voltage range associated with the first block is identified by scanning the first block at the first boundary of the plurality of sorted blocks, wherein the first voltage range is a first set of read level threshold voltages for performing a read operation at the first block; A second voltage range associated with the second block is identified by scanning a second block at a predetermined position of the plurality of sorted blocks, wherein the second voltage range is a second set of read level threshold voltages for performing a read operation at the second block; as well as In response to determining that the first voltage range matches the second voltage range, the first voltage range is assigned to each block located between the first boundary of the plurality of sorted blocks and the predetermined position of the plurality of sorted blocks.

9. The method of claim 8, further comprising: A third voltage range associated with the third block is identified by scanning the third block at the second boundary of the plurality of sorted blocks, wherein the third voltage range is a third set of read level threshold voltages for performing a read operation at the third block; as well as In response to determining that the second voltage range matches the third voltage range, the second voltage range is assigned to each block located between the predetermined position of the plurality of sorted blocks and the second boundary of the plurality of sorted blocks.

10. The method of claim 8, wherein the sorting of the plurality of blocks is performed based on the age of each of the plurality of blocks.

11. The method of claim 8, further comprising: In response to determining that the first voltage range and the second voltage range do not match: Scan each block located between the first boundary of the plurality of sorted blocks and the predetermined position of the plurality of sorted blocks; and The corresponding interval associated with the corresponding block is identified based on the corresponding scan results of the corresponding block.

12. The method of claim 8, further comprising: In response to determining that the first voltage range and the second voltage range do not match: Scan the third block located between the first boundary of the plurality of sorted blocks and the predetermined position of the plurality of sorted blocks; Based on the scan results of the third block, a third voltage range associated with the third block is identified, wherein the third voltage range is a third set of read level threshold voltages for performing a read operation at the third block; as well as In response to determining that the first voltage range matches the third voltage range, the first voltage range is assigned to each block in a second subset of the sorted plurality of blocks, wherein the second subset of blocks is located between the first boundary of the plurality of sorted blocks and the intermediate position between the first boundary of the plurality of sorted blocks and the predetermined position.

13. The method of claim 8, wherein scanning the first block further comprises performing a read operation on data stored in the first block using a read level offset of the first voltage range, and generating a first scan result based on a reliability metric associated with the read operation.

14. A non-transitory computer-readable storage medium including instructions that, when executed by a processing means, cause the processing means to perform operations including: Sort multiple blocks of the memory device; The sorted blocks are divided into multiple block segments; A first voltage range associated with the first block is identified by scanning the first block at the first boundary of the first block segment among the plurality of block segments, wherein the first voltage range is a first set of read level threshold voltages for performing a read operation at the first block; A second voltage range associated with the second block is identified by scanning a second block at the second boundary of the first block segment, wherein the second voltage range is a second set of read level threshold voltages for performing a read operation at the second block; and In response to determining that the first voltage range matches the second voltage range, the first voltage range is assigned to each block in the first block segment.

15. The non-transitory computer-readable storage medium of claim 14, wherein the sorting of the plurality of blocks is performed based on the age of each of the plurality of blocks.

16. The non-transitory computer-readable storage medium of claim 14, wherein each of the plurality of block segments comprises a corresponding subset of the blocks of the plurality of blocks of the memory device.

17. The non-transitory computer-readable storage medium of claim 14, wherein each of the plurality of block segments comprises a corresponding subset of blocks in the plurality of blocks, wherein the corresponding subset of blocks is determined based on the age of each block in the corresponding subset of blocks.

18. The non-transitory computer-readable storage medium of claim 14, wherein the processing means further performs operations including: In response to determining that the first voltage range and the second voltage range do not match: Scan each block in the subset of the plurality of blocks assigned to the first block segment; and The corresponding interval associated with the corresponding block is identified based on the corresponding scan results of the corresponding block.

19. The non-transitory computer-readable storage medium of claim 14, wherein the processing means further performs operations including: In response to determining that the first voltage range and the second voltage range do not match: A third voltage range associated with the third block is identified by scanning a third block at a predetermined location within the first block segment, wherein the third voltage range is a third set of read level threshold voltages for performing a read operation at the third block; and In response to determining that the first voltage range matches the third voltage range, the first voltage range is assigned to each block in a second subset of the sorted plurality of blocks, wherein the second subset of the blocks is located between the first boundary of the first block segment and the predetermined position within the first block segment.

20. The non-transitory computer-readable storage medium of claim 14, wherein the processing means further performs operations including: For each of the plurality of block segments: A third voltage interval associated with the third block is identified by scanning the third block at the corresponding first boundary of the respective block segment in the plurality of block segments, wherein the third voltage interval is a third set of read level threshold voltages for performing a read operation at the third block; A fourth voltage interval associated with the fourth block is identified by scanning the fourth block at the corresponding second boundary of the corresponding block segment, wherein the fourth voltage interval is a fourth set of read level threshold voltages for performing a read operation at the fourth block; and In response to determining that the third voltage range matches the fourth voltage range, the third voltage range is assigned to each block in the corresponding block segment.

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