A high electron mobility transistor and a method for manufacturing the same
By directing the drain to the back of the wafer in AlGaN/GaN HEMT devices, the restriction problem of electrodes on the surface side is solved, achieving a wider and flexible application.
Patent Information
- Application Number
- CN202210564925.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-05-23
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2042-05-23
Smart Images
Figure CN115148809B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor device preparation, and particularly relates to a high electron mobility transistor (AlGaN / GaN HEMT) and a preparation method thereof. Background Art
[0002] AlGaN / GaN HEMT (high electron mobility transistor) mostly uses heteroepitaxial GaN thin films obtained by metal organic chemical vapor deposition (MOCVD) or hydride vapor phase epitaxy (HVPE). Heteroepitaxy most commonly selects materials such as Si, sapphire, and SiC as substrate materials, and grows GaN on them.
[0003] For example, see Figure 1 , on the substrate material, using the MOCVD method, a GaN buffer layer, an AlGaN barrier layer, and a GaN cap layer are sequentially grown. After the heterojunction material growth is completed, a series of key process steps such as source and drain ohmic contacts, device isolation, surface passivation, gate trench etching, gate metal evaporation, protective passivation, interconnect opening, and interconnect metal evaporation are sequentially carried out to complete the preparation of the HEMT device.
[0004] In the typical AlGaN / GaN HEMT device structure prepared in this way, the three electrodes (source, gate, and drain) are all on one side of the surface of the device. When this HEMT device is connected to other circuits or devices, this structure with the three electrodes all on one side of the surface of the device will limit its application in some fields or is not very convenient to use. Summary of the Invention
[0005] One of the technical problems to be solved by the present invention is to provide a high electron mobility transistor in which the source and drain of the three electrodes (source, gate, and drain) are respectively on both sides of the device, aiming at the above-mentioned deficiencies of the existing AlGaN / GaN HEMT device structure where the three electrodes (source, gate, and drain) are all on one side of the surface of the device.
[0006] Another technical problem to be solved by the present invention is to provide a preparation method for the above-mentioned high electron mobility transistor.
[0007] The AlGaN / GaN high electron mobility transistor as the first aspect of the present invention includes a wafer, and is characterized in that the wafer is prepared by sequentially growing an N+-type GaN layer, a GaN buffer layer, an AlGaN barrier layer, and a GaN cap layer on a substrate material by using the MOCVD method, and the drain (or source) of the transistor is led out from the back surface of the wafer, and the gate and the source (or drain) are led out from the front surface of the wafer.
[0008] In a preferred embodiment of the present invention, the drain (or source) of the transistor is led out through the back N+-type GaN layer after the substrate is peeled off.
[0009] In a preferred embodiment of the present invention, the substrate is selected as sapphire.
[0010] As a method for manufacturing a high electron mobility transistor according to the first aspect of the present invention, it includes the following steps:
[0011] 1) Material preparation. On the substrate, first epitaxially grow an N+-type GaN layer, and then sequentially epitaxially grow a GaN buffer layer, an AlGaN barrier layer, and a GaN cap layer;
[0012] 2) On the surface of the GaN cap layer of the wafer, first determine the source and drain of the device. The source contact hole and the drain contact hole sequentially penetrate the GaN cap layer and the AlGaN barrier layer until the GaN buffer layer; deposit a metal layer on the surface of the wafer by sputtering or evaporation; after photolithographic stripping, form the source pattern and the drain pattern of the device; anneal to form a good ohmic contact;
[0013] 3) Etch to fabricate the device isolation region, and the depth of the isolation groove needs to reach the N+-type GaN layer;
[0014] 4) Deposit the first passivation layer. Specifically, passivate the GaN cap layer, the source, the drain, the bottom and side walls of the isolation groove to form the first passivation layer;
[0015] 5) Determine the gate region and perform gate trench etching. Specifically, determine the gate region on the first passivation layer between the source and the drain and perform gate trench etching;
[0016] 6) Sputter or evaporate to prepare the gate metal. Specifically, sputter or evaporate the gate metal on the surface of the wafer, and pattern the gate metal at the gate trench as the gate electrode, and the gate metal protrudes from the first passivation layer between the source and the drain;
[0017] 7) Deposit the second passivation layer. Specifically: deposit the second passivation layer on the surface of the first passivation layer and the surface of the gate metal;
[0018] 8) Interconnection opening, and at the same time open the drain (or source) contact hole in the isolation groove. Specifically: open holes on the top of the source metal, the top of the drain metal, and the top of the gate metal, and at the same time open the drain (or source) contact hole at the bottom of the isolation groove on the side close to the drain (or source); etch away the first passivation layer and the second passivation layer on the source metal layer and the drain metal layer, etch away the second passivation layer on the gate metal layer, and etch away the first passivation layer and the second passivation layer at the drain (or source) contact hole at the bottom of the isolation groove;
[0019] 9) Interconnect metal is prepared, and the drain (or source) of the device is led to the drain (or source) contact hole in the isolation trench. Specifically: deposit a metal thin film on the wafer surface, etch the source, gate, and drain, and at the same time connect the drain (or source) to the drain (or source) contact hole at the bottom of the isolation trench, which is connected to the N+-type GaN layer.
[0020] 10) Source (or drain) bumps and gate bumps are fabricated on the source (or drain) metal layer and the gate metal layer;
[0021] 11) The front side of the wafer is encapsulated, and the formed encapsulation layer covers the entire surface of the wafer, including the source (or drain) bumps and the gate bumps; then grind the encapsulation layer on the front side of the wafer to expose the source (or drain) bumps and the gate bumps;
[0022] 12) The back side of the wafer is peeled off to separate the substrate from the back side of the wafer, exposing the N+-type GaN layer, thereby exposing the drain (or source) of the device.
[0023] In a preferred embodiment of the present invention, the etching depth of the isolation trench needs to reach the N+-type GaN layer.
[0024] In a preferred embodiment of the present invention, the encapsulation layer is epoxy resin.
[0025] In a preferred embodiment of the present invention, in step 12), the back side of the wafer is peeled off to separate the substrate from the back side of the wafer, and the laser lift-off method is adopted.
[0026] The laser lift-off method adopted in the present invention is a very mature processing technology. The basic principle of laser lift-off is to utilize the different absorption efficiencies of the epitaxial layer material and the sapphire material for ultraviolet laser. For example, sapphire has a relatively high bandgap energy (9.9 eV), so sapphire is transparent to the 248 nm krypton fluoride (KrF) excimer laser (5 eV radiation energy), while gallium nitride (with a bandgap energy of about 3.3 eV) strongly absorbs the energy of the 248 nm laser. The laser passes through the sapphire and reaches the gallium nitride layer, and laser lift-off is performed at the contact surface between the gallium nitride and the sapphire. This will generate a local explosion shock wave, causing the gallium nitride and the sapphire to separate at that location. Based on the same principle, the 193 nm argon fluoride (ArF) excimer laser can be used to separate aluminum nitride (AlN) and sapphire. Aluminum nitride with a bandgap energy of 6.3 eV can absorb the 6.4 eV ArF laser radiation, while sapphire with a bandgap energy of 9.9 eV is transparent to the ArF excimer laser.
[0027] Due to the adoption of the above technical solution, the drain (or source) of the AlGaN / GaN HEMT device of the present invention is led to the back side of the wafer, expanding the application scope of the AlGaN / GaN HEMT device and making the application simpler and more flexible. Description of the Drawings
[0028] Figure 1 It is a schematic structural diagram of an existing AlGaN / GaN HEMT device.
[0029] Figures 2a to 2m It is a schematic flowchart of the preparation method of the electron mobility transistor according to Embodiment 1 of the present invention.
[0030] Figures 3a to 3m It is a schematic flowchart of the preparation method of the electron mobility transistor according to Embodiment 2 of the present invention. Detailed Embodiments
[0031] The present invention will be further described below in conjunction with the drawings and specific embodiments.
[0032] Embodiment 1
[0033] The preparation method of the high electron mobility transistor (AlGaN / GaN HEMT) in this embodiment includes the following steps:
[0034] 1) Material preparation. First, an N+-type GaN layer 2 is epitaxially grown on a sapphire substrate 1, and then a GaN buffer layer 3, an AlGaN barrier layer 4, and a GaN cap layer 5 are sequentially epitaxially grown.
[0035] 2) On the surface of the GaN cap layer 5 of the wafer, first determine the source 6 and drain 7 of the device. The source contact hole and the drain contact hole sequentially penetrate the GaN cap layer 5 and the AlGaN barrier layer 4 until the GaN buffer layer 3; a metal layer is deposited on the wafer surface by sputtering or evaporation; after photolithography and lift-off, the source pattern and the drain pattern of the device are formed; annealing is performed to form a good ohmic contact.
[0036] 3) Etch to fabricate the device isolation region, and the depths of the isolation grooves 8 and 9 need to reach the N+-type GaN layer 2.
[0037] 4) Deposit the first passivation layer 10. Specifically, the GaN cap layer 5, the source 6, the drain 7, the bottoms and side walls of the isolation grooves 8 and 9 are passivated to form the first passivation layer 10.
[0038] 5) Determine the gate region and perform gate trench etching. Specifically, the gate region is determined and the gate trench 11 is etched on the first passivation layer 10 between the source 6 and the drain 7.
[0039] 6) Prepare the gate metal 12 by sputtering or evaporation. Specifically, sputter or evaporate the gate metal on the surface of the wafer, and pattern the gate metal at the gate trench 11 as the gate electrode 12, and the gate metal protrudes from the first passivation layer 10 between the source electrode 6 and the drain electrode 7;
[0040] 7) Deposit the second passivation layer 13. Specifically: deposit the second passivation layer 13 on the surface of the first passivation layer 10 and the surface of the gate metal 12;
[0041] 8) Open the interconnection holes, and also open the drain contact hole 8a in the isolation trench 8. Specifically: open holes 6a, 7a, 12a on the top of the source metal 6, the top of the drain metal 7, and the top of the gate metal 12, and at the same time open the drain contact hole 8a at the bottom of the isolation trench on the side close to the drain 7; etch away the first passivation layer 10 and the second passivation layer 13 on the source metal layer 6 and the drain metal layer 7, etch away the second passivation layer 13 on the gate metal layer 12, and etch away the first passivation layer 10 and the second passivation layer 13 at the drain contact hole 8a at the bottom of the isolation trench;
[0042] 9) Prepare the interconnection metal and lead the drain 7 of the device to the drain contact hole 8a in the isolation trench. Specifically: deposit a metal thin film 14 on the surface of the wafer, etch out the source electrode 6b, the gate electrode 12b, and the drain electrode 7b, and at the same time connect the drain 7 and 7b to the drain contact 8b at the bottom of the isolation trench, which is connected to the N+-type GaN layer 2.
[0043] 10) Fabricate source bumps 6c and gate bumps 12c on the source metallization layer 6b and the gate metallization layer 12b;
[0044] 11) Encapsulate the front side of the wafer, and the formed encapsulation layer 15 covers the entire surface of the wafer, including the source bumps 6c and the gate bumps 12c; then grind the encapsulation layer 15 on the front side of the wafer to expose the source bumps 6c and the gate bumps 12c;
[0045] 12) Perform laser lift-off on the back side of the wafer to peel off the sapphire substrate 1 from the back side of the wafer, exposing the N+-type GaN layer 2, and this N+-type GaN layer is connected to the drain 7 / 7b / 8b, thereby forming the high electron mobility transistor (AlGaN / GaN HEMT) of this embodiment. The drain 7 / 7b / 8b of the high electron mobility transistor (AlGaN / GaN HEMT) of this embodiment is led out from the back side of the wafer, and the source 6 / 6b / 6c and the gate 12 / 12b / 12c are led out from the front side of the wafer.
[0046] Embodiment 2
[0047] The preparation method of the high electron mobility transistor (AlGaN / GaN HEMT) of this embodiment includes the following steps:
[0048] 1) Material preparation. First, an N+-type GaN layer 2 is epitaxially grown on a sapphire substrate 1, and then a GaN buffer layer 3, an AlGaN barrier layer 4, and a GaN cap layer 5 are sequentially epitaxially grown.
[0049] 2) On the surface of the GaN cap layer 5 of the wafer, the source electrode 6 and the drain electrode 7 of the device are first determined. The source contact hole and the drain contact hole sequentially penetrate the GaN cap layer 5 and the AlGaN barrier layer 4 until reaching the GaN buffer layer 3; a metal layer is deposited on the wafer surface by sputtering or evaporation; after lift-off lithography, the source pattern and the drain pattern of the device are formed; annealing is performed to form a good ohmic contact.
[0050] 3) Etch to fabricate the device isolation region. The depths of the isolation grooves 8 and 9 need to reach the N+-type GaN layer 2.
[0051] 4) Deposition of the first passivation layer 10. Specifically, the GaN cap layer 5, the source electrode 6, the drain electrode 7, the bottoms and sidewalls of the isolation grooves 8 and 9 are passivated to form the first passivation layer 10.
[0052] 5) Determine the gate region and perform gate trench etching. Specifically, the gate region is determined on the first passivation layer 10 between the source electrode 6 and the drain electrode 7, and gate trench 11 etching is performed.
[0053] 6) Prepare the gate metal 12 by sputtering or evaporation. Specifically, the gate metal is sputtered or evaporated on the wafer surface, and the gate metal is patterned at the gate trench 11 as the gate electrode 12, and the gate metal protrudes from the first passivation layer 10 between the source electrode 6 and the drain electrode 7.
[0054] 7) Deposition of the second passivation layer 13. Specifically, the second passivation layer 13 is deposited on the surface of the first passivation layer 10 and the surface of the gate metal 12.
[0055] 8) Interconnection via opening, and at the same time, open the source contact hole 9a in the isolation groove 8. Specifically, openings 6a, 7a, and 12a are opened on the tops of the source metal 6, the drain metal 7, and the gate metal 12, and at the same time, a source contact hole 9a is opened at the bottom of the isolation groove near the source electrode 6; the first passivation layer 10 and the second passivation layer 13 on the source metal layer 6 and the drain metal layer 7 are etched away, the second passivation layer 13 on the gate metal layer 12 is etched away, and the first passivation layer 10 and the second passivation layer 13 of the source contact hole 9a at the bottom of the isolation groove are etched away.
[0056] 9) Prepare the interconnection metal and lead the source electrode 6 of the device to the source contact hole 9a in the isolation groove. Specifically, a metal thin film 16 is deposited on the wafer surface, and the source electrode 6b, the gate electrode 12b, and the drain electrode 7b are etched out. At the same time, the source electrode 6 and 6b are connected to the source contact 9b at the bottom of the isolation groove and connected to the N+-type GaN layer 2.
[0057] 10) Form drain bumps 7c and gate bumps 12c on the drain metallization layer 7b and the gate metallization layer 12b;
[0058] 11) Encapsulate the front side of the wafer, and the formed encapsulation layer 15 covers the entire surface of the wafer, including the drain bumps 7c and the gate bumps 12c; then grind the encapsulation layer 15 on the front side of the wafer to expose the drain bumps 7c and the gate bumps 12c;
[0059] 12) Perform laser lift-off on the back side of the wafer to peel off the sapphire substrate 1 from the back side of the wafer, exposing the N+-type GaN layer 2, and this N+-type GaN layer is connected to the source 6 / 6b / 9b, thereby forming the high electron mobility transistor (AlGaN / GaN HEMT) of this embodiment. The source 6 / 6b / 9b of the high electron mobility transistor (AlGaN / GaN HEMT) of this embodiment is led out from the back side of the wafer, and the drain 7 / 7b / 7c and the gate 12 / 12b / 12c are led out from the front side of the wafer.
Claims
1. A method for fabricating a high electron mobility transistor, characterized in that, It includes the following steps: 1) Material preparation: On a substrate, first epitaxially grow an N+-type GaN layer, and then sequentially epitaxially grow a GaN buffer layer, an AlGaN barrier layer, and a GaN cap layer; 2) On the surface of the GaN cap layer of the wafer, first determine the source and drain of the device. The source contact hole and the drain contact hole sequentially penetrate the GaN cap layer and the AlGaN barrier layer until reaching the GaN buffer layer; deposit a metal layer on the wafer surface by sputtering or evaporation; after lift-off lithography, form the source pattern and the drain pattern of the device; anneal to form a good ohmic contact; 3) Etch to fabricate the device isolation region, and the depth of the isolation groove needs to reach the N+-type GaN layer; 4) Deposit the first passivation layer, specifically passivate the GaN cap layer, the source, the drain, the bottom and side walls of the isolation groove to form the first passivation layer; 5) Determine the gate region and perform gate trench etching, specifically determine the gate region on the first passivation layer between the source and the drain and perform gate trench etching; 6) Prepare the gate metal by sputtering or evaporation, specifically sputter or evaporate the gate metal on the wafer surface, pattern the gate metal at the gate trench as the gate electrode, and the gate metal protrudes from the first passivation layer between the source and the drain; 7) Deposit the second passivation layer, specifically deposit the second passivation layer on the surface of the first passivation layer and the surface of the gate metal; 8) Interconnection opening, and also open the drain contact hole or the source contact hole in the isolation groove. Specifically, open holes on the top of the source metal, the top of the drain metal, and the top of the gate metal, and at the same time open the drain contact hole or the source contact hole at the bottom of the isolation groove on the side close to the drain or the source; Etch away the first passivation layer and the second passivation layer on the source metal layer and the drain metal layer, etch away the second passivation layer on the gate metal layer, and etch away the first passivation layer and the second passivation layer of the drain contact hole or the source contact hole at the bottom of the isolation groove; 9) Prepare the interconnection metal and lead the drain or the source of the device to the drain contact hole or the source contact hole in the isolation groove. Specifically, deposit a metal thin film on the wafer surface, etch out the source, the gate, and the drain, and at the same time connect the drain or the source to the drain contact hole or the source contact hole at the bottom of the isolation groove, and connect to the N+-type GaN layer; 10) Fabricate source bumps or drain bumps and gate bumps on the source or drain metal layer and the gate metal layer; 11) Encapsulate the front side of the wafer, and the formed encapsulation layer covers the entire surface of the wafer, including the source bumps or drain bumps and the gate bumps; then grind the encapsulation layer on the front side of the wafer to expose the source bumps or drain bumps and the gate bumps; 12) Peel the back side of the wafer to separate the substrate from the back side of the wafer, exposing the N+-type GaN layer, thereby exposing the drain or the source of the device.
2. The preparation method of the high electron mobility transistor according to claim 1, wherein, The encapsulation layer is an epoxy resin.
3. The manufacturing method of the high electron mobility transistor as described in claim 1, characterized in that, In step 12), peeling the back side of the wafer to separate the substrate from the back side of the wafer is carried out by a laser lift-off method.