Interrupt control method, interrupt controller, electronic device, medium and chip

Abstract

The present disclosure provides an interrupt control method, an interrupt controller, an electronic device, a medium and a chip, relates to the technical field of computers, and in particular to interrupt control. The implementation scheme is as follows: storing at least one interrupt signal from at least one interrupt source; determining an interrupt number corresponding to each of the at least one interrupt signal based on a mapping relationship between each of the at least one interrupt source and the interrupt number; determining a target interrupt number to be sent based on the at least one interrupt signal and the interrupt number corresponding to each of the interrupt signals; determining interrupt information corresponding to the target interrupt number based on the target interrupt number, wherein the interrupt information comprises information data to be written and a target address of the information data to be written; and writing corresponding information data to the target address of a slave interface of a peripheral component interconnect express (PCIe) device based on the interrupt information.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of computer technology, in particular to the field of interrupt control, and more particularly to an interrupt control method, an interrupt controller, an electronic device, a medium and a chip. BACKGROUND

[0002] An interrupt is an important component of a modern computer system and is an important means for a CPU and an external device to communicate and perform task scheduling. Using a more efficient interrupt mechanism to achieve efficient interrupt reporting and processing can improve the efficiency of system operation.

[0003] The methods described in this section can not necessarily be prior art methods. Unless otherwise indicated, nothing in this section should be assumed to be prior art merely because it is included in this section. Similarly, unless otherwise indicated, nothing in this section should be assumed to have been admitted prior to the filing date of the present application. SUMMARY

[0004] The present disclosure provides an interrupt control method, an interrupt controller, an electronic device, a medium and a chip.

[0005] According to an aspect of the present disclosure, an interrupt control method is provided, comprising: storing at least one interrupt signal from at least one interrupt source; determining an interrupt number corresponding to each of the at least one interrupt signal based on a mapping relationship between each of the at least one interrupt source and the interrupt number; determining a target interrupt number to be sent based on the at least one interrupt signal and the interrupt number corresponding to each of the at least one interrupt signal; determining interrupt information corresponding to the target interrupt number based on the target interrupt number, wherein the interrupt information comprises information data to be written and a target address at which the information data is to be written; and writing corresponding information data to the target address of a slave interface of a Peripheral Component Interconnect Express (PCIe) device based on the interrupt information.

[0006] According to another aspect of the present disclosure, there is provided an interrupt controller, comprising: at least one interrupt status register, each of the at least one interrupt status register being configured to store an interrupt signal from a corresponding interrupt source; a mapping register configured to store a mapping relationship between each interrupt source and an interrupt number, for determining the interrupt number corresponding to the interrupt signal from each interrupt source; an interrupt arbitrator configured to determine a target interrupt number to be sent based on the contents stored in the interrupt status register and the mapping register; an interrupt information storage configured to store interrupt information corresponding to each interrupt number, wherein the interrupt information comprises information data to be written and a target address at which the information data is to be written; and a direct memory access controller configured to determine the interrupt information corresponding to the target interrupt number from the interrupt information storage based on the target interrupt number determined by the interrupt arbitrator, and write the corresponding information data to the target address of a slave interface of a peripheral component interconnect express (PCIe) device based on the interrupt information.

[0007] According to another aspect of the present disclosure, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform an interrupt control method.

[0008] According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform an interrupt control method.

[0009] According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements an interrupt control method.

[0010] According to another aspect of the present disclosure, there is provided a chip, comprising: an interrupt controller as described above.

[0011] According to one or more embodiments of the present disclosure, there is provided an interrupt control method, by collecting an interrupt signal from an interrupt source and determining interrupt information corresponding to the interrupt signal, the interrupt information data corresponding to the interrupt signal is written to a corresponding address in a PCIe, thereby realizing the reporting of the interrupt, and thus the control of the interrupt can be realized independently of the interrupt source and a peripheral component interconnect express (PCIe) device. Meanwhile, the interrupt information can be configured according to requirements, to support more interrupt numbers while having good flexibility.

[0012] It is to be understood that the details set forth herein do not limit the scope of the embodiments of the present disclosure but merely constitute illustrative examples of how the embodiments can be practiced. Other suitable embodiments will be readily apparent to one of ordinary skill in the art in view of the disclosure herein. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments and together with the description serve to explain exemplary implementations of the embodiments. The illustrated embodiments are merely examples and do not limit the scope of the claims. In all the drawings, like reference numerals refer to like parts throughout the various figures. The drawings are in simplified form and are not to precise scale. Not all details of the embodiments are shown, giving attention to the relevant details in order to not obscure the disclosure. Additionally, like reference numerals are used to denote like elements throughout the description as well.

[0014] Figure 1 A diagram illustrating an INTx interrupt mechanism in the related art is shown;

[0015] Figure 2 A diagram illustrating an interrupt mechanism of an extended message signal interrupt in the related art is shown; and

[0016] Figure 3 A flowchart illustrating an interrupt control method according to an embodiment of the present disclosure is shown;

[0017] Figure 4 A block diagram illustrating an interrupt controller according to an embodiment of the present disclosure is shown; and

[0018] Figure 5 A block diagram illustrating an exemplary electronic device that can be used to implement an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0019] Exemplary embodiments of the present disclosure are described herein with reference to the accompanying drawings, in which various details are set forth to facilitate an understanding of the embodiments of the present disclosure. However, it will be apparent to one of ordinary skill in the art that various changes in the details can be made without departing from the scope of the present disclosure. Likewise, it will be apparent that the various features described herein can be implemented in different embodiments. As such, the disclosure and examples set forth herein are to be construed in an illustrative and not a restrictive sense, and the scope of the embodiments of the present disclosure is to be measured only in terms of the claims. The following description is presented to enable any person skilled in the art to make and use the embodiments of the present disclosure.

[0020] In the present disclosure, the terms "first", "second", and the like, used to describe various elements, unless otherwise specified, are not intended to define the positional relationship, the chronological relationship, or the importance of the elements, and such terms are only used to distinguish one element from another. In some examples, the first element and the second element can refer to the same instance of the element, and in some cases, based on the context of the description, they can also refer to different instances.

[0021] The terminology used in the description of the various described examples in the present disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless specifically defined otherwise, any term conforms with the broadest plain meaning of the term as used in the corresponding technical field. Furthermore, the use of the term "and / or" in the present disclosure encompasses any and all possible combinations of the listed items, even if the list is long.

[0022] In the related art, the interrupt control is mainly implemented by three interrupt mechanisms, namely, INTx, Message Signaled Interrupt (MSI) and Extended Message Signaled Interrupt (MSI-X).

[0023] Figure 1 A schematic diagram of the INTx interrupt mechanism in the related art is shown. As shown in Figure 1 In the INTx interrupt, the Peripheral Component Interconnect express (PCIe) controller 106 in the PCIe device 101 collects the interrupt signals of the function modules 102-105, and maps the interrupt signals INT0-INT3 of the function modules 102-105 to the interrupt output signals INTA / B / C / D respectively, so that the PCIe device 101 generates an interrupt request through the sideband signal INTx, converts it into the INTR signal through the Programmable Interrupt Controller (PIC) 108 of the host south bridge 107, and sends it to the CPU 109.

[0024] Since the output pin of the interrupt signal of the PCIe device is only 4 bits, namely, INTA, INTB, INTC and INTD, the maximum number of interrupts that can be used is 4, which greatly limits the efficiency of the system interrupt processing and reduces the overall performance of the system.

[0025] Figure 2 A schematic diagram of the interrupt mechanism of the Extended Message Signaled Interrupt in the related art is shown. As shown in Figure 2As shown, in the MSI-X interrupt, the PCIe controller 206 converts the collected interrupt signals INT0 to INT3 from each functional module 202 to 205 into memory write transactions, and writes the information data corresponding to the interrupt signals INT0 to INT3 from each functional module 202 to 205 to a specific address in the CPU memory. When the CPU receives this information data, it considers that a corresponding interrupt has occurred. Typically, each interrupt number corresponds to a unique pair of write addresses and information data. The mapping relationship between interrupt numbers, write addresses, and information data is stored in the MSI-X list, and the mapping relationship can be queried through the address information of the MSI-X list stored in the MSI-X Capability table 208. The MSI-X list consists of multiple entries. Each entry corresponds to an interrupt number and contains information about the control corresponding to a specific interrupt, the information data to be written, and the target address of the information data to be written.

[0026] Since MSI-X is a relatively new technology, whether an on-chip system can use the MSI-X interrupt depends heavily on the sophistication of third-party PCIe devices.

[0027] To address the aforementioned issues, this disclosure provides an interrupt control method. By collecting interrupt signals from interrupt sources and determining the corresponding interrupt information, the interrupt information data is written to the corresponding address in the PCIe network, thereby achieving interrupt reporting. This allows for interrupt control independently of the interrupt source and the high-speed interconnect standard PCIe device. Furthermore, the interrupt information can be configured as needed to support a larger number of interrupts while maintaining good flexibility.

[0028] Exemplary embodiments of this disclosure will now be described in detail.

[0029] Figure 3 A flowchart of an interruption control method according to an embodiment of the present disclosure is shown. Figure 3 As shown, the interrupt control method 300 includes: step S301, storing at least one interrupt signal from at least one interrupt source; step S302, determining the interrupt number corresponding to each interrupt signal among the at least one interrupt signal based on the mapping relationship between each interrupt source and interrupt number among the at least one interrupt source; step S303, determining the target interrupt number to be sent based on the at least one interrupt signal and the interrupt number corresponding to each interrupt signal; step S304, determining the interrupt information corresponding to the target interrupt number based on the target interrupt number, wherein the interrupt information includes information data to be written and the target address to which the information data is to be written; and step S305, writing the corresponding information data to the target address of the slave interface of the peripheral high-speed interconnect standard PCIe device based on the interrupt information.

[0030] Thus, the interrupt signal from the interrupt source can be collected through step S301. In step S302, the interrupt number can be determined based on the previously stored mapping relationship between the interrupt source and the interrupt number, and in step S302, the interrupt information corresponding to the interrupt signal is determined based on the previously stored mapping relationship between the interrupt number and the interrupt information, so as to write the interrupt information data corresponding to the interrupt signal into the corresponding address of the PCIe, and further to realize the reporting of the interrupt. Thus, the control of the interrupt can be realized independently of the interrupt source and the peripheral component interconnect express (PCIe) device. At the same time, the interrupt information can be configured according to the requirement, so as to support more interrupt numbers while having better flexibility. By using the memory write transaction to report the interrupt to the PCIe device, the limitation of the physical pin is eliminated, more interrupt numbers can be supported, and the speed and efficiency of the interrupt processing are greatly improved.

[0031] According to some embodiments, the interrupt type controlled by the method is a message signaled interrupt (MSI-X).

[0032] The interrupt control method 300 converts the interrupt signal into a memory write transaction by using the MSI-X interrupt mechanism, so as to realize the reporting of the interrupt signal. Specifically, the interrupt control method 300 maps the interrupt signal from the interrupt source to the interrupt number according to the mapping relationship, and maps the interrupt number to the information data to be written corresponding to the interrupt number and the target address where the information data is to be written, and realizes the reporting of the interrupt signal by writing the information data to be written corresponding to the interrupt signal into the target address of the slave interface of the PCIe device.

[0033] Thus, the interrupt control method 300 has the advantages of the MSI-X interrupt mechanism, eliminates the limitation of the physical pin, can support more interrupt numbers than INTx, and improves the speed and efficiency of the interrupt processing. In addition, since the MSI-X does not require the continuity of the target address corresponding to the interrupt signal, compared with the MSI interrupt which requires all interrupts to have continuous and uninterrupted target addresses, the interrupt control method 300 based on the MSI-X interrupt can support up to 2048 interrupt numbers. At the same time, in the process of communicating with the PCIe device to realize the interrupt control, the PCIe device does not need to support the MSI-X interrupt mechanism, compared with the application of the MSI-X interrupt mechanism in the related art, the dependence on the third-party PCIe device can be eliminated, so as to realize the independent control of the interrupt.

[0034] According to some embodiments, in the mapping relationship between the interrupt source and the interrupt number, one interrupt source corresponds to only one interrupt number, and one interrupt number can correspond to multiple interrupt sources.

[0035] Exemplarily, before performing the interrupt control method 300, a mapping relationship between interrupt sources and interrupt numbers needs to be stored or set in advance. Specifically, a corresponding mapping register can be set for each interrupt source, and the value in the mapping register determines the mapping relationship between the corresponding interrupt source and the interrupt number. When the configured interrupt type is MSI-X, the value in the mapping register determines the number of MSI-X entries used to send the interrupt signal of the corresponding interrupt source.

[0036] Exemplarily, when the configured interrupt type is MSI-X, an MSI-X list needs to be stored in advance to store the interrupt information of the information data to be written and the target address of the information data to be written corresponding to each MSI-X interrupt number. In one example, the interrupt information stored in the MSI-X list further includes control information for the interrupt number to realize individual control of each interrupt. The maximum number of interrupts supported by the MSI-X list can be reduced or expanded according to the size of the system on chip.

[0037] According to some embodiments, the interrupt type configured by the method can be message signal interrupt (MSI).

[0038] According to some embodiments, the interrupt control method 300 further includes: before storing the at least one interrupt signal, determining, for each of the at least one interrupt source, whether to receive an interrupt signal from the interrupt source.

[0039] Exemplarily, a corresponding mask register can be set for each interrupt source, and whether to receive an interrupt signal from the interrupt source is selected by configuring the mask register corresponding to the interrupt source, thereby realizing the reception control of the interrupt signal of each interrupt source.

[0040] Exemplarily, the mask register determines that the received interrupt signal is to be stored in the corresponding interrupt status register.

[0041] According to some embodiments, step S103 includes: recording the generation order of the at least one interrupt signal; and determining the target interrupt number to be sent based on the generation order and the interrupt number corresponding to each interrupt signal.

[0042] It can be understood that at the same time, there can be multiple interrupt signals waiting to be sent from the interrupt source side, in which case the generation order of the multiple interrupt signals can be recorded, and the target interrupt number can be determined based on the generation order, so that the interrupt signal generated earlier can be sent first.

[0043] According to some embodiments, the target interrupt number is determined by using a round-robin scheduling arbitrator.

[0044] The polling scheduling arbitrator determines the target interrupt number based on the generation order when arbitrating a plurality of pending interrupt signals, and determines the next pending interrupt signal by polling in turn. There is no priority relationship between interrupt sources, and all of them can be sent within a limited time.

[0045] In one example, whether a corresponding bit has an interrupt signal is represented by whether bit 0-bit 10 is set. When bit 2 is set first to represent that the bit generates an interrupt signal first, the polling scheduling arbitrator determines the interrupt number corresponding to bit 2 as the target interrupt number, and polls in the order of bit 3-bit 2 to determine the next pending interrupt signal.

[0046] According to some embodiments, a priority encoder can also be used as an arbitrator, and the sending order of the interrupt signals is determined based on the priority configured for the interrupt sources.

[0047] According to some embodiments, the interrupt control method 300 further comprises: remapping the target address of the slave interface of the PCIe device into a CPU physical address based on a preset rule; and forwarding the information data in the target address to the CPU physical address by the slave interface.

[0048] For example, the address space of the slave interface of the PCIe device is smaller than the physical address space of the CPU, and therefore, part of the address information received at the slave interface is lost, and an address translator is needed to remap the target address of the slave interface into a CPU physical address, so that the slave interface can forward the information data in the target address to the CPU physical address. In one example, the process of remapping the target address of the slave interface into a CPU physical address by the address translator comprises zero padding the high bits of the target address of the slave interface, so that the remapped CPU physical address has the same number of bits as the physical address space of the CPU.

[0049] According to another aspect of the present disclosure, an interrupt controller is provided. As Figure 4As shown, the interrupt controller 400 comprises: at least one interrupt status register, each of the at least one interrupt status register 401 is configured to store an interrupt signal from an interrupt source; a mapping register 402 configured to store a mapping relationship between each interrupt source and an interrupt number, for determining the interrupt number corresponding to the interrupt signal from each interrupt source; an interrupt arbitrator 403 configured to determine a target interrupt number to be sent based on the contents stored in the interrupt status register and the mapping register; an interrupt information storage 404 configured to store interrupt information corresponding to each interrupt number, wherein the interrupt information comprises information data to be written and a target address at which the information data is to be written; and a direct memory access controller 405 configured to determine the interrupt information corresponding to the target interrupt number from the interrupt information storage based on the target interrupt number determined by the interrupt arbitrator, and write the corresponding information data to the target address of the slave interface of the peripheral component interconnect express (PCIe) device based on the interrupt information.

[0050] In this way, by setting the interrupt controller independent of the interrupt source and the PCIe device, independent control of the interrupt is achieved. The interrupt controller 300 receives the interrupt signal from the interrupt source through the interrupt status register 301, and configures the interrupt signal through the mapping register 302, the interrupt arbitrator 303, and the interrupt information storage 304, so that the direct memory access controller 305 can convert the interrupt signal from the interrupt source into write data and write the information data corresponding to the interrupt signal to the slave interface of the PCIe device. At the same time, the interrupt information storage 304 can be configured according to requirements to support more interrupts while having better flexibility. By using memory write transactions to report interrupts to the PCIe device, the limitation of physical pins is overcome, more interrupts can be supported, and the speed and efficiency of interrupt processing are greatly improved.

[0051] According to some embodiments, the interrupt controller 300 is configured to support an extended message signal interrupt (MSI-X).

[0052] The interrupt controller 300 converts the interrupt signal into a memory write transaction by using the MSI-X interrupt mechanism, thereby realizing the reporting of the interrupt signal. Specifically, the interrupt controller 300 maps the interrupt signal from the interrupt source to an interrupt number according to the mapping register 302, and maps the interrupt number to the information data to be written corresponding to the interrupt number and the target address at which the information data is to be written according to the interrupt information storage 304, and realizes the reporting of the interrupt signal by writing the information data to be written corresponding to the interrupt signal to the target address of the slave interface of the PCIe device.

[0053] Thus, the interrupt controller 300 has the advantages of the MSI-X interrupt mechanism, is free from the limitation of physical pins, can support more interrupt numbers than INTx, and improves the speed and efficiency of interrupt processing. In addition, since the MSI-X does not require the continuity of the target address corresponding to the interrupt signal, the interrupt controller 300 based on the MSI-X interrupt can support up to 2048 interrupt numbers, compared with the MSI interrupt which requires all interrupts to have continuous and uninterrupted target addresses. Meanwhile, the interrupt controller 300 is independent of the interrupt source and the PCIe device, and in the process of communicating with the PCIe device to implement interrupt control, the PCIe device does not need to support the MSI-X interrupt mechanism, compared with the application of the MSI-X interrupt mechanism in the related art, the dependence on the third-party PCIe device is eliminated, thereby realizing independent control of the interrupt.

[0054] According to some embodiments, in the mapping relationship between each interrupt source and interrupt number indicated by the mapping register, one interrupt source corresponds to one interrupt number, and one interrupt number can correspond to multiple interrupt sources.

[0055] For example, in the interrupt controller, a corresponding mapping register 302 is provided for each interrupt source, and the value in the mapping register 302 determines the mapping relationship between the interrupt numbers of the corresponding interrupt source. When the interrupt type configured by the interrupt controller 300 is MSI-X, the value in the mapping register 302 determines the number of MSI-X entries used to send the interrupt signal of the corresponding interrupt source.

[0056] For example, when the interrupt type configured by the interrupt controller 300 is MSI-X, the interrupt information storage 304 in the interrupt controller 300 is used to store the MSI-X list to store the interrupt information such as the information data to be written and the target address of the information data to be written corresponding to each MSI-X interrupt number. In one example, the interrupt information stored in the MSI-X list of the interrupt information storage 304 further includes control information for the interrupt number to realize the individual control of each interrupt. The maximum number of interrupts supported by the MSI-X list can be reduced or expanded according to the size of the system on chip.

[0057] According to some embodiments, the interrupt type configured by the interrupt controller 300 can be message signal interrupt MSI.

[0058] According to some embodiments, the interrupt controller 300 further includes a masking register corresponding to the interrupt source, configured to determine whether to receive the interrupt signal from the interrupt source.

[0059] For example, a corresponding mask register can be set for each interrupt source in the interrupt controller 300. By configuring the mask register corresponding to an interrupt source, the interrupt controller can choose whether to receive the interrupt signal from the interrupt source, thereby achieving the control of the reception of the interrupt signal from each interrupt source.

[0060] For example, the mask register determines that the received interrupt signal will be stored in the corresponding interrupt status register 301.

[0061] According to some embodiments, the interrupt arbiter 303 is further configured to, in response to the interrupt status register receiving a plurality of interrupt signals, record the generation order of the plurality of interrupt signals, and determine the target interrupt number based on the generation order.

[0062] It can be understood that there can be multiple interrupt signals waiting to be sent from the interrupt source side at the same time. In this case, the interrupt arbiter 303 is used to record the generation order of the plurality of interrupt signals, and determine the target interrupt number based on the generation order, so that the interrupt signal generated earlier can be sent first.

[0063] According to some embodiments, the interrupt arbiter 303 is a polling scheduling arbiter. When arbitrating a plurality of interrupt signals to be sent, the polling scheduling arbiter determines the target interrupt number based on the generation order, and sequentially polls to determine the next interrupt signal to be sent. There is no priority relationship between interrupt sources, and all can be sent within a limited time.

[0064] In one example, whether a corresponding bit has an interrupt signal is represented by whether bit 0-bit 10 is set. When bit 2 is set first to indicate that the bit generates an interrupt signal first, the polling scheduling arbiter determines the interrupt number corresponding to the interrupt signal corresponding to bit 2 as the target interrupt number, and polls in the order of bit 3-bit 2 to determine the next interrupt signal to be sent.

[0065] According to some embodiments, a priority encoder can also be used as the interrupt arbiter 303, and the sending order of the interrupt signal is determined based on the priority configured for the interrupt source.

[0066] According to some embodiments, the interrupt controller 300 further comprises an address translator configured to remap the target address of the slave interface of the PCIe device to a CPU physical address based on a preset rule, so that the slave interface forwards the information data in the target address to the CPU physical address.

[0067] For example, the address space of a PCIe device's slave interface is smaller than the CPU's physical address space. Therefore, the address information received at the slave interface will lose some information. An address translator is needed to remap the target address of the slave interface to the CPU physical address so that the slave interface can forward the information data from the target address to the CPU physical address. In one example, the process of the address translator remapping the target address of the slave interface to the CPU physical address includes padding the high-order bits of the target address with zeros so that the remapped CPU physical address has the same number of bits as the CPU's physical address space.

[0068] According to another aspect of this disclosure, a chip is also provided, including the interrupt controller as described above.

[0069] like Figure 5 As shown, the electronic device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. The RAM 503 may also store various programs and data required for the operation of the electronic device 500. The computing unit 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0070] Multiple components in electronic device 500 are connected to I / O interface 505, including: input unit 506, output unit 507, storage unit 508, and communication unit 509. Input unit 506 can be any type of device capable of inputting information to electronic device 500. Input unit 506 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of electronic device, and may include, but is not limited to, a mouse, keyboard, touchscreen, trackpad, trackball, joystick, microphone, and / or remote control. Output unit 507 can be any type of device capable of presenting information, and may include, but is not limited to, a monitor, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 508 may include, but is not limited to, disk and optical disk. Communication unit 509 allows electronic device 500 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth. TM Devices, 802.11 devices, WiFi devices, WiMax devices, cellular communication devices and / or the like.

[0071] The computing unit 501 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 501 performs various methods and processes described above, such as the interrupt control method. For example, in some embodiments, the interrupt control method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 508. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 500 via the ROM 502 and / or the communication unit 509. When the computer program is loaded onto the RAM 503 and executed by the computing unit 501, one or more steps of the interrupt control method described above can be performed. Alternatively, in other embodiments, the computing unit 501 can be configured to perform the interrupt control method by any other appropriate means, such as by means of firmware.

[0072] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a complex programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0073] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, implements the functions / acts specified in the flowcharts and / or block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine and partially on a remote machine or entirely on a remote machine or server.

[0074] In the context of this disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0075] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0076] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0077] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0078] It should be understood that the various forms of flow illustrated above can be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technology disclosed in the present disclosure can be achieved, which is not limited herein.

[0079] While embodiments or examples of the present disclosure have been described with reference to the drawings, it should be understood that the methods, systems, and devices described above are merely exemplary embodiments or examples, and the scope of the present disclosure is not limited by these embodiments or examples, but is only limited by the claims and their equivalents. Various elements in the embodiments or examples can be omitted or replaced by equivalent elements thereof. In addition, each step can be performed in an order different from that described in the present disclosure. Further, various elements in the embodiments or examples can be combined in various ways. It is important that many of the elements described herein can be replaced by equivalent elements that appear after the present disclosure as technology evolves.

Claims

1. An interrupt control method, comprising: Store at least one interrupt signal from at least one interrupt source; Based on the mapping relationship between each interrupt source and interrupt number in the at least one interrupt source, determine the interrupt number corresponding to each interrupt signal in the at least one interrupt signal; Based on the at least one interrupt signal and the interrupt number corresponding to each interrupt signal, the target interrupt number to be sent is determined, including: Record the generation sequence of the at least one interrupt signal; and Based on the generation order and the interrupt number corresponding to each interrupt signal, the target interrupt number to be sent is determined so that the earlier generated interrupt signal can be sent first. Based on the target interrupt number, the interrupt information corresponding to the target interrupt number is determined, wherein the interrupt information includes information data to be written and the target address to which the information data is to be written; and Based on the interrupt information, the corresponding information data is written to the target address of the slave interface of the peripheral high-speed interconnect standard PCIe device.

2. The method according to claim 1, further comprising: Before storing the at least one interrupt signal, for each of the at least one interrupt source, it is determined whether to receive an interrupt signal from that interrupt source.

3. The method according to claim 1 or 2, wherein, The target interrupt number is determined using a polling scheduling arbitrator.

4. The method according to claim 1 or 2, further comprising: Based on preset rules, the target address of the slave interface of the PCIe device is remapped to the CPU physical address; as well as The information data in the target address is forwarded to the CPU physical address using the slave interface.

5. The method according to claim 1 or 2, wherein, The interrupt type controlled by the method is Extended Message Signal Interrupt (MSI-X).

6. The method according to claim 1 or 2, wherein, In the aforementioned mapping relationship between interrupt sources and interrupt numbers, one interrupt source corresponds to only one interrupt number, and one interrupt number can correspond to multiple interrupt sources.

7. An interrupt controller, comprising: At least one interrupt status register, each of the at least one interrupt status registers being configured to store an interrupt signal from a corresponding interrupt source; The mapping register is configured to store the mapping relationship between each interrupt source and the interrupt number, so as to determine the interrupt number corresponding to the interrupt signal from each interrupt source; An interrupt arbiter is configured to determine the target interrupt number to be sent based on the contents stored in the interrupt status register and the mapping register, wherein the interrupt arbiter is further configured to: In response to the interrupt status register receiving multiple interrupt signals, the generation order of the multiple interrupt signals is recorded, and the target interrupt number is determined based on the generation order, so that the earlier interrupt signal can be sent first; An interrupt information memory is configured to store interrupt information corresponding to each interrupt number, wherein the interrupt information includes information data to be written and a target address to which the information data is to be written; and The direct memory access controller is configured to determine the interrupt information corresponding to the target interrupt number from the interrupt information memory based on the target interrupt number determined by the interrupt arbitrator, and write the corresponding information data to the target address of the slave interface of the peripheral high-speed interconnect standard PCIe device based on the interrupt information.

8. The interrupt controller according to claim 7, further comprising: The mask register corresponding to the interrupt source is configured to determine whether to receive the interrupt signal from that interrupt source.

9. The interrupt controller according to claim 7 or 8, wherein the interrupt arbitrator is a polling scheduling arbitrator.

10. The interrupt controller according to claim 7 or 8, further comprising: An address translator is configured to remap the target address of the slave interface of the PCIe device to a CPU physical address based on preset rules, so that the slave interface forwards the information data in the target address to the CPU physical address.

11. The interrupt controller according to claim 7 or 8, wherein the interrupt type configured by the interrupt controller is Extended Message Signal Interrupt MSI-X.

12. The interrupt controller according to claim 7 or 8, wherein in each interrupt source and interrupt number mapping relationship indicated by the mapping register, one interrupt source corresponds to only one interrupt number, and one interrupt number can correspond to multiple interrupt sources.

13. An electronic device, comprising: At least one processor; as well as A memory that is communicatively connected to the at least one processor; in The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

14. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-6.

15. A computer program product comprising a computer program, wherein, The computer program, when executed by a processor, implements the method of any one of claims 1-6.

16. A chip, comprising: The interrupt controller according to any one of claims 7-12.

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