A control method and system for a LCCL type simplified three-level inverter

Abstract

The present invention discloses a control method and system for a LCCL type simplified three-level inverter, comprising: sampling the three-phase current on the output side of the LCCL type simplified three-level inverter and the voltage of two capacitors on the DC side; sending the obtained three-phase current on the output side to a fixed time regulator to obtain a first distribution factor of a P-type / N-type small vector duty ratio; sending the voltage of the two capacitors on the DC side to an error processing unit and a proportional regulator to obtain a second distribution factor of a P-type / N-type small vector duty ratio; adding the first distribution factor and the second distribution factor to obtain a total distribution factor; distributing the duty ratio of the small vector in the basic voltage vector by the total distribution factor to obtain the duty ratio of the P-type and N-type small vectors; and designing a switch sequence by using the duty ratio of the P-type and N-type small vectors and the duty ratio of the remaining vectors in the basic voltage vector except the small vector. The method of the present invention can effectively suppress the common-mode resonant current, ensure the balance of the midpoint voltage, and thus improve the reliability of system operation.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic power conversion, and in particular to a control method and system for a LCCL type simplified three-level inverter. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] The three-level inverter has obvious advantages such as low voltage stress of power switch tube, high output waveform quality, and small filter size. It is widely used in renewable energy generation, composite energy storage, power quality management and other fields. Diode clamped and T-type three-level inverters are the two most commonly used three-level inverter topologies, but both require a large number of power switch tubes, which inevitably increases system cost and volume.

[0004] In order to further reduce the number of power switches, reduce system size and cost, Tung Ngo and other scholars from Auckland University of Technology in New Zealand proposed a simplified Neutral-Point Clamped (SNPC) three-level inverter topology, which contains ten power switches, which is further reduced than the traditional T-type three-level inverter topology, and does not require a clamping diode.

[0005] However, the inherent high-frequency switching action of power devices causes common-mode voltage problems, which further generates common-mode leakage current, inevitably leading to output current distortion, increased power loss and common-mode electromagnetic interference, and even threatening personal safety.

[0006] The LCCL filter is a solution to the common-mode leakage current problem. It splits the AC filter capacitor into two parts. The common point of a group of capacitors with smaller capacity is connected to the neutral point on the DC side. However, the only drawback is that it causes common-mode resonant current and midpoint voltage imbalance.

[0007] The inventors found that although the traditional passive damping method can suppress the common-mode resonant current to a certain extent, it increases the system cost and loss and reduces the system efficiency. Therefore, the common-mode resonant current suppression and DC side midpoint voltage balance control method based on the control method need to be studied urgently. Summary of the invention

[0008] In order to solve the above problems, the present invention proposes a control method and system for a LCCL type simplified three-level inverter, which can effectively suppress the common-mode resonant current, ensure the balance of the midpoint voltage, and thus improve the system operation reliability.

[0009] To achieve the above object, the present invention adopts the following technical solution:

[0010] In a first aspect, a control method of a LCCL type simplified three-level inverter is proposed, comprising:

[0011] Sample the three-phase current on the output side of the simplified LCCL three-level inverter and the voltage of the two capacitors on the DC side;

[0012] The obtained three-phase current on the output side is sent to the fixed time regulator to obtain the first distribution factor of the P-type / N-type small vector duty ratio, the voltage of the two capacitors on the DC side is sent to the error processing unit and the proportional regulator to obtain the second distribution factor of the P-type / N-type small vector duty ratio, and the first distribution factor and the second distribution factor are added to obtain the total distribution factor;

[0013] The duty ratios of the small vectors in the basic voltage vector are distributed by the total distribution factor to obtain the duty ratios of the P-type and N-type small vectors. The switching sequence is designed using the duty ratios of the P-type and N-type small vectors and the duty ratios of the remaining vectors in the basic voltage vector except the small vector.

[0014] Furthermore, the total allocation factor is clipped to limit the value of the total allocation factor to between -1 and 1.

[0015] Furthermore, the fixed time regulator is:

[0016] Δζ1=k1·sig(i a1 +i b1 +i c1 ) λ +k2·sig(i a1 +i b1 +i c1 ) μ

[0017] Among them, i a1 、i b1 、i c1 represents the three-phase current on the output side, k1, k2, λ, μ are the parameters of the fixed time regulator, and k1 and k2 are both greater than 0, 0<λ<1, μ>1; sig[e(t)] λ =sgn[e(t)] λ ·|e(t)| λ , sgn is the sign function.

[0018] Furthermore, the error processing unit and the proportional regulator are:

[0019]

[0020] Among them, k p,np is the parameter of the proportional regulator; V C1、V C2 is the voltage of the two capacitors on the DC side; ΔV C12 is the preset capacitor voltage deviation threshold.

[0021] Furthermore, based on the sector and region where the reference voltage vector is located, the volt-second balance equation is listed, and the volt-second balance equation is solved to obtain the duty cycle of the basic voltage vector.

[0022] Furthermore, each sector includes two regions, region ① and region ②, wherein the basic voltage vector of region ① includes two large vectors and two pairs of small vectors; the basic voltage vector of region ② includes a zero vector and two pairs of small vectors;

[0023] When the reference voltage vector is located in region ① within sector 1, the duty ratios of the two large vectors and the two pairs of small vectors are:

[0024]

[0025]

[0026]

[0027]

[0028]

[0029] Among them, V r is the reference voltage vector, V rg and V rh are the g-axis and h-axis components of the reference voltage vector, V dc is the DC bus voltage, d L1 ,d L2 ,d S1 and d S2 are the duty cycles of large vector [PNN], large vector [PPN], small vector [POO] / [ONN], and small vector [PPO] / [OON], respectively. β is the duty cycle allocation factor of the small vector. s12 is the sum of the duty cycles of the small vectors [POO] / [ONN] and [PPO] / [OON];

[0030] When the reference voltage vector is located in region ② within sector 1, the duty ratios of the two large vectors and the two pairs of small vectors are:

[0031]

[0032] Among them, V r is the reference voltage vector, V rg and V rh are the g-axis and h-axis components of the reference voltage vector, V dcis the DC bus voltage; d S1 ,d S2 and d Z They are the duty cycles of the small vector [POO] / [ONN], the small vector [PPO] / [OON] and the zero vector [OOO] respectively.

[0033] Furthermore, the duty ratios of the small vectors in the basic voltage vector are allocated by the total allocation factor, and the duty ratios of the P-type and N-type small vectors are obtained as follows:

[0034]

[0035] Among them, Δζ1+Δζ2 is the total allocation factor, Δζ1 is the first allocation factor, Δζ2 is the second allocation factor, and d S1 and d S2 are the duty cycles of the small vector [POO] / [ONN] and the small vector [PPO] / [OON], respectively, 7p ,d 7n ,d 8p and d 8n V 7p [POO], V 7n [ONN], V 8p [PPO] and V 8n The duty cycle of [OON].

[0036] Secondly, a control system of a LCCL type simplified three-level inverter is proposed, including:

[0037] A data sampling module is used to obtain the three-phase current on the output side of the LCCL simplified three-level inverter and the voltage of two capacitors on the DC side;

[0038] The total allocation factor calculation module is used to send the sampled output side three-phase current into the fixed time regulator to obtain the first allocation factor of the P-type / N-type small vector duty ratio; send the voltage of the two capacitors on the DC side into the error processing unit and the proportional regulator to obtain the second allocation factor of the P-type / N-type small vector duty ratio; add the first allocation factor and the second allocation factor to obtain the total allocation factor;

[0039] The duty cycle calculation and switching sequence acquisition module is used to allocate the duty cycle of the small vectors in the basic voltage vector through the total allocation factor to obtain the duty cycle of the P-type and N-type small vectors; the switching sequence is designed using the duty cycle of the P-type and N-type small vectors and the duty cycle of the remaining vectors in the basic voltage vector except the small vector.

[0040] In a third aspect, an electronic device is proposed, comprising a memory and a processor, and computer instructions stored in the memory and executed on the processor, wherein when the computer instructions are executed by the processor, the steps of a control method of a LCCL type simplified three-level inverter are completed.

[0041] In a fourth aspect, a computer-readable storage medium is proposed for storing computer instructions. When the computer instructions are executed by a processor, the steps of a control method of a LCCL type simplified three-level inverter are completed.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] 1. The method of the present invention effectively suppresses the common-mode resonant current of the LCCL type simplified three-level inverter system by designing a fixed-time regulator, without setting a hardware-type damping resistor, thereby reducing the system cost.

[0044] 2. The method of the present invention can keep the system at a low common-mode leakage current, thereby improving the operational safety of the system.

[0045] 3. The method of the present invention can effectively control the voltage balance of the DC side capacitor and improve the operating reliability of the system.

[0046] Advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings in the specification, which constitute a part of the present application, are used to provide further understanding of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0048] Figure 1 The circuit topology diagram of the simplified LCCL three-level inverter;

[0049] Figure 2 The space vector diagram of the simplified three-level inverter of LCCL type;

[0050] Figure 3 This is a control block diagram of the method disclosed in Example 1;

[0051] Figure 4(a) shows the system phase voltage v when the neutral point of the filter capacitor is not connected back to the neutral point of the DC side. ao , line voltage v ab and capacitor voltage V C1 、V C2 Waveform diagram of

[0052] Figure 4(b) shows the three-phase current i on the output side of the system when the neutral point of the filter capacitor is not connected back to the neutral point of the DC side.a1 、i b1 、i c1 , three-phase current i on the grid side a2 、i b2 、i c2 and common mode leakage current i cm Waveform diagram of

[0053] Figure 5(a) shows the system phase voltage v when the neutral point of the filter capacitor is connected back to the neutral point of the DC side and there is no common mode resonant current suppression strategy. ao 、Line voltage v ab and capacitor voltage V C1 、V C2 Waveform diagram of

[0054] Figure 5(b) shows the three-phase current i on the output side of the system when the neutral point of the filter capacitor is connected back to the neutral point of the DC side and there is no common-mode resonant current suppression strategy. a1 、i b1 、i c1 , three-phase current i on the grid side a2 、i b2 、i c2 and common mode leakage current i cm Waveform diagram of

[0055] Figure 6(a) shows the system phase voltage v when the neutral point of the filter capacitor is connected back to the neutral point of the DC side and passive damping is used to suppress the common mode resonant current. ao 、Line voltage v ab and capacitor voltage V C1 、V C2 Waveform diagram of

[0056] Figure 6(b) shows the three-phase current i on the output side of the system when the neutral point of the filter capacitor is connected back to the neutral point of the DC side and passive damping is used to suppress the common-mode resonant current. a1 、i b1 、i c1 , three-phase current i on the grid side a2 、i b2 、i c2 and common mode leakage current i cm Waveform diagram of

[0057] FIG. 7( a ) shows the system phase voltage v when the neutral point of the filter capacitor is connected back to the neutral point of the DC side and the method disclosed in Example 1 is adopted. ao 、Line voltage v ab and capacitor voltage V C1 、V C2 Waveform diagram of

[0058] FIG7( b ) shows the three-phase current i at the output side of the system when the neutral point of the filter capacitor is connected back to the neutral point of the DC side and the method disclosed in Example 1 is adopted.a1 、i b1 、i c1 , three-phase current i on the grid side a2 、i b2 、i c2 and common mode leakage current i cm Waveform diagram of

[0059] Figure 8 When the neutral point of the filter capacitor is connected back to the neutral point of the DC side, the method disclosed in Example 1 is adopted, and the given current amplitude is increased from 10A to 20A in a stepwise manner, the three-phase current i a1 、i b1 、i c1 , three-phase current i on the grid side a2 、i b2 、i c2 and common mode leakage current i cm Waveform diagram of . DETAILED DESCRIPTION

[0060] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0061] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0062] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0063] Example 1

[0064] In this embodiment, a control method of a LCCL type simplified three-level inverter is disclosed.

[0065] The circuit topology diagram of the simplified LCCL three-level inverter is as follows: Figure 1 As shown, it includes a DC input power supply, DC side capacitors C1 and C2, a simplified three-level inverter and an LCCL output filter.

[0066] The DC input power supply and the two DC side capacitors are connected in series to form a DC input side circuit. The values ​​of the two DC side capacitors are equal, and the connection point of the two DC side capacitors serves as the DC input side neutral point, that is, point O1. The DC input side neutral point is connected to the neutral point of the simplified three-level inverter.

[0067] The simplified three-level inverter includes power switches S1, S2, S3, S4, S5, S6, S7, S8, S9 and S 10 The power switches S1, S2, S3, and S4 are connected in series in sequence to form a common switch unit. The power switches S5 and S6 are connected in series to form a first group of independent switch units. The power switches S7 and S8 are connected in series to form a second group of independent switch units. The power switches S9 and S 10 The third group of independent switch units are formed by connecting in series. The connection point of power switches S2, S3, is the neutral point of the simplified three-level inverter. The two ends of the common switch unit are connected to the output end of the DC input power supply. The connection point of power switches S5, S6, the connection point of power switches S7, S8 and the connection point of power switches S9, S 10 The connection points of are used as the output ends of the simplified three-level inverter and are respectively connected to the input ends of the LCCL output filter.

[0068] The LCCL output filter includes inductors L1, L2 and three capacitors C f1 , C f2 , capacitor C f1 , C f2 The series connection forms a capacitor series circuit, and the three capacitor series circuits are connected in parallel to form a capacitor parallel circuit. f1 , C f2 The connection points are connected to the output end of the simplified three-level inverter through the inductor L1. Each capacitor C f1 , C f2 The connection point is also connected to the inductor L2 as the output end of the LCCL type simplified three-level inverter for connecting to the load, and the neutral point of the DC input side is connected to the capacitor parallel circuit.

[0069] The DC input power source adopts photovoltaic array PV, C pv It is the parasitic capacitance between the photovoltaic array and the ground, which causes common-mode leakage current and poses a serious threat to the safe and reliable operation of the system. f1 The common point of the capacitors, that is, the parallel circuit of capacitors is connected to the neutral point of the DC input side, which can suppress the common-mode leakage current and ensure the safe and reliable operation of the system.

[0070] The power switch is implemented using an insulated-gate bipolar transistor (IGBT) or other forms of transistors.

[0071] The switching states of the LCCL simplified three-level inverter include three types: [P], [O] and [N]. Select the DC side neutral point (i.e. Figure 1 Point O1 in the figure is used as the reference point. When the switch state is [P], the output voltage of the bridge arm is +Vdc / 2; when the switch state is [O], the bridge arm output voltage is 0; when the switch state is [N], the bridge arm output voltage is -V dc / 2.

[0072] Table 1 Basic voltage vectors and switching states of LCCL simplified three-level inverter

[0073]

[0074] The space vector diagram of the simplified LCCL three-level inverter is shown in Figure 2 As shown, the basic voltage vector, switch state and turned-on switch tubes are shown in Table 1.

[0075] In order to achieve the goals of efficient suppression of common-mode leakage current and common-mode resonant current and balanced control of DC-side capacitor voltage, a control method for a simplified LCCL three-level inverter is proposed. Figure 3 As shown, the specific steps include:

[0076] S1: Sample the three-phase current i at the output side of the simplified LCCL three-level inverter a1 、i b1 and i c1 , the voltage V of the two capacitors on the DC side C1 、V C2 .

[0077] S2: The sampled output three-phase current i a1 、i b1 and i c1 It is sent to the fixed time regulator to obtain the first allocation factor Δζ1 of the P-type / N-type small vector duty cycle.

[0078] Among them, the fixed time regulator is:

[0079] Δζ1=k1·sig(i a1 +i b1 +i c1 ) λ +k2·sig(i a1 +i b1 +i c1 ) μ (1)

[0080] Wherein, k1, k2, λ, μ are the parameters of the fixed time regulator, and k1 and k2 are both greater than 0, 0<λ<1, μ>1; sig[e(t)] λ =sgn[e(t)] λ ·|e(t)| λ , sgn is the sign function.

[0081] S3: The voltage V of the two capacitors on the DC side C1 、V C2 It is sent to the error processing unit and the proportional regulator to obtain the second allocation factor Δζ2 of the P-type / N-type small vector duty cycle.

[0082] Among them, the error processing unit and the proportional regulator are:

[0083]

[0084] Among them, k p,np is the parameter of the proportional regulator; V C1 、V C2 is the voltage of the two capacitors on the DC side; ΔV C12 is the preset capacitor voltage deviation threshold.

[0085] S4: Add the first allocation factor Δζ1 and the second allocation factor Δζ2 to obtain a total allocation factor, and perform a limiting process on the total allocation factor.

[0086] To ensure the accuracy of the generated switching sequence, the first allocation factor Δζ1 of the P-type / N-type small vector duty cycle and the second allocation factor Δζ2 of the P-type / N-type small vector duty cycle are added, and a limiting unit is used to limit Δζ1+Δζ2 between -1 and 1, that is:

[0087] -1<Δζ1+Δζ2<1 (3)

[0088] S5: The duty ratios of the small vectors in the basic voltage vector are distributed by the total distribution factor to obtain the duty ratios of the P-type and N-type small vectors; the switching sequence is designed using the duty ratios of the P-type and N-type small vectors and the duty ratios of the remaining vectors in the basic voltage vector except the small vector.

[0089] Among them, based on the sector and area where the reference voltage vector is located, the duty cycle of the basic voltage vector is determined, and the process is:

[0090] Determine the sector and region where the reference voltage vector is located;

[0091] Write the volt-second balance equation based on the sector you are in;

[0092] The volt-second balance equation is solved to obtain the duty cycle of the basic voltage vector.

[0093] The space vector diagram of the simplified LCCL three-level inverter is shown in Figure 2 As shown, there are six sectors in total, each of which can be further divided into two areas, namely area ① and area ②. The basic voltage vector of area ① includes two large vectors and two pairs of small vectors; the basic voltage vector of area ② includes a zero vector and two pairs of small vectors.

[0094] The modulation index and the phase angle of the reference voltage vector are used to determine the sector and region where the reference voltage vector is located.

[0095] When the reference voltage vector is located in area ① within sector 1, the four basic voltage vectors closest to each other are selected to synthesize the reference voltage vector, and the volt-second balance equation is written. The four basic voltage vectors include a large vector [PNN], a large vector [PPN], a small vector [POO] / [ONN], and a small vector [PPO] / [OON]. The volt-second balance equation is written as follows:

[0096]

[0097] Among them, V r is the reference voltage vector, V L1 、V L2 、V S1 and V S2 They represent large vector [PNN], large vector [PPN], small vector [POO] / [ONN], small vector [PPO] / [OON], respectively. L1 ,d L2 ,d S1 and d S2 They are the duty cycles of large vector [PNN], large vector [PPN], small vector [POO] / [ONN], and small vector [PPO] / [OON] respectively.

[0098] An indirect calculation method is designed to solve equation (4), and the small vector duty cycle allocation factor β and the sum of the duty cycles of the small vectors [POO] / [ONN] and [PPO] / [OON] d are introduced. s12 , the duty cycle of each basic voltage vector is obtained as:

[0099]

[0100] Among them, V rg and V rh are the g-axis and h-axis components of the reference voltage vector, V dc is the DC bus voltage, β is the small vector duty cycle allocation factor, d s12 is the sum of the duty cycles of the small vectors [POO] / [ONN] and [PPO] / [OON], which can be expressed as:

[0101]

[0102] Take the small vector duty cycle allocation factor β as its upper limit β max and the lower limit β min The arithmetic mean of

[0103]

[0104] Among them, the upper limit value and the lower limit value of the small vector duty cycle allocation factor β are expressed as formula (8) and formula (9) respectively.

[0105]

[0106]

[0107] Using the total allocation factor Δζ1+Δζ2 after the limiting process, the duty cycle d of the small vector is S1 and d S2 Assign and obtain the duty cycle (d 7p ,d 7n ,d 8p and d 8n ), the duty cycle of the large vector remains unchanged, then the duty cycle of the P-type and N-type small vectors can be expressed as:

[0108]

[0109] Among them, d 7p ,d 7n ,d 8p and d 8n V 7p [POO], V 7n [ONN], V 8p [PPO] and V 8n The duty cycle of [OON].

[0110] Using the duty cycle of small vectors of P type and N type and the duty cycle of large vectors d L1 ,d L2 , the design switching sequence is as follows:

[0111] [PNN]-[ONN]-[OON]-[PPN]-[PPO]-[POO]-[PNN].

[0112] When the reference voltage vector is located in area ② within sector 1, the three closest basic voltage vectors are selected to synthesize the reference voltage vector, and the volt-second balance equation is written. The three basic voltage vectors include a small vector [POO] / [ONN], a small vector [PPO] / [OON], and a zero vector [OOO]. The volt-second balance equation is written as follows:

[0113]

[0114] Among them, V Z is the zero vector, d Z Duty cycle of zero vector

[0115] A direct calculation method is designed to solve equation (11) and obtain the duty cycle of each basic voltage vector:

[0116]

[0117] Among them, V rg and V rh are the g-axis and h-axis components of the reference voltage vector, V dc is the DC bus voltage.

[0118] Using the total allocation factor Δζ1+Δζ2 after the limiting process, the duty cycle d of the small vector is S1 and d S2 Assign and obtain the duty cycle (d 7p ,d 7n ,d 8p and d 8n ), the duty cycle of the zero vector remains unchanged, and the duty cycles of the P-type and N-type small vectors are obtained as follows:

[0119]

[0120] Among them, d 7p ,d 7n ,d 8p and d 8n V 7p [POO], V 7n [ONN], V 8p [PPO] and V 8n The duty cycle of [OON].

[0121] Using the duty cycle of the P-type and N-type small vectors and the duty cycle of the zero vector d Z , the design switching sequence is as follows:

[0122] [ONN]-[OON]-[OOO]-[POO]-[PPO]-[POO]-[OOO]-[OON]-[ONN].

[0123] When the reference voltage vector is located in sectors other than sector 1, the duty cycle of each voltage vector and the corresponding switching sequence can be obtained by utilizing the symmetry of the space vector diagram, which will not be described in detail.

[0124] Figure 4 (a) and Figure 4 (b) are the output waveforms of the system when the neutral point of the filter capacitor is not connected back to the neutral point of the DC side, including: phase voltage (v ao )、Line voltage(v ab ) and capacitor voltage (V C1 、V C2 ), output side three-phase current (i a1 、i b1 、i c1 ), three-phase current on the grid side (i a2 、i b2、i c2 ) and common-mode leakage current (i cm ). It can be seen that the parasitic capacitance between the photovoltaic array and the ground causes a common-mode leakage current with an effective value of up to 1426mA, which seriously threatens the safety and reliability of system operation; the three-phase current on the grid side is seriously distorted, with a THDi as high as 6.37%.

[0125] Figure 5(a) and Figure 5(b) are the output waveforms of the system when the neutral point of the filter capacitor is connected back to the neutral point of the DC side and there is no common-mode resonant current suppression strategy, including: phase voltage (v ao )、Line voltage(v ab ) and capacitor voltage (V C1 、V C2 ), output side three-phase current (i a1 、i b1 、i c1 ), three-phase current on the grid side (i a2 、i b2 、i c2 ) and common-mode leakage current (i cm ). It can be seen that by connecting the neutral point of the filter capacitor back to the neutral point of the DC side, the common-mode leakage current of the system is significantly suppressed, and its effective value is reduced to 102.4mA. However, this connection method causes serious common-mode resonant current, and the three-phase current waveform on the output side oscillates significantly, with a maximum value exceeding 50A, which can easily cause the system to shut down due to overcurrent protection.

[0126] Figure 6 (a) and Figure 6 (b) are the output waveforms of the system when the neutral point of the filter capacitor is connected back to the neutral point of the DC side and passive damping is used to suppress the common mode resonant current, including: phase voltage (v ao )、Line voltage(v ab ) and capacitor voltage (V C1 、V C2 ), output side three-phase current (i a1 、i b1 、i c1 ), three-phase current on the grid side (i a2 、i b2 、i c2 ) and common-mode leakage current (i cm ). It is not difficult to see that the hardware-based passive damping method can suppress the common-mode resonant current to a certain extent, but the effect is limited and increases the system cost and power loss.

[0127] FIG. 7( a ) and FIG. 7( b ) are output waveform diagrams of the system when the method disclosed in this embodiment is adopted, including: phase voltage (v ao )、Line voltage(v ab ) and capacitor voltage (V C1 、V C2), output side three-phase current (i a1 、i b1 、i c1 ), three-phase current on the grid side (i a2 、i b2 、i c2 ) and common-mode leakage current (i cm ). Obviously: the method disclosed in this embodiment can achieve the goals of effectively suppressing common-mode leakage current and common-mode resonant current, and controlling the balanced voltage of the DC side capacitor; compared with the traditional passive damping method, the method of the present invention has obvious advantages and does not need to increase the system cost; the quality of the three-phase current waveform on the grid side is significantly improved, and THDi is reduced to 4.05%.

[0128] When the method disclosed in this embodiment is adopted and the given current amplitude is increased from 10A to 20A in a stepwise manner, the output side three-phase current (i a1 、i b1 、i c1 ), three-phase current on the grid side (i a2 、i b2 、i c2 ) and common-mode leakage current (i cm ) Waveform diagram Figure 8 It can be seen that when the given current amplitude of the system undergoes a step change, the method of the present invention can effectively suppress the common-mode leakage current in the dynamic process.

[0129] The method disclosed in this embodiment effectively suppresses the common-mode resonant current of the LCCL type simplified three-level inverter system by designing a fixed-time regulator, without setting a hardware-type damping resistor, thereby reducing the system cost; it can keep the system at a low common-mode leakage current, thereby improving the operating safety of the system; it can effectively control the voltage balance of the DC side capacitors, thereby improving the operating reliability of the system.

[0130] Example 2

[0131] In this embodiment, a control system of a LCCL type simplified three-level inverter is disclosed, comprising:

[0132] A data sampling module is used to obtain the three-phase current on the output side of the LCCL simplified three-level inverter and the voltage of two capacitors on the DC side;

[0133] The total allocation factor calculation module is used to send the sampled output side three-phase current into the fixed time regulator to obtain the first allocation factor of the P-type / N-type small vector duty ratio; send the voltage of the two capacitors on the DC side into the error processing unit and the proportional regulator to obtain the second allocation factor of the P-type / N-type small vector duty ratio; add the first allocation factor and the second allocation factor to obtain the total allocation factor;

[0134] The duty cycle calculation and switching sequence acquisition module is used to allocate the duty cycle of the small vectors in the basic voltage vector through the total allocation factor to obtain the duty cycle of the P-type and N-type small vectors; the switching sequence is designed using the duty cycle of the P-type and N-type small vectors and the duty cycle of the remaining vectors in the basic voltage vector except the small vector.

[0135] Example 3

[0136] In this embodiment, an electronic device is disclosed, including a memory and a processor, and computer instructions stored in the memory and running on the processor. When the computer instructions are executed by the processor, the steps described in the control method of a LCCL type simplified three-level inverter disclosed in Example 1 are completed.

[0137] Example 4

[0138] In this embodiment, a computer-readable storage medium is disclosed for storing computer instructions. When the computer instructions are executed by a processor, the steps of the control method of a LCCL type simplified three-level inverter disclosed in Embodiment 1 are completed.

[0139] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A control method for a LCCL type simplified three-level inverter, characterized in that: include: Sample the three-phase current on the output side of the simplified LCCL three-level inverter and the voltage of the two capacitors on the DC side; The obtained three-phase current on the output side is sent to the fixed time regulator to obtain the first distribution factor of the P-type / N-type small vector duty ratio, the voltage of the two capacitors on the DC side is sent to the error processing unit and the proportional regulator to obtain the second distribution factor of the P-type / N-type small vector duty ratio, and the first distribution factor and the second distribution factor are added to obtain the total distribution factor; The fixed time regulator is: in, i a1 , i b1 , i c1 Indicates the three-phase current on the output side, k 1. k 2. λ , μ are the parameters of the fixed time regulator, and k 1. k 2 are both greater than 0, 0 < λ < 1, μ > 1; sig [ e ( t )] λ = sgn [ e ( t )] λ ·| e ( t ) | λ , sgn is a symbolic function; The duty ratios of the small vectors in the basic voltage vector are distributed by the total distribution factor to obtain the duty ratios of the P-type and N-type small vectors. The switching sequence is designed using the duty ratios of the P-type and N-type small vectors and the duty ratios of the remaining vectors in the basic voltage vector except the small vector.

2. The control method of a LCCL type simplified three-level inverter according to claim 1, characterized in that: The total allocation factor is clipped to limit its value to between -1 and 1.

3. The control method of a LCCL type simplified three-level inverter according to claim 1, characterized in that: The error processing unit and the proportional regulator are: in, k p,np is the parameter of the proportional regulator; V C1 , V C2 is the voltage of the two capacitors on the DC side; Δ V C12 is the preset capacitor voltage deviation threshold.

4. The control method of a LCCL type simplified three-level inverter according to claim 1, characterized in that: Based on the sector and region where the reference voltage vector is located, the volt-second balance equation is listed and solved to obtain the duty cycle of the basic voltage vector.

5. The control method of a LCCL type simplified three-level inverter according to claim 1, characterized in that: Each sector includes two areas, namely area ① and area ②. The basic voltage vector of area ① includes two large vectors and two pairs of small vectors; the basic voltage vector of area ② includes a zero vector and two pairs of small vectors. When the reference voltage vector is located in region ① within sector 1, the duty ratios of the two large vectors and the two pairs of small vectors are: in, V rg and V rh The reference voltage vector g Axis and h Axis component, V dc is the DC bus voltage, d L1 , d L2 , d S1 and d S2 They are the duty cycles of large vector [PNN], large vector [PPN], small vector [POO] / [ONN], and small vector [PPO] / [OON], respectively. β is the small vector duty cycle allocation factor, d s12 is the sum of the duty cycles of the small vectors [POO] / [ONN] and [PPO] / [OON]; When the reference voltage vector is located in region ② within sector 1, the duty ratios of the two large vectors and the two pairs of small vectors are: in, V rg and V rh The reference voltage vector g Axis and h Axis component, V dc is the DC bus voltage; d S1 , d S2 and d Z They are the duty cycles of the small vector [POO] / [ONN], the small vector [PPO] / [OON] and the zero vector [OOO] respectively.

6. A control method for a LCCL type simplified three-level inverter as claimed in claim 5, characterized in that: The duty ratios of the small vectors in the basic voltage vector are distributed by the total distribution factor, and the duty ratios of the P-type and N-type small vectors are obtained as follows: Among them, Δ ζ 1+Δ ζ 2 is the total allocation factor, Δ ζ 1 is the first distribution factor, is the second distribution factor, d S1 and d S2 are the duty cycles of the small vector [POO] / [ONN] and the small vector [PPO] / [OON], d 7p , d 7n , d 8p and d 8n They are V 7p [POO] V 7n [ONN] V 8p [PPO] and V 8n The duty cycle of [OON].

7. A control system of a LCCL type simplified three-level inverter, characterized in that: include: A data sampling module is used to obtain the three-phase current on the output side of the LCCL simplified three-level inverter and the voltage of two capacitors on the DC side; A total allocation factor calculation module is used to send the sampled output side three-phase current to the fixed time regulator to obtain the first allocation factor of the P-type / N-type small vector duty cycle; The voltages of the two capacitors on the DC side are sent to the error processing unit and the proportional regulator to obtain the second allocation factor of the P-type / N-type small vector duty cycle; the first allocation factor and the second allocation factor are added to obtain the total allocation factor; The fixed time regulator is: in, i a1 , i b1 , i c1 Indicates the three-phase current on the output side, k 1. k 2. λ , μ are the parameters of the fixed time regulator, and k 1. k 2 are both greater than 0, 0 < λ < 1, μ > 1; sig [ e ( t )] λ = sgn [ e ( t )] λ ·| e ( t ) | λ , sgn is a symbolic function; The duty cycle calculation and switch sequence acquisition module is used to allocate the duty cycle of the small vectors in the basic voltage vector through the total allocation factor to obtain the duty cycle of the P-type and N-type small vectors; The switching sequence is designed using the duty ratios of the P-type and N-type small vectors and the duty ratios of the remaining vectors in the basic voltage vector except the small vector.

8. An electronic device, characterized in that: The invention comprises a memory and a processor and computer instructions stored in the memory and executed on the processor. When the computer instructions are executed by the processor, the steps of the control method of a LCCL type simplified three-level inverter as claimed in any one of claims 1 to 6 are completed.

9. A computer-readable storage medium, characterized in that: Used to store computer instructions, when the computer instructions are executed by a processor, the steps of the control method of a LCCL type simplified three-level inverter as described in any one of claims 1-6 are completed.

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