A method for fabricating a GaN die

Abstract

This invention provides a method for fabricating GaN dies, comprising: performing a front-side process on a GaN wafer to obtain multiple GaN dies; defining dicing channels between adjacent GaN dies on the front side of the GaN wafer and removing the GaN epitaxial layer within the dicing channels; aligning the front side of the GaN wafer with a temporary bonding substrate and bonding it to the temporary bonding substrate; thinning the back side of the substrate to obtain a thin wafer; performing surface treatment on the back side of the thin wafer; etching back-side vias on the thin wafer; metallizing the back side of the thin wafer; separating the thin wafer from the temporary bonding substrate; performing laser stealth dicing along the dicing channels on the front side of the thin wafer; and splitting the GaN dies along the dicing channels. This invention achieves chip-free and debris-free stealth dicing and splitting of GaN dies, avoiding chipping and breakage caused by material property differences between the substrate and the heteroepitaxially grown GaN epitaxial layer during die cutting.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing, and in particular relates to a method for preparing a GaN die. Background Technology

[0002] In recent years, the engineering and commercialization of GaN epitaxial materials and devices on silicon carbide substrates and silicon substrates have accelerated. In order to meet the high power and high frequency requirements of radio frequency devices and to leverage the advantages of gallium nitride-based heterojunction materials in manufacturing high-frequency devices, in addition to continuously proposing new epitaxial structures and processes to improve the performance of devices in high-frequency modes, more and more technological development and research have begun to focus on improving wafer yield and reliability.

[0003] Currently, the process method commonly used for the back-side fabrication of SiC-based GaN RF devices is as follows: after completing the front-side process of the wafer, the front side of the wafer is temporarily bonded to the substrate. After bonding, the back side of the wafer is exposed. The back side of the wafer is then thinned, and after thinning, back-side vias, back-side metallization, chip dicing and other processing methods are performed.

[0004] However, the current processing methods may cause the following problems in wafer yield and reliability: 1) After back-side thinning and polishing, the wafer surface stress is high, which can easily lead to difficulty in controlling the etching uniformity of the wafer vias. In severe cases, the wafer may develop microcracks or break due to the introduction of stress; 2) The commonly used wafer dicing process is to attach the wafer to the dicing film, with the back side in contact with the dicing film and the dicing film located on the dicing ring; the wafer is diced along the dicing track on the front side, and then the thin wafer is split into diced pieces, so that the die is separated into individual pieces along the crack direction. During the wafer splitting process after the dicing step, due to the material characteristics difference between the substrate and the GaN epitaxial layer, such as the material characteristics difference between the SiC substrate and the GaN epitaxial layer, edge chipping is likely to occur, causing dicing loss of the die. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating GaN chips, which solves the problems of device yield loss caused by edge chipping due to material property differences between the substrate and the heteroepitaxially grown GaN epitaxial layer, as well as microcracks or fractures caused by stress due to back metallization in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for preparing a GaN die, comprising:

[0007] A substrate is provided, and heteroepitaxial growth is performed on the front side of the substrate to obtain a GaN wafer;

[0008] Perform a front-side process on the GaN wafer to obtain multiple GaN dies;

[0009] A dicing channel is defined on the front side of the GaN wafer between adjacent GaN dies, and the GaN epitaxial layer in the dicing channel is removed.

[0010] The GaN wafer is positioned so that its front side faces the temporary bonding substrate and is bonded to the temporary bonding substrate;

[0011] The back side of the substrate is thinned to obtain a thin wafer;

[0012] The back side of the thin wafer is subjected to surface treatment;

[0013] The thin wafer is subjected to back-side via etching;

[0014] The thin wafer is then back-side metallized;

[0015] Separate the thin wafer from the temporary bonding substrate;

[0016] Laser stealth cutting is performed on the front side of the thin wafer along the cutting path;

[0017] The GaN die is separated into fracties along the cutting path.

[0018] Optionally, the thin wafer is back-side metallized, including the following steps:

[0019] A metal seed layer is formed on the back side of the thin wafer;

[0020] A photoresist layer is formed on the back side of the thin wafer, and a preset trench area aligned with the dicing track is defined by a photolithography process. The preset trench area is covered by the exposed photoresist layer, and the area outside the preset trench area is exposed.

[0021] A first metal layer is formed on the back side of the thin wafer, and the first metal layer is formed at least in the area outside the preset trench region;

[0022] The photoresist layer covering the preset trench area is peeled off.

[0023] Optionally, a second metal layer is further provided on the GaN wafer, and the via is formed by etching from the back side of the wafer to the second metal layer using an etching process, for realizing the back side lead-out of the device unit in the wafer.

[0024] Optionally, the metal seed layer is a TiW layer or a stack of Ti and Au layers, wherein the thickness of the TiW layer or Ti layer ranges from 100 nm to 200 nm, and the thickness of the Au layer ranges from 400 nm to 600 nm.

[0025] Optionally, the surface treatment is dry etching, wet etching, or a combination of both processes.

[0026] Optionally, the first metal layer is formed by electroplating or vapor deposition, and the first metal layer includes an Au coating with a thickness ranging from 3 micrometers to 5 micrometers.

[0027] Optionally, the first metal layer covers the photoresist layer on the preset trench area; the photoresist layer covering the preset trench area is peeled off, and the first metal layer formed on the surface of the photoresist layer is removed to expose the preset trench, wherein the width of the preset trench is in the range of 20 micrometers to 50 micrometers.

[0028] Optionally, after back-side metallization of the thin wafer, a protective layer resistant to wet etching is formed on the back side of the thin wafer.

[0029] Optionally, the material used to form the protective layer is selected from either polyimide or poly(p-phenylenebenzodioxazole).

[0030] Optionally, a thermal separation process or a chemical immersion method is used to separate the thin wafer from the temporary bonding substrate, and the bonding surface of the thin wafer is wet-cleaned.

[0031] As described above, the present invention provides a method for fabricating GaN dies, which achieves the following beneficial effects in terms of wafer backplane process yield and wafer reliability:

[0032] 1) This invention achieves chip-free and debris-free cleaving of GaN dies. By providing a GaN die cleaving scheme that avoids chipping caused by material property differences between the substrate and the heteroepitaxially grown GaN epitaxial layer, it avoids chipping caused by material property differences between the substrate and the heteroepitaxially grown GaN epitaxial layer. In addition, the thin wafer is cut by laser stealth cleaving process, and the stress is released by extending to the back side of the thin wafer by the modified layer formed at different depths, ensuring that there is no chipping, debris and obvious tortuosity during the cleaving process.

[0033] 2) This invention introduces surface treatment after wafer thinning and polishing to release the residual stress caused by thinning and polishing;

[0034] 3) The back-side metallization of the thin wafer of the present invention utilizes a photoresist layer to define a preset trench area, which is aligned with the dicing track on the front side of the wafer. The preset trench area is covered by the photoresist layer to metallize the back side of the thin wafer, thereby shielding the trench area and preventing the possibility of forming a continuous thick metal layer on the back side. This avoids the problem of stress affecting device yield caused by full-surface metallization of the back side, effectively simplifies the back-side dicing process, saves manufacturing costs, and improves device yield.

[0035] 4) Furthermore, the present invention forms a protective layer on the back side of the thin wafer to reduce stress unevenness caused by subsequent processes and avoid microcracks or fractures caused by stress. Attached Figure Description

[0036] Figures 1 to 7 The diagram shows the structural schematics of each step in the fabrication method of the GaN die according to an embodiment of the present invention.

[0037] Component designation explanation

[0038] 100 substrate

[0039] 102 Thin-film wafer

[0040] 110 GaN epitaxial layer

[0041] 112 Cutting Track

[0042] 120 through hole

[0043] 130 Metal Seed Layer

[0044] 140, 140a photoresist layers

[0045] 150 Electroplated or vapor-deposited metal layer

[0046] 152 Pre-set groove

[0047] 200 Temporary Bonding Substrate Detailed Implementation

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0050] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0051] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0052] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] To address the issues of edge chipping caused by material property differences between the substrate and the heteroepitaxially grown GaN epitaxial layer, as well as microcracks or fractures caused by stress from back-side metallization in existing technologies, this invention utilizes a photoresist layer to cover a predetermined trench area before metallizing the wafer. By defining and shielding the predetermined trench area aligned with the dicing ridges on the back side of the wafer using the photoresist layer, the possibility of forming a metal layer on the entire back side is blocked, avoiding the stress caused by full-surface back-side metallization and the resulting impact on device yield. Simultaneously, the back-side process is simplified. This invention achieves chip splitting without edge chipping or die dicing loss by cutting and splitting the GaN die after back-side metallization of the thin wafer, avoiding edge chipping caused by material property differences between the substrate and the heteroepitaxially grown GaN epitaxial layer and the resulting reduction in wafer reliability.

[0054] like Figures 1 to 7 As shown, this embodiment provides a method for fabricating a GaN die, including the following steps:

[0055] like Figure 1As shown, step 1) is performed first, a substrate 100 is provided, and heteroepitaxial growth is performed on the front side of the substrate 100 to obtain a GaN wafer.

[0056] As an example, the substrate material includes any one of sapphire, SiC, and Si.

[0057] See also Figure 1 Step 2) involves performing a front-side process on the GaN wafer to obtain a plurality of GaN dies, wherein the GaN dies are formed based on a GaN epitaxial layer 110 heteroepitaxially grown on the substrate 100.

[0058] As an example, the front side of the substrate 100 has GaN-based die-based device units formed by a front-side process, such as GaN-based optoelectronic devices, GaN-based high-mobility power devices, GaN-based diodes, etc. In this embodiment, the substrate is a SiC-based substrate, and the front side of the SiC-based substrate can have GaN-based RF device units formed.

[0059] Next, in step 3), a dicing channel 112 is defined on the front side of the GaN wafer between adjacent GaN dies, and the GaN epitaxial layer in the dicing channel is removed.

[0060] As an example, a dicing channel 112 is defined on the surface of the GaN wafer using photolithography between adjacent GaN dies. The GaN epitaxial layer within the dicing channel 112 is removed using dry etching, wet etching, or a combination of both processes. Because a step to remove the GaN epitaxial layer within the dicing channel is introduced in the wafer front-side process, the subsequent wafer dicing process is essentially an epitaxial layer-free dicing, avoiding edge chipping caused by material property differences between the substrate (e.g., SiC-based substrate) and the GaN epitaxial layer.

[0061] like Figure 2 As shown, step 4) is then performed, bonding the GaN wafer to the temporary bonding substrate 200. Specifically, step 4) includes: coating the front side of the GaN wafer with bonding adhesive or bonding wax, so that the GaN wafer faces the temporary bonding substrate 200 and is bonded to the temporary bonding substrate 200, so that the two form a bonding sheet.

[0062] See also Figure 2 Step 5) is performed, using the bonding sheet obtained in step 4) to thin the back side of the substrate 100 to obtain a thin wafer 102.

[0063] As an example, step 5) further includes: polishing the thinned substrate to obtain a thin wafer 102 bonded to a temporary bonding substrate 200, wherein the thickness of the thin wafer 102 is 50 micrometers to 100 micrometers. In this embodiment, the thickness of the thin wafer 102 can be 75 micrometers.

[0064] Next, step 6) is performed to surface treat the back side of the thin wafer 102. Specifically, after the thinning and polishing processes, the back side of the thin wafer 102 is surface treated to release the residual stress on the substrate surface caused by the thinning and polishing processes. In this embodiment, the surface treatment is dry etching, wet etching, or a combination of both processes.

[0065] Next, step 7) is performed to etch through-holes in the thin wafer 102.

[0066] Specifically, an etching process is used to form a via 120 extending from the back side of the thin wafer 102 to the second metal layer, for the back side lead-out of the device units in the thin wafer 102. That is, the via 120 is formed to extend from the back side of the thin wafer to the front side of the second metal layer (not shown), which is formed on the surface of the GaN wafer during the front side process of the GaN wafer.

[0067] like Figures 3-5 and Figures 6A-6B As shown, step 8) is then performed to metallize the back side of the thin wafer 102, which includes at least the following steps: 8-1) forming a metal seed layer 130 on the back side of the thin wafer 102; 8-2) forming a photoresist layer 140 on the back side of the thin wafer 102, and defining a preset trench area aligned with the dicing channel 112 by photolithography; 8-3) forming a first metal layer 150 on the back side of the thin wafer 102.

[0068] As an example, step 8) further includes: before forming the metal seed layer 130 on the back side of the thin wafer 102 in step 8-1), cleaning the thin wafer 102 and the via 120, wherein the cleaning can be wet cleaning, dry cleaning, or a combination of both. The cleaning can remove oxide layers or impurities, such as polymers, from the surface of the thin wafer and the via 120 to obtain a smooth surface on the thin wafer and a smooth inner wall on the via 120.

[0069] As an example, such as Figure 3As shown, in step 8-1), a continuous metal seed layer 130 is formed on the back side of the thin wafer 102 by a sputtering process. The metal seed layer 130 is formed on the back side of the thin wafer 102 and the inner wall of the via 120, forming a continuous metal film layer. The metal seed layer has an appropriate thickness to ensure the continuity of the metal seed layer around the back via, avoiding discontinuity of the metal seed layer from affecting subsequent electroplating, and will not affect the subsequent splitting effect. For example, the metal seed layer 130 may include a TiW layer or a stack of Ti and Au layers, the thickness of the TiW layer or Ti layer ranging from 100 nm to 200 nm, and the thickness of the Au layer ranging from 400 nm to 600 nm. In this embodiment, the thickness of the TiW layer is 150 nm, and the thickness of the Au layer is 500 nm.

[0070] like Figures 4-5 As shown, at step 8-2), a photoresist layer 140 is formed on the back side of the thin wafer 102, and a preset trench area aligned with the dicing channel 112 is defined by photolithography. The preset trench area is covered by the photoresist layer 140a, and the area outside the preset trench area is exposed.

[0071] As an example, a photoresist layer 140 can be formed on the back side of the thin wafer 102 by spin coating and the photoresist layer 140 can be baked. Then, the photoresist layer 140 can be exposed and developed by photolithography to define a preset trench region. The preset trench region is covered by the developed photoresist layer 140a and the area outside the preset trench region is exposed.

[0072] As an example, in step 8-3), a first metal layer 150 is formed on the back side of the thin wafer 102, and the first metal layer 150 is formed at least in the area outside the preset trench area.

[0073] As an example, the first metal layer 150 is formed by electroplating or vapor deposition, and the first metal layer 150 includes an Au coating with a thickness of 3 to 5 micrometers. In this embodiment, the thickness of the Au coating is 4 micrometers.

[0074] In one example, such as Figure 6AAs shown, the first metal layer is formed using an electroplating process. During the electroplating process, the preset trench area is covered by the photoresist layer 140a, preventing the formation of the first metal layer. This results in the first metal layer not forming a continuous metal plating layer, but rather being divided into multiple segments by the photoresist layer 140a. Since the metal plating layer is formed on the back side of the wafer after the preset trench area is defined by the photoresist layer 140a, stress caused by full-surface metallization of the back side of the wafer 102 is avoided, and the process is simplified.

[0075] In other examples, such as Figure 6B As shown, the first metal layer is formed by vapor deposition. During the vapor deposition process, the preset trench area is covered by the photoresist layer 140a, and the first metal layer is formed on the surface of the photoresist layer 140a. When the photoresist layer 140a is removed, the first metal layer located on the surface of the photoresist layer 140a is also removed at the same time.

[0076] See also Figure 6A Step 8) further includes: 8-4) peeling off the photoresist layer 140a covering the preset trench area to expose the preset trench 152. In this embodiment, the depth of the preset trench 152 is determined based on the thickness of the first metal layer 150, and the width of the preset trench 152 ranges from 20 micrometers to 50 micrometers.

[0077] As an example, in step 8-4), the photoresist layer 140a covering the preset trench area is removed using a wet stripping process. At this time, the thin wafer surface in the preset trench 152 is only covered by a thin metal seed layer 130, forming a back dicing channel.

[0078] Next, step 9) is performed to separate the thin wafer 102 from the temporary bonding substrate 200.

[0079] Specifically, before separating the wafer 102 from the temporary bonding substrate 200 in step 9), a protective layer (not shown) resistant to wet etching can be formed on the back side of the substrate. As an example, the protective layer can be formed by spin-coating the back side of the substrate and then curing it by baking, protecting the wafer surface from uneven stress in subsequent processes. The material used to form the protective layer can be an organic material resistant to the chemicals used in subsequent cleaning processes, such as polyimide (PI), poly(p-phenylenebenzodioxazole) (PBO), or similar organic materials, to withstand the erosion of chemicals including anhydrous ethanol and acetone in subsequent cleaning processes.

[0080] As an example, a thermal separation process or a chemical immersion method is used to separate the front side of the wafer 102 from the temporary bonding substrate 200, and the bonding surface of the wafer 102 is wet-cleaned to remove oxide layers or impurities on the surface of the wafer, such as residual bonding adhesive or bonding wax.

[0081] Finally, proceed to step 10), as follows: Figure 7 As shown, a cutting process is performed along the cutting channel 112, causing multiple GaN die particles to split and separate along the cutting channel 112.

[0082] As an example, a laser stealth dicing process is performed on the front side of the thin wafer 102, including: forming multiple modified layers in the substrate by focusing laser energy, for example, forming multiple modified layers (generally three modified layers) with unequal spacing in a SiC substrate, so that the stress released by the modified layers extends to the back side of the thin wafer. In this embodiment, step 10) can fix the thin wafer 102 on a dicing ring with a blue film, and perform a laser stealth dicing process on the front side of the thin wafer 102, resulting in die splitting without chipping, debris, or obvious meandering, further reducing die dicing loss. Since a protective layer is formed on the back side of the thin wafer 102 in the previous step 9), it can further mitigate microcracks or fractures that may occur during the wafer dicing process.

[0083] Furthermore, it should be noted that although this embodiment uses laser to form the modified layer and perform the stealth dicing process, the present invention does not exclude the use of methods other than laser to achieve the dicing process, such as plasma deep etching or deep etching followed by chemical etching. Step 10) may further include: after splitting the GaN die along the dicing path 112, using a film expansion process to obtain independent device units.

[0084] As described above, the method for preparing GaN dies provided by the present invention has the following beneficial effects:

[0085] The present invention relates to back-side metallization of thin wafers. A photoresist layer defines a pre-defined trench region, which is aligned with the dicing track on the front side of the wafer. The photoresist layer covers the pre-defined trench region, metallizing the back side of the wafer simultaneously with defining the back-side dicing track. This prevents the formation of a continuous thick metal layer on the back side, avoiding the stress-induced impact on device yield caused by full-surface back-side metallization. It effectively simplifies the back-side dicing process, saves manufacturing costs, and improves device yield. Furthermore, the present invention introduces a surface treatment step after wafer thinning and polishing to release residual stress caused by thinning and polishing, further improving the yield of the back-side process.

[0086] This invention achieves chip-free and debris-free cleaving of GaN dies after the back side metallization of thin wafers. It provides a GaN die fabrication scheme that avoids chipping caused by the material property differences between the GaN epitaxial layer and the SiC substrate by providing a chip-free and die-dicing loss-free cutting method. In addition, the thin wafer is cut by laser stealth dicing, and the stress is extended to the back side of the thin wafer by the modified layers formed at different depths to release stress, ensuring that there is no chipping, debris, or obvious bends during the cutting process, further improving the yield of the wafer back side process and the reliability of the wafer.

[0087] Therefore, this invention effectively overcomes several shortcomings of the prior art and has high industrial application value.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a GaN die, characterized in that, The preparation method includes: A substrate is provided, and heteroepitaxial growth is performed on the front side of the substrate to obtain a GaN wafer; Perform a front-side process on the GaN wafer to obtain multiple GaN dies; Define a dicing channel between adjacent GaN dies on the front side of the GaN wafer, and remove the GaN epitaxial layer within the dicing channel; The GaN wafer is positioned so that its front side faces the temporary bonding substrate and is bonded to the temporary bonding substrate; The back side of the substrate is thinned to obtain a thin wafer with a thickness of 50 micrometers to 100 micrometers; The back side of the thin wafer is subjected to surface treatment; The thin wafer is subjected to back-side via etching; The back-side metallization of the thin wafer includes: A metal seed layer is formed on the back side of the thin wafer; A photoresist layer is formed on the back side of the thin wafer, and a preset trench area aligned with the dicing track is defined by a photolithography process. The preset trench area is covered by the exposed photoresist layer, and the area outside the preset trench area is exposed. A first metal layer is formed covering the back side of the thin wafer and the predetermined trench area; The photoresist layer covering the preset trench area is stripped off, and the first metal layer formed on the surface of the photoresist layer is removed to expose the preset trench. A protective layer resistant to wet etching is formed on the back side of the thin wafer; wherein the material used to form the protective layer is selected from either polyimide or poly(p-phenylenebenzodioxazole); Separate the thin wafer from the temporary bonding substrate; Laser stealth cutting is performed on the front side of the thin wafer along the cutting path; The GaN die is split along the dicing path, thereby achieving dicing without an epitaxial layer.

2. The preparation method according to claim 1, characterized in that, The GaN wafer is further provided with a second metal layer. The via is formed by etching from the back side of the wafer to the second metal layer using an etching process, which is used to realize the back side lead-out of the device unit in the wafer.

3. The preparation method according to claim 1, characterized in that, The metal seed layer is a TiW layer or a stack of Ti and Au layers, wherein the thickness of the TiW layer or Ti layer ranges from 100 nm to 200 nm, and the thickness of the Au layer ranges from 400 nm to 600 nm.

4. The preparation method according to claim 1, characterized in that, The surface treatment is dry etching, wet etching, or a combination of both processes.

5. The preparation method according to claim 1, characterized in that: The first metal layer is formed by electroplating or vapor deposition, and the first metal layer includes an Au coating with a thickness ranging from 3 micrometers to 5 micrometers.

6. The preparation method according to claim 1, characterized in that: The width of the preset groove ranges from 20 micrometers to 50 micrometers.

7. The preparation method according to claim 1, characterized in that, The step of separating the thin wafer from the temporary bonding substrate is performed by a thermal separation process or a chemical immersion method, and the bonding surface of the thin wafer is wet-cleaned.

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