Semiconductor devices

Abstract

A semiconductor device having a plurality of semiconductor chips is provided that can simultaneously achieve a longer life and miniaturization of the device. Among the RC-IGBT chips (1 to 3), a pair of RC-IGBT chips having an adjacent relationship in the X direction are RC-IGBT chips (1) and (2) and RC-IGBT chips (2) and (3). The RC-IGBT chips (1) and (2) satisfy a first configuration condition in which they are separately configured in the Y direction in such a manner that the dotted areas (61) and the dotted areas (62) do not overlap each other, and a second configuration condition in which they are partially repeated in the Y direction in such a manner that a portion of the emitter electrode other than the dotted areas (61) and the dotted areas (62) is repeated. The RC-IGBT chips (2) and (3) also satisfy the above-mentioned first and second configuration conditions.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a plurality of semiconductor chips. Background Art

[0002] Conventionally, there is a semiconductor device having a plurality of semiconductor chips, such as a semiconductor module disclosed in Patent Document 1. In the semiconductor module disclosed in Patent Document 1, a semiconductor chip (hereinafter referred to as "RC-IGBT chip") in which a switching element and a freewheeling element are integrated into a single chip is arranged in a staggered manner, thereby achieving improved heat dissipation. The RC-IGBT chip uses an IGBT as a switching element and a diode as a freewheeling element.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2018-10982

[0004] In the conventional semiconductor module disclosed in Patent Document 1, since the RC-IGBT chips are arranged in a staggered pattern, the heat dissipation between the RC-IGBT chips is improved, and a longer life of the device can be expected.

[0005] On the other hand, in the conventional semiconductor module, since the distance between the chips becomes longer as the RC-IGBT chips are arranged in a staggered manner, there is a problem that the size of the semiconductor device increases. Summary of the invention

[0006] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device having a plurality of semiconductor chips that can achieve both a longer life and a smaller size of the device.

[0007] The semiconductor device according to the present invention comprises: a common circuit pattern; and a plurality of semiconductor chips arranged along a first direction on the common circuit pattern, each of the plurality of semiconductor chips having a switching element, a first main electrode of the switching element being provided on an upper surface of the plurality of semiconductor chips, and a second main electrode of the switching element being provided on a lower surface, a portion of the first main electrode being allocated to a wiring connection region, the semiconductor device further comprising a plurality of external wirings, each of the plurality of external wirings being electrically connected to the wiring connection region of a corresponding semiconductor chip among the plurality of semiconductor chips, a pair of semiconductor chips among the plurality of semiconductor chips that are adjacent to each other in the first direction satisfying a first configuration condition and a second configuration condition, the first configuration condition being that the pair of semiconductor chips are separately configured in a manner that the wiring connection regions of each other do not overlap in a second direction intersecting the first direction, and the second configuration condition being that the pair of semiconductor chips are partially configured in a manner that overlaps a portion of a region outside the wiring connection region in the second direction.

[0008] Effects of the Invention

[0009] The semiconductor device of the present invention satisfies the first arrangement condition, and therefore can increase the distance between wiring connection regions in a pair of semiconductor chips to suppress thermal interference between the pair of semiconductor chips.

[0010] As a result, the semiconductor device of the present invention can suppress the temperature rise inside the plurality of semiconductor chips, thereby achieving a longer life of the device.

[0011] Furthermore, the semiconductor device of the present invention satisfies the second arrangement condition, and therefore the formation area of ​​the plurality of semiconductor chips provided on the common circuit pattern can be suppressed to a necessary minimum, thereby achieving miniaturization of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a plan view schematically showing the structure of the semiconductor device according to the first embodiment.

[0013] Figure 2 It is a magnified representation Figure 1 Top view of the RC-IGBT chipset for the upper arm.

[0014] Figure 3 It means by Figure 1 The circuit diagram of the equivalent circuit implemented by 6 RC-IGBT chips is shown.

[0015] Figure 4 It is a plan view schematically showing the structure of a semiconductor device according to the second embodiment.

[0016] Figure 5 It is a top view schematically showing the structure of a semiconductor device according to a third embodiment.

[0017] Figure 6 It is a magnified representation Figure 5 A top view of the RC-IGBT chip and the surrounding wires.

[0018] Figure 7 It is a top view schematically showing the structure of a semiconductor device according to a fourth embodiment.

[0019] Figure 8 It is a top view schematically showing the structure of a modified example of embodiment 4.

[0020] Fig. 9 Yes means Figure 8 A cross-sectional view of the cross-sectional structure at the AA section.

[0021] Fig.10 This is an explanatory diagram schematically showing the structure of a semiconductor device according to a fifth embodiment.

[0022] Fig.11 It is an explanatory diagram schematically showing the structure of a comparative semiconductor device.

[0023] Fig.12 It is a top view schematically showing the structure of a semiconductor device according to a sixth embodiment.

[0024] Fig.13 It is a top view schematically showing the structure of a semiconductor device according to a seventh embodiment.

[0025] Fig.14 This is a plan view showing the connection of wires to three copper circuit patterns of the semiconductor device according to the seventh embodiment.

[0026] Fig.15 This is an explanatory diagram schematically showing the structure of a semiconductor device according to an eighth embodiment.

[0027] Fig.16 It is a top view schematically showing the structure of a semiconductor device according to a ninth embodiment. DETAILED DESCRIPTION

[0028] <Implementation Method 1>

[0029] Figure 1 It is a plan view schematically showing the structure of a semiconductor device 101 according to the first embodiment of the present invention. Figure 2 It is a magnified representation Figure 1 FIG. 1 is a top view of the RC-IGBT chipset 10 for the upper arm. Figure 3 It means by Figure 1 The circuit diagram of the equivalent circuit implemented by the six RC-IGBT chips 1 to 6 shown in FIG. Figure 1 and Figure 2 The XYZ orthogonal coordinate system is described respectively.

[0030] As shown in these figures, the semiconductor device 101 includes a resin insulating substrate 51 , RC-IGBT chips 1 to 6 , copper circuit patterns 40 to 43 and 48 , a P terminal 20 , a U terminal 21 , a V terminal 22 , a W terminal 23 , an N terminal 28 , and a case 50 as main components.

[0031] The resin insulating substrate 51 , the RC-IGBT chips 1 to 6 , and the copper circuit patterns 40 to 43 and 48 are accommodated in the case 50 , and the P terminal 20 , the U terminal 21 , the V terminal 22 , the W terminal 23 , and the N terminal 28 are provided outside the case 50 .

[0032] Each of the copper circuit patterns 40 to 43 and 48 functions as a single wiring board having conductivity as a whole, such as a metal electrode or a die pad.

[0033] In the housing 50, copper circuit patterns 40 to 43 and 48 are provided on a resin insulating substrate 51. The copper circuit patterns 40 to 43 and 48 are electrically independent from each other.

[0034] The RC-IGBT chips 1 to 3 are arranged along the first direction, i.e., the X direction, on the chip arrangement region of the copper circuit pattern 40. The copper circuit pattern 40 is a common circuit pattern for the RC-IGBT chips 1 to 3. The copper circuit pattern 40 has a chip arrangement region on the +Y side and an elongated relay region extending from the chip arrangement region in the -Y direction.

[0035] The RC-IGBT chip 4 is arranged on the chip arrangement region of the copper circuit pattern 41 , the RC-IGBT chip 5 is arranged on the chip arrangement region of the copper circuit pattern 42 , and the RC-IGBT chip 6 is arranged on the chip arrangement region of the copper circuit pattern 43 .

[0036] Each of the copper circuit patterns 41 to 43 includes a chip placement region on the +Y side and a relay region that bends from an end portion on the -Y side of the chip placement region in the -X direction and then further extends in the -Y direction.

[0037] The copper circuit pattern 48 is provided so as to extend in the X direction on the −Y side of the relay region of the copper circuit pattern 43 .

[0038] The RC-IGBT chips 1 to 3 arranged on the same copper circuit pattern 40 constitute an upper arm RC-IGBT chip group 10 .

[0039] like Figure 3 As shown, each RC-IGBT chip i (i=any one of 1 to 6) has a combination of an N-channel IGBT 1i, which is a switching element, and a diode D1i, which is a freewheeling element. Specifically, the collector of IGBT 1i is connected to the cathode of diode D1i, and the emitter of IGBT 1i is connected to the anode of diode D1i. For example, in RC-IGBT chip 1, the collector of IGBT 11 is connected to the cathode of diode D11, and the emitter of IGBT 11 is connected to the anode of diode D11.

[0040] like Figure 3 As shown, RC-IGBT chips 1, 2, and 3 are used for upper bridge arms UP, VP, and WP of a three-phase AC inverter, and RC-IGBT chips 4, 5, and 6 are used for lower bridge arms UN, VN, and WN of the three-phase AC inverter.

[0041] exist Figure 1 and Figure 2 In the embodiment, most of the upper surface of the RC-IGBT chips 1 to 6 except for the signal pads 31 to 36 becomes the first main electrode, that is, the emitter electrode. Figure 2As shown, most of the regions on the upper surfaces of the RC-IGBT chips 1 to 3 excluding the signal pads 31 to 33 serve as emitter electrodes E1 to E3 .

[0042] The lower surfaces of the RC-IGBT chips 1 to 6 serve as collector electrodes, which are second main electrodes. The emitter electrode also serves as an anode electrode of the diode D1i, and the collector electrode also serves as a cathode electrode of the diode D1i.

[0043] That is, each of the RC-IGBT chips 1 to 6 includes an IGBT 1i as a switching element, an emitter electrode serving as a first main electrode of the IGBT 1i is provided on the upper surface, and a collector electrode serving as a second main electrode of the IGBT 1i is provided on the lower surface.

[0044] Therefore, the collector electrodes of the RC-IGBT chips 1 to 3 are electrically connected in common to the copper circuit pattern 40, the collector electrode of the RC-IGBT chip 4 is electrically connected to the copper circuit pattern 41, the collector electrode of the RC-IGBT chip 5 is electrically connected to the copper circuit pattern 42, and the collector electrode of the RC-IGBT chip 6 is electrically connected to the copper circuit pattern 43. As described above, the copper circuit patterns 40 to 43 and 48 each function as a single wiring board.

[0045] Furthermore, a portion of the emitter electrode of each of the RC-IGBT chips 1 to 6 is allocated to a wiring connection region, i.e., a bonding point region 6i (i=any one of 1 to 6). For example, a portion of the emitter electrode E1 of the RC-IGBT chip 1 is allocated to the bonding point region 61. Figure 1 and Figure 2 In FIG. 1 , the region including four black circles along the X direction is a dotted region. A conductor 7 serving as a relay conductor for external wiring is connected to each dotted region.

[0046] The dotted area at the end of the -Y side of the copper circuit pattern 40 is electrically connected to the dotted area of ​​the P terminal 20 via four wires 7. That is, one end of each of the four wires 7 is bonded to the dotted area of ​​the copper circuit pattern 40, and the other end of each of the four wires 7 is bonded to the dotted area of ​​the P terminal 20.

[0047] As described above, including the case where the dotted areas are electrically connected via four wires 7, for convenience of description, it is simply described as “the dotted area of ​​X and the dotted area of ​​Y are electrically connected via wires 7.” In addition, X and Y refer to connection target components such as copper circuit pattern 40 and U terminal 21, respectively.

[0048] like Figure 1 and Figure 2As shown in FIG. 1 , each of the RC-IGBT chips 1 to 6 is in a rectangular shape consisting of the first to fourth sides when viewed from above. Figure 2 As shown in the RC-IGBT chip 1, there are sides S1 to S4 as the first to fourth sides. That is, the first side is side S1, the second side is side S2, the third side is side S3, and the fourth side is side S4.

[0049] The dotted region 61 of the RC-IGBT chip 1 is provided along the X direction on the side of the side S1 among the sides S1 to S4 , the sides S2 and S3 are adjacent to the side S1 , and the side S4 is opposite to the side S1 .

[0050] The dotted regions 62 to 66 of the RC-IGBT chips 2 to 6 are also provided along the X direction on the side of the side S1 similarly to the RC-IGBT chip 1 .

[0051] like Figure 1 As shown, the dotted area 61 of the RC-IGBT chip 1 is electrically connected to the dotted area on the +Y side of the copper circuit pattern 41 via the wire 7 , and the dotted area on the −Y side of the copper circuit pattern 41 is electrically connected to the dotted area 81 of the U terminal 21 via the wire 7 .

[0052] Therefore, the +Y side wire 7 provided between the dotted area 61 of the RC-IGBT chip 1 and the dotted area 81 of the U terminal 21 , the relay area of ​​the copper circuit pattern 41 , and the -Y side wire 7 function as the first external wiring that electrically connects the emitter electrode of the RC-IGBT chip 1 and the U terminal 21 .

[0053] The dotted region 62 of the RC-IGBT chip 2 is electrically connected to the dotted region on the +Y side of the copper circuit pattern 42 via the wire 7 , and the dotted region on the −Y side of the copper circuit pattern 42 is electrically connected to the dotted region 82 of the V terminal 22 via the wire 7 .

[0054] Therefore, the +Y side wire 7 provided between the dotted area 62 of the RC-IGBT chip 2 and the dotted area 82 of the V terminal 22 , the relay area of ​​the copper circuit pattern 42 , and the −Y side wire 7 function as the second external wiring that electrically connects the emitter electrode of the RC-IGBT chip 2 and the V terminal 22 .

[0055] The dotted region 63 of the RC-IGBT chip 3 is electrically connected to the dotted region on the +Y side of the copper circuit pattern 43 via the wire 7 , and the dotted region on the −Y side of the copper circuit pattern 43 is electrically connected to the dotted region 83 of the W terminal 23 via the wire 7 .

[0056] Therefore, the +Y side wire 7 provided between the dotted area 63 of the RC-IGBT chip 3 and the dotted area 83 of the W terminal 23 , the relay area of ​​the copper circuit pattern 43 , and the −Y side wire 7 function as the third external wiring that electrically connects the emitter electrode of the RC-IGBT chip 3 and the W terminal 23 .

[0057] The first to third external wirings are formed to extend in the -Y direction from the dotted regions 61 to 63 of the RC-IGBT chips 1 to 3. Thus, the first to third external wirings are electrically connected to the dotted regions of the corresponding chips among the RC-IGBT chips 1 to 3.

[0058] The dotted area 64 of the RC-IGBT chip 4 is electrically connected to the dotted area on the +Y side and the -X side of the copper circuit pattern 48 via the wire 7. Furthermore, the dotted area 65 of the RC-IGBT chip 5 is electrically connected to the dotted area on the +Y side and the center of the copper circuit pattern 48 via the wire 7, and the dotted area 66 of the RC-IGBT chip 6 is electrically connected to the dotted area on the +Y side and the +X side of the copper circuit pattern 48 via the wire 7.

[0059] Furthermore, the dotted region on the −Y side of the copper circuit pattern 48 and the dotted region of the N terminal 28 are electrically connected via the wire 7 .

[0060] As described above, by electrically connecting the RC-IGBT chips 1 to 6 and the external terminals 20 to 23 and 28, it is possible to realize Figure 3 The circuit structure of a three-phase AC inverter is shown in the equivalent circuit of FIG.

[0061] like Figure 2 As shown, the semiconductor device 101 according to the first embodiment includes RC-IGBT chips 1 to 3 as a plurality of semiconductor chips arranged in the X direction on a copper circuit pattern 40 .

[0062] Furthermore, among the RC-IGBT chips 1 to 3 , a pair of semiconductor chips that are adjacent to each other in the first direction, ie, the X direction, satisfy the first and second arrangement conditions described below.

[0063] Furthermore, among the RC-IGBT chips 1 to 3, a pair of RC-IGBT chips adjacent to each other in the X direction are RC-IGBT chips 1 and 2 and RC-IGBT chips 2 and 3. The RC-IGBT chips 1 to 3 have dotted regions 61 to 63 as wiring connection regions.

[0064] RC-IGBT chips 1 and 2 are separated and arranged in the Y direction, which is the second direction perpendicular to the X direction, so that dotted regions 61 and dotted regions 62 do not overlap each other. That is, dotted regions 61 and dotted regions 62 have different coordinate positions in the Y direction and do not overlap each other. Similarly, between RC-IGBT chips 2 and 3, dotted regions 62 and dotted regions 63 are separated and arranged in the Y direction so as not to overlap each other.

[0065] Therefore, the semiconductor device 101 according to the first embodiment satisfies the following first arrangement condition.

[0066] First arrangement condition: A pair of semiconductor chips that are adjacent to each other in the X direction among the plurality of semiconductor chips are arranged to be separated in the Y direction so that their wiring connection regions do not overlap.

[0067] RC-IGBT chips 1 and 2 are partially overlapped in the Y direction so that a portion of the emitter electrodes other than dotted regions 61 and dotted regions 62 are overlapped. That is, there are regions where the coordinate positions in the Y direction overlap with respect to a portion of the emitter electrodes other than dotted regions 61 and dotted regions 62. Similarly, RC-IGBT chips 2 and 3 are partially overlapped in the Y direction so that a portion of the emitter electrodes other than dotted regions 62 and dotted regions 63 are overlapped.

[0068] Therefore, the semiconductor device 101 according to the first embodiment satisfies the following second arrangement condition.

[0069] Second arrangement condition: A pair of semiconductor chips that are adjacent to each other in the X direction among the plurality of semiconductor chips are arranged to overlap each other in the Y direction so that a portion of the region other than the wiring connection region overlaps each other.

[0070] Furthermore, with respect to the pair of semiconductor chips, from the viewpoint of reducing the formation area, it is preferable that the overlap degree of the emitter electrodes in the Y direction is equal to or greater than half.

[0071] In the semiconductor device 101 of the first embodiment, the plurality of semiconductor chips, namely the RC-IGBT chips 1 to 3, satisfy the first arrangement condition. Therefore, the distance between the dotted regions 61 and 62 of the RC-IGBT chips 1 and 2 can be set long to suppress thermal interference between the RC-IGBT chips 1 and 2. Similarly, the distance between the dotted regions 62 and 63 of the RC-IGBT chips 2 and 3 can be set long to suppress thermal interference between the RC-IGBT chips 2 and 3.

[0072] That is, since the semiconductor device 101 of the first embodiment satisfies the first arrangement condition, the distance between the wiring connection regions in the pair of semiconductor chips can be set long to suppress thermal interference between the pair of semiconductor chips.

[0073] RC-IGBT chips 1 to 3 generate heat from dotted areas 61 to 63 and their surroundings bonded to wire 7. Considering this, the distance between dotted areas 61 and 62 of a pair of RC-IGBT chips 1 and 2 adjacent in the X direction and the distance between dotted areas 62 and 63 of RC-IGBT chips 2 and 3 are set long.

[0074] As a result, the semiconductor device 101 of the first embodiment can suppress the temperature rise inside the plurality of semiconductor chips, ie, the RC-IGBT chips 1 to 3 , by suppressing the thermal interference between a pair of RC-IGBT chips adjacent in the X direction, thereby achieving a longer life of the device.

[0075] Furthermore, in the semiconductor device 101 of the first embodiment, the plurality of semiconductor chips, namely the RC-IGBT chips 1 to 3, satisfy the second arrangement condition. Therefore, the semiconductor device 101 can reduce the formation area of ​​the RC-IGBT chips 1 to 3 provided on the common circuit pattern, namely the copper circuit pattern 40, thereby achieving miniaturization of the device.

[0076] In addition, the RC-IGBT chips 1 and 3 that are not adjacent to each other in the X direction are repeatedly arranged so that the entirety including the dotted areas 61 and 63 in the Y direction overlap with each other, thereby suppressing the formation area of ​​the RC-IGBT chips 1 to 3 to the minimum required. Figure 1 and Figure 2 In the example shown, the positions of the side S1 in the Y direction are aligned between the RC-IGBT chips 1 and 3 .

[0077] As described above, the semiconductor device 101 according to the first embodiment can achieve both a longer life and smaller size of the device.

[0078] That is, the semiconductor device 101 including the RC-IGBT chips 1 to 3 used in the upper arm of the inverter can achieve miniaturization and a longer life of the device, wherein the RC-IGBT chips 1 to 3 each include a combination of an IGBT and a diode.

[0079] <Implementation Method 2>

[0080] Figure 4 FIG. 1 is a top view schematically showing the structure of a semiconductor device 102 according to Embodiment 2 of the present invention. Figure 4 The XYZ orthogonal coordinate system is recorded in.

[0081] Next, Figure 1 to Figure 3 The same structures as the semiconductor device 101 of the first embodiment are denoted by the same reference numerals and the description thereof is appropriately omitted. The description will focus on the characteristic parts of the semiconductor device 102 of the second embodiment. The semiconductor device 102 also implements the same Figure 3 The equivalent circuit is shown.

[0082] like Figure 4 As shown, in the semiconductor device 102 of the second embodiment, similarly to the first embodiment, dotted regions 61 to 66 serving as wiring connection regions are provided along the X direction on the first side of the -Y side of the RC-IGBT chips 1 to 6 .

[0083] The dotted region 61 of the RC-IGBT chip 1 is electrically connected to the dotted region on the +Y side of the copper circuit pattern 41 via the wire 7 , and the dotted region on the −Y side of the copper circuit pattern 41 is electrically connected to the dotted region 81 of the U terminal 21 via the wire 7 .

[0084] Therefore, the electrically connected portion including the +Y side wire 7 provided between the dotted area 61 of the RC-IGBT chip 1 and the dotted area 81 of the U terminal 21, the relay area of ​​the copper circuit pattern 41, and the -Y side wire 7 becomes the external wiring L1. The external wiring L1 functions as the first external wiring that electrically connects the emitter electrode of the RC-IGBT chip 1 and the U terminal 21.

[0085] The dotted region 62 of the RC-IGBT chip 2 is electrically connected to the dotted region on the +Y side of the copper circuit pattern 42 via the wire 7 , and the dotted region on the −Y side of the copper circuit pattern 42 is electrically connected to the dotted region 82 of the V terminal 22 via the wire 7 .

[0086] Therefore, the electrically connected portion including the +Y-side wire 7 provided between the dotted area 62 of the RC-IGBT chip 2 and the dotted area 82 of the V terminal 22, the relay area of ​​the copper circuit pattern 42, and the -Y-side wire 7 becomes the external wiring L2. The external wiring L2 functions as a second external wiring that electrically connects the emitter electrode of the RC-IGBT chip 2 and the V terminal 22.

[0087] The dotted region 63 of the RC-IGBT chip 3 is electrically connected to the dotted region on the +Y side of the copper circuit pattern 43 via the wire 7 , and the dotted region on the −Y side of the copper circuit pattern 43 is electrically connected to the dotted region 83 of the W terminal 23 via the wire 7 .

[0088] Therefore, the electrically connected portion including the +Y side wire 7 provided between the dotted area 63 of the RC-IGBT chip 3 and the dotted area 83 of the W terminal 23, the relay area of ​​the copper circuit pattern 43, and the -Y side wire 7 becomes the external wiring L3. The external wiring L3 functions as a third external wiring that electrically connects the emitter electrode of the RC-IGBT chip 3 and the W terminal 23.

[0089] The plurality of semiconductor chips, namely, RC-IGBT chips 1 to 3, are classified into a first number of two RC-IGBT chips 1 and 3 and a second number of one RC-IGBT chip 2. RC-IGBT chips 1 and 3 are classified as first type semiconductor chips, and RC-IGBT chip 2 is classified as second type semiconductor chip.

[0090] Therefore, the first quantity of the first type of semiconductor chips, namely, RC-IGBT chips 1 and 3, and the second quantity of the second type of semiconductor chips, namely, RC-IGBT chip 2, are alternately arranged along the first direction, namely, the X direction, and the first quantity is "2" and the second quantity is "1", having the quantity characteristic of "the first quantity is greater than or equal to the second quantity".

[0091] Furthermore, the two U terminals 21 and the W terminal 23 for the RC-IGBT chips 1 and 3 are classified as the first type of external terminals, and the one V terminal 22 for the RC-IGBT chip 2 is classified as the second type of external terminal.

[0092] Therefore, the external wirings L1 and L3 electrically connecting the dotted areas 61 and 63 of the RC-IGBT chips 1 and 3 with the dotted areas 81 and 83 of the U terminal 21 and the W terminal 23 are classified as two first-type external wirings. Furthermore, the external wiring L2 electrically connecting the dotted area 62 of the RC-IGBT chip 2 with the dotted area 82 of the V terminal 22 is classified as the second number of second-type external wirings.

[0093] Thus, in the second embodiment, the plurality of external wirings, i.e., the external wirings L1 to L3, include two external wirings L1 and L3 and one external wiring L2. The external wirings L1 and L3 are first-type external wirings for the RC-IGBT chips 1 and 3 classified as the first-type semiconductor chips, and the external wiring L2 is an external wiring for the RC-IGBT chip 2 classified as the second-type semiconductor chip.

[0094] Furthermore, the semiconductor device 102 according to the second embodiment is characterized in that the wiring lengths of the two external wirings L1 and L3 are both set shorter than the wiring length of the single external wiring L2.

[0095] That is, the semiconductor device 102 according to the second embodiment satisfies the wiring length condition that the wiring length of the first number of first-type external wirings is shorter than the wiring length of the second number of second external wirings.

[0096] The semiconductor device 102 of the second embodiment satisfies the wiring length condition, that is, the wiring lengths of the external wirings L1 to L3 are set so that the wiring lengths of the two external wirings L1 and L3 are shorter than the wiring length of the one external wiring L2. Moreover, regarding the first number "2" and the second number "1", there is a quantity characteristic that "the first number is greater than or equal to the second number".

[0097] Therefore, for the semiconductor device 102, by making the wiring length of at least two external wirings L1 and L3, which are greater than or equal to half of the external wirings L1 to L3, shorter than the wiring length of one external wiring L2, the wiring impedance of the external wirings L1 and L3 of the two RC-IGBT chips 1 and 3 can be relatively reduced compared to the wiring impedance of one external wiring L2.

[0098] As a result, the semiconductor device 102 according to the second embodiment can suppress the temperature rise of the two external wirings L1 and L3 electrically connected to the two RC-IGBT chips 1 and 3 , thereby extending the life of the device.

[0099] In addition, the semiconductor device 102 of the second embodiment can be expanded so that the above wiring length condition is satisfied even for 4 or more semiconductor chips. However, when the number of semiconductor chips is an even number, the first number is equal to the second number. Therefore, in the expanded structure of the semiconductor device 102, when the number of semiconductor chips is an even number, the wiring impedance of the first type of external wiring, which is half of the first number of the plurality of external wirings, is relatively reduced.

[0100] <Implementation Method 3>

[0101] Figure 5 It is a plan view schematically showing the structure of a semiconductor device 103 according to Embodiment 3 of the present invention. Figure 6 is the magnified representation and Figure 5 FIG. 1 is a plan view of the RC-IGBT chips 1 to 3 and the periphery of three wires 7 bonded to dotted regions 61 to 63 . Figure 5 and Figure 6 The XYZ orthogonal coordinate system is described respectively.

[0102] Hereinafter, the same reference numerals are used for the same structures as those of the semiconductor device 101 of the first embodiment, and the description thereof will be omitted as appropriate. The description will be centered on the characteristic parts of the semiconductor device 103 of the third embodiment. Figure 3 The equivalent circuit is shown.

[0103] like Figure 5 and Figure 6As shown, in the semiconductor device 103 of the third embodiment, similarly to the first embodiment, dotted regions 61 to 66 serving as wiring connection regions are provided along the X direction on the first side of the -Y side of the RC-IGBT chips 1 to 6 .

[0104] The copper circuit patterns 41 to 43 that serve as a plurality of relay terminals function as a portion of a plurality of external wirings that electrically connect the RC-IGBT chips 1 to 3 to the U terminal 21, the V terminal 22, and the W terminal 23. The copper circuit patterns 41 to 43 are electrically independent of each other. That is, there is no electrical connection between the copper circuit patterns 41 to 43.

[0105] The dotted area 61 of the RC-IGBT chip 1 is electrically connected to the dotted area on the +Y side of the copper circuit pattern 41 via the wire 7, and the dotted area on the -Y side of the copper circuit pattern 41 is electrically connected to the dotted area 81 of the U terminal 21 via the wire 7. The formation position of the dotted area on the +Y side of the copper circuit pattern 41 is changed to the -Y side compared with the first embodiment.

[0106] Therefore, the electrically connected portion including the +Y side wire 7 provided between the dotted area 61 of the RC-IGBT chip 1 and the dotted area 81 of the U terminal 21, the relay area of ​​the copper circuit pattern 41, and the -Y side wire 7 becomes the first external wiring. Figure 4 The external wiring L1 of the second embodiment shown in FIG. Figure 6 As shown, the wire 7 ( 1 ) electrically connecting the dotted area 61 of the RC-IGBT chip 1 and the dotted area of ​​the copper circuit pattern 41 functions as a first relay wire. The wire 7 ( 1 ) forms a part of the first external wiring.

[0107] The dotted region 62 of the RC-IGBT chip 2 is electrically connected to the dotted region on the +Y side of the copper circuit pattern 42 via the wire 7 , and the dotted region on the −Y side of the copper circuit pattern 42 is electrically connected to the dotted region 82 of the V terminal 22 via the wire 7 .

[0108] Therefore, the electrically connected portion including the +Y side wire 7 provided between the dotted area 62 of the RC-IGBT chip 2 and the dotted area 82 of the V terminal 22, the relay area of ​​the copper circuit pattern 42, and the -Y side wire 7 becomes the second external wiring. Figure 4 The external wiring L2 shown is equivalent. Figure 6 As shown, the wire 7 ( 2 ) electrically connecting the dotted area 62 of the RC-IGBT chip 2 and the dotted area of ​​the copper circuit pattern 42 functions as a second relay wire. The wire 7 ( 2 ) forms a part of the second external wiring.

[0109] The dotted region 63 of the RC-IGBT chip 3 is electrically connected to the dotted region on the +Y side of the copper circuit pattern 43 via the wire 7 , and the dotted region on the −Y side of the copper circuit pattern 43 is electrically connected to the dotted region 83 of the W terminal 23 via the wire 7 .

[0110] Therefore, the electrically connected portion including the +Y side wire 7 provided between the dotted area 63 of the RC-IGBT chip 3 and the dotted area 83 of the W terminal 23, the relay area of ​​the copper circuit pattern 43, and the -Y side wire 7 becomes the third external wiring. Figure 4 The external wiring L3 shown is equivalent. Figure 6 As shown, the wire 7 (3) electrically connecting the dotted area 63 of the RC-IGBT chip 3 and the dotted area of ​​the copper circuit pattern 43 functions as a third relay wire. The wire 7 (3) forms a part of the third external wiring.

[0111] Thus, the first to third external wirings include relay terminals, copper circuit patterns 41 to 43, and relay conductors 7 ( 1 ) to 7 ( 3 ). The copper circuit patterns 41 to 43 are provided corresponding to the RC-IGBT chips 1 to 3 , which are semiconductor chips.

[0112] like Figure 6 As shown, the semiconductor device 103 of the third embodiment has the following characteristics: the wiring lengths d1 to d3 of the plurality of relay wires, namely the wires 7 ( 1 ) to 7 ( 3 ), are the same, that is, set to “ d1 = d2 = d3 ”.

[0113] Since the semiconductor device 103 of the third embodiment sets the wiring lengths d1 to d3 of the wires 7 ( 1 ) to 7 ( 3 ) connecting the RC-IGBT chips 1 to 3 and the copper circuit patterns 41 to 43 to be the same, the wiring impedance can be made consistent between the wires 7 ( 1 ) to 7 ( 3 ) of the copper circuit patterns 41 to 43.

[0114] As a result, the semiconductor device 103 according to the third embodiment can balance the currents among the RC-IGBT chips 1 to 3 , thereby improving the convenience of the device.

[0115] The same wiring lengths d1 to d3 of the conductors 7(1) to 7(3) mean that the wiring impedances of the conductors 7(1) to 7(3) are the same to the extent that there is no substantial difference in wiring impedances. In addition, the number of conductors 7 is preferably the same among the conductors 7(1) to 7(3).

[0116] When the current balance between the RC-IGBT chips 1 to 3 is not achieved and there is a local weak portion, it is necessary to adjust the driving capability on the driving circuit side of the semiconductor device.

[0117] On the other hand, since the semiconductor device 103 of the third embodiment achieves current balance among the RC-IGBT chips 1 to 3 , it is expected that the convenience will be improved in that the drive circuit of the semiconductor device 103 does not need to adjust the drive capability.

[0118] <Implementation Method 4>

[0119] (Basic structure)

[0120] Figure 7 FIG. 1 is a top view schematically showing a basic structure of a semiconductor device 104 according to Embodiment 4 of the present invention. Figure 7 The XYZ orthogonal coordinate system is recorded in.

[0121] Hereinafter, the same reference numerals are used for the same structures as those of the semiconductor device 101 of the first embodiment, and the description thereof will be omitted as appropriate. The description will be centered on the characteristic parts of the semiconductor device 104 of the fourth embodiment. Figure 3 The equivalent circuit is shown.

[0122] like Figure 7 As shown, the semiconductor device 104 as a basic example of the fourth embodiment has signal pads 31 to 33 functioning as control electrodes provided on the fourth side on the +Y side of the RC-IGBT chips 1 to 3 .

[0123] By bonding the tips of the signal wirings W1 to W3 to the signal pads 31 to 33, the signal wirings W1 to W3 are electrically connected to the signal pads 31 to 33. Therefore, the signal wirings W1 to W3 function as a plurality of control wirings, and the signal pads 31 to 33 function as control electrodes of the IGBTs 11 to 13.

[0124] like Figure 7 As shown in FIG. 1 , the signal wirings W1 to W3 are provided so as to extend in the +Y direction from the signal pads 31 to 33. That is, the direction of the control wiring formed by the signal wirings W1 to W3 is set in the +Y direction.

[0125] On the other hand, similarly to the first to third embodiments, in the semiconductor device 104 of the fourth embodiment, the first to third external wirings, which are a plurality of external wirings, are also formed to extend toward the -Y direction from the dotted regions 61 to 63 of the plurality of semiconductor chips, i.e., the RC-IGBT chips 1 to 3. That is, the direction of the external wirings formed by the first to third external wirings is set to the -Y direction.

[0126] In the semiconductor device 104 of the fourth embodiment, the control wiring direction of the signal wirings W1 to W3 is the +Y direction, and the external wiring direction of the first to third external wirings is the -Y direction. Therefore, the control wiring direction of the signal wirings W1 to W3 and the external wiring direction of the first to third external wirings are set to be separated from each other in opposite directions.

[0127] In the semiconductor device 104 of embodiment 4, since the control wiring direction of the signal wiring W1~W3 is set to the opposite direction of the external wiring direction of the multiple external wirings, the multiple external wirings can be set in a manner to suppress interference from the signal wiring W1~W3, and the setting freedom of the multiple external wirings can be increased.

[0128] As a result, the semiconductor device 104 of the fourth embodiment can increase the number of wires 7 used as relay wires for a plurality of external wirings, and accordingly can suppress wiring impedance and wiring inductance associated with the plurality of external wirings, thereby achieving a longer life of the device.

[0129] (Variation Example)

[0130] Figure 8 It is a plan view schematically showing the structure of a semiconductor device 104B which is a modification of the fourth embodiment of the present invention. Fig. 9 Yes means Figure 8 A cross-sectional view of the cross-sectional structure at the AA section. Figure 8 and Fig. 9 The XYZ orthogonal coordinate system is described respectively.

[0131] In the following, the same reference numerals are used for the same structures as the semiconductor device 101 of the first embodiment, and the description thereof is omitted as appropriate. The description will be centered on the characteristic parts of the semiconductor device 104B, which is a modification of the fourth embodiment. The semiconductor device 104B of the modification also implements the same Figure 3 The equivalent circuit is shown.

[0132] like Figure 8 As shown, similar to the basic example of the fourth embodiment, in the semiconductor device 104B of the modified example, signal pads 31 to 33 functioning as control electrodes are provided on the fourth side on the +Y side of the RC-IGBT chips 1 to 6 .

[0133] Moreover, if Figure 7 As shown in FIG. 1 , the signal wirings W1 to W3 are provided so as to extend in the +Y direction from the signal pads 31 to 33. That is, the direction of the control wiring formed by the signal wirings W1 to W3 is set in the +Y direction.

[0134] On the other hand, similarly to the first to third embodiments, in the semiconductor device 104B of the fourth embodiment, the first to third external wirings, which are a plurality of external wirings, are also formed to extend toward the -Y direction from the dotted regions 61 to 63 of the plurality of semiconductor chips, i.e., the RC-IGBT chips 1 to 3. That is, the direction of the external wirings formed by the first to third external wirings is set to the -Y direction.

[0135] In the semiconductor device 104B of the modification example, similarly to the semiconductor device 104 of the basic structure, the control wiring directions of the signal wirings W1 to W3 and the external wiring directions of the first to third external wirings are set in directions that are separated from each other and opposite to each other.

[0136] Therefore, the semiconductor device 104B, which is a modification example, can achieve an effect of extending the life of the device, similarly to the semiconductor device 104 .

[0137] Furthermore, the semiconductor device 104B has the following inherent characteristics.

[0138] The RC-IGBT chip 1 has a first separated wiring connection region, that is, a dotted region 611, and a second separated wiring connection region, that is, a dotted region 612 as wiring connection regions. The dotted regions 611 and 612 are provided to be separated from each other along the second direction, that is, the Y direction. Thus, the first and second separated wiring connection regions become part of the wiring connection region.

[0139] like Fig. 9 As shown, the end of the wire 7(1) serving as a relay wire for the RC-IGBT chip 1 is bonded to the dotted area 611, and the middle portion of the wire 7(1) is bonded to the dotted area 612. That is, the wire 7(1) is bonded to the emitter electrode of the RC-IGBT chip 1 at two locations, the dotted areas 611 and 612. Hereinafter, such a structure in which the wire is connected to the emitter electrode at multiple locations is sometimes referred to as a "wire stitch structure".

[0140] In addition, if Fig. 9 As shown in FIG. 1 , the semiconductor device 104B further comprises: a resin insulating substrate 51 having a copper circuit pattern 40 disposed on its upper surface; and a base plate 52 having the resin insulating substrate 51 disposed on its upper surface. In addition, in the basic structure of the first to third and fourth embodiments, in addition to the seam welding structure of the lead wire, a structure similar to the above is also provided. Fig. 9 Same cross-section structure.

[0141] The RC-IGBT chip 2 includes a dotted region 621 as a first separated wiring connection region and a dotted region 622 as a second separated wiring connection region as wiring connection regions. The dotted regions 621 and 622 are provided to be separated from each other in the Y direction.

[0142] Although not shown, the wire 7 ( 2 ) serving as a relay wire for the RC-IGBT chip 2 is also joined at two locations, the dotted regions 621 and 622 , similarly to the wire 7 ( 1 ).

[0143] The RC-IGBT chip 3 includes a dotted region 631 as a first separated wiring connection region and a dotted region 632 as a second separated wiring connection region as wiring connection regions. The dotted regions 631 and 632 are provided to be separated from each other in the Y direction.

[0144] Although not shown, the wire 7 ( 3 ) serving as a relay wire for the RC-IGBT chip 3 is also joined at two locations, the dotted regions 631 and 632 , similarly to the wire 7 ( 1 ).

[0145] As described above, the semiconductor device 104B according to the modification has the following features: The wiring connection region of each of the RC-IGBT chips 1 to 3 includes first and second separate wiring connection regions provided separately in the Y direction.

[0146] Furthermore, the relay conductors that are parts of each of the plurality of external wirings are electrically connected to the first separate wiring connection region and the second separate wiring connection region.

[0147] In the semiconductor device 104B of the modified example, the wiring connection regions of each of the RC-IGBT chips 1 to 3 include the first and second separate wiring connection regions, and accordingly the area of ​​the wiring connection regions of each of the RC-IGBT chips 1 to 3 can be increased, thereby reducing the current density flowing from the emitter electrode, which becomes the first main electrode, to the external wiring.

[0148] As a result, the semiconductor device 104B serving as a modification of the fourth embodiment suppresses a temperature rise in the dotted regions serving as wiring connection regions of the RC-IGBT chips 1 to 3 , thereby achieving a longer life of the device.

[0149] Furthermore, in the modification, two joints are shown as the seam welding structure of the conductor wire, but it is of course possible to expand the number of joints to three or more.

[0150] <Implementation method 5>

[0151] Fig.10 1 and 2 are explanatory diagrams schematically showing the structure of a semiconductor device 105 according to Embodiment 5 of the present invention. FIG. (a) is a cross-sectional view, and FIG. (b) is a top view. FIG. (a) shows a cross section taken along line BB in FIG. (b). Fig.10 (a) and (b) each describe an XYZ orthogonal coordinate system.

[0152] Hereinafter, the same reference numerals are used to designate the same structures as those of the semiconductor device 101 of the first embodiment, and description thereof will be omitted as appropriate. The description will focus on the characteristic parts of the semiconductor device 105 of the fifth embodiment. Figure 3 The equivalent circuit is shown.

[0153] like Fig.10 As shown in (a), the semiconductor device 105 further includes a resin insulating substrate 51 and a base plate 52, the resin insulating substrate 51 is provided on the base plate 52, and the copper circuit pattern 40 is provided on the resin insulating substrate 51. In addition, the lower surface of the copper circuit pattern 40 is entirely located above the upper surface of the resin insulating substrate 51. That is, the resin insulating substrate 51 has an area that includes the entire copper circuit pattern 40 when viewed from above.

[0154] As described above, the semiconductor device 105 further includes the resin insulating substrate 51, which is an insulating substrate having the copper circuit pattern 40 as a common circuit pattern provided on the upper surface. The film thickness of the copper circuit pattern 40 is set to a thickness t40.

[0155] As shown in FIG. 1( b ), each of the RC-IGBT chips 1 to 3 is a rectangle having first to fourth sides, i.e., sides S1 to S4, when viewed from above. The dotted areas 61 to 63 of the RC-IGBT chips 1 to 3 are each arranged along the X direction on the side of side S1 among the sides S1 to S4, with sides S2 and S3 being adjacent to side S1, and side S4 being opposite to side S1.

[0156] Furthermore, the sides S1 to S4 are formed in the same direction among the RC-IGBT chips 1 to 3. That is, the sides S1 and S4 are formed in the X direction, and the sides S2 and S3 are formed in the Y direction.

[0157] In addition, the planar shapes of all the RC-IGBT chips 1 to 3 are the same. This feature is also the same in the first to fourth embodiments and the sixth embodiment described later.

[0158] The common circuit pattern, namely the copper circuit pattern 40, has first to third opposing sides, namely opposing sides FS1 to FS3, opposing sides S1 to S3 in a plan view. That is, the first opposing side is opposing side FS1, the second opposing side is opposing side FS2, and the third opposing side is opposing side FS3.

[0159] Furthermore, the formation direction of the opposing side FS1 is the same X direction as the formation direction of the side S1 , and the formation directions of the opposing sides FS2 and FS3 are the same Y directions as the sides S2 and S3 .

[0160] The following first to third margin distances are defined between the RC-IGBT chips 1 to 3 and the copper circuit pattern 40 in the semiconductor device 105 .

[0161] First margin distance: The shortest distance among three first distances from the side S1 of each of the RC-IGBT chips 1 to 3 to the facing side FS1 of the copper circuit pattern 40 is defined as a margin distance d11. This margin distance d11 is the first margin distance.

[0162] exist Fig.10 In the planar structure shown in (b), the first distance from the side S1 of the RC-IGBT chip 1 to the opposite side FS1 of the copper circuit pattern 40 among the three first distances that constitute the plurality of first distances is the margin distance d11. The margin distance d11 is the same length as the first distance from the side S1 of the RC-IGBT chip 3 to the opposite side FS1 of the copper circuit pattern 40.

[0163] Second margin distance: The shortest distance among the three second distances from the side S2 of each of the RC-IGBT chips 1 to 3 to the facing side FS2 of the copper circuit pattern 40 is set as the margin distance d12. The margin distance d12 is the second margin distance.

[0164] exist Fig.10 In the planar structure shown in (b), the second distance from the side S2 of the RC-IGBT chip 1 to the opposing side FS2 of the copper circuit pattern 40 among three second distances of the plurality of second distances is the margin distance d12.

[0165] Third margin distance: The shortest distance among the three third distances from the side S3 of each of the RC-IGBT chips 1 to 3 to the facing side FS3 of the copper circuit pattern 40 is set as a margin distance d13. This margin distance d13 is the third margin distance.

[0166] exist Fig.10 In the planar structure shown in (b), the third distance from the side S3 of the RC-IGBT chip 3 to the facing side FS3 of the copper circuit pattern 40 among the three third distances constituting the plurality of third distances is the margin distance d13.

[0167] Regarding the semiconductor device 105, the relationship between the thickness t40 of the copper circuit pattern 40 and the three margin distances d11 to d13 satisfies the length condition that the margin distances d11 to d13 are longer than the thickness t40 of the copper circuit pattern 40. That is, the semiconductor device 105 satisfies the length condition "d11>t40, d12>t40, d13>t40".

[0168] In the semiconductor device 105 of the fifth embodiment, the margin distances d11 to d13 and the thickness t40 of the copper circuit pattern 40 satisfy the above-mentioned length condition. Therefore, in the copper circuit pattern 40 of the semiconductor device 105, the first to third heat dissipation regions from the sides S1 to S3 of the RC-IGBT chips 1 to 3 to the opposite sides FS1 to FS3 of the copper circuit pattern 40 can be ensured to be relatively wide. This point will be described in detail below.

[0169] like Fig.10 As shown in (a), a perpendicular line V2 is drawn from the side S2 of the RC-IGBT chip 1 in the −Z direction. Furthermore, an auxiliary line L42 is drawn from the lower end P2 of the side S2 of the RC-IGBT chip 1 to the lower end P42 of the opposite side FS2 of the copper circuit pattern 40 .

[0170] The angle θ2 between the vertical line V2 and the auxiliary line L42 determines the heat dissipation characteristics on the -X direction side generated by the copper circuit pattern 40. The reason is that the area sandwiched by the vertical line V2 and the auxiliary line L42 in the copper circuit pattern 40 is the second heat dissipation area on the -X direction. Therefore, the larger the angle θ2 is, the larger the second heat dissipation area of ​​the copper circuit pattern 40 is, so the resin insulating substrate 51 can effectively perform heat dissipation from the second heat dissipation area on the -X direction side. Since the semiconductor device 105 satisfies "d12>t40", the angle θ2 is greater than 45 degrees.

[0171] like Fig.10 As shown in (a), a perpendicular line V3 is drawn in the −Z direction from the side S3 of the RC-IGBT chip 3. Furthermore, an auxiliary line L43 is drawn from the lower end P3 of the side S3 of the RC-IGBT chip 2 to the lower end P43 of the opposite side FS3 of the copper circuit pattern 40.

[0172] The angle θ3 between the vertical line V3 and the auxiliary line L43 determines the heat dissipation characteristics on the +X direction side generated by the copper circuit pattern 40. The reason is that the area sandwiched by the vertical line V3 and the auxiliary line L43 in the copper circuit pattern 40 is the third heat dissipation area on the +X direction side. Therefore, the larger the angle θ3 is, the larger the third heat dissipation area of ​​the copper circuit pattern 40 is, so the resin insulating substrate 51 can effectively perform heat dissipation from the third heat dissipation area on the +X direction side. Since the semiconductor device 105 satisfies "d13>t40", the angle θ3 is greater than 45 degrees.

[0173] Although in Fig.10 Although not shown in the figure, the angle θ1 is determined by the margin distance d11 and the thickness t40 for the first heat dissipation region in the -Y direction of the copper circuit pattern 40. Since "d11>t40" is satisfied, the angle θ1 is larger than 45 degrees.

[0174] Therefore, the first heat dissipation region can also be ensured to be as wide as the second and third heat dissipation regions described above, so that the resin insulating substrate 51 can effectively dissipate heat from the first heat dissipation region on the -Y direction side.

[0175] In addition, as described above, the heat generation from the RC-IGBT chips 1 to 3 becomes significant in the dot regions 61 to 63 and their peripheries. Therefore, the semiconductor device 105 with the first to third heat dissipation regions widened at the sides S1 to S3 close to the dot regions 61 to 63 can perform an effective heat dissipation operation.

[0176] Fig.11 It is an explanatory diagram schematically showing the structure of the comparative semiconductor device 110. Figure (a) of this figure is a cross-sectional view, and figure (b) of this figure is a top view. Figure (a) shows the C-C cross-section of figure (b). Fig.11 (a) and (b) each record an XYZ orthogonal coordinate system.

[0177] Hereinafter, for the same structure as the semiconductor device 105 of the fifth embodiment, the same reference numerals are given and the description is appropriately omitted, and the description will be centered on the differences between the comparative semiconductor device 110 and the semiconductor device 105.

[0178] The comparative semiconductor device 110 defines margin distances d21 to d23 corresponding to the margin distances d11 to d13 of the semiconductor device 105.

[0179] For the comparative semiconductor device 110, regarding the thickness t40 of the copper circuit pattern 40 and the above margin distances d21 to d23, the margin distances d21 to d23 are shorter than the thickness t40 of the copper circuit pattern 40. That is, the comparative semiconductor device 110 is "d21 < t40, d22 < t40, d23 < t40", and does not satisfy the above length condition in the fifth embodiment.

[0180] As Fig.11 (a) shows, a perpendicular line V2 is drawn from the side S2 of the RC-IGBT chip 1 in the -Z direction. Moreover, an auxiliary line L52 is drawn from the lower end P2 of the side S2 of the RC-IGBT chip 1 to the lower end P42 of the opposite side FS2 of the copper circuit pattern 40.

[0181] For the comparative semiconductor device 110, the angle θ12 between the perpendicular line V2 and the auxiliary line L52 is smaller than the angle θ2 of the semiconductor device 105. The reason is that since "d22 < t40", the angle θ12 is less than 45 degrees.

[0182] As Fig.11As shown in (a), a perpendicular line V3 is drawn from the side S3 of the RC-IGBT chip 3 in the -Z direction. Moreover, an auxiliary line L53 is drawn from the lower end P3 of the side S3 of the RC-IGBT chip 2 to the lower end P43 of the opposite side FS3 of the copper circuit pattern 40.

[0183] For the comparative semiconductor device 110, the angle θ13 between the perpendicular line V3 and the auxiliary line L53 is smaller than the angle θ3 of the semiconductor device 105. The reason is that since "d23 < t40", the angle θ13 is less than 45 degrees.

[0184] Although not shown in Fig.11 for the comparative semiconductor device 110, regarding the first heat dissipation region in the -Y direction of the copper circuit pattern 40, the angle θ11 is determined based on the margin distance d21 and the thickness t40. Since "d21 < t40", the angle θ11 is less than 45 degrees. Therefore, the angle θ11 of the comparative semiconductor device 110 is smaller than the angle θ1 of the semiconductor device 105.

[0185] Therefore, the comparative semiconductor device 110, where the first to third heat dissipation regions near the sides S1 to S3 of the dot regions 61 to 63 are narrower than those of the semiconductor device 105, cannot perform an effective heat dissipation operation.

[0186] Thus, for the semiconductor device 105 of Embodiment 5, by satisfying the length condition that the margin distances d11 to d13 are longer than t40 of the copper circuit pattern 40, the first to third heat dissipation regions in the copper circuit pattern 40 from the sides S1 to S3 of the RC-IGBT chips 1 to 3 to the opposite sides FS1 to FS3 of the copper circuit pattern 40 can be ensured to be relatively wide.

[0187] Therefore, the semiconductor device 105 of Embodiment 5 can improve the heat dissipation performance from the first to third heat dissipation regions through the resin insulation substrate 51, and accordingly can effectively suppress the temperature rise of the multiple semiconductor chips and achieve the long life of the device.

[0188] <Embodiment 6>

[0189] Fig.12 is a top view schematically showing the structure of the semiconductor device 106 according to Embodiment 6 of the present invention. An XYZ orthogonal coordinate system is described in Fig.12 it.

[0190] Hereinafter, for the same structures as those of the semiconductor device 101 in Embodiment 1, the same reference numerals are given and the description is appropriately omitted, and the description will be centered on the characteristic parts of the semiconductor device 106 in Embodiment 6.

[0191] The semiconductor device 106 of the sixth embodiment is characterized in that each of the RC-IGBT chips 1 to 3 includes a plurality of partial semiconductor chips, and emitter electrodes serving as first main electrodes of the plurality of partial semiconductor chips are electrically connected in common. Fig.12 , and explain it in detail.

[0192] RC-IGBT chip 1 is composed of RC-IGBT chips 1A and 1B, which are partial semiconductor chips. Similarly, RC-IGBT chip 2 is composed of RC-IGBT chips 2A and 2B, which are partial semiconductor chips. RC-IGBT chip 3 is composed of RC-IGBT chips 3A and 3B, which are partial semiconductor chips.

[0193] Hereinafter, the RC-IGBT chips 1A and 1B will be described as a representative among the RC-IGBT chips 1A and 1B, 2A and 2B, and 3A and 3B.

[0194] exist Fig.12 In the embodiment, most of the upper surface of the RC-IGBT chip 1A except the signal pad 31A becomes the first main electrode, i.e., the emitter electrode, and most of the upper surface of the RC-IGBT chip 1B except the signal pad 31B becomes the first main electrode, i.e., the emitter electrode. Furthermore, the lower surfaces of the RC-IGBT chips 1A and 1B respectively become the second main electrode, i.e., the collector electrode.

[0195] That is, each of the RC-IGBT chips 1A and 1B has an IGBT as a switching element, an emitter electrode as a first main electrode of the IGBT is provided on the upper surface, and a collector electrode as a second main electrode of the IGBT is provided on the lower surface. Furthermore, a diode as a freewheeling element is provided in parallel with respect to each of the IGBTs of the RC-IGBT chips 1A and 1B.

[0196] The emitter electrodes of the RC-IGBT chips 1A and 1B are electrically connected to each other through an internal wiring 91 such as a wire. On the other hand, the collector electrodes of the RC-IGBT chips 1A and 1B are electrically connected to the copper circuit pattern 40 in common.

[0197] In the RC-IGBT chip 1A, part of the emitter electrode is allocated as a first partial wiring connection region, ie, dotted region 61A, and in the RC-IGBT chip 1B, part of the emitter electrode is allocated as a second partial wiring connection region, ie, dotted region 61B.

[0198] That is, in the sixth embodiment, the wiring connection region of the RC-IGBT chip 1 is a combination of the first and second partial wiring connection regions.

[0199] In the section of Embodiment 7 described later, connection details of the wire 7 to the copper circuit patterns 41 to 43 of the semiconductor device 106 according to Embodiment 6 will be described.

[0200] The semiconductor device 106 of the sixth embodiment is characterized in that the plurality of partial semiconductor chips, namely the RC-IGBT chips 1A and 1B, are repeatedly arranged in a manner that the entirety including the dotted regions 61A and 61B overlap each other in the Y direction. That is, the formation positions of the dotted regions 61A and 61B in the Y direction are the same between the RC-IGBT chips 1A and 1B.

[0201] In addition, the RC-IGBT chips 2A and 2B and the RC-IGBT chips 3A and 3B also have the same features as the RC-IGBT chips 1A and 1B. That is, the signal pads 32A and 32B and the signal pads 33A and 33B have the same features as the signal pads 31A and 31B, and the dotted areas 62A and 62B and the dotted areas 63A and 63B have the same features as the dotted areas 61A and 61B.

[0202] Internal wirings 92 and 93 have the same features as internal wiring 91. That is, emitter electrodes of RC-IGBT chips 2A and 2B are electrically connected via internal wiring 92 such as a wire, and emitter electrodes of RC-IGBT chips 3A and 3B are electrically connected via internal wiring 93 such as a wire.

[0203] Furthermore, in the semiconductor device 106, the RC-IGBT chips 2A and 2B are characterized in that they are repeatedly arranged in the Y direction so that the dotted regions 62A and 62B are overlapped as a whole. That is, the formation positions of the dotted regions 62A and 62B in the Y direction are the same between the RC-IGBT chips 2A and 2B.

[0204] Similarly, in the semiconductor device 106, the RC-IGBT chips 3A and 3B are characterized in that they are repeatedly arranged in the Y direction so that the dotted regions 63A and 63B are overlapped as a whole. That is, the formation positions of the dotted regions 63A and 63B in the Y direction are the same between the RC-IGBT chips 3A and 3B.

[0205] Thus, the semiconductor device 106 of the sixth embodiment has a structure in which a plurality of partial semiconductor chips are combined as one unit of semiconductor chip. That is, the combination of RC-IGBT chips 1A and 1B is set as one unit of RC-IGBT chip 1, the combination of RC-IGBT chips 2A and 2B is set as one unit of RC-IGBT chip 2, and the combination of RC-IGBT chips 3A and 3B is set as one unit of RC-IGBT chip 3.

[0206] Therefore, the RC-IGBT chips 1 to 3 each formed by a combination of a plurality of partial semiconductor chips have electrically equivalent properties to the RC-IGBT chips 1 to 3 described in the first to fifth embodiments.

[0207] Therefore, the semiconductor device 106 of the sixth embodiment also realizes the same as the first embodiment. Figure 3 For example, in the RC-IGBT chip 1, two IGBTs formed in the RC-IGBT chips 1A and 1B are connected in parallel to form IGBT 11, and two diodes formed in the RC-IGBT chips 1A and 1B are connected in parallel to form diode D11.

[0208] However, the semiconductor device 106 of the sixth embodiment satisfies the first and second arrangement conditions for the RC-IGBT chips 1 to 3, similarly to the semiconductor device 101 of the first embodiment. This point will be described in detail below.

[0209] Among the RC-IGBT chips 1 to 3 , a pair of RC-IGBT chips that are adjacent to each other in the X direction are the RC-IGBT chips 1B and 2A and the RC-IGBT chips 2B and 3A.

[0210] RC-IGBT chips 1B and 2A are separated and arranged in the Y direction so that dotted regions 61B and 62A do not overlap. Similarly, RC-IGBT chips 2B and 3A are separated and arranged in the Y direction so that dotted regions 62B and 63A do not overlap.

[0211] As described above, in the semiconductor device 106 according to the sixth embodiment, the plurality of semiconductor chips, namely, the RC-IGBT chips 1 to 3 satisfy the first arrangement condition similarly to the first embodiment.

[0212] In addition, the RC-IGBT chips 1B and 2A are partially overlapped in the Y direction in a manner that a portion of the emitter electrodes other than the dotted regions 61B and 62A are overlapped. Similarly, the RC-IGBT chips 2B and 3A are partially overlapped in the Y direction in a manner that a portion of the emitter electrodes other than the dotted regions 62B and 63A are overlapped.

[0213] As described above, in the semiconductor device 106 of the sixth embodiment, the plurality of semiconductor chips, namely, the RC-IGBT chips 1 to 3 satisfy the second arrangement condition similarly to the first embodiment.

[0214] The semiconductor device 106 of the sixth embodiment satisfies the first and second arrangement characteristics as in the first embodiment, and thus can achieve both a longer life and smaller size of the device.

[0215] In the semiconductor device 106 of the sixth embodiment, the RC-IGBT chip 1 is composed of the RC-IGBT chips 1A and 1B, the RC-IGBT chip 2 is composed of the RC-IGBT chips 2A and 2B, and the RC-IGBT chip 3 is composed of the RC-IGBT chips 3A and 3B. Therefore, the semiconductor device 106 can increase the arrangement area of ​​each of the RC-IGBT chips 1 to 3 at the copper circuit pattern 40.

[0216] As a result, the semiconductor device 106 of the sixth embodiment can improve heat dissipation in the direction in which the copper circuit pattern 40 is formed, and thus can effectively suppress the temperature rise of each of the RC-IGBT chips 1 to 3 and extend the life of the device.

[0217] In the semiconductor device 106, a plurality of partial semiconductor chips are repeatedly arranged in the Y direction including partial wiring connection regions. For example, the RC-IGBT chips 1A and 1B are entirely repeatedly arranged in the Y direction including dotted regions 61A and 61B.

[0218] Therefore, the semiconductor device 106 of the sixth embodiment can suppress the formation length of each of the RC-IGBT chips 1 to 3 in the Y direction to a necessary minimum, and accordingly can achieve miniaturization of each of the RC-IGBT chips 1 to 3 .

[0219] <Implementation Method 7>

[0220] Fig.13 FIG. 1 is a top view schematically showing the structure of a semiconductor device 107 according to Embodiment 7 of the present invention. Fig.13 The XYZ orthogonal coordinate system is recorded in.

[0221] Hereinafter, the same reference numerals are used to denote the same structures as those of the semiconductor device 106 according to the sixth embodiment, and description thereof will be omitted as appropriate, and description will be mainly focused on the characteristic parts of the semiconductor device 107 according to the seventh embodiment.

[0222] The semiconductor device 107 of the seventh embodiment is characterized in that, similar to the sixth embodiment, each of the RC-IGBT chips 1 to 3 includes a plurality of partial semiconductor chips, and the emitter electrodes serving as the first main electrodes of the plurality of partial semiconductor chips are electrically connected in common. Fig.13 The following will be described in detail.

[0223] RC-IGBT chip 1 is composed of RC-IGBT chips 1A and 1B, which are partial semiconductor chips. Similarly, RC-IGBT chip 2 is composed of RC-IGBT chips 2A and 2B, which are partial semiconductor chips. RC-IGBT chip 3 is composed of RC-IGBT chips 3A and 3B, which are partial semiconductor chips.

[0224] The semiconductor device 107 of the seventh embodiment is similar to the sixth embodiment in that a combination of a plurality of partial semiconductor chips is used as a single unit semiconductor chip.

[0225] Fig.14 It is a plan view showing the connection of the wire 7 to the copper circuit patterns 41 to 43 of the semiconductor device 107 according to the seventh embodiment.

[0226] As shown in the figure, dotted regions 61A of RC-IGBT chip 1A and dotted regions 71A of copper circuit pattern 41 are electrically connected via wires 7 , and dotted regions 61B of RC-IGBT chip 1B and dotted regions 71B of copper circuit pattern 41 are electrically connected via wires 7 .

[0227] Therefore, the combination of the dotted regions 61A and 61B serves as a wiring connection region of the RC-IGBT chip 1 , and thus the electrical connection relationship between the emitter electrode of the RC-IGBT chip 1 and the copper circuit pattern 41 is equivalent to that of the first to fifth embodiments.

[0228] like Fig.14 As shown, dotted regions 62A of the RC-IGBT chip 2A and dotted regions 72A of the copper circuit pattern 42 are electrically connected via wires 7 , and dotted regions 62B of the RC-IGBT chip 2B and dotted regions 72B of the copper circuit pattern 42 are electrically connected via wires 7 .

[0229] Therefore, the combination of the dotted regions 62A and 62B serves as a wiring connection region of the RC-IGBT chip 2 , and thus the electrical connection relationship between the emitter electrode of the RC-IGBT chip 2 and the copper circuit pattern 42 is equivalent to that of the first to fifth embodiments.

[0230] like Fig.14 As shown, dotted regions 63A of RC-IGBT chip 3A and dotted regions 73A of copper circuit pattern 43 are electrically connected via wires 7 , and dotted regions 63B of RC-IGBT chip 3B and dotted regions 73B of copper circuit pattern 43 are electrically connected via wires 7 .

[0231] Therefore, the combination of the dotted regions 63A and 63B is a wiring connection region of the RC-IGBT chip 3 , and thus the electrical connection relationship between the emitter electrode of the RC-IGBT chip 3 and the copper circuit pattern 43 is equivalent to that of the first to fifth embodiments.

[0232] As described above, in the semiconductor device 107 of the seventh embodiment, the electrical connection relationship between the emitter electrodes of the RC-IGBT chips 1 to 3 and the copper circuit patterns 41 to 43 is equivalent to that of the first to fifth embodiments.

[0233] Furthermore, the RC-IGBT chips 1 to 3 each formed by a combination of a plurality of partial semiconductor chips have electrically equivalent properties to the RC-IGBT chips 1 to 3 described in the first to fifth embodiments.

[0234] In addition, in the semiconductor device 106 of the sixth embodiment, the emitter electrodes of the RC-IGBT chips 1 to 3 and the copper circuit patterns 41 to 43 are also as follows. Fig.14 Therefore, the electrical connection relationship between the emitter electrodes of the RC-IGBT chips 1 to 3 and the copper circuit patterns 41 to 43 in the sixth embodiment is also equivalent to that in the first to fifth embodiments.

[0235] Therefore, the semiconductor device 106 of the sixth embodiment and the semiconductor device 107 of the seventh embodiment can be configured by using the RC-IGBT chips 1 to 6 in the same manner as in the first embodiment. Figure 3 The equivalent circuit is shown.

[0236] Thus, the semiconductor device 107 according to the seventh embodiment has the same features as the semiconductor device 106 according to the sixth embodiment. Next, the unique features of the semiconductor device 107 according to the seventh embodiment will be described.

[0237] In the semiconductor device 107 , a pair of partial semiconductor chips that are adjacent to each other in the X direction among the plurality of partial semiconductor chips satisfy the third and fourth arrangement conditions described below.

[0238] In addition, regarding the RC-IGBT chip 1 , a pair of partial semiconductor chips that are adjacent to each other in the X direction are the RC-IGBT chips 1A and 1B.

[0239] Between the RC-IGBT chips 1A and 1B, the dotted regions 61A and 61B are separated and arranged in the Y direction so as not to overlap each other.

[0240] Therefore, the semiconductor device 107 of the seventh embodiment satisfies the following third arrangement condition.

[0241] Third arrangement condition: A pair of partial semiconductor chips that are adjacent to each other in the X direction among the plurality of partial semiconductor chips are separated and arranged in the Y direction so that their partial wiring connection regions do not overlap.

[0242] The RC-IGBT chips 1A and 1B are arranged so that emitter electrodes partially overlap in the Y direction except for the dotted regions 61A and 61B.

[0243] Therefore, the semiconductor device 101 according to the first embodiment satisfies the following fourth arrangement condition.

[0244] Fourth arrangement condition: A pair of partial semiconductor chips adjacent to each other in the X direction among the plurality of partial semiconductor chips are arranged to overlap partially in the Y direction so that a portion of the region other than the partial wiring connection region overlaps.

[0245] In addition, the RC-IGBT chips 2A and 2B and the RC-IGBT chips 3A and 3B also satisfy the third and fourth arrangement conditions described above, similarly to the RC-IGBT chips 1A and 1B.

[0246] As described above, the semiconductor device 107 according to the seventh embodiment is different from the semiconductor device 106 in that a pair of partial semiconductor chips adjacent to each other among the plurality of partial semiconductor chips satisfies the third and fourth arrangement conditions.

[0247] Furthermore, the semiconductor device 107 according to the seventh embodiment also satisfies the first and second arrangement characteristics similarly to the semiconductor device 101 according to the first embodiment and the semiconductor device 106 according to the sixth embodiment. This point will be described in detail below.

[0248] Among the RC-IGBT chips 1 to 3 , a pair of RC-IGBT chips that are adjacent to each other in the X direction are the RC-IGBT chips 1B and 2A and the RC-IGBT chips 2B and 3A.

[0249] RC-IGBT chips 1B and 2A are separated and arranged in the Y direction so that dotted regions 61B and 62A do not overlap. Similarly, RC-IGBT chips 2B and 3A are separated and arranged in the Y direction so that dotted regions 62B and 63A do not overlap.

[0250] As described above, in the semiconductor device 107 according to the seventh embodiment, the RC-IGBT chips 1 to 3 constituting a plurality of semiconductor chips satisfy the first arrangement characteristic similarly to the first embodiment.

[0251] The RC-IGBT chips 1B and 2A are partially overlapped in the Y direction in a manner that a portion of the emitter electrodes other than the dotted regions 61B and 62A are overlapped. Similarly, the RC-IGBT chips 2B and 3A are partially overlapped in the Y direction in a manner that a portion of the emitter electrodes other than the dotted regions 62B and 63A are overlapped.

[0252] As described above, in the semiconductor device 107 of the seventh embodiment, the RC-IGBT chips 1 to 3 constituting a plurality of semiconductor chips satisfy the second arrangement characteristic similarly to the first embodiment.

[0253] The semiconductor device 107 of the seventh embodiment satisfies the first and second arrangement characteristics as in the first embodiment, and thus can simultaneously achieve a longer life and smaller size of the device.

[0254] In the semiconductor device 107 of the seventh embodiment, the RC-IGBT chip 1, the RC-IGBT chip 2 and the RC-IGBT chip 3 are composed of the RC-IGBT chips 1A and 1B, 2A and 2B, and 3A and 3B, and accordingly, the configuration area of ​​each of the RC-IGBT chips 1 to 3 at the copper circuit pattern 40 can be set large.

[0255] As a result, the semiconductor device 107 of the seventh embodiment can improve heat dissipation in the direction in which the copper circuit pattern 40 is formed, similarly to the sixth embodiment, and can therefore effectively suppress the temperature rise of each of the RC-IGBT chips 1 to 3 and extend the life of the device.

[0256] Furthermore, in the semiconductor device 107 , each of the plurality of semiconductor chips, ie, the RC-IGBT chips 1 to 3 , satisfies the third arrangement condition described above.

[0257] Therefore, for each of the RC-IGBT chips 1 to 3, the distance between the partial wiring connection areas of a pair of partial semiconductor chips can be set long to suppress thermal interference between the pair of partial semiconductor chips. For example, for the RC-IGBT chip 1, the distance between the dotted areas 61A and 61B of the RC-IGBT chips 1A and 1B can be set long to suppress thermal interference between the RC-IGBT chips 1A and 1B.

[0258] As a result, the RC-IGBT chips 1 to 3 in the semiconductor device 107 of the seventh embodiment can each suppress the temperature rise inside the plurality of partial semiconductor chips and achieve a longer life. For example, the RC-IGBT chip 1 can suppress the temperature rise inside the RC-IGBT chips 1A and 1B and achieve a longer life.

[0259] Furthermore, in the semiconductor device 107 , each of the plurality of semiconductor chips, ie, the RC-IGBT chips 1 to 3 , satisfies the fourth arrangement condition.

[0260] Therefore, the semiconductor device 107 of the seventh embodiment can suppress the formation area of ​​the plurality of partial semiconductor chips provided on the copper circuit pattern 40 to the minimum required, thereby realizing miniaturization of each chip. For example, with respect to the RC-IGBT chip 1 provided on the copper circuit pattern 40, the formation area of ​​the RC-IGBT chips 1A and 1B can be suppressed to the minimum required, thereby realizing miniaturization of the RC-IGBT chip 1.

[0261] <Implementation Method 8>

[0262] Fig.15 1 and 2 are explanatory diagrams schematically showing the structure of a semiconductor device 108 according to an eighth embodiment of the present invention. FIG. (a) is a cross-sectional view, and FIG. (b) is a top view. FIG. (a) shows a cross section taken along line DD in FIG. (b). Fig.15 (a) and (b) each describe an XYZ orthogonal coordinate system.

[0263] Hereinafter, the same reference numerals are used for the same structures as those of the semiconductor device 101 of the first embodiment, and the description thereof will be omitted as appropriate. The description will be mainly focused on the characteristic parts of the semiconductor device 108 of the eighth embodiment. Figure 3 The equivalent circuit is shown.

[0264] like Fig.15 As shown in (a), the semiconductor device 108 further includes a resin insulating substrate 51 and a base plate 52. The resin insulating substrate 51 is provided on the base plate 52, and the copper circuit pattern 40B is provided on the resin insulating substrate 51.

[0265] As described above, the semiconductor device 108 further includes the resin insulating substrate 51 which is an insulating substrate having the copper circuit pattern 40B as a common circuit pattern provided on its upper surface.

[0266] The semiconductor device 108 according to the eighth embodiment is characterized in that the film thickness of the copper circuit pattern 40B, that is, the thickness t40B is set to be greater than or equal to 0.3 mm.

[0267] In addition, the copper circuit pattern 40 has the same features as those of the copper circuit pattern 40 described in the first to seventh embodiments except that the thickness t40B serving as the film thickness of the copper circuit pattern 40B is set to be greater than or equal to 0.3 mm.

[0268] The semiconductor device 108 of the eighth embodiment can improve the heat dissipation by the copper circuit pattern 40B by setting the thickness t40B of the common circuit pattern, ie, the copper circuit pattern 40B, to be greater than or equal to 0.3 mm, thereby improving the reliability of the device.

[0269] <Implementation Method 9>

[0270] Fig.16 FIG. 1 is a top view schematically showing a planar structure of a semiconductor device 109 according to Embodiment 9 of the present invention. Fig.16 The XYZ orthogonal coordinate system is recorded in.

[0271] Hereinafter, the same reference numerals are used to denote the same structures as those of the semiconductor device 101 according to the first embodiment, and description thereof will be appropriately omitted, and description will be mainly focused on the characteristic parts of the semiconductor device 109 according to the ninth embodiment.

[0272] As shown in the figure, a semiconductor device 109 according to the ninth embodiment is characterized in that the RC-IGBT chips 1 to 6 are replaced with SiC-MOSFET chips 1S to 6S.

[0273] Each SiC-MOSFET chip iS (i=any of 1 to 6) has an N-channel MOSFET as a switching element. Each MOSFET is formed on a SiC substrate. In addition, the MOSFET may be a planar type or a trench type.

[0274] exist Fig.16 In the embodiment, most of the upper surface of SiC-MOSFET chips 1S-6S except signal pads 31-36 serves as the first main electrode, and the lower surface of each SiC-MOSFET chip 1S-6S serves as the second main electrode. Signal pads 31-36 function as control electrodes of MOSFETs.

[0275] SiC-MOSFET chips 1S to 3S are used for the upper bridge arms UP, VP, and WP of the three-phase AC inverter, and SiC-MOSFET chips 4S to 6S are used for the lower bridge arms UN, VN, and WN of the three-phase AC inverter. Figure 3 In the equivalent circuit of the semiconductor device 101 shown, a circuit configuration in which the combination of the IGBT 1i and the diode D1i (i=any of 1 to 6) is replaced with a SiC-MOSFET becomes a circuit configuration of the semiconductor device 109 of the ninth embodiment.

[0276] The semiconductor device 109 of the ninth embodiment has the same features as those of the first embodiment except for the above features. Therefore, the semiconductor device 109 of the ninth embodiment has the plurality of semiconductor chips, namely, SiC-MOSFET chips 1S to 3S, satisfying the first and second arrangement characteristics as in the first embodiment.

[0277] Therefore, the semiconductor device 109 of the ninth embodiment having SiC-MOSFET chips 1S to 3S each having a circuit structure including a SiC-MOSFET can achieve miniaturization and a longer life as in the first embodiment.

[0278] Furthermore, the semiconductor device 109 of the ninth embodiment uses SiC-MOSFET for each of the SiC-MOSFET chips 1S to 6S, thereby shortening the switching time and reducing the switching loss.

[0279] In addition, Fig.16 The ninth embodiment shown shows a structure in which the RC-IGBT chips 1 to 6 are replaced with SiC-MOSFET chips 1S to 6S in the structure of the first embodiment. The present invention is not limited to this structure, and the RC-IGBT chips 1 to 6 may be replaced with SiC-MOSFET chips 1S to 6S in the structures of the second to eighth embodiments.

[0280] <Others>

[0281] Furthermore, the present invention can freely combine the various embodiments within the scope of the invention, and can appropriately modify or omit the various embodiments.

[0282] For example, in the above embodiment, three semiconductor chips are shown as the plurality of semiconductor chips satisfying the first and second arrangement characteristics, such as the RC-IGBT chips 1 to 3 or the SiC-MOSFET chips 1S to 3S, but the number can be expanded to four or more semiconductor chips.

[0283] For example, Fig.13 and Fig.14 The semiconductor device 107 of the seventh embodiment shown in the figure can be regarded as a plurality of semiconductor chips arranged on the same common circuit pattern, and can be regarded as six partial semiconductor chips consisting of RC-IGBT chips 1A and 1B, RC-IGBT chips 2A and 2B, and RC-IGBT chips 3A and 3B arranged on a copper circuit pattern 40.

[0284] In this case, regarding the first to fourth arrangement conditions described in Embodiment 7, the first arrangement condition and the third arrangement condition are the same condition, and the second arrangement condition and the fourth arrangement condition are the same condition.

[0285] Therefore, when the six partial semiconductor chips in the semiconductor device 107 of the seventh embodiment are each set as one unit semiconductor chip, the semiconductor device 107 satisfies the first and second arrangement characteristics as in the first embodiment.

[0286] Description of the label

[0287] 1~6 RC-IGBT chips, 1S~6S SiC-MOSFET chips, 7, 7(1)~7(3) wires, 11~16 IGBTs, 20 P terminals, 21 U terminals, 22 V terminals, 23 W terminals, 28 N terminal, 31~36, 31A, 31B, 32A, 32B, 33A, 33B signal pads, 40~43, 40B, 48 copper circuit patterns, 51 resin insulating substrate, 52 base plate, 61~66, 61A, 61B, 62A, 62B, 63A, 63B, 71A, 71B, 72A, 72B, 73A, 73B, 81~83, 611, 612, 621, 622, 631, 632 dotting areas, 101~109 semiconductor devices, D11~D16 diodes, L1~L3 external wiring, W1~W3 signal wiring.

Claims

1. A semiconductor device comprising: common circuit pattern; and a plurality of semiconductor chips arranged along a first direction on the common circuit pattern, in, Each of the plurality of semiconductor chips has a switch element, and the plurality of semiconductor chips has a first main electrode of the switch element disposed on an upper surface and a second main electrode of the switch element disposed on a lower surface, and a portion of the first main electrode is allocated to a wiring connection region. The semiconductor device further includes a plurality of external wirings, each of which is electrically connected to the wiring connection region of a corresponding semiconductor chip among the plurality of semiconductor chips. A pair of semiconductor chips that are adjacent to each other in the first direction among the plurality of semiconductor chips satisfy a first arrangement condition and a second arrangement condition, The first arrangement condition is that the pair of semiconductor chips are arranged to be separated in a second direction intersecting the first direction so that the wiring connection regions do not overlap each other. The second arrangement condition is that the pair of semiconductor chips are partially overlapped in the second direction so that a portion of the region other than the wiring connection region overlaps, The plurality of semiconductor chips are classified into a first number of first-type semiconductor chips and a second number of second-type semiconductor chips, the first number of first-type semiconductor chips and the second number of second-type semiconductor chips are alternately arranged along the first direction, the first number is greater than or equal to the second number, The semiconductor device further comprises: a first number of first type of external terminals for the first number of first type of semiconductor chips; and a second number of second type external terminals for the second number of second type semiconductor chips, The wiring electrically connecting the wiring connection area of ​​the first number of the first type of semiconductor chips and the first number of the first type of external terminals is defined as the first number of the first type of external wiring, and the wiring electrically connecting the wiring connection area of ​​the second number of the second type of semiconductor chips and the second number of the second type of external terminals is defined as the second number of the second type of external wiring, and the plurality of external wirings include the first number of the first type of external wiring and the second number of the second type of external wiring, The wiring length of the first number of first-type external wirings is set to be shorter than the wiring length of the second number of second-type external wirings.

2. The semiconductor device according to claim 1, wherein A control electrode of the switch element is also provided on the upper surface of each of the plurality of semiconductor chips. The semiconductor device further includes a plurality of control wirings electrically connected to the control electrodes of the plurality of semiconductor chips, wherein each of the plurality of control wirings is provided so as to extend from the control electrodes in a control wiring direction. The plurality of external wirings are provided so as to extend from the wiring connection regions of the plurality of semiconductor chips in an external wiring direction, The control wiring direction and the external wiring direction are set to be opposite directions separated from each other.

3. The semiconductor device according to claim 2, wherein: The wiring connection regions of the plurality of semiconductor chips each include a first separated wiring connection region and a second separated wiring connection region which are provided in a manner separated from each other along the second direction. Each of the plurality of external wirings is electrically connected to the first separation wiring connection region and the second separation wiring connection region.

4. The semiconductor device according to any one of claims 1 to 3, wherein: It also has an insulating substrate on which the common circuit pattern is provided. Each of the plurality of semiconductor chips is a rectangle having a first side to a fourth side when viewed from above, the wiring connection region of each of the plurality of semiconductor chips is arranged along the first direction on the first side of the first side to the fourth side, and the second side and the third side are sides adjacent to the first side. The common circuit pattern has first to third opposing sides that are opposed to the first to third sides in a plan view, defining the shortest distance among a plurality of first distances from the first side of each of the plurality of semiconductor chips to the first opposing side of the common circuit pattern as a first margin distance, defining the shortest distance among a plurality of second distances from the second side of each of the plurality of semiconductor chips to the second opposing side of the common circuit pattern as a second margin distance, defining the shortest distance among a plurality of third distances from the third side of each of the plurality of semiconductor chips to the third opposing side of the common circuit pattern as a third margin distance, The first to third margin distances are larger than a film thickness of the common circuit pattern.

5. A semiconductor device comprising: common circuit pattern; and a plurality of semiconductor chips arranged along a first direction on the common circuit pattern, Each of the plurality of semiconductor chips has a switch element, and the plurality of semiconductor chips has a first main electrode of the switch element disposed on an upper surface and a second main electrode of the switch element disposed on a lower surface, and a portion of the first main electrode is allocated to a wiring connection region. The semiconductor device further includes a plurality of external wirings, each of which is electrically connected to the wiring connection region of a corresponding semiconductor chip among the plurality of semiconductor chips. A pair of semiconductor chips that are adjacent to each other in the first direction among the plurality of semiconductor chips satisfy a first arrangement condition and a second arrangement condition, The first arrangement condition is that the pair of semiconductor chips are arranged to be separated in a second direction intersecting the first direction so that the wiring connection regions do not overlap each other. The second arrangement condition is that the pair of semiconductor chips are partially overlapped in the second direction so that a portion of the region other than the wiring connection region overlaps, Each of the plurality of semiconductor chips includes a plurality of partial semiconductor chips, and the first main electrodes of the plurality of partial semiconductor chips are electrically connected in common. The first main electrodes of the plurality of semiconductor chips are not electrically connected to one another.

6. The semiconductor device according to claim 5, wherein: allocating a portion of the first main electrode of each of the plurality of partial semiconductor chips as a partial wiring connection region, The plurality of partial semiconductor chips are repeatedly arranged in the second direction so as to overlap each other including the partial wiring connection regions.

7. The semiconductor device according to claim 5, wherein: allocating a portion of the first main electrode of each of the plurality of partial semiconductor chips as a partial wiring connection region, A pair of partial semiconductor chips that are adjacent to each other in the first direction among the plurality of partial semiconductor chips satisfy a third arrangement condition and a fourth arrangement condition, The third arrangement condition is that the pair of partial semiconductor chips are arranged separately in the second direction so that the partial wiring connection regions do not overlap each other. The fourth arrangement condition is that the pair of partial semiconductor chips are partially overlapped in the second direction so that a portion of the region other than the partial wiring connection region overlaps.

8. The semiconductor device according to any one of claims 1 to 3 and 5 to 7, wherein: The film thickness of the common circuit pattern is greater than or equal to 0.3 mm.

9. The semiconductor device according to any one of claims 1 to 3 and 5 to 7, wherein: Each of the plurality of semiconductor chips includes a combination of the switching element and the freewheeling element, and the plurality of semiconductor chips are used for an upper arm of an inverter.

10. The semiconductor device according to any one of claims 1 to 3 and 5 to 7, wherein: The switching element is SiC-MOSFET.

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