Random interruption test method, device, electronic device and storage medium

Abstract

Embodiments of the present disclosure disclose a random interruption test method, apparatus, and device. A specific implementation of the method includes: generating interrupts through various interrupt generation mechanisms of an embedded operating system kernel; setting a header information flag bit for the interrupts of various interrupt generation mechanisms, and performing processing priority division according to a preset weight based on the header flag bit information; adding a random seed to send random interrupt signals in a random interrupt signal processing sequence at random time intervals; the random interrupt signals sequentially trigger an interrupt register to perform a state switch; after the state switch, determining that an interrupt program is executed; calculating a random interrupt processing delay according to the embedded operating system kernel; and adjusting the weight information corresponding to the header information flag bits of various interrupts according to the random interrupt processing delay. This implementation realizes the optimization of the random interrupt processing delay of the operating system, and the test process is simple and easy to repeat the measurement of the random interrupt processing time.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of operating system interrupt testing, and more particularly to a random interrupt testing method, apparatus, electronic device, and storage medium. Background Art

[0002] In the new century, information technology centered on computer technology, communication technology, and software technology has developed rapidly. The wide application of embedded computing and systems in various equipment and devices has greatly promoted the penetration of the industry. An embedded system is described as: "a dedicated computer system centered on applications, with software and hardware being customizable, and meeting the strict comprehensive requirements of application systems for functions, reliability, cost, volume, power consumption, etc.", and consists of two parts: embedded hardware and embedded software. Hardware is the support, and software is the soul. Almost all embedded products require embedded software to provide flexible and application-specific functions. Due to the wide application of embedded systems, embedded software occupies an important position in the entire software industry and has received extensive attention from countries around the world; it has now become one of the most dazzling "stars" in the information industry.

[0003] Generally, devices use open-source operating systems, such as the Linux system, to manage and control the hardware resources and software resources in the devices. The operating system of the device uses a process method to implement the operation of software programs, that is, the software programs are called into the set processes, and the central processing unit (CPU) of the device schedules the processes of the operating system under the interrupt call using the clock interrupt method. Summary of the Invention

[0004] The content part of the present disclosure is used to briefly introduce concepts, which will be described in detail in the specific implementation part later. The content part of the present disclosure is not intended to identify the key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution. Some embodiments of the present disclosure propose a random interrupt testing method, apparatus, and device to solve the technical problems mentioned in the above background art part.

[0005] In a first aspect, some embodiments of the present disclosure provide a random interrupt testing method, the method including: generating interrupts through various interrupt generation mechanisms of the embedded operating system kernel;

[0006] Setting a header information flag bit for the interrupts of the various interrupt generation mechanisms, and performing a processing priority division according to the preset weight based on the header flag bit information to obtain a random interrupt signal processing sequence;

[0007] Add a random seed to send the random interrupt signals in the random interrupt signal processing sequence at random time intervals; wherein the random interrupt signals trigger the interrupt register to switch states in sequence;

[0008] In response to the interrupt processor scanning the state switch of the interrupt register, determine the execution of the interrupt program;

[0009] Calculate the random interrupt processing delay according to the embedded operating system kernel;

[0010] Adjust the corresponding weight information of the header information flag bits of various interrupts according to the random interrupt processing delay.

[0011] In some optional implementation manners of some embodiments, generating interrupts through various interrupt generation mechanisms of the embedded operating system kernel includes:

[0012] Generate random interrupt signals according to various interrupt generation mechanisms of the embedded operating system, wherein the interrupt generation mechanisms include: clock interrupt mechanism, registered interrupt function mechanism, input / output interrupt mechanism, console interrupt mechanism.

[0013] In some optional implementation manners of some embodiments, the header information flag bits include interrupt generation mechanism, interrupt entry address, interrupt task weight information, and preset value of random interrupt interval. Set the header information flag bits for the interrupts of various interrupt generation mechanisms, and perform processing priority division according to the preset weights of the header flag bit information to obtain the random interrupt signal processing sequence, including:

[0014] Set the header information flag bits for each interrupt generation mechanism;

[0015] Perform processing priority division on the random interrupt signals corresponding to the header information flag bits according to the interrupt task weight information in the header information flag bits to obtain the random interrupt signal processing sequence.

[0016] In some optional implementation manners of some embodiments, configure the interrupt type and interrupt enable sequence for various random interrupt signals through a random instruction configurator.

[0017] In some optional implementation manners of some embodiments, the determining the execution of the interrupt program in response to the interrupt processor scanning the state switch of the interrupt register includes:

[0018] The interrupt processor scans the rising edge signal of the interrupt register;

[0019] Based on the interrupt entry address, access the interrupt handling function to determine the execution of the interrupt program.

[0020] In some alternative implementations of some embodiments, the random seed generates a pseudo-random number according to a preset value of a random interruption interval as the time interval for transmitting a random interruption signal.

[0021] In some alternative implementations of some embodiments, after the random interruption signal triggers the interruption register each time, the state of the interruption register is converted from a falling-edge signal to a rising-edge signal, and switches back to the falling-edge signal state at the preset minimum value of the interruption interval time.

[0022] In a second aspect, some embodiments of the present disclosure provide a random interruption test device, including: a generating unit configured to generate an interruption through various interruption generating mechanisms of the embedded operating system kernel;

[0023] a dividing unit configured to set a header information flag bit for the interruptions of the various interruption generating mechanisms, and perform a processing priority division according to the preset weight based on the header flag bit information to obtain a random interruption signal processing sequence;

[0024] a sending unit configured to add a random seed and send the random interruption signals in the random interruption signal processing sequence at random time intervals; wherein the random interruption signals sequentially trigger the interruption register to perform a state switch;

[0025] an execution unit configured to determine the execution of an interruption program in response to the interruption processor scanning the state switch of the interruption register;

[0026] a calculating unit configured to calculate a random interruption processing delay according to the embedded operating system kernel;

[0027] an adjusting unit configured to adjust the weight information corresponding to the header information flag bits of the various interruptions according to the random interruption processing delay.

[0028] In some alternative implementations of some embodiments, the generating unit includes: a generating subunit configured to generate a random interruption signal according to various interruption generating mechanisms of the embedded operating system, wherein the interruption generating mechanisms include: a clock interruption mechanism, a registered interruption function mechanism, an input / output interruption mechanism, a console interruption mechanism

[0029] In some alternative implementations of some embodiments, the header information flag bits include an interruption generating mechanism, an interruption entry address, an interruption task weight information, and a preset value of a random interruption interval. The dividing unit includes: a setting subunit configured to set a header information flag bit for each interruption generating mechanism;

[0030] A sub - division unit, configured to perform a processing priority division on the random interrupt signal corresponding to the header information flag bit according to the interrupt task weight information in the header information flag bit, so as to obtain the random interrupt signal processing sequence.

[0031] In some optional implementation manners of some embodiments, the various random interrupt signals configure the interrupt type and the interrupt enable sequence through a random instruction configurator.

[0032] In some optional implementation manners of some embodiments, the execution unit includes: a scanning sub - unit, configured to scan the rising - edge signal of the interrupt register by the interrupt processor;

[0033] A determination sub - unit, configured to access an interrupt processing function based on an interrupt entry address to determine the execution of an interrupt program.

[0034] In some optional implementation manners of some embodiments, the device further includes: a pseudo - random number generation unit, configured to generate a pseudo - random number according to a preset value of a random interrupt interval by the random seed as the transmission time interval of the random interrupt signal.

[0035] In some optional implementation manners of some embodiments, the device further includes: a conversion unit, configured to, after the random interrupt signal triggers the interrupt register each time, convert the state of the interrupt register from a falling - edge signal to a rising - edge signal, and switch back to the falling - edge signal state at a preset minimum value of the interrupt interval time.

[0036] In a third aspect, some embodiments of the present disclosure provide an electronic device, including: a memory, configured to store executable instructions; a processor, configured to operate the electronic device according to the control of the instructions to execute the method described in the first aspect of the present invention content.

[0037] In a fourth aspect, some embodiments of the present disclosure provide a computer - readable medium, on which a computer program is stored, wherein when the program is executed by a processor, the method described in the first aspect of the present invention content is implemented.

[0038] One embodiment among the above - mentioned various embodiments of the present disclosure has the following beneficial effects: First, interrupts are generated through various interrupt generation mechanisms of the embedded operating system kernel; second, a header information flag bit is set for the interrupts of the various interrupt generation mechanisms, and the processing priorities are divided according to the preset weights based on the header flag bit information to obtain a random interrupt signal processing sequence; then, a random seed is added and the random interrupt signals in the random interrupt signal processing sequence are sent at random time intervals; the random interrupt signals trigger the interrupt register to perform state switching in sequence; in response to the interrupt processor scanning the state switching of the interrupt register, it is determined that the interrupt program is executed; the random interrupt processing delay is calculated according to the embedded operating system kernel; and according to the random interrupt processing delay, the corresponding weight information of the header information flag bits of various interrupts is adjusted. The present invention realizes the optimization of the random interrupt processing delay of the operating system, and the test process is simple and it is easy to realize the repeated measurement of the random interrupt processing time. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In combination with the accompanying drawings and with reference to the following specific embodiments, the above - mentioned and other features, advantages and aspects of each embodiment of the present disclosure will become more obvious. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic and the original elements and elements are not necessarily drawn to scale.

[0040] Figure 1 is a flowchart of some embodiments of a random interrupt test method according to the present disclosure;

[0041] Figure 2 is a schematic diagram of an application scenario of a random interrupt test method according to some embodiments of the present disclosure;

[0042] Figure 3 is a schematic diagram of an application scenario of the state switching of an interrupt register according to the present disclosure;

[0043] Figure 4 is a schematic structural diagram of some embodiments of a random interrupt test device according to the present disclosure;

[0044] Figure 5 is a schematic structural diagram of an electronic device suitable for implementing some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not used to limit the protection scope of the present disclosure.

[0046] In addition, it should be noted that for ease of description, only parts related to the relevant invention are shown in the drawings. Without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other.

[0047] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0048] It should be noted that the modifications of "one" and "plural" mentioned in the present disclosure are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly specified in the context, it should be understood as "one or more".

[0049] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only for illustrative purposes, and are not used to limit the scope of these messages or information.

[0050] The present disclosure will be described in detail below with reference to the drawings and in combination with embodiments.

[0051] Embodiment 1

[0052] Figure 1 , which shows a process 100 of some embodiments of a random interruption test method according to the present disclosure. The random interruption test method includes the following steps:

[0053] Step 101, generating an interruption through various interruption generation mechanisms of the embedded operating system kernel.

[0054] In some embodiments, the execution subject of the random interruption test method can generate an interruption through various interruption generation mechanisms of the embedded operating system kernel.

[0055] In some optional implementation manners of some embodiments, a random interruption signal is generated according to various interruption generation mechanisms of the embedded operating system, and different interruption types generate different interruption signals, where the interruption generation mechanisms include: a clock interruption mechanism, a registered interruption function mechanism, an input / output interruption mechanism, and a console interruption mechanism.

[0056] Step 102, setting a header information flag bit for the interruption of each interruption generation mechanism, and performing a processing priority division according to the preset weight based on the header flag bit information to obtain a random interruption signal processing sequence.

[0057] In some embodiments, the above-mentioned execution entity may set a header information flag bit for the interruption of various interruption generation mechanisms, and perform a processing priority division according to a preset weight based on the header flag bit information to obtain a random interruption signal processing sequence.

[0058] In some alternative implementation manners of some embodiments, the header information flag bit includes an interruption generation mechanism, an interruption entry address, interruption task weight information, and a preset value of a random interruption interval. Setting the header information flag bit for the interruption of various interruption generation mechanisms and performing a processing priority division according to a preset weight based on the header flag bit information includes: setting a header information flag bit for each interruption generation mechanism; performing a processing priority division on the random interruption signals corresponding to the header information flag bits according to the interruption task weight information in the header information flag bits to obtain the random interruption signal processing sequence. The above-mentioned interruption generation mechanism may refer to the specific interruption type of the interruption; the interruption entry address refers to the memory address of the processor that processes this interruption signal. The above-mentioned interruption task weight information (i.e., the preset weight) refers to different types of interruptions such as a clock interruption, a registered interruption function, an input / output interruption, and a console interruption. We can preset a processing priority for them, and the operating system can determine which interruptions are processed first.

[0059] Step 103, adding a random seed and sending the random interruption signals in the random interruption signal processing sequence at random time intervals; wherein the random interruption signals sequentially trigger the interruption register to perform a state switch.

[0060] In some embodiments, the execution entity of the random interruption test method adds a random seed and sends the random interruption signals in the random interruption signal processing sequence at random time intervals. The above-mentioned random seed may refer to that the computer presets an initial value according to different attributes such as the system time. Then, the complex random number generation algorithm can be regarded as a black box. The initial value is input into it to obtain a random number and a new initial value. If more random numbers are needed, the new initial value obtained each time is put in and the loop is continuously performed. Among them, this black box is the complex random number generation algorithm, such as the existing random functions, numpy functions, torch functions, etc. of the computer.

[0061] In some alternative implementation manners of some embodiments, the random seed generates a pseudo-random number according to the preset value of the random interruption interval as the transmission time interval of the random interruption signal. The preset value of the random interruption interval is regarded as the initial value of the random seed. According to the initial value, a random number can be obtained through a complex random number generation algorithm, such as the existing random functions, numpy functions, torch functions, etc. of the computer. This random number is the pseudo-random number.

[0062] In some alternative implementations of some embodiments, each time the random interrupt signal triggers the interrupt register, the state of the interrupt register is converted from a falling-edge signal to a rising-edge signal, and switches back to the falling-edge signal state at the preset minimum value of the interrupt interval time. The preset minimum value of the interrupt interval time here can be equivalent to the random interrupt interval preset value in the header information flag bit.

[0063] Step 104, in response to the interrupt processor scanning the state change of the interrupt register, determine to execute the interrupt program.

[0064] In some embodiments, the above-mentioned execution entity can, in response to the interrupt processor scanning the state change of the interrupt register, determine to execute the interrupt program.

[0065] In some alternative implementations of some embodiments, the interrupt processor scans the rising-edge signal of the interrupt register; based on the interrupt entry address, access the interrupt handling function to determine the execution of the interrupt program. When the interrupt processor scans the rising-edge signal of the interrupt register, the interrupt processor queries the random interrupt signal header flag bit, and responds to the interrupt handling access program corresponding to the interrupt entry address and executes it. The interrupt handling access program is the interface program for the operating system to start processing interrupts, that is, to start subsequent processing. The interrupt handling access program includes accessing the interrupt handling function.

[0066] Step 105, calculate the random interrupt processing delay according to the embedded operating system kernel.

[0067] In some embodiments, the above-mentioned execution entity can calculate the random interrupt processing delay according to the embedded operating system kernel.

[0068] Step 106, adjust the weight information corresponding to the header information flag bits of various interrupts according to the random interrupt processing delay.

[0069] In some embodiments, the above-mentioned execution entity can adjust the weight information corresponding to the header information flag bits of various interrupts according to the random interrupt processing delay.

[0070] In some alternative implementations of some embodiments, the various random interrupt signals are configured with interrupt types and interrupt enable sequences through a random instruction configurator. The above-mentioned interrupt types refer to clock interrupts, input / output interrupts, console interrupts, etc. The above-mentioned interrupt enable sequences refer to some parameter attributes that the operating system needs to obtain when processing different interrupts, such as the current interrupt processing state, interrupt flag bits, the current processor working mode, and some other control information.

[0071] Some embodiments of the present disclosure disclose a random interruption test method. First, interruptions are generated through various interruption generation mechanisms of the embedded operating system kernel. Secondly, header information flag bits are set for the interruptions of the various interruption generation mechanisms, and processing priorities are divided according to preset weights based on the header flag bit information to obtain a random interruption signal processing sequence. Then, a random seed is added and the random interruption signals in the random interruption signal processing sequence are sent at random time intervals. The random interruption signals sequentially trigger the interruption register to perform a state switch. In response to the interruption processor scanning the state switch of the interruption register, it is determined that the interruption program is executed. The random interruption processing delay is calculated according to the embedded operating system kernel. According to the random interruption processing delay, the corresponding weight information of the header information flag bits of various interruptions is adjusted. The present invention realizes the optimization of the random interruption processing delay of the operating system, and the test process is simple and it is easy to realize the repeated measurement of the random interruption processing time.

[0072] Embodiment 2

[0073] Continue to refer to Figure 2 , which is a schematic diagram of an application scenario of the random interruption test method according to some embodiments of the present disclosure;

[0074] First, random interruption signals are generated according to various interruption generation mechanisms of the embedded operating system; various random interruption signals are configured with interruption types and interruption enable sequences through a random instruction configurator. The above-mentioned various interruption generation mechanisms are the same as the interruption types. Secondly, header information flag bits are set for the various random interruption signals, and the flag bit sequence includes interruption generation mechanisms, interruption entry addresses, interruption task weight information, and preset values of random interruption intervals. Thirdly, processing priorities are divided according to the interruption task weight information of the header flag bit information of the random interruption signals. Sorting is performed according to the interruption task weights. Then, a pseudo-random number is added as the signal transmission interval. When the interruption processor scans the rising edge signal of the interruption register, the interruption processor queries the header flag bit of the random interruption signal and responds to the interruption processing access program corresponding to the interruption entry address and executes it. After that, the processing times of various random interruption signals calculated by the operating system kernel are obtained. Finally, the weights are adjusted according to the random interruption signal processing times.

[0075] Embodiment 3

[0076] Continue to refer to Figure 3 , which is a schematic diagram of an application scenario of the state switch of the interruption register according to the present disclosure;

[0077] After each interruption signal triggers the interruption register, the state of the interruption register is converted from a falling edge signal to a rising edge signal and switches back to the falling edge signal state at the preset minimum value of the interruption interval time.

[0078] As shown in the figure, for the random interrupt signal 1, at time t0, which is the time when the random interrupt signal 1 triggers the interrupt register, after the interrupt register is triggered, the state of the interrupt register switches from the low level state to the high level state. After a time period T1, which is the preset minimum value of the random interrupt sending interval time, it switches back to the low level state. Among them, the time period from time t0 to before the random interrupt signal 2 triggers the interrupt register is T2, which is the actual value of the sending interval of the random interrupt signal 1.

[0079] Embodiment 4

[0080] Further reference Figure 4 , as an implementation of the methods shown in the above figures, the present disclosure provides some embodiments of a device. These device embodiments correspond to those method embodiments shown in Figure 1 , and the device can be specifically applied to various electronic devices.

[0081] As Figure 4 shown, the random interrupt test device 400 in some embodiments includes: a generating unit 401, a dividing unit 402, a sending unit 403, an executing unit 404, a calculating unit 405, and an adjusting unit 406. Among them, the generating unit 401 is used to generate interrupts through various interrupt generating mechanisms of the embedded operating system kernel; the dividing unit 402 is used to set a header information flag bit for the interrupts of the various interrupt generating mechanisms, and perform a processing priority division according to the preset weights of the header flag bit information to obtain a random interrupt signal processing sequence; the sending unit 403 is used to add a random seed and send the random interrupt signals in the random interrupt signal processing sequence at random time intervals; wherein the random interrupt signals trigger the interrupt register in sequence to perform state switching; the executing unit 404 is used to determine the execution of the interrupt program in response to the interrupt processor scanning the state switching of the interrupt register; the calculating unit 405 is used to calculate the random interrupt processing delay according to the embedded operating system kernel; the adjusting unit 406 is used to adjust the corresponding weight information of the header information flag bits of various interrupts according to the random interrupt processing delay.

[0082] In an optional implementation manner of some embodiments, based on the generating unit 401 in the random interrupt test device 400, it includes: a generating subunit, which is used to generate random interrupt signals according to various interrupt generating mechanisms of the embedded operating system, wherein the interrupt generating mechanisms include: a clock interrupt mechanism, a registered interrupt function mechanism, an input / output interrupt mechanism, and a console interrupt mechanism.

[0083] In an alternative implementation of some embodiments, the header information flag bits include an interrupt generation mechanism, an interrupt entry address, interrupt task weight information, and a preset value of a random interrupt interval. The partitioning unit 402 in the random interrupt test apparatus 400 based on interrupt latency response includes: a setting subunit, configured to set the header information flag bits for each interrupt generation mechanism; and a partitioning subunit, configured to perform a processing priority partitioning on the random interrupt signals corresponding to the header information flag bits according to the interrupt task weight information in the header information flag bits, to obtain a random interrupt signal processing sequence.

[0084] In an alternative implementation of some embodiments, the various random interrupt signals are configured with an interrupt type and an interrupt enable sequence through a random instruction configurator.

[0085] In an alternative implementation of some embodiments, the execution unit 403 in the random interrupt test apparatus 400 includes: a scanning subunit, configured to scan, by the interrupt processor, a rising edge signal of the interrupt register; and a determining subunit, configured to access an interrupt processing function based on the interrupt entry address to determine the execution of an interrupt program.

[0086] In an alternative implementation of some embodiments, the random interrupt test apparatus 400 further includes: a pseudo-random number generation unit, configured to generate a pseudo-random number according to the preset value of the random interrupt interval by the random seed as a time interval for transmitting the random interrupt signal.

[0087] In an alternative implementation of some embodiments, the random interrupt test apparatus 400 further includes: a conversion unit, configured to, after each triggering of the interrupt register by the random interrupt signal, convert the state of the interrupt register from a falling edge signal to a rising edge signal, and switch back to the falling edge signal state at a preset minimum value of the interrupt interval time.

[0088] It can be understood that the various units described in the apparatus 400 correspond to the respective steps in the method described with reference to Figure 1 Therefore, the operations, features, and beneficial effects described above for the method also apply to the apparatus 400 and the units included therein, and will not be elaborated herein.

[0089] Corresponding to the above method embodiment, in this embodiment, an electronic device is further provided. Please refer to Figure 5 which is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.

[0090] As Figure 5 shown, the electronic device 500 may include a processor 520 and a memory 510. The memory 510 is configured to store executable instructions; and the processor 520 is configured to operate the electronic device according to the control of the instructions to execute the method according to any embodiment of the present disclosure.

[0091] It should be noted that, in some embodiments of the present disclosure, the above-mentioned computer-readable medium may be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In some embodiments of the present disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In some embodiments of the present disclosure, the computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0092] In some embodiments, the client and the server can communicate using any currently known or future-developed network protocol such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include local area networks (“LAN”), wide area networks (“WAN”), the Internet (e.g., the Internet), and end-to-end networks (e.g., ad hoc end-to-end networks), as well as any currently known or future-developed networks.

[0093] The above computer-readable medium may be included in the above electronic device; or may exist separately without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device is caused to: generate interrupts through various interrupt generation mechanisms of the embedded operating system kernel; set a header information flag bit for the interrupts of the various interrupt generation mechanisms, and perform processing priority division according to the preset weights based on the header flag bit information to obtain a random interrupt signal processing sequence; add a random seed and send the random interrupt signals in the random interrupt signal processing sequence at random time intervals; the random interrupt signals sequentially trigger the interrupt register to perform a state switch; in response to the interrupt processor scanning the state switch of the interrupt register, determine to execute the interrupt program; calculate the random interrupt processing delay according to the embedded operating system kernel; and adjust the weight information corresponding to the header information flags of various interrupts according to the random interrupt processing delay.

[0094] Computer program code for performing the operations of some embodiments of the present disclosure may be written in one or more programming languages or combinations thereof. The above programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (for example, by using an Internet service provider to connect through the Internet).

[0095] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks may occur in an order different from that noted in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or by a combination of dedicated hardware and computer instructions.

[0096] The units described in some embodiments of the present disclosure can be implemented in software or in hardware. The described units can also be provided in a processor. For example, it can be described as: a processor includes a generating unit, a dividing unit, a transmitting unit, a switching unit, an executing unit, a calculating unit, and an adjusting unit. Among them, the names of these units do not constitute a limitation on the unit itself in some cases. For example, the generating unit can also be described as "the unit that generates interrupts through various interrupt generation mechanisms of the embedded operating system kernel".

[0097] The functions described above can be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), Systems on Chip (SOCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0098] The above description is only some preferred embodiments of the present disclosure and an explanation of the technical principles applied. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above inventive concept. For example, technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the embodiments of the present disclosure.

Claims

1. A random interruption test method, which is implemented under an embedded operating system, comprising: generating interruptions through various interruption generation mechanisms of the embedded operating system kernel; setting a header information flag bit for the interruptions of the various interruption generation mechanisms, and performing processing priority division according to a preset weight based on the header flag bit information to obtain a random interruption signal processing sequence; adding a random seed and sending the random interruption signals in the random interruption signal processing sequence at random time intervals; wherein the random interruption signals sequentially trigger the interruption register to perform state switching; responding to the interruption processor scanning the state switching of the interruption register, determining the execution of the interruption program; calculating the random interruption processing delay according to the embedded operating system kernel; adjusting the weight information corresponding to the header information flag bits of various interruptions according to the random interruption processing delay; wherein, the header information flag bit includes an interruption generation mechanism, an interruption entry address, an interruption task weight information, and a preset value of a random interruption interval. The step of setting a header information flag bit for the interruptions of the various interruption generation mechanisms and performing processing priority division according to a preset weight based on the header flag bit information to obtain a random interruption signal processing sequence includes: setting a header information flag bit for each of the interruption generation mechanisms; performing processing priority division on the random interruption signals corresponding to the header information flag bits according to the interruption task weight information in the header information flag bits to obtain the random interruption signal processing sequence.

2. The method according to claim 1, wherein, the step of generating interruptions through various interruption generation mechanisms of the embedded operating system kernel includes: generating random interruption signals according to multiple types of interruption generation mechanisms of the embedded operating system, wherein the interruption generation mechanisms include: a clock interruption mechanism, a registered interruption function mechanism, an input / output interruption mechanism, and a console interruption mechanism.

3. The method according to claim 1, wherein, each of the random interruption signals configures an interruption type and an interruption enable sequence through a random instruction configurator.

4. The method according to claim 3, wherein, the step of responding to the interruption processor scanning the state switching of the interruption register and determining the execution of the interruption program includes: the interruption processor scans the rising edge signal of the interruption register; based on the interruption entry address, accessing an interruption processing function and determining the execution of the interruption program.

5. The method according to claim 3, wherein, the method further includes: the random seed generates a pseudo-random number according to a preset value of a random interruption interval as the transmission time interval of the random interruption signal.

6. The method according to claim 1, wherein, the method further includes: after each trigger of the interruption register by the random interruption signal, the state of the interruption register is converted from a falling edge signal to a rising edge signal, and switches back to the falling edge signal state at the minimum preset value of the interruption interval time.

7. A random interruption test device, which is implemented under an embedded operating system, comprising: A generation unit for generating interrupts through various interrupt generation mechanisms of the embedded operating system kernel; A division unit for setting a header information flag bit for the interrupts of the various interrupt generation mechanisms, and performing a processing priority division according to a preset weight based on the header flag bit information to obtain a random interrupt signal processing sequence, where the header information flag bit includes an interrupt generation mechanism, an interrupt entry address, interrupt task weight information, and a preset value of a random interrupt interval; A sending unit for adding a random seed and sending a random interrupt signal in the random interrupt signal processing sequence at random time intervals; wherein the random interrupt signals sequentially trigger the interrupt register to perform a state switch; An execution unit for determining the execution of an interrupt program in response to the interrupt processor scanning the state switch of the interrupt register; A calculation unit for calculating a random interrupt processing delay according to the embedded operating system kernel; An adjustment unit for adjusting the weight information corresponding to the header information flag bits of various interrupts according to the random interrupt processing delay; The division unit is further configured to set a header information flag bit for each of the interrupt generation mechanisms; and perform a processing priority division on the random interrupt signals corresponding to the header information flag bits according to the interrupt task weight information in the header information flag bits to obtain the random interrupt signal processing sequence.

8. An electronic device, characterized in that, it includes: a memory for storing executable instructions; a processor for operating the electronic device to execute the method according to any one of claims 1-6 under the control of the instructions.

9. A computer-readable medium having a computer program stored thereon, wherein, the program, when executed by a processor, implements the method according to any one of claims 1-6.

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