Solid state drive offset voltage configuration method, system, device and storage medium

Abstract

The present invention relates to a solid state hard disk offset voltage configuration method, system, computer equipment and storage medium, the method comprising: starting the initialization process of the solid state hard disk to initialize the value of the register in the solid state hard disk; obtaining the offset voltage configuration table of the solid state hard disk, obtaining the offset voltage value corresponding to each logic unit from the offset voltage configuration table, and obtaining the register value corresponding to each logic unit from the register; subtracting the offset voltage value and the register value corresponding to each logic unit in turn, and performing absolute value processing to obtain the absolute value; comparing the absolute value with the offset voltage step reference value, if the absolute value corresponding to the logic unit is within the offset voltage step reference value, then there is no need to perform offset voltage configuration on the logic unit; if the absolute value corresponding to the logic unit is outside the offset voltage step reference value, then it is necessary to perform offset voltage configuration on the logic unit according to the offset voltage value. The present invention improves the performance of the solid state hard disk.

Description

Technical Field

[0001] The present invention relates to the field of solid state hard disks, and in particular to a solid state hard disk offset voltage configuration method, system, computer equipment and storage medium. Background Art

[0002] With the development and widespread application of technologies such as the Internet, cloud computing, and the Internet of Things, massive amounts of data are generated at all times in human life and need to be processed and stored. The rapid development of information technology has put forward higher requirements on the performance of storage systems.

[0003] Solid-state drives are widely used because of their fast read and write speeds and low energy consumption. As PE (program & erase endurance) increases, NAND (computer flash memory device) may be in an unstable state due to factors such as read interference, write interference, and data retention time, which triggers more data error correction processes, that is, a suitable read offset voltage needs to be configured before reading to ensure data accuracy. Especially when PE is high, this configuration method is very frequent, which will affect the current read latency and thus affect the performance of the solid-state drive. Summary of the invention

[0004] Based on this, it is necessary to provide a solid-state hard disk offset voltage configuration method, system, computer device and storage medium that can reduce read latency and improve solid-state hard disk performance in response to the above technical problems.

[0005] In one aspect, a solid state drive offset voltage configuration method is provided, the solid state drive offset voltage configuration method comprising:

[0006] Starting an initialization process of the solid state drive to initialize the values ​​of registers in the solid state drive;

[0007] Obtaining an offset voltage configuration table of the solid state drive, obtaining an offset voltage value corresponding to each logic unit from the offset voltage configuration table, and obtaining a register value corresponding to each logic unit from the register;

[0008] Subtracting the offset voltage value corresponding to each logic unit from the register value in turn, and performing absolute value processing to obtain an absolute value;

[0009] Comparing the absolute value with an offset voltage step reference value, if the absolute value corresponding to the logic unit is within the offset voltage step reference value, then there is no need to perform offset voltage configuration on the logic unit;

[0010] If the absolute value corresponding to the logic unit is outside the offset voltage step reference value, it is necessary to perform offset voltage configuration on the logic unit according to the offset voltage value.

[0011] In one of the embodiments, before comparing the absolute value with the offset voltage step reference value, the method further comprises:

[0012] The offset voltage step reference value is obtained.

[0013] In one embodiment, obtaining the offset voltage step reference value includes:

[0014] Selecting data block samples from computer flash memory device particles of the solid state drive and setting different offset voltage test step sizes;

[0015] Performing a read disturbance test on the data block sample at different offset voltage test step lengths to obtain corresponding bit error numbers at different offset voltage test step lengths;

[0016] The corresponding bit error rates under different offset voltage test step sizes are obtained by calculation.

[0017] In one embodiment, obtaining the offset voltage step reference value further includes:

[0018] Obtaining a maximum bit error rate that can be accommodated by the maximum error correction capability of the solid state drive from the bit error rates corresponding to different offset voltage test step sizes;

[0019] Obtaining the offset voltage test step length corresponding to the maximum bit error rate;

[0020] The offset voltage test step length is used as the offset voltage step length reference value.

[0021] In one embodiment, the solid state drive uses different error correction algorithms to perform error correction processing, and the step of obtaining the offset voltage step reference value further includes:

[0022] Different error correction algorithms are adopted to test the data block samples to obtain offset voltage step reference values ​​corresponding to different error correction algorithms.

[0023] In one embodiment, the solid state drive offset voltage configuration method further includes:

[0024] The configuration criteria of the read disturbance and data retention time are configured.

[0025] In one embodiment, the solid state drive offset voltage configuration method further includes:

[0026] When the actual read disturbance and data retention time of the solid state hard disk do not meet the configuration standard, comparing the absolute value corresponding to each of the logic units with the offset voltage step reference value;

[0027] If the absolute value corresponding to the logic unit is within the offset voltage step reference value, there is no need to perform offset voltage configuration on the logic unit;

[0028] If the absolute value corresponding to the logic unit is outside the offset voltage step reference value, the offset voltage configuration needs to be performed on the logic unit according to zero.

[0029] On the other hand, a solid state drive offset voltage configuration system is provided, the solid state drive offset voltage configuration system comprising:

[0030] An initialization module, used to start the initialization process of the solid state drive to initialize the values ​​of the registers in the solid state drive;

[0031] An information processing module, used to obtain an offset voltage configuration table of the solid state drive, obtain an offset voltage value corresponding to each logic unit from the offset voltage configuration table, and obtain a register value corresponding to each logic unit from the register;

[0032] A numerical comparison module, used for sequentially subtracting the offset voltage value corresponding to each of the logic units from the register value, performing absolute value processing to obtain an absolute value, and comparing the absolute value with an offset voltage step reference value;

[0033] The voltage configuration module is used to perform offset voltage configuration on the logic unit.

[0034] In another aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the following steps are implemented:

[0035] Starting an initialization process of the solid state drive to initialize the values ​​of registers in the solid state drive;

[0036] Obtaining an offset voltage configuration table of the solid state drive, obtaining an offset voltage value corresponding to each logic unit from the offset voltage configuration table, and obtaining a register value corresponding to each logic unit from the register;

[0037] Subtracting the offset voltage value corresponding to each logic unit from the register value in turn, and performing absolute value processing to obtain an absolute value;

[0038] Comparing the absolute value with an offset voltage step reference value, if the absolute value corresponding to the logic unit is within the offset voltage step reference value, then there is no need to perform offset voltage configuration on the logic unit;

[0039] If the absolute value corresponding to the logic unit is outside the offset voltage step reference value, it is necessary to perform offset voltage configuration on the logic unit according to the offset voltage value.

[0040] On the other hand, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a program, and when the program is executed by a processor, the processor performs the following steps:

[0041] Starting an initialization process of the solid state drive to initialize the values ​​of registers in the solid state drive;

[0042] Obtaining an offset voltage configuration table of the solid state drive, obtaining an offset voltage value corresponding to each logic unit from the offset voltage configuration table, and obtaining a register value corresponding to each logic unit from the register;

[0043] Subtracting the offset voltage value corresponding to each logic unit from the register value in turn, and performing absolute value processing to obtain an absolute value;

[0044] Comparing the absolute value with an offset voltage step reference value, if the absolute value corresponding to the logic unit is within the offset voltage step reference value, then there is no need to perform offset voltage configuration on the logic unit;

[0045] If the absolute value corresponding to the logic unit is outside the offset voltage step reference value, it is necessary to perform offset voltage configuration on the logic unit according to the offset voltage value.

[0046] The above technical solution of the present invention has the following advantages compared with the prior art:

[0047] The above-mentioned solid-state hard disk offset voltage configuration method, system, computer device and storage medium first obtain the offset voltage value and register value corresponding to each logical unit of the solid-state hard disk, then make a difference between the offset voltage value and the register value and perform absolute value processing on the difference, the absolute value reflects the degree of deviation of the offset voltage value relative to the register value, and the degree of deviation reflects the bit error rate of the data, and the degree of deviation of the offset voltage value relative to the register value is controlled within the error correction capability of the solid-state hard disk algorithm, that is, the absolute value is controlled within the offset voltage step reference value; if the absolute value is within the offset voltage step reference value, there is no need to configure the offset voltage, and error correction processing can be performed through the algorithm, which not only ensures the correctness of data reading, but also reduces the number of configuration times of the offset voltage, reduces the read delay, and improves the performance of the solid-state hard disk. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0049] Figure 1 is a first method flow chart of the solid state hard disk offset voltage configuration method of the present invention;

[0050] Figure 2 is a flow chart of a second method of configuring the offset voltage of a solid state hard disk of the present invention;

[0051] Figure 3 is a system structure diagram of a solid state hard disk offset voltage configuration system of the present invention;

[0052] Figure 4 It is a device structure diagram of the computer device of the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0054] Solid-state hard disks are widely used because of their fast read and write speeds and low energy consumption. With the increase of PE (program & erase endurance), affected by read interference, write interference, data retention time and other factors, NAND (computer flash memory device) may be in an unstable state, which is manifested as triggering more data error correction processes, that is, a suitable read offset voltage needs to be configured before reading to ensure the accuracy of the data. Especially when PE is high, this configuration method is very frequent, which will affect the current read delay and further affect the performance. Therefore, the present invention proposes a solid-state hard disk offset voltage configuration method, system, computer device and storage medium, which reduces the number of configurations when configuring the offset voltage of the solid-state hard disk to reduce the read delay and effectively improve the performance of the solid-state hard disk.

[0055] Embodiment 1:

[0056] The method of this embodiment refers to Figure 1-2 As shown, Figure 1 A first method flow chart of the solid state hard disk offset voltage configuration method of the present invention; Figure 2 This is a second method flow chart of the solid state hard disk offset voltage configuration method of the present invention.

[0057] The method comprises the following steps:

[0058] Starting an initialization process of the solid state drive to initialize the values ​​of registers in the solid state drive;

[0059] Start the initialization process of the solid-state drive to initialize the values ​​of the registers in the solid-state drive, that is, set the values ​​of the registers to 0, so that the offset voltage value in the offset voltage configuration table can be compared with the register value to determine whether the offset voltage configuration is required. By comparing and judging the offset voltage value with the register value, the logic units that do not need to be configured with the offset voltage are excluded, so as to reduce the number of configurations, reduce the read delay, and effectively improve the performance of the solid-state drive.

[0060] Obtaining an offset voltage configuration table of the solid state drive, obtaining an offset voltage value corresponding to each logic unit from the offset voltage configuration table, and obtaining a register value corresponding to each logic unit from the register;

[0061] After initializing the register values ​​in the solid-state drive, obtain the offset voltage configuration table of the solid-state drive. The offset voltage configuration table stores the offset voltage value that needs to be configured for each logic unit. Therefore, after obtaining the offset voltage configuration table, the offset voltage value corresponding to each logic unit can be obtained from the offset voltage configuration table; then obtain the register value corresponding to each logic unit from the register. At this time, the register value has been initialized, so the register value is 0.

[0062] Subtracting the offset voltage value corresponding to each logic unit from the register value in turn, and performing absolute value processing to obtain an absolute value;

[0063] After obtaining the offset voltage value corresponding to the logic unit and the register value corresponding to the logic unit, the offset voltage value and the register value corresponding to the logic unit are subtracted to obtain a difference value, and the difference value is processed by absolute value to obtain the absolute value of the difference value. The absolute value reflects the degree of deviation of the offset voltage value relative to the register value. The greater the deviation, the higher the read operation error rate.

[0064] Comparing the absolute value with an offset voltage step reference value, if the absolute value corresponding to the logic unit is within the offset voltage step reference value, then there is no need to perform offset voltage configuration on the logic unit;

[0065] If the absolute value corresponding to the logic unit is outside the offset voltage step reference value, it is necessary to perform offset voltage configuration on the logic unit according to the offset voltage value.

[0066] After obtaining the offset voltage value corresponding to each logic unit and the register value corresponding to each logic unit, it is necessary to compare the absolute value corresponding to each logic unit with the offset voltage step reference value in turn to determine whether the absolute value corresponding to the logic unit is within the offset voltage step reference value; if the absolute value corresponding to the logic unit is within the offset voltage step reference value, it means that the bit error rate corresponding to the logic unit can be corrected normally, and there is no need to perform offset voltage configuration on the logic unit, which reduces the number of offset voltage configurations; if the absolute value corresponding to the logic unit is within the offset voltage step reference value, it means that the bit error rate corresponding to the logic unit cannot be corrected normally, and the offset voltage configuration needs to be performed on the logic unit according to the offset voltage value. Among them, performing offset voltage configuration according to the offset voltage value means modifying the register value corresponding to the logic unit to the offset voltage value to ensure the correctness of data reading. The solid state drive includes multiple logical units (Logical Unit Number, LUN), which is the smallest unit for directly executing commands. The computer device flash memory in the solid state drive includes three types, SLC, MLC and TLC. Each type of logical unit can be configured with an offset voltage according to the solid state drive offset voltage configuration method of the present invention.

[0067] In one of the embodiments, before comparing the absolute value with the offset voltage step reference value, it also includes:

[0068] The offset voltage step reference value is obtained.

[0069] When the corresponding absolute value of each logic unit is compared with the offset voltage step reference value, it is necessary to obtain the absolute value corresponding to the logic unit and then determine whether the absolute value is within the offset voltage step reference value. Therefore, the offset voltage step reference value must be obtained first.

[0070] In one implementation manner, obtaining the offset voltage step reference value includes:

[0071] Selecting data block samples from computer flash memory device particles of the solid state drive and setting different offset voltage test step sizes;

[0072] The acquisition of the offset voltage step reference value needs to be obtained in advance through test data. First, a data block sample must be selected from the computer flash memory device particles of the solid-state drive, and then different offset voltage test steps must be set to test the data block sample at different offset voltage test steps through the offset configuration voltage. Among them, different offset voltage test steps refer to the absolute value of the difference between the offset voltage value and the register value. The absolute value reflects the degree of deviation of the offset voltage value relative to the register value, and the offset voltage test step also reflects the degree of deviation of the offset voltage value relative to the register value.

[0073] Performing a read disturbance test on the data block sample at different offset voltage test step lengths to obtain corresponding bit error numbers at different offset voltage test step lengths;

[0074] After selecting data block samples and setting different offset voltage test step lengths, read interference tests are performed on the data block samples at different offset voltage test step lengths through the offset configuration voltage to obtain the corresponding number of bit errors at different offset voltage test step lengths, so as to obtain the corresponding bit error rates at different offset voltage test step lengths.

[0075] The corresponding bit error rates under different offset voltage test step sizes are obtained by calculation.

[0076] After obtaining the corresponding bit error numbers under different offset voltage test step lengths, the corresponding bit error rates under different offset voltage test step lengths are obtained by calculation, so as to obtain the offset voltage step length reference value through the bit error rate and the offset voltage test step length.

[0077] In one embodiment, obtaining the offset voltage step reference value further includes:

[0078] Obtaining a maximum bit error rate that can be accommodated by the maximum error correction capability of the solid state drive from the bit error rates corresponding to different offset voltage test step sizes;

[0079] Each offset voltage test step gets a corresponding bit error rate after the data block test. The larger the offset voltage test step, that is, the larger the absolute value of the difference between the offset voltage value and the register value, the greater the bit error rate. When performing a read operation, the solid-state drive will use an algorithm to perform error correction processing on the erroneous data, and the algorithm itself has a certain error correction capability. If the bit error rate is too large, it will exceed the error correction capability of the solid-state drive algorithm itself, and the data cannot be read correctly at this time. For example, the error correction capability of the algorithm itself is A, and the maximum bit error rate that can be corrected within the error correction capability A is B. As long as the bit error rate is within B, the error correction algorithm can correct the data. Then B is the maximum bit error rate that can be accommodated by the maximum error correction capability of the solid-state drive.

[0080] Obtaining the offset voltage test step length corresponding to the maximum bit error rate;

[0081] After obtaining the maximum bit error rate that can be accommodated by the maximum error correction capability of the solid state drive, the offset voltage test step length corresponding to the maximum bit error rate during the read interference test is obtained.

[0082] The offset voltage test step length is used as the offset voltage step length reference value.

[0083] The offset voltage test step length corresponding to the maximum bit error rate is obtained, and the offset voltage test step length is used as the offset voltage step length reference value. That is, when the absolute value of the difference between the offset voltage value corresponding to the logic unit and the register value is within the offset voltage step length reference value, it means that the bit error rate is within the error correction capability of the solid state drive, and the algorithm can be used to perform error correction processing to read data normally; when the absolute value of the difference between the offset voltage value corresponding to the logic unit and the register value is outside the offset voltage step length reference value, it means that the bit error rate exceeds the error correction capability of the solid state drive, and the algorithm cannot be used to perform error correction processing. Therefore, the offset voltage step length reference value is used as a judgment standard for offset voltage configuration, so as to reduce the number of offset voltage configurations and improve the performance of the solid state drive while ensuring the error correction capability of the solid state drive. For example, the offset voltage test step sizes are 0, 1, 2, 4, and 6, and the corresponding bit error rates are 0.2%, 2%, 5%, 7%, and 10%, respectively. If the algorithm's error correction capability can only handle a bit error rate within 6%, then the maximum bit error rate that the algorithm can accommodate is 5%. The offset voltage test step size of 2 corresponding to the 5% bit error rate is used as a reference value for the offset voltage test step size. If the absolute value of the difference between the offset voltage value and the register value corresponding to the logic unit is within 2, it means that the bit error rate is within the error correction capability of the solid-state drive and can be corrected by the algorithm to read data normally. If the absolute value of the difference between the offset voltage value and the register value corresponding to the logic unit is outside 2, it means that the bit error rate exceeds the error correction capability of the solid-state drive and cannot be corrected by the algorithm. The offset voltage is configured according to the offset voltage value to ensure the accuracy of data reading.

[0084] In one embodiment, the solid state drive uses different error correction algorithms to perform error correction processing, and the step of obtaining the offset voltage step reference value further includes:

[0085] Different error correction algorithms are adopted to test the data block samples to obtain offset voltage step reference values ​​corresponding to different error correction algorithms.

[0086] The solid-state drive itself will be configured with an error correction algorithm to perform data error correction processing. There are many error correction algorithms, and different error correction algorithms correspond to different error correction capabilities. Therefore, different error correction algorithms can accommodate different maximum bit error rates. Algorithms with strong error correction capabilities can accommodate higher bit error rates, so their corresponding offset voltage step reference values ​​will also be different. Therefore, different error correction algorithms are used to perform read interference tests on the data block samples to obtain offset voltage step reference values ​​corresponding to different error correction algorithms.

[0087] In one embodiment, the solid state drive offset voltage configuration method further includes:

[0088] The configuration standard of the read disturbance and data retention time is obtained.

[0089] In order to reduce the possibility of data errors during read operations, the configuration standards for read interference and data retention time must be determined. The offset voltage is configured as 0 within the standard, and the offset voltage is configured according to the offset voltage value when it exceeds the standard. Generally, the data retention time of the solid-state drive is set to 18 days. If the data retention time does not exceed 18 days, it means that the data has not been written for more than 18 days, and the bit error rate is low; the number of reads of the solid-state drive is set to 100,000 times. If the number of reads of the solid-state drive does not exceed 100,000 times, it means that the number of data reads is low and the bit error rate is also low; therefore, the configuration standards for read interference and data retention time must be set. The logic units within the configuration standards are configured with an offset voltage of 0, which can reduce the possibility of data read operation errors and reduce the number of configurations of the offset voltage.

[0090] In one embodiment, the solid state drive offset voltage configuration method further includes:

[0091] When the actual read disturbance and data retention time of the solid state hard disk do not reach the configuration standard, comparing the corresponding absolute value of each of the logic units with the offset voltage step reference value;

[0092] If the absolute value corresponding to the logic unit is within the offset voltage step reference value, there is no need to perform offset voltage configuration on the logic unit;

[0093] If the absolute value corresponding to the logic unit is outside the offset voltage step reference value, the offset voltage configuration needs to be performed on the logic unit according to zero.

[0094] When this configuration standard is not met, if the absolute value of the offset voltage value corresponding to the logic unit minus the register value is outside the offset voltage step reference value, the offset voltage configuration is performed according to 0 to reduce the possibility of data read operation errors and reduce the number of offset voltage configuration times; when this configuration standard is met, if the absolute value corresponding to the logic unit is within the offset voltage step reference value, it means that the probability of bit errors is relatively high. In order to ensure the correctness of data reading, the offset voltage configuration must be performed according to the offset voltage value in the offset voltage configuration table.

[0095] Embodiment 2:

[0096] Reference Figure 2 As shown, Figure 2 This is a second method flow chart of the solid state hard disk offset voltage configuration method of the present invention.

[0097] Starting an initialization process of the solid state drive to initialize the values ​​of registers in the solid state drive;

[0098] Start the initialization process of the solid-state drive to initialize the values ​​of the registers in the solid-state drive, that is, set the values ​​of the registers to 0, so that the offset voltage value in the offset voltage configuration table can be compared with the register value to determine whether the offset voltage configuration is required. By comparing and judging the offset voltage value with the register value, the logic units that do not need to be configured with the offset voltage are excluded, so as to reduce the number of configurations, reduce the read delay, and effectively improve the performance of the solid-state drive.

[0099] Obtaining an offset voltage configuration table of the solid state drive, obtaining an offset voltage value corresponding to each logic unit from the offset voltage configuration table, and obtaining a register value corresponding to each logic unit from the register;

[0100] After initializing the register values ​​in the solid-state drive, obtain the offset voltage configuration table of the solid-state drive. The offset voltage configuration table stores the offset voltage value that needs to be configured for each logic unit. Therefore, after obtaining the offset voltage configuration table, the offset voltage value corresponding to each logic unit can be obtained from the offset voltage configuration table; then obtain the register value corresponding to each logic unit from the register. At this time, the register value has been initialized, so the register value is 0.

[0101] Selecting data block samples from computer flash memory device particles of the solid state drive and setting different offset voltage test step sizes;

[0102] The acquisition of the offset voltage step reference value needs to be obtained in advance through test data. First, a data block sample is selected from the computer flash memory device particles of the solid-state drive, and then different offset voltage test steps are set to test the data block sample under different offset voltage test steps through the offset configuration voltage.

[0103] Performing a read disturbance test on the data block sample at different offset voltage test step lengths to obtain corresponding bit error numbers at different offset voltage test step lengths;

[0104] After selecting data block samples and setting different offset voltage test step lengths, read interference tests are performed on the data block samples at different offset voltage test step lengths through the offset configuration voltage to obtain the corresponding number of bit errors at different offset voltage test step lengths, so as to obtain the corresponding bit error rates at different offset voltage test step lengths.

[0105] The corresponding bit error rate under different offset voltage test step lengths is obtained by calculation;

[0106] After obtaining the corresponding bit error numbers under different offset voltage test step lengths, the corresponding bit error rates under different offset voltage test step lengths are obtained by calculation, so as to obtain the offset voltage step length reference value through the bit error rate and the offset voltage test step length.

[0107] Obtaining a maximum bit error rate that can be accommodated by the maximum error correction capability of the solid state drive from the bit error rates corresponding to different offset voltage test step sizes;

[0108] Each offset voltage test step gets a corresponding bit error rate after the data block test. The larger the offset voltage test step, that is, the larger the absolute value of the difference between the offset voltage value and the register value, the greater the bit error rate. When performing a read operation, the solid-state drive will use an algorithm to perform error correction processing on the error data, and the algorithm itself has a certain error correction capability. If the bit error rate is too large, it will exceed the error correction capability of the solid-state drive algorithm itself, and the data cannot be read correctly at this time. Therefore, it is necessary to obtain the maximum bit error rate that the algorithm's error correction capability can accommodate while ensuring the algorithm's own error correction capability.

[0109] Obtaining the offset voltage test step length corresponding to the maximum bit error rate;

[0110] After obtaining the maximum bit error rate that can be accommodated by the maximum error correction capability of the solid state drive, the offset voltage test step length corresponding to the maximum bit error rate during the read interference test is obtained.

[0111] Using the offset voltage test step length as the offset voltage step length reference value;

[0112] The offset voltage test step length during the test corresponding to the maximum bit error rate is obtained, and the offset voltage test step length is used as an offset voltage step length reference value.

[0113] Configuring the configuration standard of the read disturbance and data retention time;

[0114] In order to reduce the possibility of data errors during read operations, the configuration standards for read interference and data retention time must be determined. The offset voltage is configured as 0 within the standard, and the offset voltage is configured according to the offset voltage value when it exceeds the standard. Generally, the data retention time of the solid-state drive is set to 18 days. If the data retention time does not exceed 18 days, it means that the data has not been written for more than 18 days, and the bit error rate is low; the number of reads of the solid-state drive is set to 100,000 times. If the number of reads of the solid-state drive does not exceed 100,000 times, it means that the number of data reads is low and the bit error rate is also low; therefore, the configuration standards for read interference and data retention time must be set. The logic units within the configuration standards are configured with an offset voltage of 0, which can reduce the possibility of data read operation errors and reduce the number of configurations of the offset voltage.

[0115] Determine whether the actual read disturbance and data retention time of the solid state drive meet the configuration standards;

[0116] When the actual read disturbance and data retention time of the solid state hard disk do not reach the configuration standard, comparing the corresponding absolute value of each of the logic units with the offset voltage step reference value;

[0117] When the actual read disturbance and data retention time of the solid state drive do not meet the configuration standard, the corresponding absolute value of each logic unit continues to be compared with the register value to determine different voltage configuration modes.

[0118] If the absolute value corresponding to the logic unit is within the offset voltage step reference value, there is no need to perform offset voltage configuration on the logic unit;

[0119] If the absolute value corresponding to the logic unit is within the offset voltage step reference value, it means that the bit error rate corresponding to the logic unit can be corrected normally, and there is no need to perform offset voltage configuration on the logic unit, thereby reducing the number of offset voltage configuration times.

[0120] If the absolute value corresponding to the logic unit is outside the offset voltage step reference value, the offset voltage configuration of the logic unit needs to be performed according to zero;

[0121] When the actual read disturbance and data retention time of the solid-state hard disk do not meet the configuration standard, if the absolute value corresponding to the logic unit is outside the offset voltage step reference value, the offset voltage configuration is performed according to 0 to reduce the possibility of data read operation errors and reduce the number of offset voltage configuration times.

[0122] When the actual read disturbance and data retention time of the solid state hard disk reach the configuration standard, comparing the corresponding absolute value of each of the logic units with the offset voltage step reference value;

[0123] When the actual read disturbance and data retention time of the solid state drive do not meet the configuration standard, the corresponding absolute value of each logic unit continues to be compared with the register value to determine the logic unit that needs to be configured with the offset voltage.

[0124] If the absolute value corresponding to the logic unit is within the offset voltage step reference value, there is no need to perform offset voltage configuration on the logic unit;

[0125] If the absolute value corresponding to the logic unit is within the offset voltage step reference value, it means that the bit error rate corresponding to the logic unit can be corrected normally, and there is no need to perform offset voltage configuration on the logic unit, thereby reducing the number of offset voltage configuration times.

[0126] If the absolute value corresponding to the logic unit is outside the offset voltage step reference value, it is necessary to perform offset voltage configuration on the logic unit according to the offset voltage value.

[0127] If the absolute value corresponding to the logic unit is within the offset voltage step reference value, it means that the bit error rate corresponding to the logic unit cannot be corrected normally, and the offset voltage configuration of the logic unit needs to be performed according to the offset voltage value so that the read operation can read correct data.

[0128] It should be understood that although Figures 1-2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figures 1-2 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0129] Embodiment three:

[0130] Reference Figure 3 As shown, Figure 3 A system structure diagram of the solid state hard disk offset voltage configuration system of the present invention.

[0131] The solid state drive offset voltage configuration system of this embodiment includes:

[0132] An initialization module, used to start the initialization process of the solid state drive to initialize the values ​​of the registers in the solid state drive;

[0133] The initialization process of the solid-state drive is started through the initialization module to initialize the values ​​of the registers in the solid-state drive, that is, the values ​​of the registers are set to 0, so that the offset voltage value in the offset voltage configuration table is compared with the value of the register to determine whether the offset voltage configuration is required. By comparing and judging the offset voltage value with the register value, the logic units that do not need to be configured with the offset voltage are excluded, so as to reduce the number of configurations, reduce the read delay, and effectively improve the performance of the solid-state drive.

[0134] An information processing module, used to obtain an offset voltage configuration table of the solid state drive, obtain an offset voltage value corresponding to each logic unit from the offset voltage configuration table, and obtain a register value corresponding to each logic unit from the register;

[0135] After initializing the register value in the solid-state drive, the offset voltage configuration table of the solid-state drive is obtained through the information processing module. The offset voltage configuration table stores the offset voltage value that needs to be configured for each logic unit. Therefore, after obtaining the offset voltage configuration table, the offset voltage value corresponding to each logic unit can be obtained from the offset voltage configuration table; then the register value corresponding to each logic unit is obtained from the register through the information processing module. At this time, the register value has been initialized, so the register value is 0.

[0136] A numerical comparison module, used for sequentially subtracting the offset voltage value corresponding to each of the logic units from the register value, performing absolute value processing to obtain an absolute value, and comparing the absolute value with an offset voltage step reference value;

[0137] After obtaining the offset voltage value corresponding to the logic unit and the register value corresponding to the logic unit, the offset voltage value and the register value corresponding to the logic unit are subtracted through the numerical comparison module to obtain a difference value, and the difference value is processed by absolute value to obtain the absolute value of the difference value. The absolute value reflects the degree of deviation of the offset voltage value relative to the register value. The greater the deviation, the higher the read operation error rate; and the numerical comparison module compares the absolute value with the offset voltage step reference value.

[0138] The voltage configuration module is used to perform offset voltage configuration on the logic unit.

[0139] When the configuration standards for read interference and data retention time are not met, if the absolute value of the offset voltage value corresponding to the logic unit minus the register value is outside the offset voltage step reference value, the voltage configuration module performs the offset voltage configuration according to 0 to reduce the possibility of data read operation errors and reduce the number of offset voltage configuration times; when this configuration standard is met, if the absolute value corresponding to the logic unit is within the offset voltage step reference value, it means that the probability of bit errors is high. In order to ensure the correctness of data reading, the voltage configuration module must perform the offset voltage configuration according to the offset voltage value in the offset voltage configuration table.

[0140] In one embodiment, the solid state drive offset voltage configuration system further includes:

[0141] A data testing module, used for testing a data block to obtain a reference value of an offset voltage step length;

[0142] The acquisition of the offset voltage step reference value needs to be obtained in advance through test data, and a read interference test is performed on the data block sample through the data test module under different offset voltage test steps to obtain the corresponding number of bit errors under different offset voltage test steps, so as to obtain the corresponding bit error rate under different offset voltage test steps, obtain the offset voltage test step corresponding to the maximum bit error rate, and use the offset voltage test step as the offset voltage step reference value.

[0143] The standard configuration module is used to configure the configuration standards of the read disturbance and data retention time.

[0144] In order to reduce the possibility of data errors during read operations, the configuration standards for read interference and data retention time should be determined through the standard configuration module. The offset voltage should be configured as 0 within the standard, and the offset voltage should be configured as the offset voltage value when it exceeds the standard. Generally, the data retention time of the solid-state drive is set to 18 days. If the data retention time does not exceed 18 days, it means that the data writing has not exceeded 18 days, and the bit error rate is low; the number of reads of the solid-state drive is set to 100,000 times. If the number of reads of the solid-state drive does not exceed 100,000 times, it means that the number of data reads is low and the bit error rate is also low; therefore, the configuration standards for read interference and data retention time should be set. The logic units within the configuration standard should be configured with an offset voltage of 0, which can reduce the possibility of data read operation errors and reduce the number of configurations of the offset voltage.

[0145] The specific definition of the SSD offset voltage configuration system can be found in the definition of the method above, which will not be repeated here. Each module in the above-mentioned SSD offset voltage configuration system can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0146] Embodiment 4:

[0147] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of a solid state hard disk offset voltage configuration method when executing the computer program.

[0148] The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 4As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a solid-state hard disk offset voltage configuration method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0149] Those skilled in the art should understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0150] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the following steps are implemented:

[0151] Starting an initialization process of the solid state drive to initialize the values ​​of registers in the solid state drive;

[0152] Obtaining an offset voltage configuration table of the solid state drive, obtaining an offset voltage value corresponding to each logic unit from the offset voltage configuration table, and obtaining a register value corresponding to each logic unit from the register;

[0153] Subtracting the offset voltage value corresponding to each logic unit from the register value in turn, and performing absolute value processing to obtain an absolute value;

[0154] Comparing the absolute value with an offset voltage step reference value, if the absolute value corresponding to the logic unit is within the offset voltage step reference value, then there is no need to perform offset voltage configuration on the logic unit;

[0155] If the absolute value corresponding to the logic unit is outside the offset voltage step reference value, it is necessary to perform offset voltage configuration on the logic unit according to the offset voltage value.

[0156] Embodiment five:

[0157] This embodiment provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0158] Starting an initialization process of the solid state drive to initialize the values ​​of registers in the solid state drive;

[0159] Obtaining an offset voltage configuration table of the solid state drive, obtaining an offset voltage value corresponding to each logic unit from the offset voltage configuration table, and obtaining a register value corresponding to each logic unit from the register;

[0160] Subtracting the offset voltage value corresponding to each logic unit from the register value in turn, and performing absolute value processing to obtain an absolute value;

[0161] Comparing the absolute value with an offset voltage step reference value, if the absolute value corresponding to the logic unit is within the offset voltage step reference value, then there is no need to perform offset voltage configuration on the logic unit;

[0162] If the absolute value corresponding to the logic unit is outside the offset voltage step reference value, it is necessary to perform offset voltage configuration on the logic unit according to the offset voltage value.

[0163] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0164] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0165] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for configuring a solid state hard disk offset voltage, It is characterized in that The solid state hard disk offset voltage configuration method comprises: Starting an initialization process of the solid state drive to initialize the values ​​of registers in the solid state drive; Obtaining an offset voltage configuration table of the solid state drive, obtaining an offset voltage value corresponding to each logic unit from the offset voltage configuration table, and obtaining a register value corresponding to each logic unit from the register; Subtracting the offset voltage value corresponding to each logic unit from the register value in turn, and performing absolute value processing to obtain an absolute value; Get the offset voltage step reference value; Comparing the absolute value with the offset voltage step reference value, if the absolute value corresponding to the logic unit is within the offset voltage step reference value, then there is no need to perform offset voltage configuration on the logic unit; If the absolute value corresponding to the logic unit is outside the offset voltage step reference value, the offset voltage configuration of the logic unit needs to be performed according to the offset voltage value; Wherein, obtaining the offset voltage step reference value includes: Selecting data block samples from computer flash memory device particles of the solid state drive and setting different offset voltage test step sizes; Performing a read disturbance test on the data block sample at different offset voltage test step lengths to obtain corresponding bit error numbers at different offset voltage test step lengths; The corresponding bit error rate under different offset voltage test step lengths is obtained by calculation; Obtaining a maximum bit error rate that can be accommodated by the maximum error correction capability of the solid state drive from the bit error rates corresponding to different offset voltage test step sizes; Obtaining the offset voltage test step length corresponding to the maximum bit error rate; The offset voltage test step length is used as the offset voltage step length reference value.

2. The solid state hard disk offset voltage configuration method according to claim 1, It is characterized in that The solid state drive uses different error correction algorithms to perform error correction processing, and the step of obtaining the offset voltage step reference value also includes: Different error correction algorithms are adopted to test the data block samples to obtain offset voltage step reference values ​​corresponding to different error correction algorithms.

3. The solid state hard disk offset voltage configuration method according to claim 1, It is characterized in that The solid state hard disk offset voltage configuration method further includes: The configuration criteria of the read disturbance and data retention time are configured.

4. The solid state hard disk offset voltage configuration method according to claim 3, It is characterized in that The solid state hard disk offset voltage configuration method further includes: When the actual read disturbance and data retention time of the solid state hard disk do not meet the configuration standard, comparing the absolute value corresponding to each of the logic units with the offset voltage step reference value; If the absolute value corresponding to the logic unit is within the offset voltage step reference value, there is no need to perform offset voltage configuration on the logic unit; If the absolute value corresponding to the logic unit is outside the offset voltage step reference value, the offset voltage configuration needs to be performed on the logic unit according to zero.

5. A solid state hard disk offset voltage configuration system based on the method according to any one of claims 1 to 4, It is characterized in that The solid state drive offset voltage configuration system comprises: An initialization module, used to start the initialization process of the solid state drive to initialize the values ​​of the registers in the solid state drive; An information processing module, used to obtain an offset voltage configuration table of the solid state drive, obtain an offset voltage value corresponding to each logic unit from the offset voltage configuration table, and obtain a register value corresponding to each logic unit from the register; A numerical comparison module, used for sequentially subtracting the offset voltage value corresponding to each of the logic units from the register value, performing absolute value processing to obtain an absolute value, and comparing the absolute value with an offset voltage step reference value; The voltage configuration module is used to perform offset voltage configuration on the logic unit.

6. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, It is characterized in that When the processor executes the computer program, the steps of the method according to any one of claims 1 to 4 are implemented.

7. A computer-readable storage medium, Features: The computer-readable storage medium stores a program, and when the program is executed by a processor, the processor is caused to execute the steps of the method according to any one of claims 1 to 4.

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