Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel. The array substrate includes a base and a thin film transistor arranged on one side of the base. Through the induction of external or internal light by the thin film transistor, the gate turn-on voltage of the thin film transistor can be reduced, thereby reducing the power consumption of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In recent years, liquid crystal display (LCD) panels have been widely used in many fields and continue to show a rapid growth trend. Liquid crystal display devices with thin film transistors distributed in a matrix pattern in each pixel of the LCD panel are now widely used. In this active matrix LCD panel, the thin film transistors are switched on and off by applying a scan pulse and the voltage applied by the data line to the pixel electrode is used to flip the liquid crystal in the corresponding position in the liquid crystal layer to achieve the purpose of display.

[0003] When a positive voltage is input to the data line connected to the source of a thin-film transistor, the source voltage of the thin-film transistor is equivalent to a positive voltage. To turn on the thin-film transistor, a large turn-on voltage must be applied to the gate of the thin-film transistor to ensure that the voltage difference between the gate and the source exceeds the turn-on threshold of the thin-film transistor. Since thin-film transistors generally require a large gate turn-on voltage, a large amount of power is consumed within the thin-film transistor.

[0004] In summary, existing display panels have the problem of increased power consumption due to the high gate turn-on voltage of thin film transistors. Therefore, it is necessary to provide an array substrate and a display panel to improve this defect. Summary of the Invention

[0005] Embodiments of the present application provide an array substrate and a display panel, which can reduce the gate turn-on voltage of a thin film transistor, thereby reducing the power consumption of the display panel.

[0006] An embodiment of the present application provides an array substrate, comprising:

[0007] substrate;

[0008] A thin film transistor is disposed on one side of the substrate, and the thin film transistor includes:

[0009] gate;

[0010] an active layer, disposed on one side of the gate;

[0011] a source electrode, disposed on a side of the active layer away from the gate and in contact with the active layer;

[0012] a drain electrode, disposed on a side of the active layer away from the gate and in contact with the active layer, with a gap between the source electrode and the drain electrode;

[0013] a quasi-ohmic contact layer, disposed on a side of the active layer away from the gate, the quasi-ohmic contact layer being electrically connected to the drain; and

[0014] The photosensitive semiconductor layer is arranged on a side of the active layer away from the gate, and the photosensitive semiconductor layer is electrically connected to the source electrode and the quasi-ohmic contact layer respectively.

[0015] According to one embodiment of the present application, one end of the quasi-ohmic contact layer is overlapped on the side of the drain electrode facing away from the active layer, and the opposite ends of the photosensitive semiconductor layer are respectively overlapped on the side of the source electrode facing away from the ohmic contact layer and the side of the quasi-ohmic contact layer facing away from the active layer.

[0016] By adding a photosensitive semiconductor layer and a quasi-ohmic contact layer on the thin film transistor, the two ends of the photosensitive semiconductor layer are respectively overlapped on the source and the quasi-ohmic contact layer, and one end of the quasi-ohmic contact layer is overlapped on the drain of the thin film transistor. The photosensitive semiconductor layer and the quasi-ohmic contact layer, the source, the drain, the active layer, and the gate constitute a Schottky diode. By utilizing the current hysteresis effect of the Schottky diode under the forward bias condition in the current-voltage characteristic under light conditions, the minimum voltage for turning on the thin film transistor can be reduced when receiving light, and the output current of the thin film transistor can be controlled by the voltage applied to the gate and the light applied to the photosensitive semiconductor layer, thereby achieving control of the logical state of the thin film transistor.

[0017] According to an embodiment of the present application, the material of the quasi-ohmic contact layer is graphite, and the material of the photosensitive semiconductor layer is indium selenide.

[0018] Indium selenide is a typical two-dimensional layered semiconductor material with excellent electrical properties and a moderate and adjustable direct band gap. Its spectral response covers the range from near-infrared to ultraviolet. Selecting indium selenide as the material for the photosensitive semiconductor layer can improve the photosensitivity and response speed of thin-film transistors. Graphite has an electron affinity similar to that of indium selenide. Overlapping a quasi-ohmic contact layer made of graphite material on the drain of a thin-film transistor to construct a quasi-ohmic contact can weaken the Fermi level pinning at the interface, which is beneficial to the input and output of current.

[0019] According to an embodiment of the present application, the thickness of the quasi-ohmic contact layer is between 20 nanometers and 30 nanometers, and the thickness of the photosensitive semiconductor layer is between 20 nanometers and 30 nanometers.

[0020] By limiting the thickness of the quasi-ohmic contact layer and the photosensitive semiconductor layer to between 20 nanometers and 30 nanometers, the occurrence of breakage due to the quasi-ohmic contact layer or the photosensitive semiconductor layer being too thin can be avoided.

[0021] According to an embodiment of the present application, the photosensitive semiconductor layer and the quasi-ohmic contact layer are disposed on a side of the gate facing away from the substrate.

[0022] The embodiment of the present application further defines the thin film transistor as a bottom-gate structure. The photosensitive semiconductor layer in the thin film transistor with a bottom-gate structure can receive light from an internal light source or an external light source, and achieve the effect of lowering the minimum voltage for turning on the thin film transistor.

[0023] According to an embodiment of the present application, the photosensitive semiconductor layer and the quasi-ohmic contact layer are arranged on a side of the gate close to the substrate.

[0024] The embodiment of the present application further defines the thin film transistor as a top-gate structure. The photosensitive semiconductor layer in the thin film transistor with the top-gate structure can receive light from an internal light source or an external light source, and achieve the effect of lowering the minimum voltage for turning on the thin film transistor.

[0025] According to an embodiment of the present application, the gate is made of a transparent conductive metal oxide material.

[0026] Selecting transparent conductive metal oxide as the gate material can prevent the gate from blocking light irradiating the photosensitive semiconductor layer. Both light from the side of the photosensitive semiconductor layer close to the gate and light from the side far from the gate can be received by the photosensitive semiconductor layer.

[0027] According to an embodiment of the present application, the metal oxide material includes an oxide of any one of indium, tin, zinc and cadmium; or a composite multi-component oxide formed by a composite of oxides of at least two metals.

[0028] Selecting an oxide of any one of indium, tin, zinc and cadmium; or a composite multi-component oxide composed of oxides of at least two metals as the gate material can ensure the transmittance of the gate and prevent the gate from blocking light irradiating the photosensitive semiconductor layer.

[0029] According to an embodiment of the present application, the gate is made of metal.

[0030] When the material of the gate is metal, the light-sensitive semiconductor layer can only receive light from the side away from the gate, thereby achieving the effect of lowering the minimum voltage for turning on the thin film transistor.

[0031] According to one embodiment of the present application, the minimum voltage for turning on the thin film transistor when the photosensitive semiconductor layer receives specific light is a first voltage, and when the photosensitive semiconductor layer does not receive the specific light, the minimum voltage for turning on the thin film transistor is a second voltage, and the first voltage is lower than the second voltage.

[0032] By utilizing the above-mentioned characteristics of the thin film transistor, the output current of the thin film transistor can be controlled by applying a voltage to the gate and light to the photosensitive semiconductor layer, thereby achieving control over the logic state of the thin film transistor.

[0033] According to an embodiment of the present application, the array substrate includes a gate control line, and the gate control line is connected to the gate;

[0034] When executing the low power consumption mode, the photosensitive semiconductor layer continuously receives the specific light, and when the gate control line applies a first turn-on voltage to the gate, the thin film transistor is turned on, and the first turn-on voltage is greater than or equal to the first voltage and less than the second voltage.

[0035] By providing specific light through an external light source or an internal light source to continuously illuminate the photosensitive semiconductor layer of the thin film transistor, the minimum voltage for turning on the thin film transistor can be reduced. When the gate control line applies a first turn-on voltage to the gate of the thin film transistor, the thin film transistor can be turned on, thereby achieving the effect of reducing power consumption.

[0036] According to an embodiment of the present application, the array substrate includes a gate control line, and the gate control line is connected to the gate;

[0037] When executing the writing demonstration mode, the gate control line applies a second turn-on voltage to the gate that is insufficient to turn on the thin film transistor until the photosensitive semiconductor layer is exposed to the specific light, thereby turning on the thin film transistor;

[0038] The second turn-on voltage is greater than or equal to the first voltage and less than the second voltage.

[0039] When executing the writing demonstration mode, the gate control line can continuously apply a second turn-on voltage to the gate of the thin film transistor, which is insufficient to turn on the thin film transistor, until it receives specific light, and the minimum voltage required to turn on the thin film transistor is reduced, thereby turning on the thin film transistor and realizing the function of the writing demonstration mode.

[0040] According to the array substrate provided in the above embodiment of the present application, the embodiment of the present application further provides a display panel, wherein the display panel includes:

[0041] The array substrate as described in the above embodiment;

[0042] an opposing substrate, arranged opposite to the array substrate;

[0043] a liquid crystal layer, disposed between the array substrate and the counter substrate; and

[0044] The backlight module is arranged on a side of the array substrate away from the opposing substrate.

[0045] The display panel is a liquid crystal display panel. By irradiating the thin film transistor with light emitted by the backlight module of the display panel, the minimum voltage for turning on the thin film transistor can be reduced, thereby achieving the effect of reducing power consumption.

[0046] Beneficial effects of the embodiments of the present application: The embodiments of the present application provide an array substrate and a display panel including the array substrate, wherein the array substrate includes a base and a thin film transistor arranged on one side of the base, the thin film transistor includes a quasi-ohmic contact layer arranged on one side of the active layer and connected to the drain, and a photosensitive semiconductor layer connected to the source and the quasi-ohmic contact layer. By irradiating the photosensitive semiconductor layer with external or internal light, the gate turn-on voltage of the thin film transistor can be reduced, thereby reducing the power consumption of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0048] Figure 1 A schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0049] Figure 2 A schematic diagram of a first illumination mode of a display panel provided in an embodiment of the present application;

[0050] Figure 3 A schematic diagram of a second illumination mode of a display panel provided in an embodiment of the present application;

[0051] Figure 4 A schematic structural diagram of another array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The following descriptions of the embodiments refer to the accompanying figures to illustrate specific embodiments that may be implemented in this application. Directional terms used in this application, such as [upper], [lower], [front], [back], [left], [right], [inner], [outer], and [side], refer only to the directions in the accompanying figures. Therefore, the directional terms used are intended to illustrate and facilitate understanding of this application and are not intended to limit this application. In the figures, similarly structured elements are denoted by the same reference numerals.

[0053] The present application will be further described below with reference to the accompanying drawings and specific embodiments.

[0054] Embodiments of the present application provide an array substrate and a display panel, which can be used to reduce the gate turn-on voltage of thin film transistors in the display panel and lower the power consumption of the display panel.

[0055] The array substrate includes a substrate 10 and a plurality of thin film transistors 20 arranged in an array on the substrate 10, as well as pixel electrodes 30. The thin film transistors 20 include a gate electrode 21, an active layer 22, a source electrode 23, and a drain electrode 24. The source electrode 23 is disposed on a side of the active layer 22 facing away from the gate electrode 21 and in contact with the active layer 22. The drain electrode 24 is disposed on a side of the active layer 22 facing away from the gate electrode 21 and in contact with the active layer 22. A gap is formed between the source electrode 23 and the drain electrode 24.

[0056] In an embodiment of the present application, the active layer 22 includes a semiconductor layer 221 and an ohmic contact layer 222, the semiconductor layer 221 is arranged on one side of the gate 21, and the ohmic contact layer 222 is arranged at opposite ends of the semiconductor layer 221 away from the gate 21, the source 23 is arranged on the side of the ohmic contact layer 222 at one end away from the semiconductor layer 221, and the drain 24 is arranged on the side of the ohmic contact layer 222 at the other end away from the semiconductor layer 221, and the pixel electrode 30 is electrically connected to the drain 24.

[0057] The thin film transistor 20 further includes a quasi-ohmic contact layer 25 and a photosensitive semiconductor layer 26 . The quasi-ohmic contact layer 25 is disposed in the gap between the source 23 and the drain 24 and is located on a side of the semiconductor layer 221 away from the gate 21 . The quasi-ohmic contact layer 25 is electrically connected to the drain 24 .

[0058] The photosensitive semiconductor layer 26 is arranged in the gap between the source 23 and the drain 24, and is located on the side of the semiconductor layer 221 away from the gate 21. The opposite ends of the photosensitive semiconductor layer 26 are electrically connected to the source 23 and the quasi-ohmic contact layer 25, respectively. The quasi-ohmic contact layer 25 and the photosensitive semiconductor layer 26 fill the gap between the source 23 and the drain 24.

[0059] By utilizing the current hysteresis effect of the thin film transistor 20 under forward bias conditions in the current-voltage characteristics under light conditions, the output current of the thin film transistor 20 device is controlled by applying voltage and light to the gate 21, thereby realizing the control of the logic state of the thin film transistor 20 and the optical storage function.

[0060] In one embodiment, the thin film transistor 20 is a bottom-gate structure, and the quasi-ohmic contact layer 25 and the photosensitive semiconductor layer 26 are both disposed on a side of the gate 21 away from the substrate 10 .

[0061] like Figure 1 As shown, Figure 1 This is a structural diagram of an array substrate provided in an embodiment of the present application. The substrate 10 is a transparent glass substrate so that light can be irradiated from one side of the substrate 10 to the photosensitive semiconductor layer 26 .

[0062] In some other embodiments, the material of the substrate 10 may also be a transparent organic material, and the organic material may include but is not limited to one or more of polyimide (PI), polyamide (PA), polycarbonate (PC), polyether sulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymethyl methacrylate (PMMA), and cycloolefin copolymer (COC). A mixture of the above materials.

[0063] The gate 21 is disposed on one side of the substrate 10. It should be noted that the gate 21 being disposed on one side of the substrate 10 may mean that the gate 21 is in direct contact with the surface of the substrate 10 or in indirect contact with the substrate 10.

[0064] The gate insulating layer 27 is disposed flatly on one side of the substrate 10 and covers the surface of the gate 21 facing away from the substrate 10. The gate insulating layer 27 is made of a transparent inorganic material, which may include at least one of silicon nitride, silicon oxide, and silicon oxynitride, or a mixture of multiple materials. The gate insulating layer 27 may be a single layer structure formed from any of the aforementioned inorganic materials, or a double or multilayer structure formed by stacking one or more of the aforementioned inorganic materials.

[0065] The semiconductor layer 221 is disposed on a side of the gate insulating layer 27 facing away from the gate 21. The semiconductor layer 221 is made of amorphous silicon (α-Si). The ohmic contact layer 222 is disposed at opposite ends of the semiconductor layer 221 facing away from the gate 21. The ohmic contact layer 222 is made of amorphous silicon (α-Si), and has a higher ion doping concentration than the semiconductor layer 221.

[0066] The source electrode 23 is disposed on a side of the ohmic contact layer 222 away from the semiconductor layer 221, and the drain electrode 24 is disposed on a side of the ohmic contact layer 222 away from the semiconductor layer 221. The source electrode 23 and the drain electrode 24 are disposed in the same layer and are made of the same material.

[0067] In the embodiment of the present application, the source electrode 23 and the drain electrode 24 are both made of copper.

[0068] In some other embodiments, the material of the source 23 and the drain 24 is not limited to copper, but may also include any one or more combinations of aluminum, molybdenum, copper, chromium, tungsten, tantalum and titanium. The source 23 and the drain 24 may also be a single-layer metal film structure or a two-layer or multi-layer metal film structure.

[0069] The source electrode 23 and the drain electrode 24 are spaced apart from each other. One end of the quasi-ohmic contact layer 25 is overlapped on the side of the drain electrode 24 facing away from the ohmic contact layer 222. The opposite ends of the photosensitive semiconductor layer 26 are respectively overlapped on the side of the source electrode 23 facing away from the ohmic contact layer 222 and the side of the quasi-ohmic contact layer 25 facing away from the semiconductor layer 221. An insulating protective layer 28 is disposed on the side of the quasi-ohmic contact layer 25 and the photosensitive semiconductor layer 26 facing away from the substrate 10 and covers the source electrode 23 and the drain electrode 24. The pixel electrode 30 is disposed on the side of the insulating protective layer 28 facing away from the substrate 10 and is connected to the drain electrode 24 via a via hole penetrating the insulating protective layer 28.

[0070] In the embodiment of the present application, the material of the pixel electrode 30 may be a conductive transparent metal oxide. The metal oxide material may include an oxide of any one of indium, tin, zinc, and cadmium; or a composite oxide formed by a composite of oxides of at least two metals. For example, the metal oxide material may be any one of indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), cadmium oxide (CdO), and aluminum-doped zinc oxide (AZO).

[0071] In the embodiment of the present application, the material of the photosensitive semiconductor layer 26 is two-dimensional indium selenide, and the material of the quasi-ohmic contact layer 25 is graphite. Two-dimensional indium selenide is a typical two-dimensional layered semiconductor material with excellent electrical properties and a moderate and adjustable direct band gap. Its spectral response covers the range from near-infrared to ultraviolet. Selecting indium selenide as the material for the photosensitive semiconductor layer can improve the light responsivity and response speed of the thin-film transistor. Graphite has an electron affinity similar to that of indium selenide. Overlapping the quasi-ohmic contact layer 25 made of graphite on the drain electrode 24 to construct a quasi-ohmic contact can reduce Fermi level pinning at the interface, facilitating the input and output of current.

[0072] The thin film transistor 20 composed of the photosensitive semiconductor layer 26, the quasi-ohmic contact layer 25, the source electrode 23, the drain electrode 24, etc. is a metal copper-two-dimensional indium selenide-graphite Schottky diode. The current hysteresis effect under the forward bias condition in the current-voltage characteristic of the thin film transistor under light conditions is utilized. The output current of the thin film transistor is controlled by applying a voltage to the gate 21 and light applied to the photosensitive semiconductor layer 26, thereby realizing the control of the logic state of the thin film transistor.

[0073] Furthermore, the thickness of the quasi-ohmic contact layer 25 is greater than or equal to 20 nanometers and less than or equal to 30 nanometers, and the thickness of the photosensitive semiconductor layer 26 is greater than or equal to 20 nanometers and less than or equal to 30 nanometers. The thickness of the quasi-ohmic contact layer 25 and the photosensitive semiconductor layer 26 may be equal or different. The thickness of the quasi-ohmic contact layer 25 may be greater than the thickness of the photosensitive semiconductor layer 26 or less than the thickness of the photosensitive semiconductor layer 26. There is no limitation here.

[0074] For example, the thickness of the quasi-ohmic contact layer 25 can be 20 nanometers, 22 nanometers, 25 nanometers, 27 nanometers or 30 nanometers, and the thickness of the photosensitive semiconductor layer 26 can be 20 nanometers, 23 nanometers, 26 nanometers, 27 nanometers or 30 nanometers, so as to avoid the situation where the film thickness of the photosensitive semiconductor layer 26 and the quasi-ohmic contact layer 25 is too thin and causes breakage.

[0075] The minimum voltage for turning on the thin film transistor 20 when the photosensitive semiconductor layer 26 receives specific light is a first voltage, and the minimum voltage for turning on the thin film transistor 20 when the photosensitive semiconductor layer 26 does not receive the specific light is a second voltage. The first voltage is lower than the second voltage.

[0076] By adding a photosensitive semiconductor layer 26 and a quasi-ohmic contact layer 25 on the thin film transistor, and connecting the quasi-ohmic contact layer 25 to the drain 24, and connecting the photosensitive semiconductor layer 26 to the source 23 and the quasi-ohmic contact layer 25 respectively, light is used to illuminate the photosensitive semiconductor layer 26, thereby reducing the minimum voltage for turning on the thin film transistor 20.

[0077] In the embodiment of the present application, the display panel has a low power consumption mode. When in the low power consumption mode, under specific lighting conditions, the data line of the display panel applies a positive voltage to the source electrode 23 of the thin film transistor 20, and the gate control line applies a low potential voltage to the gate electrode 21. The low potential voltage is lower than the first voltage, and the thin film transistor 20 cannot be turned on normally because the potential of the gate electrode 21 is too low.

[0078] When the low power consumption mode is executed, the condition for triggering the thin film transistor 20 to turn on is a first turn-on voltage. Under the specific light, when the gate control line applies the first turn-on voltage to the gate 21, the thin film transistor 20 is turned on because the first turn-on voltage is greater than or equal to the first voltage and less than the second voltage.

[0079] Compared with the second voltage for turning on the thin film transistor 20 when not receiving the specific light, in the embodiment of the present application, the thin film transistor 20 can be turned on with a smaller first turn-on voltage when the thin film transistor 20 receives the specific light, thereby reducing the power consumption of the display panel.

[0080] It should be noted that the light source of the specific illumination may be a light source in the external environment or a light source inside the display panel.

[0081] In one embodiment, Figure 2 As shown, Figure 2 A schematic diagram of a first illumination mode of a display panel provided in an embodiment of the present application, Figure 2 The display panel shown is a liquid crystal display panel, which may include an array substrate 100, an opposing substrate 200, a liquid crystal layer 300 and a backlight module 400. The array substrate 100 may be any one of the array substrates provided in the embodiments of the present application. The array substrate 100 and the opposing substrate 200 are arranged opposite to each other, the liquid crystal layer 300 is arranged between the array substrate 100 and the opposing substrate 200, and the backlight module 400 is arranged on the side of the array substrate 100 facing away from the opposing substrate 200.

[0082] exist Figure 2 In the embodiment shown, the array substrate 100 may include: Figure 1 In the illustrated embodiment, the substrate 10 and the thin film transistor 20 , the counter substrate 200 may include a glass substrate and a color filter layer disposed on a side of the glass substrate close to the array substrate 100 .

[0083] In one embodiment, the material of the gate 21 is a transparent conductive metal oxide material. The light emitted by the backlight module 400 can penetrate the gate 21 in the direction indicated by the arrow in the figure and illuminate the photosensitive semiconductor layer 26, thereby reducing the turn-on voltage of the thin film transistor 20.

[0084] The metal oxide material may include an oxide of any one of indium, tin, zinc, and cadmium; or a composite oxide formed by combining oxides of at least two metals. For example, the metal oxide material may be any one of indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), cadmium oxide (CdO), and aluminum-doped zinc oxide (AZO).

[0085] In one embodiment, the gate 21 may be made of metal. In this case, the specific light source may be a light source in the external environment. When there is sufficient light in the external environment, such as a strong light environment, the light in the external environment may be used to illuminate the photosensitive semiconductor layer 26 of the thin film transistor 20 to reduce the turn-on voltage of the thin film transistor 20, thereby reducing the power consumption of the display panel.

[0086] Specifically, the material of the gate 21 can be any one or more combinations of metal materials such as aluminum, molybdenum, copper, chromium, tungsten, tantalum, and titanium. The gate 21 can also be a single-layer metal film structure formed by any one of the above-mentioned metal materials, or a multi-layer metal film structure formed by stacking two or more of the above-mentioned materials.

[0087] Furthermore, the display panel may also have a writing demonstration mode. When the writing demonstration mode is executed, the condition for triggering the thin film transistor 20 to turn on is specific light, rather than the second turn-on voltage.

[0088] When executing the writing demonstration mode, in the absence of specific light, the gate control line can continuously apply a second turn-on voltage to the gate 21, where the second turn-on voltage is less than the minimum voltage for turning on the thin film transistor 20 when the photosensitive semiconductor layer 26 is not exposed to light (i.e., the second voltage), and is greater than or equal to the minimum voltage for turning on the thin film transistor 20 when exposed to specific light (i.e., the first voltage), so that the thin film transistor 20 cannot be turned on. Until the photosensitive semiconductor layer 26 receives specific light, the minimum voltage for turning on the thin film transistor is reduced and is less than or equal to the second turn-on voltage, so that the thin film transistor 20 can be turned on.

[0089] When the writing demonstration mode is executed, the light source of the specific illumination is an external light source.

[0090] It should be noted that the illumination intensity of the specific illumination when executing the low power consumption mode may be different from the illumination intensity of the specific illumination when executing the writing demonstration mode, and the magnitude of the first voltage when executing the low power consumption mode may be different from the magnitude of the first voltage when executing the writing demonstration mode.

[0091] For example Figure 3 As shown, Figure 3 This is a schematic diagram of the second illumination mode of the display panel provided in an embodiment of the present application. The external light source can be an infrared pen or a laser pen. The strong light beam emitted by the external light source such as the infrared pen or the laser pen can penetrate the opposing substrate 200 in the direction of the arrow shown in the figure and irradiate the thin film transistor 20 to reduce the minimum voltage for turning on the thin film transistor 20, turn on the thin film transistor 20, and thereby realize the control of turning on and off the thin film transistor 20 by the lighting conditions. On the display panel, the function of writing demonstration under the illumination of the front beam can be realized.

[0092] In one embodiment, the thin film transistor 20 may also be a top-gate structure.

[0093] like Figure 4 As shown, Figure 4 This is a structural diagram of another array substrate provided in an embodiment of the present application, and its structure is similar to Figure 1 The structures of the array substrates shown are substantially the same, with the difference being that the photosensitive semiconductor layer 26 and the quasi-ohmic contact layer 25 are disposed on a side of the gate 21 close to the substrate 10 .

[0094] like Figure 4 As shown, the photosensitive semiconductor layer 26 is disposed on one side of the substrate 10. It should be noted that being disposed on one side of the substrate 10 may refer to being in direct contact with one side surface of the substrate 10 or in indirect contact with the substrate 10.

[0095] The quasi-ohmic contact layer 25 is arranged on one side of the substrate 10, and one end of the quasi-ohmic contact layer 25 is overlapped on the side of the photosensitive semiconductor layer 26 facing away from the substrate 10. The source electrode 23 is arranged on the side of the photosensitive semiconductor layer 26 facing away from the substrate 10 and is in direct contact with the surface of the photosensitive semiconductor layer 26 facing away from the substrate 10. The drain electrode 24 is arranged on the side of the quasi-ohmic contact layer 25 facing away from the substrate 10 and is in direct contact with the surface of the quasi-ohmic contact layer 25 facing away from the substrate 10.

[0096] The ohmic contact layer 222 is respectively disposed on the side of the source electrode 23 facing away from the substrate 10 and the side of the drain electrode 24 facing away from the substrate 10. The semiconductor layer 221 is disposed on the side of the ohmic contact layer 222 facing away from the substrate 10 and covers the surface of the quasi-ohmic contact layer 25 and the photosensitive semiconductor layer 26 facing away from the substrate 10. The gate insulating layer 27 is disposed on the side of the semiconductor layer 221 facing away from the substrate 10. The gate 21 is disposed on the side of the gate insulating layer 27 facing away from the substrate 10 and is disposed directly opposite the semiconductor layer 221.

[0097] exist Figure 4 In the embodiment shown, if the writing demonstration mode function is required, the material of the gate 21 can be a transparent conductive metal oxide material, and a strong light beam outside the display panel can penetrate the gate 21 and irradiate the photosensitive semiconductor layer 26.

[0098] Specifically, the metal oxide material may include an oxide of any one of indium, tin, zinc, and cadmium; or a composite oxide formed by combining oxides of at least two metals. For example, the metal oxide material may be any one of indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), cadmium oxide (CdO), and aluminum-doped zinc oxide (AZO).

[0099] exist Figure 4 In the embodiment shown, if only the power consumption of the display panel needs to be reduced, the material of the gate 21 can be either the transparent conductive metal oxide material described in the above embodiment or a metal material. The metal material can be any one or a combination of metal materials such as aluminum, molybdenum, copper, chromium, tungsten, tantalum, and titanium.

[0100] Based on the display panel provided in the above-mentioned embodiments of the present application, embodiments of the present application further provide a display device, comprising a housing, a circuit board, a power supply, and the display panel provided in the above-mentioned embodiments. The circuit board and the power supply can be mounted within the housing, and the display panel can be mounted on the housing. The display device can be a mobile terminal, such as color electronic paper, a color e-book, or a smartphone. The display device can also be a wearable terminal, such as a smartwatch or smart bracelet. The display device can also be a fixed terminal, such as a color electronic billboard or color electronic poster.

[0101] Beneficial effects of the embodiments of the present application: The embodiments of the present application provide an array substrate and a display panel including the array substrate, wherein the array substrate includes a base and a thin film transistor arranged on one side of the base, the thin film transistor includes a quasi-ohmic contact layer arranged on one side of the semiconductor layer and connected to the drain, and a photosensitive semiconductor layer connected to the source and the quasi-ohmic contact layer. By irradiating the quasi-ohmic contact layer and the photosensitive semiconductor layer with external or internal light, the gate turn-on voltage of the thin film transistor can be reduced, thereby reducing the power consumption of the display panel.

[0102] In summary, although the present application is disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims

1. An array substrate, characterized in that: include: substrate; A thin film transistor is disposed on one side of the substrate, and the thin film transistor includes: gate; an active layer, disposed on one side of the gate; a source electrode, disposed on a side of the active layer away from the gate and in contact with the active layer; a drain electrode, disposed on a side of the active layer away from the gate and in contact with the active layer; a gap is provided between the source electrode and the drain electrode; a quasi-ohmic contact layer, disposed on a side of the active layer away from the gate, the quasi-ohmic contact layer being electrically connected to the drain; and a photosensitive semiconductor layer, disposed on a side of the active layer away from the gate, the photosensitive semiconductor layer being electrically connected to the source electrode and the quasi-ohmic contact layer; The minimum voltage for turning on the thin film transistor when the photosensitive semiconductor layer receives specific light is a first voltage, and the minimum voltage for turning on the thin film transistor when the photosensitive semiconductor layer does not receive the specific light is a second voltage, and the first voltage is lower than the second voltage.

2. The array substrate according to claim 1, wherein: One end of the quasi-ohmic contact layer is overlapped on the side of the drain electrode away from the active layer, and the opposite ends of the photosensitive semiconductor layer are respectively overlapped on the side of the source electrode away from the active layer and the side of the quasi-ohmic contact layer away from the active layer.

3. The array substrate according to claim 1, wherein: The material of the quasi-ohmic contact layer is graphite, and the material of the photosensitive semiconductor layer is indium selenide.

4. The array substrate according to claim 1, wherein: The thickness of the quasi-ohmic contact layer is between 20 nanometers and 30 nanometers, and the thickness of the photosensitive semiconductor layer is between 20 nanometers and 30 nanometers.

5. The array substrate according to claim 1, wherein: The photosensitive semiconductor layer and the quasi-ohmic contact layer are arranged on a side of the gate away from the substrate.

6. The array substrate according to claim 1, wherein: The photosensitive semiconductor layer and the quasi-ohmic contact layer are arranged on a side of the gate close to the substrate.

7. The array substrate according to claim 5 or 6, wherein: The gate is made of a transparent conductive metal oxide material.

8. The array substrate according to claim 7, wherein: The metal oxide material includes an oxide of any one of indium, tin, zinc and cadmium; or a composite multi-component oxide formed by a composite of oxides of at least two metals.

9. The array substrate according to claim 5 or 6, wherein: The gate is made of metal.

10. The array substrate according to claim 1, wherein: The array substrate includes a gate control line, and the gate control line is connected to the gate; When executing the low power consumption mode, the photosensitive semiconductor layer continuously receives the specific light, and when the gate control line applies a first turn-on voltage to the gate, the thin film transistor is turned on, and the first turn-on voltage is greater than or equal to the first voltage and less than the second voltage.

11. The array substrate according to claim 1, wherein: The array substrate includes a gate control line, and the gate control line is connected to the gate; When executing the writing demonstration mode, the gate control line applies a second turn-on voltage to the gate that is insufficient to turn on the thin film transistor until the photosensitive semiconductor layer receives the specific light, and the second turn-on voltage that turns on the thin film transistor is greater than or equal to the first voltage and less than the second voltage.

12. A display panel, characterized in that: The display panel includes: The array substrate according to any one of claims 1 to 11; an opposing substrate, arranged opposite to the array substrate; a liquid crystal layer, disposed between the array substrate and the counter substrate; and The backlight module is arranged on a side of the array substrate away from the opposing substrate.

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