Self-calibration circuit, corresponding equipment and method for Δ-Σ modulator

Abstract

Various embodiments of this disclosure relate to self-calibration circuits, corresponding devices, and methods for Δ-Σ modulators. A Δ-Σ modulator includes: a quantizer; a signal propagation path including a plurality of cascaded integrators coupled between an input node and the quantizer; and a feedback network including a plurality of digital-to-analog converters (DACs). In calibration operation mode, a first DAC of the plurality of DACs in the feedback network receives a signal comprising a periodically alternating digital sequence. The first DAC is coupled to a first integrator of the plurality of cascaded integrators. The integrators other than the first integrator operate in gain operation mode. The Δ-Σ modulator generates a digital test signal at the output of the quantizer based on the signal comprising the periodically alternating digital sequence, and the calibration circuit system generates a calibration signal based on the digital test signal and a reference digital word.

Description

Technical Field

[0001] This manual relates to self-calibration circuits.

[0002] For example, one or more embodiments can be applied to a continuous-time Δ-Σ modulator. Background Technology

[0003] The built-in anti-aliasing filter, low noise, and reduced power consumption have contributed to the widespread adoption of continuous-time Δ-Σ modulators (CTDSMs) over the past two decades.

[0004] The literature reports a variety of design examples for various applications, demonstrating the versatility of this type of high-performance ADC.

[0005] The problem with CTDSMs may lie in the fact that they may be implemented using active RC integrators, relatively low-performance quantizers, and resistor-regulated or current-regulated digital-to-analog converters (DACs). In fact, RC integrators are susceptible to process variations, and using them almost always involves calibration. Calibration can be primarily achieved by applying a force to the integrator's feedback capacitor during the final test operation, which can take several seconds per individual device.

[0006] To address these issues, it has been proposed to deduce the RC time constant from an auxiliary circuit representing a copy of the RC network. However, this circuit may be located far from the modulator loop filter, making the entire calibration process sensitive to gradients in variables associated with chip fabrication. Furthermore, calibration not performed within the modulator loop may be less accurate.

[0007] Area issues may also arise; due to area constraints, the auxiliary circuitry may not represent an accurate copy of the RC network, which can adversely affect the measurements that form the basis of the calibration. Summary of the Invention

[0008] One or more embodiments may relate to a device. A Δ-Σ modulator may be an example of such a device.

[0009] One or more embodiments may relate to a method.

[0010] In one or more embodiments, a modulator such as a CTDSM can enter a test mode (opposite to the operating configuration), which facilitates direct measurement of loop filter parameters while providing effective calibration of the Δ-Σ coefficients.

[0011] In response to entering test mode:

[0012] The modulator is set to open-loop mode, with all integrators except the first integrator configured as gain stages, and under these conditions, a square waveform is generated that conveys the information involved in the trimming.

[0013] The average value of the waveform is compared with the expected value stored in the register set. The adjustment value is calculated based on the difference generated by the comparison, and once the calibration is completed, the system enters the operating mode (closed-loop configuration).

[0014] In one or more embodiments, the circuitry involved in such operation includes a digital chain and an analog integrator that can be configured as a gain stage.

[0015] As an advantage, one or more embodiments help to achieve improved accuracy and reduced calibration time.

[0016] Furthermore, the trimming process according to the embodiment can provide direct measurement of loop filter parameters that take into account possible variations associated with coefficients and voltage references.

[0017] One or more embodiments help to achieve the desired accuracy of the results by reusing or reconfiguring hardware already present on the modulator chip, with the addition of a simple digital state machine for implementing the successive approximation register (SAR) search algorithm.

[0018] In one embodiment, a device includes a Δ-Σ modulator having an input node; a quantizer; a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer; and a feedback network including a plurality of digital-to-analog converters (DACs). In quantization operation mode, each of the plurality of DACs in the feedback network is coupled between the output of the quantizer and a corresponding integrator of the plurality of cascaded integrators; the Δ-Σ modulator generates a digital signal at the output of the quantizer based on an analog input signal received at the input node. In calibration operation mode, a calibration circuit system is coupled to the output of the quantizer. A first DAC of the plurality of DACs in the feedback network receives a signal comprising a periodically alternating digital sequence, and the first DAC is coupled to a first integrator of the plurality of cascaded integrators. The integrators other than the first integrator of the plurality of cascaded integrators operate in gain operation mode. The Δ-Σ modulator generates a digital test signal at the output of the quantizer based on the signal comprising a periodically alternating digital sequence, and the calibration circuit system generates an integrator calibration signal based on the digital test signal and a reference digital word.

[0019] In one embodiment, a system includes a sensor; a Δ-Σ modulator coupled to the sensor, the Δ-Σ modulator having a quantizer; a signal propagation path including a plurality of cascaded integrators coupled between the sensor and the quantizer; and a feedback network including a plurality of digital-to-analog converters (DACs), wherein in a quantization operation mode, each of the plurality of DACs in the feedback network is coupled between the output of the quantizer and a corresponding integrator of the plurality of cascaded integrators; and the Δ-Σ modulator generates a digital signal at the output of the quantizer based on an analog input signal received from the sensor; and a calibration circuit system coupled to the output of the quantizer, wherein in a calibration operation mode, a first DAC of the plurality of DACs in the feedback network receives a signal comprising a periodically alternating digital sequence, the first DAC being coupled to a first integrator of the plurality of cascaded integrators; the integrators of the plurality of cascaded integrators other than the first integrator operating in a gain operation mode; the Δ-Σ modulator generates a digital test signal at the output of the quantizer based on the signal comprising a periodically alternating digital sequence; and the calibration circuit system generates an integrator calibration signal based on the digital test signal and a reference digital word.

[0020] In one embodiment, a method includes: operating a Δ-Σ modulator having a calibration circuitry in a calibration operation mode to generate an integrator calibration signal; calibrating the Δ-Σ modulator based on the integrator calibration signal; operating the calibrated Δ-Σ modulator in a quantization operation mode, wherein the Δ-Σ modulator includes an input node; a quantizer; a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer; and a feedback network including a plurality of digital-to-analog converters, wherein in the quantization operation mode, the calibration circuitry is coupled to the output of the quantizer; a first digital-to-analog converter of the plurality of digital-to-analog converters in the feedback network receives a signal comprising a periodically alternating digital sequence, the first... A digital-to-analog converter (DAC) is coupled to the first integrator in a plurality of cascaded integrators; the integrators other than the first integrator in the plurality of cascaded integrators operate in gain operation mode; a delta-sigma modulator generates a digital test signal at the output of a quantizer based on a signal comprising a periodically alternating digital sequence; and a calibration circuit system generates an integrator calibration signal based on the digital test signal and a reference digital word, and in quantization operation mode, each of the plurality of DACs in the feedback network is coupled between the quantizer and the corresponding integrator in the plurality of cascaded integrators; and the delta-sigma modulator generates a digital signal at the output of the quantizer based on the analog input signal received at the input node.

[0021] In one embodiment, the content of a non-transitory computer-readable medium configures a Δ-Σ modulator having a calibration circuitry system to perform a method comprising: operating the Δ-Σ modulator in a calibration operation mode to generate an integrator calibration signal; calibrating the Δ-Σ modulator based on the integrator calibration signal; and operating the calibrated Δ-Σ modulator in a quantization operation mode, wherein the Δ-Σ modulator includes an input node; a quantizer; a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer; and a feedback network including a plurality of digital-to-analog converters, wherein in the quantization operation mode, the calibration circuitry system is coupled to the output of the quantizer; and a first digital-to-analog converter of the plurality of digital-to-analog converters in the feedback network receives packets. The signal includes a periodically alternating digital sequence; a first digital-to-analog converter is coupled to a first integrator in a plurality of cascaded integrators; the integrators other than the first integrator in the plurality of cascaded integrators operate in gain operation mode; a Δ-Σ modulator generates a digital test signal at the output of a quantizer based on the signal including the periodically alternating digital sequence; and a calibration circuit system generates an integrator calibration signal based on the digital test signal and a reference digital word, and in quantization operation mode, each of the plurality of digital-to-analog converters in the feedback network is coupled between the quantizer and the corresponding integrator in the plurality of cascaded integrators; and the Δ-Σ modulator generates a digital signal at the output of the quantizer based on the analog input signal received at the input node. Attached Figure Description

[0022] Now, one or more embodiments will be described by way of example only with reference to the accompanying drawings, wherein

[0023] Figure 1 This is a general block diagram of a traditional Δ-Σ converter (DSM).

[0024] Figure 2A Is it like this? Figure 1 A block diagram illustrating an exemplary implementation of a discrete-time (DT) converter.

[0025] Figure 2B Is it like this? Figure 1 A block diagram illustrating an exemplary implementation of a continuous-time (CT) converter.

[0026] Figure 3A This is a block diagram of an ideal fully differential quantizer.

[0027] Figure 3B It reproduces the input-output characteristics of a 3-bit ideal quantizer.

[0028] Figure 4A This is a circuit diagram of a single-ended switched capacitor (SC) integrator.

[0029] Figure 4B This is a circuit diagram of a single-ended continuous-time (CT) integrator.

[0030] Figure 4C It is possible to appear Figure 4A and Figure 4B An exemplary time plot of the possible temporal behavior of a signal in an integrator.

[0031] Figure 5 This is a circuit diagram of an active RC integrator with a adjustable feedback capacitor.

[0032] Figure 6A This is a circuit diagram of a monostable circuit suitable for measuring RC time constant.

[0033] Figure 6B yes Figure 6A The timing diagram of the circuit.

[0034] Figure 7 yes Figure 2B An example of the test mode configuration for the circuit (modulator).

[0035] Figure 8 yes Figure 7 Timing diagram of the test mode circuit.

[0036] Figure 9 This is an example of various sample patterns for converting an integrator into a gain level.

[0037] Figure 10 It is possible to appear Figure 7 An exemplary time diagram showing the possible temporal behavior of signals in a circuit.

[0038] Figure 11 This is a block diagram of an exemplary implementation of a digital signal processor (DSP) chain for offset cancellation.

[0039] Figure 12 It is possible that such events will occur. Figure 11 An exemplary timing diagram of the possible temporal behavior of signals in the DSP circuit shown.

[0040] Figure 13 The illustration shows that Figure 11 In digital signal processor circuit systems, jitter may be introduced to improve system resolution.

[0041] Figure 14 This is a block diagram highlighting the first integrator offset and the associated chopping of the Δ-Σ modulator configured under open-loop conditions.

[0042] Figure 15 It is possible to appear Figure 14 An exemplary time diagram showing the possible temporal behavior of signals in a circuit.

[0043] Figure 16This is an example of a test mode configuration for a circuit (modulator) in a successive approximation register (SAR) architecture that can be used within the framework of embodiments of this specification.

[0044] Figure 17 This is a functional block diagram of a system including a calibrated Δ-Σ converter according to an embodiment. Detailed Implementation

[0045] In the following description, various specific details are set forth to provide a thorough understanding of various exemplary embodiments of this specification. Embodiments may be implemented without one or more specific details or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail so as not to obscure the embodiments of various aspects. Throughout the specification, references to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases “in one embodiment” or “in an embodiment” that may appear in various places throughout the specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0046] The headings / references provided herein are for convenience only and therefore do not explain the extent or scope of protection of the embodiments.

[0047] Furthermore, throughout the description:

[0048] The same parts or elements in the accompanying drawings will be denoted by the same reference numerals, and the relevant descriptions will not be repeated for each drawing.

[0049] For simplicity, the same name (e.g., V) IN Or D OUT () can be used to refer to a signal and the circuit node / component that may contain such a signal.

[0050] An "adder node" will be represented as a circuit node where two or more signals are added together: as those skilled in the art will know, such a node can be "signed," that is, a node where a signal is added to one or more other signals with negative signs that are subtracted from the combination. In other words, designating / illustrating a node as an adder node does not mean that the signals added at that node have the same sign.

[0051] Δ-Σ modulators (DSMs) represent a well-known class of analog-to-digital converters (ADCs) that use relatively simple hardware to combine oversampling methods with quantization noise shaping techniques to achieve high-resolution conversion (16 bits or higher).

[0052] Figure 1 The scheme shown illustrates the general structure of the Δ-Σ modulator (DSM) 10, including:

[0053] The loop filter (LF) 12 is characterized by two different transfer functions H1 and H2, which are respectively associated with the input signal path and the feedback path.

[0054] Quantizer (analog-to-digital converter or A / D converter) 14, through a period of T (generated in a manner known to those skilled in the art). S The clock control signal is used for clock control, and

[0055] Feedback digital-to-analog converter or D / A converter 16.

[0056] Generally speaking, DSMs can be divided into two types based on the technology used to implement the loop filter 12.

[0057] If the loop filter 12 uses a switched capacitor (SC) circuit system, the modulator is called a discrete-time Δ-Σ modulator (DTDSM) series.

[0058] If the loop filter 12 uses a continuous-time (CT) circuit, the modulator is called a continuous-time Δ-Σ modulator (CTDSM).

[0059] Both methods have advantages and disadvantages. Generally speaking, the envisioned usage environment determines the option adopted for a specific application.

[0060] These basic concepts are otherwise well known to those skilled in the art, making it unnecessary to provide a complete comparison between DTDSM and CTDSM in this paper.

[0061] exist Figure 2A (for discrete-time loop filter DT-LF) and Figure 2B The block diagram for the continuous-time loop filter CT-LF presents some differences of interest for the present description.

[0062] These two figures illustrate a second-order modulator implemented using an integrator cascaded feedback (CIFB) topology.

[0063] Integrators 121 and 122 (two are shown for simplicity, but three or more integrators may be provided in some embodiments) are labeled z -1 / 1–z -1 Or a block representation of 1 / s.

[0064] The digital-to-analog converter (DAC) feedback network 16 uses a reference voltage V. REF DAC, and several coefficients C1, C2 (for Figure 2A (for switched capacitors or SC cases) and k1, k2 (for Figure 2B The continuous time or CT case represents the feedback coefficient of the loop that defines the feedback transfer function H2(z) or H2(s).

[0065] For simplicity, assume that the coefficients of the input transfer function (H1(z),H1(s)) are one.

[0066] The analog-to-digital converter or quantizer 14 operates at a reference voltage of V. REF ADC and multiple N bits BIT In this case, it operates at a sampling frequency FS = 1 / TS (which is the same frequency at which the loop filter LF in the DT solution is clocked).

[0067] like Figure 3A As shown, the analog-to-digital converter or quantizer 14 is tasked with converting the analog input signal V... IN Convert to a digital output code proportional to the ratio VIN / VREFADC.

[0068] For example, the number of quantization bits can range from 1 to 4 or 5, and in the case of a multi-bit quantizer, the associated input-output characteristics may be essentially the same. Figure 3B The situation reported (for the 3-bit case, a fully differential quantizer). It should be noted that the output digital value on the y-axis is... Figure 3B The expression is a fraction to indicate its relationship with the ratio VIN / VREFADC.

[0069] The feedback DAC network 16 converts the quantizer's digital output into an analog quantity that enables the modulator loop to close. This operation adjusts the feedback coefficients C1, C2 (for switched capacitors or SC cases) and k1, k2 (for continuous-time or CT cases), which represent the gain terms of the feedback signal. These gain terms are calculated based on the implementation of the desired noise transfer function (NTF).

[0070] Specifically, the switched capacitor or SC modulator uses a capacitive feedback DAC arrangement 16, which provides a charge injection into the loop during each sampling period. The value of this charge injection depends on the digital output code of the converter. Since this charge is typically integrated into the feedback capacitor of the active switched capacitor or SC integrator, coefficients C1 and C2 are typically defined according to the capacitance ratio.

[0071] In the case of continuous-time or CT modulators, current-directed DACs or resistive DACs use current distributed over the entire sampling period (for non-return-to-zero or NRZ DACs) or distributed over a small portion of the sampling period (for return-to-zero or RTZ DACs) to produce the same code-related charge injection.

[0072] For continuous-time or CT pathways, the coefficients will be related to parameters such as resistance, capacitance, and sampling frequency.

[0073] like Figure 2A and Figure 2B The voltage V shown REF DAC can represent the number of (analog) feedback DACs 131 and 132 in feedback network 16 used to generate appropriate feedback signals.

[0074] Depending on the implementation of DACs 131, 132, ... (as noted, there may be more than two integrators, and therefore more than two feedback DACs), this number can be sampled directly in the capacitor DAC in the SC case, or used to generate current in the feedback resistor DAC in the CT case, or also paired with a resistor to generate a current reference I. REF DAC, the current reference I REF The DAC provides a bias signal for the current-regulated DAC (in the case of CT).

[0075] This situation is in Figure 4A and Figure 4B The two circuits are illustrated, and for simplicity, they are presented in single-ended version (in both diagrams, DW indicates the digital word to be converted to analog).

[0076] Figure 4A This refers to a conventional switched capacitor integrator, including a "tunable" capacitor C. DAC (its meaning) Figure 2A The feedback DAC), the "adjustable" capacitor C DAC Configured to sample the reference voltage V during phase F1 (which is the first half of the sampling period). REF The DAC performs sampling, and during phase F2 (which is the second half of the sampling period), a charge V is shared on the virtual ground of the operational transconductance amplifier (OTA) 100. REF DAC·C DAC .

[0077] The output voltage change of this circuit after one sampling period can be calculated as follows:

[0078]

[0079] and Figure 4C The second figure illustrates the potentially relevant temporal behavior.

[0080] Figure 2A The coefficients C1 and C2 in the graph can be calculated as follows:

[0081]

[0082]

[0083] Where C DAC1 C INT1 C DAC2 and C INT2 These represent the DAC capacitor and feedback capacitor of the first integrator and the second integrator, respectively.

[0084] Figure 4B The diagram illustrates an architecture known as an active RC integrator, which is a common solution for implementing analog CT integrators, incorporating a continuous-time (CT) modulator.

[0085] In this example, the adjustable resistor R DAC express Figure 2B The feedback DAC in the continuous-time circuit, the current V of the continuous-time circuit REF DAC / R DAC The output voltage change is generated during the sampling period, and this output voltage change is calculated as follows:

[0086]

[0087] Figure 4C The third figure illustrates the potentially relevant temporal behavior.

[0088] Regarding this solution, Figure 2B The coefficients of the corresponding block scheme can be determined as follows:

[0089]

[0090]

[0091] Where R DAC1 C INT1 R DAC2 and C INT2 These represent the DAC resistor and feedback capacitor of the first integrator and the second integrator, respectively.

[0092] In summary, parameter V REF ADC and V REF The DAC plays a similar role in defining the feedback transfer function for both discrete-time or DT(SC) cases (H2(z)) and continuous-time or CT cases (H2(s)).

[0093] Conversely, the coefficients of integrators 121, 122, ... are expressed very differently for these two cases: for the switched capacitor or SC method, Equation 2 shows that the coefficients depend on the capacitance ratio, which can be an accurate process parameter in most cases.

[0094] Conversely, the continuous time or CT coefficients described in Equation 4 indicate a dependence on parameters such as the sampling frequency and the RC time constant, which are typically affected by process deviations.

[0095] This difference between the two architectures can be a major drawback of using continuous-time or CT modulators, as the inherent biases involved in large-scale industrial production and the range of “propagation” effects on the loop coefficients can degrade from the signal-to-quantum-to-noise ratio (SQNR) to modulator instability.

[0096] One proposed technique for addressing this situation involves adjusting the coefficients in integrators 121, 122, ..., which can be performed based on the three parameters of Equation 4.

[0097] It should be noted that the sampling frequency F of the analog-to-digital converter (ADC) 14 can be changed under various circumstances. S Adjusting the loop factor may not be easy, and the resistance term extends to the array of the feedback DAC 16.

[0098] One possible solution is to "split" the feedback capacitor of the continuous-time (CT) integrator into smaller capacitors C. INT0 C INT1 C INTn Repairable arrays, such as Figure 5 As shown.

[0099] In this solution, the desired number of capacitors can be connected to the integrator, for example, by providing an appropriate calibration word to the associated digital register.

[0100] Otherwise, it should be noted that since the capacitance term of the integrator time constant is used to attempt to (fully) recover the process deviation, the size design of the calibration dynamics includes taking into account the maximum process deviation of all parameters involved in defining the noise transfer function (NTF).

[0101] One issue associated with this possible solution is that, during this calibration process, the capacitance in each device is adjusted, which involves accurately measuring the process parameters for each sample.

[0102] Therefore, a dedicated circuit system is involved, and it is generally expected that the test time will be increased.

[0103] Compared to traditional solutions, one or more embodiments may help provide a technique for adjusting modulator coefficients in a faster manner, using a simpler circuit system, and achieving more accurate calibration results.

[0104] One approach proposed for measuring the time constant is to construct a monostable circuit whose time interval under unstable conditions depends on the RC product.

[0105] One possible implementation of this circuit is as follows: Figure 6A As shown.

[0106] exist Figure 6A In the figure, reference numeral 200 denotes an operational transconductance amplifier (OTA) 200, one input of which is coupled to a first reference voltage V. REF1 The output drives the control node (gate in this paper) of the MOSFET transistor 202, which has a current path (source-drain in this paper) through it. This current path is coupled to the power supply voltage V at node A via resistor R. DD .

[0107] The voltage at node A is taken as V INn Another input to OTA 200 is applied. The current path through MOSFET transistor 202 is coupled to the (non-inverting) input of comparator 204 at node B (where MOSFET transistor 202 is located between nodes A and B) to provide it with a voltage V. COMP With the second reference voltage V REF2 The comparison is performed, and a set signal SET is provided to the grounded trigger 206 whose D node is coupled to the ground.

[0108] The trigger 206 is clocked by the TRIGGER signal and its Q node is coupled to the control node (gate in this document) of the electronic switch 208 (e.g., a MOSFET transistor), which has a current path (source-drain in this document) through it, which is arranged in parallel with the capacitor C. The parallel connection of the MOSFET transistor 208 and the capacitor C is arranged between node B and ground.

[0109] Figure 6B It is possible to appear Figure 6A An exemplary time graph showing the possible temporal behavior of signals in a circuit relative to a common time (horizontal axis) scale.

[0110] Assuming the circuit is in a steady state, the output of flip-flop (FF) 206 is V. DD And capacitor C is discharged (current I0 = (V) DD -V REF1 ) / R flows into switch 208, which short-circuits to make node B(V COMP (grounding).

[0111] Therefore, the output of comparator SET is in logic state 0. When a rising edge is generated at the CK input terminal of flip-flop 206, its output drops to 0, and the voltage at node B (V) COMP It begins to grow with a linear law, for example:

[0112]

[0113] Once V at node B COMP The potential reaches value V REF2 The output of comparator 204 switches its logic state from 0 to 1, thus achieving Q = V. DD In this case, the trigger is set and the capacitor C is discharged.

[0114] Therefore, the time interval under unstable conditions can be calculated as follows:

[0115]

[0116] Given V DD V REF1 and V REF2 By measuring the value of RC and the length of the time interval during which the trigger output is 0, the time constant RC associated with a specific process "corner" of the chip can be determined.

[0117] This information, along with measurements of the local clock signal, helps to determine a calibration value for each test sample that is suitable for recovering the ideal modulator coefficients of Equation 4.

[0118] A binary search can be performed to search for the optimal calibration.

[0119] Despite its obvious effectiveness, this technology is not immune to various drawbacks.

[0120] First, measuring the time interval and performing the associated binary search involves the use of test equipment: because the monostable signal must be extracted from the chip and interfaced with the test equipment, the process is inherently slow.

[0121] The micro-trim process discussed above cannot cover V REF ADC and V REF Errors related to the feedback transfer function caused by DAC.

[0122] In fact, since the main errors are the offset in the dedicated buffer and the residual calibration error of the on-chip bandgap reference, V REF The situation with DAC signals is relatively easy to manage.

[0123] For parameter V REFFor ADCs, the situation could be even worse: for example, in a modulator where a flash converter is used to implement quantizer 14, the error with respect to the reference voltage could be related to V. REF The errors referenced by the DAC signals are similar.

[0124] In the case of a large number of bits (5 or 6 bits), flash converters are not a viable option, and more complex architectures such as successive approximation ADC converters (SAR) can be considered.

[0125] In this context, the expected SAR performance is related to (and limited by) the performance specified for the quantizer. Furthermore, a simple SAR architecture involving a minimal number of DAC capacitors (typically based on top-sampling of the DAC) and capacitor modules with very low capacitance (typically in the fF range) is anticipated.

[0126] Under these conditions, the parasitic capacitance of the DAC and the gate capacitance of the comparator may ultimately play a significant role in defining the least significant bit (LSB) in the SAR. Therefore, when defining the equivalent V... REF The ADC voltage reference plays an important role, which can be affected by non-ideal factors.

[0127] Therefore, proper adjustment of the modulator coefficients may involve taking into account the LSB error associated with the process variation of parasitic capacitance.

[0128] Additionally, the trimming process discussed above is not based on direct measurement of the modulator parameters: it involves extrapolating the RC time constant from an auxiliary circuit, which, as discussed in the introductory section of this specification, can be located far from the modulator loop filter. This makes the entire calibration process sensitive to almost all process gradients associated with chip manufacturing.

[0129] Furthermore, for intermediate frequency applications (F... S In the field of MEMS sensors (~100kHz ÷ 1MHz), where low power consumption is particularly desirable, typical values ​​for feedback DAC resistors are in the tens of MΩ range, while integrator capacitors are on the order of tens of pF. These orders of magnitude make it impractical to create a replica of the RC network used for the integrator within a monostable circuit, as the cost regarding semiconductor area is often unacceptable. This suggests that using even smaller replicas could lead to other possible reasons for mismatches between the measured parameters and those used for calibration.

[0130] In one or more embodiments, these problems can be addressed by providing full-on-chip self-calibration of the modulator coefficients, which can utilize the converter hardware to directly measure the loop filter coefficient deviation and can correlate it with V. REF ADC and VREF Possible errors related to the extension of the DAC voltage reference are taken into account.

[0131] One or more embodiments may involve along Figure 7 The lines shown are configured basically as follows in test mode. Figure 2B The CTDSM is shown.

[0132] Therefore, such as Figure 7 shown Figure 2B The modulator can be viewed as making the input of the DAC (D / A1) 132 associated with the second integrator 122 zero (so-called "turning on" the feedback from the output of the quantizer 14) and imposing a periodic digital sequence DS, for example, with a period of 4T, on the input of the DAC (D / A2) 131 associated with the first integrator 121. S The pattern is -N, -N, +N, +N, and the periodic number sequence DS begins after the first single sample with a value of N / 2 (where N is a defined number code, the options of which will be discussed later, and include 0 and...). between).

[0133] The digital sequence DS can be generated in any manner known to those skilled in the art via a generator not shown for simplicity.

[0134] exist Figure 8 The relevant waveforms are reported at the top of the timing diagram.

[0135] Generally speaking, for a value of R UNIT N of the DAC element BIT Fully differential resistor DAC (with) A positive level and The current injected into integrator 121 is as follows (one negative level):

[0136]

[0137] Where N ranges from 0 to

[0138] The current is integrated into the first integrator C. INT1 On the feedback capacitor, the first integrator C INT1 A triangular waveform is generated at node y1(t), and this triangular waveform also... Figure 8 The report shows that its peak values ​​are as follows:

[0139]

[0140] From this waveform, the input sequence of the feedback DAC can be selected starting from the value N / 2 instead of N, and Equation 6 defines some criteria for the selection of parameter N: high enough to generate a non-negligible signal y1(t) at the output of the first integrator 121, but small enough to avoid saturation of the stage in every possible process.

[0141] Therefore, the feedback DAC 122 (D / A1) associated with the second integrator 122 (and all other DACs in the case of modulators of order ≥3) is disabled, thus disconnecting it from the loop filter and setting its input value to 0, while the second integrator 122 (and all other integrators in the case of modulators of order ≥3) is reconfigured as a gain stage (for simplicity, a single gain can be assumed in this example).

[0142] There are different ways to perform this operation.

[0143] This is Figure 9 The diagram illustrates the possibility of converting the CT integrator into a gain G2, which is built around the operational transconductance amplifier (OTA) 300 either in the following manner (e.g., as shown at the top of the figure):

[0144] Use resistor R GAIN Replace feedback capacitor C INT In the first case (bottom left of the diagram), it can be constructed either in the following way:

[0145] Using capacitor C GAIN Replace input resistor R INT In the second case (bottom right of the image).

[0146] Although not shown in the diagram for simplicity, as Figure 2B Any of the integrators in the CTDSM illustrated herein (e.g., integrator 122 in the exemplary case considered herein) facilitates conversion to a gain level during test mode operation by including the following:

[0147] Feedback resistor R GAIN A switching circuit system has been associated, which is configured to connect resistor R during test mode operation. GAIN Replace the feedback capacitor C INT ,or

[0148] Input capacitor C GAIN A switching circuit system has been associated, which is configured to connect capacitor C during test mode operation. GAIN Replace the input resistor R INT .

[0149] The feedback path is disconnected by converter 132 (D / A1) and the second integrator 122 is replaced with a (e.g., single) gain stage with gain G2, so that the output y1(t) of the first integrator is still carried to the input of quantizer 14.

[0150] The subsequent modulus to D OUT A digital pulse sequence with alternating symbols was generated, such as Figure 8 As shown.

[0151] The amplitude of each sample can be calculated as follows:

[0152]

[0153] The "wheel" operation represents the quantization performed by the quantizer.

[0154] It should be noted that this expression takes into account all the variables involved in defining the feedback transfer function (for integrator circuits).

[0155] Therefore, these samples collect information involved in fully calibrating the modulator coefficients.

[0156] In theory, the data generated under this test mode can be used to develop a calibration process based on a certain search algorithm.

[0157] In fact, the “ideal” value of each output sample can be calculated from the ideal value of each parameter that appears in Equation 7, or simulated under typical conditions using some SPICE (a simulation program with an integrated circuit focus) simulator.

[0158] The deviation between the measured sequence and the calculated or simulated sequence can be used to correct the loop coefficients in order to recover the extension of the parameters and fit the desired noise transfer function (NTF).

[0159] In-depth analysis shows that the simple measurements discussed in this paper may not be entirely satisfactory for various calibration processes.

[0160] For example, the original output sequence may be affected by analog-level offsets, which may reduce the accuracy of the measurement.

[0161] Furthermore, the information is encoded using the quantization level of quantizer 14, so the sensitivity of the measurement may be offset by the low resolution of the circuit.

[0162] Addressing these two aspects helps to provide satisfactory results for almost all general calibration procedures.

[0163] This situation can be studied by first considering the sole effect of the offset of the second integrator 122 (in Figure 7During the test mode proposed in [the document], it is converted to a gain stage with gain G2.

[0164] It should be noted that the conclusions reported herein regarding the offset in the stage and the offset 14 of the quantizer apply to all integrators except the first integrator (i.e., integrator 121) (as indicated, the loop filter 12 may include more than two integrators).

[0165] For the offset of the second integrator 122, we can assume (for simplicity and ease of understanding) a single gain and a sum called V OFS2 The offset input reference source. This offset produces a shift of the signal y2(t), such as... Figure 10 As shown, this shift result is the asymmetric output of the quantizer, such as... Figure 10 As shown.

[0166] Ignoring the first sample, the generated sequence of numbers presents two distinct values, which can be calculated as follows:

[0167]

[0168]

[0169] Advantageously, these two values ​​can be used to achieve offset cancellation, where the offset exists with opposite signs in the two samples.

[0170] Therefore, the ideal moving average operation is as follows:

[0171]

[0172] This will generate sequence D. AVG However, there is no offset contribution factor.

[0173] Figure 11 The diagram illustrates a simplified way to implement this operation in DSP chain 18, which uses signal F at point 181. MOD The signal D modulated from quantizer 14 OUT (Therefore, the period generated in any manner known to those skilled in the art is 2T) S The square wave, for example via a square wave generator (not shown for simplicity), and the moving average filter 182 are applied to the modulated signal D. MOD .

[0174] In this (ideal) case, the moving average in filter 182 will be able to produce the output signal D. AVG without any offset contribution factor (see Figure 12 ).

[0175] Because at the input of quantizer 14, the desired useful information is mixed with the offset in the signal that a low-resolution quantizer with the required precision cannot resolve, the "wheel" operation of Equation 8, which is associated with the quantization process, plays an important role in system performance.

[0176] This can negatively impact the offset elimination process, and more generally, affect the accuracy of the entire test mode.

[0177] The resolution of the architecture discussed in this paper can be improved by applying jitter to quantizer 14.

[0178] like Figure 13 As shown, the dith(t) source 141 of the modulator remains on during test mode: this source is already available as a design feature of the type of converter discussed in this paper, which makes it unnecessary to provide specific additional descriptions.

[0179] With a static input signal, the jitter dith(t) (which may advantageously be half the amplitude of LSB) causes the output of quantizer 14 to switch between adjacent codes: this is likely to happen when the thermal noise contribution factor alone cannot produce any output change.

[0180] The resulting signal variability helps to improve system resolution by applying digital filtering that reduces noise bandwidth: the moving average introduced for offset cancellation also represents a possible filtering strategy in this case.

[0181] In this case, the average number defines the signal D output from filter 182. AVG The final accuracy (e.g., based on the calibration used) Figure 5 The resolution of the integrator coefficients shown is specified, so the number can be chosen to be greater than two.

[0182] Generally speaking, as a general rule, doubling the average number of LSBs can be expected to result in half the resolution gain.

[0183] If desired, more complex digital input patterns can be introduced to increase the variability of the analog signal. It should be noted that digital filters can be implemented through a dedicated reconfiguration of the decimation filters used in a digital signal processing (DSP) chain, which is typically associated with such an analog-to-digital converter.

[0184] Using this method, increasing the resolution will compromise the system bandwidth, and the expected signal will be located in the lower part of the spectrum.

[0185] From this perspective, block 181, which modulates the output from quantizer 14, may play an important role in performing baseband conversion on the desired signal and modulating the offset at half the sampling frequency: at this position, the offset tone is canceled out by the zeros associated with the moving average transfer function (which are advantageously selected by an even number of averages).

[0186] Another non-ideal case to be dealt with in the circuit discussed in this article is the offset of the first integrator.

[0187] In one approach discussed in this paper, this stage is not converted into a simple amplifier (gain stage) like other integrators, but retains its original function. In test mode, the integrator operates in an open-loop manner, and if its input offset is not managed, this offset can cause undesirable saturation of the stage.

[0188] like Figure 14 As illustrated in Figure 20, introducing chopping into the operational amplifier of the first integrator can effectively counteract this effect.

[0189] This stage defines the noise and offset performance of the entire converter, and chopping is usually provided as a design feature without additional hardware (and without the need for a detailed description of this known feature).

[0190] Chopper 20 offsets the first integrator (in) Figure 14 Named V OFS1 The impact of ) such as Figure 15 As shown, for simplicity, the signal from DAC D / A2 has been set to zero.

[0191] Signal F CHOP It is a square wave with zero mean (zero average value). The frequency of this square wave can be selected; for example, it equals F. S .

[0192] like Figure 15 As shown, the chopping frequency option generates an empty signal on the output at each sampling instant, thereby (completely) eliminating undesirable non-ideals through quantization.

[0193] The test pattern approach discussed in this paper helps to achieve an accurate digital representation of the process variations that affect the Δ-Σ modulator.

[0194] This information is contained in signal D. AVG It can be used to achieve appropriate coefficient calibration.

[0195] Depending on the desired accuracy, a simple one-time calibration or a more complex search algorithm can be provided.

[0196] Figure 16This is an example of "fully on-chip" calibration, in which the DSP circuitry 18 is configured to receive, for example, a target digital word D provided via a dedicated digital register. TGT (For example, from SPICE simulation calculations / extraction). For example... Figure 16 As shown, the DSP circuit system 18 can be configured to compare the target digital word D in the comparison node 183 (illustrated herein as a signed adder). TGT With the output D of the modulator AVG (Introduce the test mode) for comparison.

[0197] Based on the comparison results, a dedicated state machine 184 in the DSP circuit system (e.g., using the SAR algorithm) can control the variable C that changes the number of feedback capacitors in the first integrator. TRIM .

[0198] This trimming action can be performed in a variety of different ways known to those skilled in the art (e.g., using a combination of...). Figure 5 The technology shown is used for execution.

[0199] Otherwise, it should be noted that one or more embodiments do not specifically address how (in a manner known per se) such a trimming action is performed.

[0200] One or more embodiments primarily relate to generating variables in a reliable and simple manner, such as C TRIM Therefore, one or more embodiments can be largely "transparent" to a specific solution that can be used according to, for example, C. TRIM Variables like these can be used to perform adjustment actions.

[0201] For example, this operation can be repeated several times, depending on the control word C. TRIM The number of bits, and the state machine F SM The operating frequency takes into account the settling time of the moving average filter 182 used in the DSP chain 18.

[0202] For example, when the search is complete, the modulator can be set to its standard closed-loop configuration, and the digital word DW is provided to the trimmable integrator of (all) loop filters 12 and to the on-chip (e.g., ROM) for writing to the circuit / device.

[0203] As noted, although implementations with two integrators 121, 122 and two feedback ADCs 131, 132 have been discussed for simplicity, one or more embodiments may include more than two (n≥2) integrators with associated feedback DACs.

[0204] In this scenario, during test mode, the first integrator 121 will be driven again as previously discussed, while all other integrators will be reconfigured as gain stages, with the associated feedback DAC "zeroed" (i.e., the corresponding feedback path "opened"), as is the case with integrator 122 and DAC 132 in the exemplary dual-integrator case discussed by way of example in this document.

[0205] In short, the circuit 10 described herein includes an input node V IN The input node V IN Configured to receive analog input signals; and a quantizer circuit (A / D) 14 having an output node D OUT .

[0206] The quantizer circuit can operate at the output node D OUT The input node V is provided at the location. IN The digital signal generated by analog-to-digital conversion of the analog input signal at the location.

[0207] As illustrated, circuit 10 includes input node V IN Multiple (two or more) integrator circuits, such as 121, 122, are cascaded in the signal propagation path to quantizer circuit 14, and the first integrator circuit 121 in the cascade has a coupling to the input node V. IN It receives analog input signals from it.

[0208] Provide feedback network 16, which provides feedback to output node D OUT The device is sensitive to digital signals and includes multiple (two or more) digital-to-analog converters 131, 132, each coupled to a corresponding integrator circuit 121, 122. The analog converters 131, 132 are configured to output a digitally weighted signal D via coefficients such as k1 and k2. OUT The analog conversion copy is injected into the input of the corresponding integrator circuits 121 and 122.

[0209] As illustrated, circuit 10 also includes comparator circuit 183, which is configured to receive comparison signal D. AVG The comparison signal D AVG The digital signal D provided at the output node of circuit 10 OUT The function. The comparison signal is intended to be compared with the target digit D. TGT The comparison is performed, and (for example, at the signed adder node) a difference signal indicating the comparison result is generated.

[0210] Circuit 10 is configured (for example, via resistor R) GAIN or capacitor CGAIN It has been switched to test mode.

[0211] During the test mode, the digital-to-analog converter 131 coupled to the first integrator circuit 121 is configured to receive a periodically alternating digital sequence DS instead of the digital output signal D. OUT A weighted simulation of a copy.

[0212] During test mode, integrator circuit 122 cascaded to first integrator circuit 121 is reconfigured as a gain stage (see, for example, G2 of integrator circuit 122), wherein the digital-to-analog converter (132 herein) coupled to the gain stage is disabled.

[0213] This interrupts the output of the digital signal D. OUT The weighted analog-converted copy is input to the corresponding integrator circuit 122, and the comparator circuit 18 (e.g., via a SAR process illustrated at 184) generates a digital calibration signal C for the integrator circuits 121, 122 (at least one of the integrator circuits) based on the difference signal (183). TRIM .

[0214] Advantageously, the digital-to-analog converter D / A2 coupled to the first integrator circuit 121 can be configured to receive a periodic alternating digital sequence DS with a pattern -N, -N, +N, +N, which optionally begins after a first single sample with a value of N / 2.

[0215] Advantageously, the quantizer circuit 14 can be used during the sampling period T S Operation. The digital-to-analog converter D / A1 coupled to the first integrator circuit 121 can be configured to receive a periodically alternating digital sequence DS, where each value in -N or +N is maintained equal to the sampling period T. S The time.

[0216] Advantageously, the comparator circuit system 18 may include a modulator 181, which is configured to utilize a square wave signal F MOD The digital signal D provided at the output node is modulated. OUT To generate the modulation signal D MOD ; and a moving average filter 181 to which a modulated signal D is supplied. MOD The moving average filter is configured to generate a comparison signal D. AVG Used with the target digit D TGT The comparison signal D is compared. AVG For the modulated signal D MOD Apply moving average filtering.

[0217] Advantageously, modulator 181 can be configured to generate a modulated signal D MOD The modulated signal D MOD The usage period is the sampling period T of quantizer circuit 14. S Twice the square wave signal F MOD Modulate the digital signal D at the output node. OUT .

[0218] Advantageously, the comparator circuit system 18 may include a state machine 184 configured to generate a digital calibration signal C based on the difference signal 183. TRIM To change the operating parameters in (at least) the first integrator circuit 121.

[0219] Advantageously, a jitter source coupled to the quantizer circuit 14 can be provided (e.g., see [reference]). Figure 13 141 in the middle).

[0220] Advantageously, the first integrator circuit 121 may include a chopper amplifier (e.g., see [link]). Figure 14 F in CHOP ).

[0221] Devices such as continuous-time Δ-Σ modulators (CTDSMs) as illustrated herein may include circuitry 10 as previously discussed, wherein comparator circuitry 18, together with integrator circuitry 121, 122, feedback networks 16, 131, 132, and quantizer circuitry 14, is integrated into a single integrated device to generate a digital calibration signal CTRIM for integrator circuitry 121, 122 (at least one of the integrator circuits) via the SAR process illustrated in block 184.

[0222] Methods of operating such a circuit or system may include switching the circuit to a test mode as previously discussed.

[0223] During this test mode, the calibration or comparator circuit system 18 generates a digital calibration signal CTRIM for the integrator circuits 121, 122 (at least one of the integrator circuits) based on the difference signal 183.

[0224] Therefore, calibration of one or more integrator circuits can be performed based on the difference signal.

[0225] After calibration, normal operation of circuit 10 can be restored, in which all integrator circuits 121 and 122 are restored to integrator operation, with the first integrator circuit 121 in the cascade starting from input node V. IN Receive analog input signals.

[0226] As circuit 10 resumes normal operation, the digital-to-analog converters 131 and 132 in feedback network 16 again generate digital output signals D weighted by coefficients such as k1 and k2. OUT The analog conversion copy is injected into the input of the corresponding integrator circuits 121 and 122.

[0227] Figure 17 This is a functional block diagram of an embodiment of an electronic device or system 1700 of the type to which the described embodiments can be applied. System 1700 includes one or more processing cores or circuits 1702. Processing core 1702 may include, for example, one or more processors, state machines, microprocessors, programmable logic circuits, discrete circuit systems, logic gates, registers, etc., and various combinations thereof. Processing core 1702 can control the overall operation of system 1700, the execution of application programs by system 1700, etc.

[0228] System 1700 includes one or more memories 1704, such as one or more volatile memories and one or more NVMs, which may store all or part of instructions and data related to, for example, control of system 1700, application of system 1700 and operations performed by system 1700.

[0229] System 1700 may include one or more interfaces 1750 (e.g., wireless communication interfaces, wired communication interfaces, controller interfaces, etc.) and other functional circuitry 1760, which may include antennas, power supplies, controllers, motors, etc., as well as a main bus system 1770. The main bus system 1770 may include one or more data, address, power, and / or control buses coupled to various components of system 100. System 100 may also include additional bus systems, such as dedicated bus systems that couple one or more processors 1702 in processors 1702 to one or more memories 1704 in memories 1704.

[0230] System 1700 includes one or more sensors 1706, such as image sensors, audio sensors, accelerometers, pressure sensors, temperature sensors, encoders or other position sensors, and various combinations thereof, which can provide sensor data for use, for example, by applications running on a processor, controllers that control the operation of devices (e.g., motor controllers that control motors), and various combinations thereof.

[0231] As illustrated, system 1700 includes an analog-to-digital converter 1780, which can be used to convert analog data (such as analog data generated by one or more sensors 1706 in the sensor 1706) into digital data (such as digital data samples), which can then be used by various applications of the system. The illustrated analog-to-digital converter includes a Δ-Σ modulator 1710 and a calibration circuit system 1718. For example, Figure 16 The Δ-Σ modulator 10 and calibration circuit system 18 can be used Figure 17 An example of an analog-to-digital converter 1780.

[0232] Figure 17 Embodiments of system 1700 may include more components than those illustrated, may include fewer components than those illustrated, may combine or separate the illustrated components, and various combinations thereof. For example, instead of having sensor 1706 and a separate analog-to-digital converter 1780, one or more sensors 1706 may be modified to include analog-to-digital converter 1780. System 1700 may include a system-on-a-chip (SoC), discrete chips coupled together, or various combinations thereof.

[0233] Without departing from the level of protection, details and embodiments may vary relative to what is disclosed herein by way of example only.

[0234] A circuit (10) can be summarized as including an input node (V) configured to receive an analog input signal. IN A quantizer circuit (A / D, 14) has an output node (D OUT The quantizer circuit (A / D, 14) is operable at the output node (D... OUT The input node (V) provides the information at the input node. IN The analog input signal at point () is converted from analog to digital to generate a digital signal, and multiple integrator circuits (1 / s; 121, 122) convert the signal from the input node (V) to a digital signal. IN The signal propagation path from the quantizer circuit (A / D, 14) is cascaded, and the first integrator circuit (121) in the cascade has an input that is coupled to the input node (V). IN ), to receive analog input signals from it, and the feedback network (16) to the output node (D) OUT The feedback network is sensitive to the digital signal at the input node (V). It includes multiple digital-to-analog converters (131, 132; D / A1, D / A2), each of which is coupled to the input node (V). IN The corresponding integrator circuits (1 / s; 121, 122) in the signal propagation path from the digital output signal (D) to the quantizer circuit (A / D, 14) are configured to convert the digital output signal (D) into a digital output signal (D). OUTThe weighted (k1, k2) analog-to-digital converter copies of the signal are injected into the inputs of the corresponding integrator circuits (1 / s; 121, 122), and the comparator circuit system (18) is configured to receive the comparison signal (D). AVG The comparison signal (D) AVG ) is the digital signal (D) provided at the output node. OUT The function is used to interact with the target digit (D). TGT The circuit is configured to perform a comparison; and generate (183) different signals indicating the result of the comparison, wherein the circuit is configured to (R) GAIN C GAIN The circuit is switched to test mode, during which the digital-to-analog converter (131; D / A2) coupled to the first integrator circuit (121) is configured to receive a periodically alternating digital sequence (DS) instead of the digital output signal (D). OUT The weighted (k2) simulated transformation copy of the input node (V) is generated from the input node (V). IN One or more integrator circuits (122) cascaded to the first integrator circuit (121) in the signal propagation path from the quantizer circuit (A / D, 14) are reconfigured (R GAIN C GAIN The signal is routed to a gain stage (G2), where the digital-to-analog converter (132; D / A1) coupled to this gain stage (G2) is disabled, and an interrupt is applied to the digital output signal (D). OUT The weighted (k1) analog-to-digital converter copy of the input is fed into the corresponding integrator circuit (1 / s; 122), and the comparator circuit system (18) generates (184) for use at the input node (V). IN The digital calibration signal (C) of at least one integrator circuit in the cascaded integrator circuits (1 / s; 121, 122) in the signal propagation path from the quantizer circuit (A / D, 14) to the quantizer circuit (A / D, 14) is a digital calibration signal. TRIM ), as a function of the difference signal (183).

[0235] The digital-to-analog converter (D / A1) coupled to the first integrator circuit (121) can be configured to receive the periodic alternating digital sequence (DS) having a pattern -N, -N, +N, +N, which, for example, begins after a first single sample with a value of N / 2.

[0236] The quantizer circuit (A / D, 14) can operate during the sampling period (T) S The digital-to-analog converter (D / A1) coupled to the first integrator circuit (121) can be configured to receive the periodic alternating digital sequence (DS), wherein each of the values ​​-N or +N is maintained equal to the sampling period (T). S (Time)

[0237] The comparator circuit system (18) may include a modulator (181) configured to generate a modulated signal (D). MOD The modulated signal (D) MOD Using square wave signals (F) MOD The digital signal (D) provided at the output node is modulated. OUT ); and moving average filter (D MOD )182, the moving average filter is supplied with the modulated signal (D) MOD And is configured to generate a comparison signal (D) AVG ), used with modulated signals (D MOD The target digital character (D) is subjected to a moving average filter. TGT (Compare)

[0238] The quantizer circuit (A / D, 14) can operate during the sampling period (T) S The modulator (181) can be configured to generate a usage period that is the sampling period (T) under the following conditions. S Twice the size of the square wave signal (F) MOD The digital signal (D) provided at the output node is modulated. OUT The modulated signal (D) MOD ).

[0239] The comparator circuit system (18) may include a state machine (184) configured to generate the digital calibration signal (C) based on the difference signal (183). TRIM ) to change from the input node (V IN The operating parameters in the first integrator circuit (121) in the signal propagation path from the quantizer circuit (A / D, 14) to the quantizer circuit (A / D, 14).

[0240] The circuit may include a jitter source (141) coupled to the quantizer circuit (A / D, 14), the jitter source (141) being operable to the output node (D OUT The digital signal is provided at ( ).

[0241] From the input node (V) IN The first integrator circuit (121) in the signal propagation path from the quantizer circuit (A / D, 14) to the quantizer circuit (F) may include a chopper amplifier (F) CHOP ).

[0242] The comparator circuit system (18) can be integrated with the plurality of integrator circuits (1 / s; 121, 122), the feedback network (16, 131, 132), and the quantizer circuit (A / D, 14) into a single integrated device to generate (184) from the input node (VIN The digital calibration signal (C) of at least one integrator circuit (1 / s; 121, 122) cascaded in the signal propagation path from the quantizer circuit (A / D, 14) to the quantizer circuit (A / D, 14) is transmitted to the quantizer circuit (A / D, 14). TRIM ).

[0243] A method of operating a circuit or device can be summarized as including switching the circuit (10) to the test mode, wherein the comparator circuit system (18) generates (184) from the input node (V) based on the difference signal (183). IN The digital calibration signal (C) of at least one integrator circuit (1 / s; 121, 122) cascaded in the signal propagation path from the quantizer circuit (A / D, 14) to the quantizer circuit (A / D, 14) is transmitted to the quantizer circuit (A / D, 14). TRIM ); based on the difference signal (183), perform the operation on the input node (V) IN Calibration of at least one integrator circuit among the integrator circuits (1 / s; 121, 122) cascaded in the signal propagation path from the input node (V) to the quantizer circuit (A / D, 14); and after calibration, restoration of operation of the circuit (10), wherein during operation, the signal propagation path from the input node (V) to the quantizer circuit (A / D, 14) is calibrated; and after calibration, restoration of operation of the circuit is restored (10), wherein during operation, the signal propagation path from the input node (V) is calibrated; and after calibration, restoration of operation of the circuit is restored (10), wherein the signal propagation path from the input node (A / D, 14 ... IN All integrator circuits (1 / s; 121, 122) cascaded in the signal propagation path to the quantizer circuit (A / D, 14) resume integrator operation, wherein the first integrator circuit (121) in the cascade receives at the input node (V IN The analog input signal at the location is fed back to the analog input signal. The multiple digital-to-analog converters (131, 132; D / A1, D / A2) in the feedback network (16) convert the analog input signal into the digital output signal (D). OUT The weighted (k1, k2) analog conversion copies are injected into the corresponding integrator circuits (1 / s; 121, 122).

[0244] In one embodiment, a device includes a Δ-Σ modulator having an input node; a quantizer; a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer; and a feedback network including a plurality of digital-to-analog converters (DACs). In quantization operation mode, each of the plurality of DACs in the feedback network is coupled between the output of the quantizer and a corresponding integrator of the plurality of cascaded integrators; and the Δ-Σ modulator generates a digital signal at the output of the quantizer based on an analog input signal received at the input node. In calibration operation mode, a calibration circuit system is coupled to the output of the quantizer. A first DAC of the plurality of DACs in the feedback network receives a signal comprising a periodically alternating digital sequence, and the first DAC is coupled to a first integrator of the plurality of cascaded integrators. The integrators other than the first integrator of the plurality of cascaded integrators operate in gain operation mode. The Δ-Σ modulator generates a digital test signal at the output of the quantizer based on the signal comprising a periodically alternating digital sequence, and the calibration circuit system generates an integrator calibration signal based on the digital test signal and a reference digital word.

[0245] In one embodiment, the signal propagation path includes a first adder having a first input coupled to an input node, a second input coupled to the output of a first digital-to-analog converter (DAC), and an output coupled to the input of a first integrator; and a second adder having a first input coupled to the output of the first integrator and an output coupled to the input of a second integrator of a plurality of cascaded integrators, wherein in quantization operation mode, the second input of the second adder is coupled to the output of the second DAC of the plurality of cascaded integrators of the feedback network. In another embodiment, in calibration operation mode, operation of the second DAC is disabled.

[0246] In an embodiment, during quantization operation mode, the digital-to-analog converter of the feedback network generates a corresponding weighted analog copy of the quantizer's output. In an embodiment, the periodically alternating digital sequence is a pattern of the form -N, -N, +N, +N, where N is a defined digital value. In an embodiment, the signal comprising the periodically alternating digital sequence includes the value N / 2, followed by the periodically alternating digital sequence. In an embodiment, the quantizer has a sampling period, and the periodically alternating digital sequence maintains the value -N or +N for a time equal to the sampling period.

[0247] In one embodiment, the calibration circuit system includes a modulator that, in calibration operation mode, modulates the output of a quantizer using a square wave signal to generate a modulated signal; a moving average filter that, in calibration operation mode, generates an average signal based on the modulated signal; and a comparator that, in calibration operation mode, compares the average signal with a reference digital word to generate a difference signal. In one embodiment, in calibration operation mode, the quantizer has a sampling period, and the period of the square wave signal is twice the sampling period. In one embodiment, the calibration circuit system includes a state machine that generates an integrator calibration signal based on the difference signal in calibration operation mode. In one embodiment, the device includes a dithering circuit coupled to an input of a signal propagation path, wherein the dithering circuit generates a dither signal in calibration operation mode. In one embodiment, the signal propagation path includes a chopper amplifier coupled to the input of a first integrator of a plurality of cascaded integrators. In one embodiment, in calibration operation mode, the trimmed values ​​of the plurality of integrators are set based on the integrator calibration signal. In one embodiment, the device includes an integrated circuit that includes a Δ-Σ modulator and the calibration circuit system.

[0248] In one embodiment, a system includes a sensor; a Δ-Σ modulator coupled to the sensor, the Δ-Σ modulator having a quantizer; a signal propagation path including a plurality of cascaded integrators coupled between the sensor and the quantizer; and a feedback network including a plurality of digital-to-analog converters (DACs), wherein in a quantization operation mode, each of the plurality of DACs in the feedback network is coupled between the output of the quantizer and a corresponding integrator of the plurality of cascaded integrators; and the Δ-Σ modulator generates a digital signal at the output of the quantizer based on an analog input signal received from the sensor; and a calibration circuit system coupled to the output of the quantizer, wherein in a calibration operation mode, a first DAC of the plurality of DACs in the feedback network receives a signal comprising a periodically alternating digital sequence, the first DAC being coupled to a first integrator of the plurality of cascaded integrators; the integrators of the plurality of cascaded integrators other than the first integrator operating in a gain operation mode; the Δ-Σ modulator generates a digital test signal at the output of the quantizer based on the signal comprising a periodically alternating digital sequence; and the calibration circuit system generates an integrator calibration signal based on the digital test signal and a reference digital word. In an embodiment, the periodically alternating digital sequence is a pattern of the form -N, -N, +N, +N, where N is a defined numerical value. In an embodiment, the signal including the periodically alternating digital sequence includes the value N / 2, followed by the periodically alternating digital sequence. In an embodiment, the calibration circuit system includes a modulator that, in calibration operation mode, modulates the output of a quantizer using a square wave signal to generate a modulated signal; a moving average filter that, in calibration operation mode, generates an average signal based on the modulated signal; and a comparator that, in calibration operation mode, compares the average signal with a reference digital word to generate a difference signal. In an embodiment, in calibration operation mode, the quantizer has a sampling period, and the period of the square wave signal is twice the sampling period. In an embodiment, the calibration circuit includes a state machine that, in calibration operation mode, generates an integrator calibration signal based on the difference signal.

[0249] In one embodiment, a method includes: operating a Δ-Σ modulator having a calibration circuitry in a calibration operation mode to generate an integrator calibration signal; calibrating the Δ-Σ modulator based on the integrator calibration signal; operating the calibrated Δ-Σ modulator in a quantization operation mode, wherein the Δ-Σ modulator includes an input node; a quantizer; a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer; and a feedback network including a plurality of digital-to-analog converters, wherein in the quantization operation mode, the calibration circuitry is coupled to the output of the quantizer; a first digital-to-analog converter of the plurality of digital-to-analog converters in the feedback network receives a signal comprising a periodically alternating digital sequence, the first... A digital-to-analog converter (DAC) is coupled to a first integrator in a plurality of cascaded integrators; the integrators other than the first integrator in the plurality of cascaded integrators operate in gain operation mode; a delta-sigma modulator generates a digital test signal at the output of a quantizer based on a signal comprising a periodically alternating digital sequence; and a calibration circuit system generates an integrator calibration signal based on the digital test signal and a reference digital word, wherein in quantization operation mode, each of the plurality of DACs in the feedback network is coupled between the quantizer and its corresponding integrator in the plurality of cascaded integrators; and the delta-sigma modulator generates a digital signal at the output of the quantizer based on an analog input signal received at the input node. In an embodiment, the periodically alternating digital sequence is a pattern having the form -N, -N, +N, +N, where N is a defined digital value. In an embodiment, the signal comprising the periodically alternating digital sequence includes the value N / 2, followed by the periodically alternating digital sequence. In one embodiment, the calibration circuit system includes a modulator that, in calibration operation mode, modulates the output of a quantizer using a square wave signal to generate a modulated signal; a moving average filter that, in calibration operation mode, generates an average signal based on the modulated signal; and a comparator that, in calibration operation mode, compares the average signal with a reference digital word to generate a difference signal.

[0250] In one embodiment, the content of a non-transitory computer-readable medium configures a Δ-Σ modulator having a calibration circuitry system to perform a method comprising: operating the Δ-Σ modulator in a calibration operation mode to generate an integrator calibration signal; calibrating the Δ-Σ modulator based on the integrator calibration signal; and operating the calibrated Δ-Σ modulator in a quantization operation mode, wherein the Δ-Σ modulator includes an input node; a quantizer; a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer; and a feedback network including a plurality of digital-to-analog converters, wherein in the quantization operation mode, the calibration circuitry system is coupled to the output of the quantizer; and a first digital-to-analog converter of the plurality of digital-to-analog converters in the feedback network receives packets. The signal includes a periodically alternating digital sequence. A first digital-to-analog converter (DAC) is coupled to a first integrator in a plurality of cascaded integrators. The integrators other than the first integrator operate in gain mode. A delta-sigma modulator generates a digital test signal at the output of a quantizer based on the signal including the periodically alternating digital sequence. A calibration circuit system generates an integrator calibration signal based on the digital test signal and a reference digital word. In quantization mode, each DAC in the feedback network is coupled between the quantizer and a corresponding integrator in the plurality of cascaded integrators. The delta-sigma modulator generates a digital signal at the output of the quantizer based on an analog input signal received at the input node. In an embodiment, the periodically alternating digital sequence is a pattern of the form -N, -N, +N, +N, where N is a defined digital value. In an embodiment, the content includes instructions executed by the processing device of the delta-sigma modulator.

[0251] Some embodiments may take the form of or include a computer program product. For example, according to one embodiment, a computer-readable medium is provided that includes a computer program adapted to perform one or more of the methods or functions described above. The medium may be a physical storage medium, such as, for example, a read-only memory (ROM) chip, or a disk, such as a digital multifunction disc (DVD-ROM), a compact disc (CD-ROM), a hard disk, a memory, a network, or a portable media article to be read by a suitable drive or via a suitable connection, the portable media article including articles in other relevant codes such as those encoded in one or more barcodes or stored on one or more such computer-readable media and readable by a suitable reader device.

[0252] Furthermore, in some embodiments, some or all of the methods and / or functions may be implemented or provided in other ways, such as at least in part in firmware and / or hardware, including but not limited to one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuit systems, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions and including microcontrollers and / or embedded controllers), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and devices employing RFID technology and various combinations thereof.

[0253] Other embodiments can be provided by combining the various embodiments described above. These and other changes can be made to the embodiments based on the specific embodiments described above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments and equivalents of the full scope of those claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A self-calibrating device comprising: a delta-sigma modulator having: an input node; a quantizer; a signal propagation path comprising a plurality of cascaded integrators coupled between the input node and the quantizer; and a feedback network comprising a plurality of digital-to-analog converters, wherein in a quantization mode of operation, each digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network is coupled between an output of the quantizer and a respective integrator of the plurality of cascaded integrators; and the delta-sigma modulator generates a digital signal at an output of the quantizer based on an analog input signal received at the input node; and calibration circuitry coupled to the output of the quantizer, wherein in a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal comprising a periodic alternating digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators; integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation; the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal comprising the periodic alternating digital sequence; and the calibration circuitry generates an integrator calibration signal based on the digital test signal and a reference digital word.

2. The device of claim 1, wherein the signal propagation path comprises: a first summer having: a first input coupled to the input node; a second input coupled to an output of the first digital-to-analog converter; and an output coupled to an input of the first integrator; and a second summer having: a first input coupled to an output of the first integrator; and an output coupled to an input of a second integrator of the plurality of cascaded integrators, wherein in the quantization mode of operation, a second input of the second summer is coupled to an output of a second digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network.

3. The device of claim 2, wherein in the calibration mode of operation, operation of the second digital-to-analog converter is disabled.

4. The device of claim 1, wherein in the quantization mode of operation, the digital-to-analog converters of the feedback network generate respective weighted analog replicas of the output of the quantizer.

5. The device of claim 1, wherein the periodic alternating digital sequence is a pattern having the form -N, -N, +N, +N, where N is a defined digital value.

6. The device of claim 5, wherein the signal comprising the periodic alternating digital sequence includes a value N / 2 followed by the periodic alternating digital sequence.

7. The device of claim 5, wherein the quantizer has a sampling period, and the periodic alternating digital sequence maintains a value of -N or +N for a time equal to the sampling period.

8. The device of claim 1, wherein the calibration circuitry comprises: ​ ​ ​ a modulator, in the calibration operating mode, to modulate the output of the quantizer with a square wave signal, thereby generating a modulated signal; a moving average filter, in the calibration operating mode, to generate an average signal based on the modulated signal; and a comparator, in the calibration operating mode, to compare the average signal to a reference digital word, thereby generating a difference signal.

9. The apparatus of claim 8, wherein in the calibration operating mode: the quantizer has a sampling period, and a period of the square wave signal is twice the sampling period.

10. The apparatus of claim 8, wherein the calibration circuitry comprises a state machine to generate the integrator calibration signal from the difference signal in the calibration operating mode.

11. The apparatus of claim 1, comprising a dithering circuit coupled to an input of the signal propagation path, wherein the dithering circuit generates a dithering signal in the calibration operating mode.

12. The apparatus of claim 1, wherein the signal propagation path comprises a chopper amplifier coupled to an input of the first integrator of the plurality of cascaded integrators.

13. The apparatus of claim 1, wherein in the calibration operating mode, trim values of the plurality of integrators are set based on the integrator calibration signal.

14. The apparatus of claim 1, comprising an integrated circuit comprising the delta-sigma modulator and the calibration circuitry.

15. A self-calibrating system, comprising: a sensor; a delta-sigma modulator coupled to the sensor, the delta-sigma modulator having: a quantizer; a signal propagation path comprising a plurality of cascaded integrators coupled between the sensor and the quantizer; and a feedback network comprising a plurality of digital-to-analog converters, wherein in a quantization operating mode, each digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network is coupled between an output of the quantizer and a respective integrator of the plurality of cascaded integrators; and the delta-sigma modulator generates a digital signal at the output of the quantizer based on an analog input signal received from the sensor; and calibration circuitry coupled to the output of the quantizer, wherein in a calibration operating mode, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal comprising a periodic alternating digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators; integrators of the plurality of cascaded integrators other than the first integrator operate in a gain operating mode; the delta-sigma modulator generates a digital test signal at the output of the quantizer based on the signal comprising the periodic alternating digital sequence; and the calibration circuitry generates an integrator calibration signal based on the digital test signal and a reference digital word. ​ 16. The system of claim 15, wherein the periodic alternating digital sequence is a pattern having the form -N, -N, +N, +N, where N is a defined digital value.

17. The system of claim 16, wherein the signal including the periodic alternating digital sequence includes a value N / 2 followed by the periodic alternating digital sequence.

18. The system of claim 15, wherein the calibration circuitry comprises: a modulator that, in the calibration operating mode, modulates the output of the quantizer with a square wave signal, thereby generating a modulated signal; a moving average filter that, in the calibration operating mode, generates an average signal based on the modulated signal; and a comparator that, in the calibration operating mode, compares the average signal to a reference digital word, thereby generating a difference signal.

19. The system of claim 18, wherein in the calibration operating mode: the quantizer has a sampling period, and a period of the square wave signal is twice the sampling period.

20. The system of claim 18, wherein the calibration circuitry comprises a state machine that, in a calibration operating mode, generates the integrator calibration signal based on the difference signal.

21. A method of self-calibration, comprising: operating a delta-sigma modulator having calibration circuitry in a calibration operating mode, thereby generating an integrator calibration signal; calibrating the delta-sigma modulator based on the integrator calibration signal; and operating the calibrated delta-sigma modulator in a quantization operating mode, wherein the delta-sigma modulator comprises: an input node; a quantizer; a signal propagation path comprising a plurality of cascaded integrators coupled between the input node and the quantizer; and a feedback network comprising a plurality of digital-to-analog converters, in the quantization operating mode, the calibration circuitry is coupled to an output of the quantizer; a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal comprising a periodic alternating digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators; integrators of the plurality of cascaded integrators other than the first integrator operate in a gain operating mode; the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal comprising the periodic alternating digital sequence; and the calibration circuitry generates an integrator calibration signal based on the digital test signal and a reference digital word; and in the quantization operating mode, each digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network is coupled between the output of the quantizer and a respective integrator of the plurality of cascaded integrators; and the delta-sigma modulator generates a digital signal at the output of the quantizer based on an analog input signal received at the input node. ​ ​ 22. The method of claim 21, wherein the periodic alternating digital sequence is a pattern having the form -N, -N, +N, +N, where N is a defined digital value.

23. The method of claim 22, wherein the signal including the periodic alternating digital sequence includes a value N / 2 followed by the periodic alternating digital sequence.

24. The method of claim 21, wherein the calibration circuitry comprises: a modulator that, in the calibration operating mode, modulates the output of the quantizer with a square wave signal, thereby generating a modulated signal; a moving average filter that, in the calibration operating mode, generates an average signal based on the modulated signal; and a comparator that, in the calibration operating mode, compares the average signal to a reference digital word, thereby generating a difference signal.

25. A non-transitory computer-readable medium having content that configures a delta-sigma modulator having calibration circuitry to perform a method comprising: operating the delta-sigma modulator in a calibration operating mode, thereby generating an integrator calibration signal; calibrating the delta-sigma modulator based on the integrator calibration signal; and operating the calibrated delta-sigma modulator in a quantization operating mode, wherein the delta-sigma modulator comprises: an input node; a quantizer; a signal propagation path comprising a plurality of cascaded integrators coupled between the input node and the quantizer; and a feedback network comprising a plurality of digital-to-analog converters, in the quantization operating mode, the calibration circuitry is coupled to an output of the quantizer; a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal comprising a periodic alternating digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators; integrators of the plurality of cascaded integrators other than the first integrator operate in a gain operating mode; the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal comprising the periodic alternating digital sequence; and the calibration circuitry generates an integrator calibration signal based on the digital test signal and a reference digital word, and in the quantization operating mode, each digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network is coupled between the output of the quantizer and a respective integrator of the plurality of cascaded integrators; and the delta-sigma modulator generates a digital signal at the output of the quantizer based on an analog input signal received at the input node.

26. The non-transitory computer-readable medium of claim 25, wherein the periodic alternating digital sequence is a pattern having the form -N, -N, +N, +N, where N is a defined digital value.

27. The non-transitory computer-readable medium of claim 25, wherein the content comprises instructions executed by a processing device of the delta-sigma modulator. ​ ​

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