Method and device for processing data

Abstract

The present disclosure provides a method and device for processing data. The method comprises: for input data for Fourier transform, using a vector processor to perform a multi-level first vector operation including a butterfly operation and a reordering operation to obtain first intermediate result data, the reordering operation is used to convert the order of the operation result of the butterfly operation into a positive order; dividing the first intermediate result data into a plurality of butterfly operation groups, the amount of data in each operation group is consistent with the amount of data in the SIMD instruction, using a vector processor to perform one or more levels of butterfly operations on the plurality of butterfly operation groups to obtain a second intermediate result; using a vector processor to perform a vector-level reverse carry operation on the second intermediate result to obtain a Fourier transform result. The present application divides the data into butterfly operation groups consistent with the SIMD width through the reordering operation, and adopts a vector-level reverse carry operation, and uses a vector processor to realize the positive order input and output of data, thereby improving the processing efficiency.

Description

Technical Field

[0001] The present disclosure relates to the field of wireless communication technology, and in particular to a method and device for processing data. Background Art

[0002] As an important algorithm for digital signal processing, Fourier transform can be widely used in the field of communication technology. For example, Fourier transform can be used for signal modulation and demodulation in UMTS Long Term Evolution (LTE) or 5G New Radio (5GNR). The existing technology has the problems of low processing efficiency and high cost when performing Fourier transform on data. Summary of the invention

[0003] The present application provides a method and device for processing data. The following introduces various aspects involved in the embodiments of the present application.

[0004] In a first aspect, a method for processing data is provided, comprising: obtaining Fourier transform input data; using a vector processor to perform multiple levels of first vector operations on the input data to obtain first intermediate result data, wherein the first vector operation includes a butterfly operation and a reordering operation, and the reordering operation is used to convert the order of the operation result of the butterfly operation into a positive order; dividing the first intermediate result data into multiple butterfly operation groups containing N data elements, N is the number of vector processing data in a SIMD instruction of the vector processor, and using the vector processor to perform one or more levels of second vector operations on the multiple butterfly operation groups to obtain a second intermediate result, wherein the second vector operation is a butterfly operation; using the vector processor to perform a third vector operation on the second intermediate result to obtain the result of the Fourier transform, wherein the third vector operation is a vector-level reverse carry operation.

[0005] In a second aspect, a device for processing data is provided, comprising: an acquisition unit, configured to acquire Fourier transformed input data; a first execution unit, configured to use a vector processor to perform multiple levels of first vector operations on the input data to obtain first intermediate result data, wherein the first vector operation includes a butterfly operation and a reordering operation, and the reordering operation is used to convert the order of the operation result of the butterfly operation into a positive order; a second execution unit, configured to divide the first intermediate result data into multiple butterfly operation groups containing N data elements, N is the number of vector processing data in the SIMD instruction of the vector processor, and use the vector processor to perform one or more levels of second vector operations on the multiple butterfly operation groups to obtain a second intermediate result, wherein the second vector operation is a butterfly operation; a third execution unit, configured to use the vector processor to perform a third vector operation on the second intermediate result to obtain the result of the Fourier transform, wherein the third vector operation is a vector-level reverse carry operation.

[0006] According to a third aspect, a computer program product is provided, the computer program product comprising: a computer program code, when the computer program code is run on a computer, the computer executes the methods in the above aspects.

[0007] According to a fourth aspect, a computer-readable medium is provided, wherein the computer-readable medium stores a program code, and when the computer program code is executed on a computer, the computer executes the methods in the above aspects.

[0008] The present application uses butterfly-weighted reverse-order operations to make the data after butterfly operations in positive order. The degree of data mixing is the width of SIMD. Vector-level butterfly operations are performed on operation groups, and after the butterfly operations, vector-level reverse-order operations are performed on the operation groups. Vector processors are used to implement positive-order input and output of data, thereby improving data processing efficiency and saving costs and overheads of software and hardware interactions. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A flowchart of a method for processing data provided in an embodiment of the present application.

[0010] Figure 2 A schematic diagram of a feasible 64-point FFT data processing process provided in an embodiment of the present application.

[0011] Figure 3 A schematic diagram of data reordering provided in an embodiment of the present application.

[0012] Figure 4 Another data reordering schematic diagram provided in an embodiment of the present application.

[0013] Figure 5 A schematic diagram of a feasible 72-point DFT data processing process provided in an embodiment of the present application.

[0014] Figure 6 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0016] Fourier transform is a very important algorithm in the field of digital signal processing, which can represent any continuously measured time series or signal as an infinite superposition of sine wave signals of different frequencies. The Fourier transform can be used to convert difficult-to-process signals into frequency domain signals that are easy to analyze, while the inverse Fourier transform can be used to convert frequency domain signals into time domain signals. It should be noted that the Fourier transform mentioned in the embodiments of the present application may refer to the Fourier transform or the inverse Fourier transform.

[0017] There are many types of Fourier transform, such as Discrete Fourier Transform (DFT), Inverse Discrete Fourier Transform (IDFT), Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT). Discrete Fourier Transform (DFT) / Inverse Discrete Fourier Transform (IDFT) is widely used in various transform domain processing occasions. For example, in the field of computer vision (CV), the data in the time domain is usually transformed to the frequency domain by DFT for processing, and then inversely transformed to the time domain by IDFT. Fast Fourier transform (FFT) is a fast calculation method of DFT, and inverse fast Fourier transform (IFFT) is a fast calculation method of IDFT. The Fourier transform method mentioned in the embodiment of the present application can be applied to any of the above types of Fourier transforms.

[0018] Reversing the bit order can also be called reordering. It is a necessary step in Fourier transform. It can output the data stream (or a set of data) that is sequentially input into the Fourier transform module in the order of binary bit reversal (i.e., reversed bit order). When performing FFT / DFT transform, the data input in positive order undergoes multi-stage butterfly operations. The butterfly is the largest at the beginning, and the butterfly will become smaller and smaller during the processing, and finally form the reversed processed data; the data input in reverse order has the smallest butterfly at the beginning, and it will become larger and larger during the processing, and finally form the result of positive order. The processing process of IFFT / IDFT can be the same as that of FFT / DFT, except that the coefficients are different.

[0019] Taking 16-point FFT data as an example, the data is input in positive order, that is, in the order of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15. After FFT transformation, the data is output in reverse order, that is, in the order of 0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15. Taking 8-point FFT reverse order input as an example, the data is input in reverse order of 0, 4, 2, 6, 1, 5, 3, 7, and after FFT transformation, it is output in positive order of 0, 1, 2, 3, 4, 5, 6, 7.

[0020] When performing frequency domain data processing, it is hoped that the data is input in positive order and output in positive order, so there is a process of reversing the order of the data after the transformation, including reversing the order of the positive order data before input to obtain the positive order output data or reversing the reversal of the order of the output data to positive order after the transformation. In the related art, the reversal of the data is a point-level processing process, which does not match the data parallel technology in the current vector processor. In other words, the reversal of the data is at the point level, and the processor, such as the central processing unit CPU or the digital signal processor (digital signal processor, DSP), can only use scalar instructions for single-point data processing when reversing the order, and cannot use single instruction multi-data (single instruction multi-data, SIMD) instructions for parallel reversal. Therefore, the reversal of the order in the related art is mostly completed by hardware accelerators.

[0021] However, the time it takes to process data reordering with scalar instructions is too long and inefficient. If a hardware accelerator is used to implement data reordering, additional data processing steps are added, and the cost and delay of software-hardware interaction also occur.

[0022] The embodiments of the present application provide a method and device for data processing. Figure 1 A flow chart of a data processing method provided in an embodiment of the present application. Figure 1 Introduce this program.

[0023] In step S110, Fourier transformed input data is acquired.

[0024] The input data of Fourier transform can be understood as data used for Fourier transform, such as FFT or DFT data used for Fourier transform, or IFFT or IDFT data used for inverse Fourier transform.

[0025] The input data may include M data elements, and therefore, the input data may also be referred to as M-point data. The present application does not limit the number of data elements in the input data, and illustratively, the input data may include 8, 16, 32, 64, or 72 data elements.

[0026] The input data is usually a complex number, including an imaginary part and a real part. In some cases, the input data can be a real number, which is a special type of complex number. The overall bit width of the input data can be w-bit. As mentioned above, the input data can include M data elements. If it is data for FFT transformation, then M = 2 m , m is a positive integer. If it is data used for DFT, then M = p1 s1 ×p2 s2 …pk sk Here, we use prime factor representation, where p1, p2…, pk (i=1~k, k in total) are all prime numbers and are different from each other, and s1, s2…, sk (i=1~k, k in total) are the corresponding powers, which are positive integers. It can be seen that FFT is a special case of DFT with only prime factor 2.

[0027] In step S120, a vector processor is used to perform a multi-stage first vector operation on the input data to obtain first intermediate result data, wherein the first vector operation includes a butterfly operation and a reordering operation, and the reordering operation is used to convert the order of the operation result of the butterfly operation into a positive order.

[0028] The vector processor can adopt SIMD architecture to complete vector operations through vector operation instructions SIMD, vector registers, vector processing arrays and vector loading units. The vector register can contain N FFT / DFT data elements, usually N = 2 n In other words, the vector processor can process N data operations at a time, that is, the number of vector processing data in the SIMD instruction of the vector processor is N, which can also be understood as the bandwidth of SIMD is N.

[0029] For input data, a reordering operation is performed after performing a first-level butterfly operation, which is called a first-level vector operation. That is, the first-level vector operation includes a first-level butterfly operation plus a reordering operation. The reordering operation is used to convert the order of the operation result after the first-level butterfly operation into a positive order. The present application does not limit the type of butterfly operation. For example, the butterfly operation can be a radix-2 butterfly. In order to improve the effect of data processing, the butterfly operation can be a radix-4 butterfly, or a radix-8 butterfly, etc.

[0030] Taking 8-point FFT data as an example, the first level vector operation is performed as an example to introduce this step exemplarily. For the positive sequence input data 0, 1, 2, 3, 4, 5, 6, 7, the first level vector operation is performed. First, the input data is processed by a first level butterfly, and the 16-point FFT data is decomposed into two 4-point sub-sequences, namely sub-sequence 0, 1, 2, 3 and sub-sequence 4, 5, 6, 7. The data elements in the two sub-sequences are processed by butterfly operations to obtain the results of the butterfly operation, X0, X2, X4, X6, X1, X3, X5, X7. It can be seen that the positive sequence input data can be separated into odd sub-sequences and even sub-sequences by parity after the first level butterfly operation. Afterwards, the order of the results of the butterfly operation is reordered. The reordering is to rearrange X0, X2, X4, X6, X1, X3, X5, and X7 into positive order. After the reordering, the order of the data is X0, X1, X2, X3, X4, X5, X6, and X7.

[0031] In step S130, the first intermediate result data is divided into a plurality of butterfly operation groups including N data elements, and a vector processor is used to perform one or more levels of second vector operations on the plurality of butterfly operation groups to obtain a second intermediate result.

[0032] The number of data elements in a single instruction multi-data (SIMD) can be understood as the number of data that can be triggered by the single instruction at the same time. It should be understood that the present application does not limit the number of data in a SIMD instruction. Exemplarily, N can be equal to 4, that is, SIMD_N=4, that is, one SIMD can perform 4 complex operations at the same time, and N can also be equal to 8, that is, SIMD_N=8, and one SIMD can perform 8 complex operations at the same time.

[0033] The first intermediate result data is divided into a plurality of butterfly operation groups according to the number of data elements in a single operation instruction. Exemplarily, taking 8-point FFT data as an example, when SIMD_N=4, the positive-order intermediate result after the first vector operation can be divided into 2 butterfly operation groups, where 0, 1, 2, 3 are a butterfly operation group, and 4, 5, 6, 7 are a butterfly operation group. Another example, taking 64-point FFT data as an example, when SIMD_N=4, the first intermediate result in the positive order after the first vector operation can be divided into 64 / 4=16 butterfly operation groups, where 0-3 is a butterfly operation group, 4-7 is a butterfly operation group, and similarly, 60-63 is a butterfly operation group. Taking 72-point FFT data as an example, when SIMD_N=8, the first intermediate result in the positive order after the first vector operation can be divided into 72 / 8=8 butterfly operation groups. It can be seen that the number of data elements in the butterfly operation group meets the width of SIMD, that is, one SIMD instruction can execute the number of data in one butterfly element group. Moreover, the order of multiple butterfly operation groups is positive order and in one butterfly operation group, the data is in positive order and the order is continuous.

[0034] The vector processor uses SIMD instructions to perform one or more stages of butterfly operations on multiple butterfly operation groups. In other words, SIMD instructions can be used to perform butterfly operations on all data elements in one butterfly operation group.

[0035] For example, Figure 2Taking the 64-point FFT data shown in the figure, SIMD_N=4, and radix 2 butterfly operation as an example, the 64-point data can be divided into 16 butterfly operation groups, and the order of the 16 butterfly operation groups is positive and continuous. When performing butterfly operation on multiple butterfly operation groups in stage3, the input order of the 16 operation groups can be x0-x3 operation group, x4-x7 operation group, x8-x11 operation group, x12-x15 operation group...x60-x63 operation group. After one level of butterfly operation, the operation result data can be separated into odd part and even part by parity. The even part includes the results of butterfly operations of 8 operation groups, which are x4-x7 operation group, x12-x15 operation group, x20-x23 operation group, x28-x31 operation group, x36-x39 operation group, x44-x47 operation group, x52-x55 operation group, and x60-x63 operation group. The odd part includes the results of butterfly operations of 8 operation groups, which are x0-x3 operation group, x8-x11 operation group, x16-x19 operation group, x24-x27 operation group, x32-x35 operation group, x40-x43 operation group, x48-x51 operation group, and x56-x59 operation group. In stage 4, the result data of the above-mentioned first-level butterfly operation is subjected to another butterfly operation, and the operation result data is further separated into 4 data blocks by odd and even, and each data block contains 4 butterfly operation groups. Specifically, after the operation, the even part of the previous level is separated into odd data blocks, including: x0-x3 operation group, x16-x19 operation group, x32-x35 operation group, x48-x51 operation group, and even data blocks, including: x8-x11 operation group, x24-x27 operation group, x40-x43 operation group, x56-x59 operation group. After the operation, the odd part of the previous level can be separated into odd data blocks, including: x4-x7 operation group, x20-x23 operation group, x36-x39 operation group, x52-x55 operation group, and even data blocks, including: x12-x15 operation group, x28-x31 operation group, x44-x47 operation group, x60-x63 operation group. In stage 5, the result data of the previous butterfly operation is subjected to another butterfly operation, and the operation result is further separated into 8 data blocks by odd and even numbers, each of which includes 2 butterfly operation groups.Specifically, the x0-x3 operation group and the x32-x35 operation group are odd data blocks, the x16-x19 operation group and the x48-x51 operation group are even data blocks, the x8-x11 operation group and the x40-x43 operation group are odd data blocks, the x24-x27 operation group and the x56-x59 operation group are even data blocks, the x4-x7 operation group and the x36-x39 operation group are odd data blocks, the x20-x23 operation group and the x52-x55 operation group are even data blocks, the x12-x15 operation group and the x44-x47 operation group are odd data blocks, and the x28-x31 operation group and the x60-x63 operation group are even data blocks. In stage 6, the result of the previous butterfly operation is subjected to another butterfly operation, and the operation result is further separated into 16 data blocks by odd and even. For example, the x0-x3 operation group and the x32-x35 operation group are separated into the x0-x3 operation group and the x32-x35 operation group for odd data blocks, and the x28-x31 operation group and the x60-x63 operation group are separated into the x28-x31 operation group and the x60-x63 operation group. It can be seen that after the multi-level second vector operation, the reverse Fourier transform result can be obtained.

[0036] In step S140, a third vector operation is performed on the second intermediate result using a vector processor to obtain a Fourier transform result, wherein the third vector operation is a vector-level reverse carry operation.

[0037] In the previous step, the reversed Fourier transform result data is obtained, wherein the result data includes multiple data operation groups, and the number of data elements of the data operation groups is consistent with the width of the SIMD. In order to achieve the positive order input and positive order output of data, a vector-level reverse carry operation can be performed to reverse the data to obtain the positive order data of the Fourier transform result. In other words, the third vector operation can be a vector-level reverse carry operation to reverse the reversed Fourier transform result data to the positive order.

[0038] The vector-level reverse carry operation can be understood as performing a reverse carry operation on the order of a group of data in the operation group. Figure 2Take as an example for an exemplary introduction. After the first vector operation of stage1 and stage2, the order of the data is positive order. In stage3, butterfly operation is performed in operation groups. The data in the operation group is positive order and continuous. After the butterfly operation of stage3, the data is separated by parity. The order of odd data groups can be 0_00, and the order of even data groups can be 1_00. After the butterfly operation of stage4, the data is separated by parity, and the order of data groups is 00_00, 10_00, 01_00, 11_00. After the butterfly operation of stage5, the data is separated by parity, and the order of data groups is 000_00, 100_00, 010_00, 110_00, 001_00, 101_00, 011_00 and 111_00. After the stage6 butterfly operation, the data is separated into 16 data groups by parity. The order of the data groups is 0000_00, 1000_00, 0100_00, 1100_00, 0010_00, 1010_00, 0110_00, 1110_00, 0001_00, 1001_00, 0101_00, 1101_00, 0011_00, 1011_00, 0111_00 and 1111_00. The vector and reverse carry operations are performed on these 16 data groups. For example, the reverse carry of 0000_00 is 0000_00, the reverse carry of 1000_00 is 0001_00, the reverse carry of 0100_00 is 0010_00, and so on, the reverse carry of 1111_00 is 111_00. After the vector and reverse carry operations, the data sequence of the operation group is positive sequence, because the data in the operation group is positive sequence and continuous, therefore, positive sequence and continuous output data can be obtained.

[0039] In some embodiments, a special vector-level reverse carry save instruction SV.REV can be used to find the corresponding positive-order output position for each vector. For example, the save position of each number can be pre-calculated according to the number of data elements in the vector-level operation group, so that the offset address of the data is hard-coded in the SV.REV instruction to achieve on-demand calling.

[0040] It can be seen that the method for processing data provided in the embodiment of the present application first makes the data after butterfly operation in positive order through butterfly weighted reverse operation, and the degree of data mixing is the width of SIMD, and then performs vector-level butterfly operation on the operation group as a unit, and after the butterfly operation, performs vector-level reverse operation on the operation group, and uses the vector processor to realize the positive order input and output of data, thereby improving the efficiency of data processing and saving the cost and overhead of software and hardware switching.

[0041] As mentioned above, data needs to go through the first level vector operation and the second level vector operation. The number of levels of different level vector operations can be determined according to the number of points in the data and the width of SIMD. Taking FFT data as an example, M = 2 n+r =N×2 r , where N = 2^n is the number of vector processing data. Taking 8-point FFT data and SIMD = 4 as an example, 8 = 4 × 2 1 , that is, r = 1, that is, one second vector operation is performed on the input data. Taking 64-point data and SIMD = 4 as an example, 64 = 4×2 4 , that is, r=4, that is, 4 second vector operations and 2 first vector operations are performed on the data.

[0042] The reordering operation during the first vector operation can be performed in a data mixing and interleaving manner. The data mixing and interleaving is introduced below.

[0043] Reordering is to reverse the order of the data elements separated by odd and even numbers after the butterfly operation in the first vector operation, and return the data elements to the normal order. The reordering operation can be represented by the instruction MIXR.x, where MIX represents the mixing action, R is the number of vectors to be mixed, and R is the basis of the butterfly processing. Taking the base 2 butterfly as an example, R=2, and taking the base 4 butterfly as an example, R=4. x is the granularity of the current mixing, that is, the number of data elements used for interleaving. Taking the base 2 butterfly as an example, For example, 64-point FFT data performs two first vector operations. In the first first vector operation, after the first butterfly operation, when the order is re-permuted, the mixing granularity x=1. In the second vector operation, after the second butterfly operation, when the order is re-permuted, the mixing granularity x=2. MIXR.x can be understood as taking x data elements from the R input quantities respectively, and putting them at the corresponding output element positions after interleaving. Figure 3 and Figure 4 An exemplary introduction to data re-ordering is given.

[0044] Figure 3 include Figure 3 .1 and Figure 3 .2 Two parts, Figure 3 .1 shows MIX2.1, Figure 3 .2 shows MIX2.2. The following will introduce these two parts separately. Figure 3.1 is to interleave 1 element of 2 input vectors. The 2 input vectors are Vi1[b7,b6,b5,b4,b2,b1,b0] and Vi0[a7,a6,a5,a4,a3,a2,a1,a0]. Take the interleaving corresponding to 1 data element in these two input vectors and put the interleaved data back accordingly to get the 2 interleaved vectors Vo1[b7,a7,b6,a6,b5,a5,b4,a4] and vector Vo0[b3,a3,b2,a2,b1,a1,b0,a0]. Figure 3 .2 is to interleave 2 elements of 2 input vectors. The 2 input vectors are Vi1[b7,b6,b5,b4,b2,b1,b0] and Vi0[a7,a6,a5,a4,a3,a2,a1,a0]. Take 2 data elements from these two input numbers and interleave them accordingly. Put the interleaved data back accordingly, and you can get 2 interleaved vectors Vo1[b7,b6,a7,a6,b5,b4,a5,a4] and vector Vo0[b3,b2,a3,a2,b1,b0,a1,a0]. Taking 16-point FFT data as an example, the first input vector can be the result data of the butterfly operation in the first first vector operation. The result data can be, for example, Vi1[1,3,5,7,9,11,13,15] and Vi0[2,4,6,8,10,12,14,16]. By performing MIX2.1 and taking one data element from the two input vectors for mixed interleaving, the interleaved output vector Vo1[1,2,3,4,5,6,7,8] and the output vector Vo0[9,10,11,12,13,14,15,16] can be obtained. The second input vector can be the result data after the butterfly operation in the second first vector operation. The result data can be, for example, Vi1[1,2,5,6,9,10,13,14] and Vi0[3,4,7,8,11,12,15,16]. By performing MIX2.2 and taking two data elements from these two vectors for mixed interleaving, the interleaved output vectors Vo1[1,2,3,4,5,6,7,8] and Vo0[9,10,11,12,13,14,15,16] can be obtained.

[0045] Figure 4 include Figure 4 .1 and Figure 4 .2 Two parts, Figure 4 .1 shows MIX4.1, Figure 4 .2 shows MIX4.2. Figure 4 It interleaves 4 input vectors (vi3~vi0) and outputs 4 vectors (vo3~vo0), where MIX4.1 interleaves 1 data element and MIX4.2 interleaves 2 data elements. Figure 4 .1 is an example of an introduction. The input vectors can be [d7, d6, d5, d4, d3, d2, d1, d0], [c7, c6, c5, c4, c3, c2, c1, c1], [b7, b6, b5, b4, b3, b2, b1, b0] and [a7, a6, a5, a4, a3, a2, a1, a0], and one data element from these four vectors is mixed and interleaved to obtain the interleaved output vectors [d7, c7, b7, a7, d6, c6, b6, a6], [d5, c5, b5, a5, d4, c4, b4, a4], [d3, c3, b3, a3, d2, c2, d2, a2] and [d1, c1, b1, a1d0, c0, b0, a0].

[0046] It can be seen that the reordering operation can reverse the data that has been reversed after the butterfly operation to the positive order. The number of elements in the input vector can be consistent with the width of SIMD, so that the reordering can be completed using vector-level SIMD instructions. Taking 16-point FFT data as an example, SIMD_N=4, the input vector can be Vi1[1,3,5,7] and Vi0[2,4,6,8], and the output vector after MIX2.1 can be Vo1[1,2,3,4,] and Vo0[5,6,7,8], the input vector can be Vi1[9,11,13,15] and Vi0[10,12,14,16], and the output vector after MIX2.1 can be Vo1[9,10,11,12] and Vo0[13,14,15,16]. In other words, the input vector consistent with the SIMD width can be taken according to the SIMD width to perform vector-level reordering operations to improve the efficiency of data processing.

[0047] DFT data, M = 2 n+r p1 s1 ×p2 s2 …pk sk , that is, the number of points M is N = 2 n Multiples of, N is the width of SIMD. Taking the radix-2 butterfly operation as an example, the data processing steps include: performing n radix-2 butterfly operations, reordering after each butterfly is completed, that is, returning the odd-even separation to the natural positive order; performing r radix-2 butterfly, s2 radix-p2 butterfly, ..., sk radix-pk butterfly in order, without reordering; combining data pk according to different advanced levels sk ×pk―1 sk―1 ……p2 s2 The left side is the highest bit, corresponding to the rightmost processing butterfly basis, and the right side is the lowest bit, corresponding to the left side, without reordering; the output of the last step, each N-point vector is stored, according to pk sk ×pk―1 sk―1 ……p2s2 ×2 r Calculate the offset address of the next vector in reverse order until all are completed. If the number of elements N contained in the vector is not M = p1 s1 ×p2 s2 …pk sk If the factor is smaller than N, a factor q is selected from M, so that q is closest to N when it is smaller than N, that is, the vector of N elements is used as q elements. Next, the butterfly of factor q is first formed and the positive order is re-formed. After the positive order of q is formed, the subsequent steps are completed in sequence according to the normal DFT. Finally, the vector (q elements) level multi-order combination data is reversed to complete the entire DFT / FFT process.

[0048] Combine the following Figure 5 The method for processing data provided in the embodiments of the present application is introduced by way of example. Figure 5 Shown is the processing of 72-point DFT data.

[0049] SIMD_N=4, that is, the width of SIMD is 4, and one SIMD instruction can process 4 data at the same time. First, two levels of first vector operations are performed, that is, a butterfly operation is performed first and then a reordering operation is performed to reverse the data to the positive order, and a butterfly operation is performed after the butterfly operation to reverse the data to the positive order. That is, in stage 1 in the figure, butterfly operation plus MIX2.1 is performed, and stage 2 is performed. Butterfly operation plus MIX2.1, after two levels of butterfly operation, the positive order of the loss is completed. After that, the operation result data of the previous level is divided into data blocks consistent with the SIMD width, and butterfly operation is performed. For example, in stage 3, 18 operation groups are butterfly operated to obtain data operation groups with parity separation. In stage 4, butterfly operation is performed on 18 butterfly operation groups to obtain 6 data blocks with parity separation, one of which includes 3 operation groups. In stage 5, butterfly operation is performed to obtain the reverse Fourier transform result. Finally, the vector level reverse carry instruction SV.REV is used to reverse the vector to positive sequence and obtain the Fourier transform result of the positive sequence output. In stage3, the order of the parity separation operation group is 0_00 for odd data blocks and 1_00 for even data blocks. After stage4 operation, the order of the parity separation data blocks is 00_00, 10_00, 20_00, 01_00, 11_00 and 21_00. After stage5 operation, the order of the parity separation data blocks is 000_00, 100_00, 200_00, 010_00, 110_00, 210_00, 020_00, 120_00, 220_00, 001_00, 101_00, 201_00, 011_00, 111_00, 211_00, 021_00, 121_00 and 221_00. The vector and SV.REV instructions are used to perform vector and reverse carry operations on the above data groups to obtain positive sequence operation groups. Since the data in each operation group is continuous and positive sequence, the positive sequence Fourier transform result can be obtained. Figure 5 The data shown can be represented in a mixed system, that is, the SV.REV instruction performs a reverse carry operation in binary or mixed system.

[0050] When processing data, when the butterfly size effect is equal to the vector size of the SIMD of the processor, the problem of appropriate butterfly processing will occur. For the example row, when SIMD_N=4, the third-level butterfly processing is the butterfly processing between 2 vectors, and SIMD vector processing instructions cannot be used, that is, the problem of butterfly processing within the vector appears from the third level. Intra-vector butterfly processing is completely different from inter-vector butterfly processing, because vector quality, that is, SIMD instructions, are defined for inter-vector operations. The larger the SIMD, the greater the throughput of data processed in a single time, but it also enters the intra-vector operation earlier. For intra-vector operations, the instructions within the vector are relatively special, costly and not universal. The intra-vector instructions are currently only SIMD=4, including base 2 butterfly or base 4 butterfly, which are used for the first 2 levels of reverse order or the last 2 levels of reverse order. The method for processing data provided in the embodiment of the present application also solves the above problems. Take positive order input, number of points M=1024, SIMD_N=4, and base 2 butterfly as an example. This application avoids scalar level reordering and defines a special and uncommon amount of internal instructions at the cost of 2-level vector reordering (MIX2.1+MIX2.2), which can achieve greater benefits when the number of points M is large. However, when SIMD_N is large, more stages need to be MIXed, and the benefits will be relatively reduced.

[0051] It can be seen that the present application, by adding some MIX instructions for exchanging elements between vectors, and the vector-level reverse storage SV.REV instruction, can avoid performing scalar-level reverse operations, thereby allowing the processor to complete the complete vector operation of FFT positive-sequence input and positive-sequence output; it also avoids performing intra-vector operations, and there is no need to define complex and non-universal intra-vector operation instructions.

[0052] Combination of the above Figures 1 to 5 , describes in detail the method embodiment of the present disclosure, and the following is combined with Figure 6 The device embodiment of the present disclosure is described in detail. It should be understood that the description of the method embodiment corresponds to the description of the device embodiment, so the parts not described in detail can refer to the previous method embodiment.

[0053] Figure 6 The data processing device 600 may include an acquisition unit 610, a first execution unit 620, a second execution unit 630 and a third execution unit 640. Each unit is exemplarily introduced below.

[0054] An acquisition unit 610 is configured to acquire Fourier transformed input data;

[0055] A first execution unit 620 is configured to use a vector processor to perform a multi-stage first vector operation on the input data to obtain first intermediate result data, wherein the first vector operation includes a butterfly operation and a reordering operation, and the reordering operation is used to convert the order of the operation result of the butterfly operation into a positive order;

[0056] The second execution unit 630 is configured to divide the first intermediate result data into a plurality of butterfly operation groups including N data elements, where N is the number of vector processing data in the SIMD instruction of the vector processor, and use the vector processor to perform one or more levels of second vector operations on the plurality of butterfly operation groups to obtain a second intermediate result, wherein the second vector operation is a butterfly operation;

[0057] The third execution unit 640 is configured to use a vector processor to perform a third vector operation on the second intermediate result to obtain the result of the Fourier transform, wherein the third vector operation is a vector-level reverse carry operation.

[0058] Optionally, the first execution unit 620 is further configured to:

[0059] Performing a butterfly operation on the input data to obtain a butterfly operation result;

[0060] For the butterfly operation result, data element mixing and interleaving is performed to convert the order of the operation result of the butterfly operation into a positive order.

[0061] Optionally, the input data includes M elements, the multi-level first vector operation is n-level, the one or more-level second vector operations are r-level, and M=2 n+r .

[0062] Optionally, the number of data elements targeted by the last-stage vector operation in the multi-stage first vector operations is greater than or equal to N.

[0063] Optionally, the butterfly operation is a radix-2 butterfly operation.

[0064] It should be understood that in the embodiments of the present disclosure, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0065] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0066] It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0067] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0068] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0069] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0070] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present disclosure is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that can be read by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0071] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for processing data, characterized in that: include: Get the input data for Fourier transform; For the input data, a vector processor is used to perform a multi-stage first vector operation to obtain first intermediate result data, wherein the first vector operation includes a butterfly operation and a reordering operation, and the reordering operation is used to convert the order of the operation result of the butterfly operation into a positive order; Dividing the first intermediate result data into a plurality of butterfly operation groups including N data elements, where N is the number of vector processing data in the SIMD instruction of the vector processor, and using the vector processor to perform one or more levels of second vector operations on the plurality of butterfly operation groups to obtain a second intermediate result, wherein the second vector operation is a butterfly operation; For the second intermediate result, the vector processor is used to perform a third vector operation to obtain the Fourier transform result, wherein the third vector operation is a vector-level reverse carry operation.

2. The method according to claim 1, characterized in that The step of performing a multi-stage first vector operation on the input data using the vector processor to obtain first intermediate result data includes: Performing a butterfly operation on the input data to obtain a butterfly operation result; For the butterfly operation result, data element mixing and interleaving is performed to convert the order of the operation result of the butterfly operation into a positive order.

3. The method according to claim 1, wherein the input data comprises M elements, the multi-stage first vector operation is n-stage, the one or more-stage second vector operation is r-stage, and .

4. The method according to claim 1, characterized in that: The number of data elements targeted by the last-stage vector operation in the multi-stage first vector operations is greater than or equal to N.

5. The method according to claim 1, characterized in that The butterfly operation is a radix-2 butterfly operation.

6. A device for processing data, characterized in that: include: An acquisition unit configured to acquire Fourier transformed input data; A first execution unit is configured to use a vector processor to perform a multi-stage first vector operation on the input data to obtain first intermediate result data, wherein the first vector operation includes a butterfly operation and a reordering operation, and the reordering operation is used to convert the order of the operation result of the butterfly operation into a positive order; a second execution unit configured to divide the first intermediate result data into a plurality of butterfly operation groups including N data elements, where N is the number of vector processing data in the SIMD instruction of the vector processor, and use the vector processor to perform one or more levels of second vector operations on the plurality of butterfly operation groups to obtain a second intermediate result, wherein the second vector operation is a butterfly operation; The third execution unit is configured to use the vector processor to perform a third vector operation on the second intermediate result to obtain the result of the Fourier transform, wherein the third vector operation is a vector-level reverse carry operation.

7. The device according to claim 6, characterized in that The first execution unit is further configured to: Performing a butterfly operation on the input data to obtain a butterfly operation result; For the butterfly operation result, data element mixing and interleaving is performed to convert the order of the operation result of the butterfly operation into a positive order.

8. The device according to claim 6, characterized in that The input data includes M elements, the multi-stage first vector operation is n-stage, the one or more-stage second vector operation is r-stage, and .

9. The device according to claim 6, characterized in that The number of data elements targeted by the last-stage vector operation in the multi-stage first vector operations is greater than or equal to N.

10. The device according to claim 6, characterized in that The butterfly operation is a radix-2 butterfly operation.

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