A general-purpose microprocessor and a signal processing method thereof

Abstract

A signal processing method of a general microprocessor, comprising the following steps: S1: the processor processes instructions in a way of out-of-order execution and branch prediction; S2: the processor performs legality detection on all instructions, and meanwhile, caches data generated by out-of-order execution and branch prediction in a cache disk; S3: the cache disk sends the cached data to a black disk, the black disk isolates the cached data and records a time node A; S4: the processor sends a legal instruction to a scheduling disk, and meanwhile, the scheduling disk records a time node B of the instruction; S5: the scheduling disk sends the time node B of the legal instruction to the black disk, and the black disk searches for a corresponding node A according to the node B to perform AB node matching. The general microprocessor and the signal processing method thereof avoid the phenomenon that the cached data of the current general microprocessor has no protection measures and can be illegally read, and improve the security of the general microprocessor.

Description

Technical Field

[0001] This invention is a divisional application of the invention patent with application number 201910404175.1, which relates to the field of microprocessor manufacturing technology, specifically a general-purpose microprocessor and its signal processing method. Background Technology

[0002] In the operation of a microprocessor, out-of-order execution and branch prediction are commonly used to improve the processor's instruction processing efficiency. Out-of-order execution means that the processor decides to execute instructions in an order determined by the availability of input data, rather than processing them sequentially according to the program's prescribed order. Branch prediction, on the other hand, predicts in advance the instructions that the processor will execute. Although these methods improve the processor's efficiency, they may become a means of exploiting kernel vulnerabilities.

[0003] For new processors with predictive execution capabilities, during actual processor execution, the memory loading stage required for subsequent instructions does not depend on whether the preceding instructions can be executed normally. Moreover, the loading stage from memory to cache does not verify whether the accessed memory is legal and valid. Even if an illegal instruction causes an exception and its subsequent instructions cannot be executed, the memory data required by the subsequent instructions of the illegal instruction has already been loaded into the processor cache. This result means that even if the subsequent instructions load memory data that they do not have permission to access, that memory data will still be loaded into the processor cache. This is because the processor only checks the address validity during the cache-to-register stage, and processor branch prediction only completes the loading of memory into the processor cache. In fact, the subsequent instructions are not actually executed, so its illegal access will not trigger an exception. Therefore, this type of general-purpose microprocessor has a security vulnerability. Summary of the Invention

[0004] To achieve the goal of improving the security of general-purpose microprocessors, the present invention provides the following technical solution:

[0005] A signal processing method for a general-purpose microprocessor includes the following steps:

[0006] S1: The processor processes instructions using out-of-order execution and branch prediction.

[0007] S2: The processor performs a valid check on all instructions, and at the same time, caches the cached data generated by out-of-order execution and branch prediction into the cache disk;

[0008] S3: The cache disk sends cached data to the black disk, which isolates the cached data and records time point A.

[0009] S4: The processor sends the valid instruction to the scheduling disk, and the scheduling disk records the time node B of the instruction.

[0010] S5: The scheduling disk sends the time node B of the valid instruction to the black zone disk. The black zone disk looks up the corresponding node A based on node B and performs A / B node matching.

[0011] S6: After a successful match, the black disk extracts the cached data corresponding to node A and sends it to the register;

[0012] S7: The processor and registers execute legal instructions.

[0013] A general-purpose microprocessor, which mainly consists of a processor, a cache disk, a scheduling disk, a black disk, and registers.

[0014] Preferably, the general-purpose microprocessor mainly consists of a processor, a cache disk, a scheduling disk, a black area disk, and registers.

[0015] Preferably, after receiving instruction data sent by an external device, the processor processes it using out-of-order execution and branch prediction.

[0016] Preferably, the black disk isolates the cached data and generates time node A. The isolated cached data is in an unreadable state, and the black disk is equipped with a firewall and a cleanup program.

[0017] Preferably, the scheduling disk adopts a one-way read-write method, and the scheduling only accepts legal instructions that have passed the legal detection and generates time node B for them.

[0018] Compared with existing technologies and products, the beneficial effects of the present invention are:

[0019] 1. The general-purpose microprocessor and its signal processing method involve a scheduling disk recording the nodes of received legal instructions, and a black disk recording the time nodes of the cached data of the instructions. The scheduling disk sends the time nodes of legal instructions to the cache disk, and the black disk then looks up the corresponding cached data and sends it to the register for the processor to execute the instructions. Meanwhile, the cached data of illegal instructions is always protected in the black disk and cannot be read. This avoids the phenomenon that the cached data of current general-purpose microprocessors has no protection measures and can be illegally read, thus improving the security of the general-purpose microprocessor.

[0020] 2. This general-purpose microprocessor and its signal processing method protect and match cached data by using time nodes. Although the instructions are executed out of order, the instructions received first are still executed first. The matching of time nodes takes less time. Therefore, this protection method does not reduce the processing speed of the general-purpose microprocessor.

[0021] 3. This general-purpose microprocessor and its signal processing method, by setting up a firewall on the black disk, prevent attackers from reading data by directly attacking the black disk, thus further improving the security of cached data. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the signal processing method of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Please see Figure 1 A signal processing method for a general-purpose microprocessor includes the following steps:

[0025] S1: The processor processes instructions using out-of-order execution and branch prediction.

[0026] S2: The processor performs a valid check on all instructions, and at the same time, caches the cached data generated by out-of-order execution and branch prediction into the cache disk;

[0027] S3: The cache disk sends cached data to the black disk, which isolates the cached data and records time point A.

[0028] S4: The processor sends the valid instruction to the scheduling disk, and the scheduling disk records the time node B of the instruction.

[0029] S5: The scheduling disk sends the time node B of the valid instruction to the black zone disk. The black zone disk looks up the corresponding node A based on node B and performs A / B node matching.

[0030] S6: After a successful match, the black disk extracts the cached data corresponding to node A and sends it to the register;

[0031] S7: The processor and registers execute legal instructions.

[0032] The aforementioned general-purpose microprocessor mainly consists of a processor, cache disk, scheduling disk, black disk, and registers.

[0033] Furthermore, after receiving instruction data from an external device, the processor processes it using out-of-order execution and branch prediction.

[0034] Furthermore, the aforementioned black disk isolates the cached data and generates time node A. The isolated cached data is in an unreadable state, and the black disk is equipped with a firewall and a cleanup program.

[0035] Furthermore, the aforementioned scheduling disk adopts a one-way read-write method, whereby the scheduling only accepts valid instructions that have undergone valid checks and generates time node B for them.

[0036] In use, the general-purpose microprocessor of this invention performs garbled execution and branch prediction processing on the received instructions. The cached data of the branch prediction is loaded onto the cache disk, which then sends the cached data to the black disk. The black disk isolates and protects the cached data while recording the time node A of the cached instruction. The isolated cached data is in an unreadable state. A firewall protects the data on the black disk, preventing any instructions that have not undergone legal checks from reading the black disk. When the processor receives an instruction, it checks the legality of the instruction and sends the legal instructions to the scheduling disk. The scheduling disk records the time node B of each instruction. The scheduling disk adopts a one-way read-write method, accepting only legal instructions and sending the time node B of the legal instructions to the black disk. The black disk uses the time node B to find the corresponding time node A. After finding the corresponding time node A, it removes the unreadable state of the cached data corresponding to node A. Then, the black disk extracts the cached data of time node A and sends it to the register. After the processor and register receive the data, they begin to execute the legal instructions. When the scheduling disk detects an invalid instruction, it will not execute any subsequent operations.

[0037] The cache disk, as a storage device to accelerate processor efficiency, is loaded with a large amount of cached data. Because the processor needs to perform legality checks on instructions, the loading efficiency of the cache disk is much higher than the execution efficiency of legal instructions. The high efficiency of the cache disk is not fully utilized. By setting up a black disk area to isolate cached data and generate time node A, the excessively high loading speed of the cache disk is used to transfer cached data to the black disk area without affecting the normal loading of the cache disk. After receiving a legal instruction, the scheduling disk generates time node B and sends node B to the black disk for matching and cache retrieval. Since a legal instruction generates node A in the black disk and node B in the scheduling disk, after the A and B nodes are matched, the legal instruction... Cache data will be retrieved, while illegal instructions, lacking proper authorization, will not have a time node B. Therefore, cached information lacking a corresponding time node B remains in an unreadable protected state, constituting unretrievable cached information and thus will not be retrieved. By configuring cache disk cleanup, cached data that has not been retrieved for a long time is periodically cleared, thereby reducing cache disk memory usage and workload. Because a time node approach is used to protect and match cached data, although instructions are executed out of order, the first received instructions are still executed first, resulting in less time spent on time node matching. Therefore, this protection method does not reduce the processing speed of general-purpose microprocessors.

[0038] Please refer to the above structure and process. Figure 1 .

[0039] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A signal processing method for a general-purpose microprocessor, characterized in that, Includes the following steps: S1: The processor processes instructions using out-of-order execution and branch prediction. S2: The processor performs a valid check on all instructions, and at the same time, caches the cached data generated by out-of-order execution and branch prediction into the cache disk; S3: The cache disk sends cached data to the black disk, which isolates the cached data and records time point A. S4: The processor sends the valid instruction to the scheduling disk, and the scheduling disk records the time node B of the instruction. S5: The scheduling disk sends the time node B of the valid instruction to the black zone disk. The black zone disk looks up the corresponding node A based on node B and performs A / B node matching. S6: After a successful match, the black disk extracts the cached data corresponding to node A and sends it to the register; S7: The processor and registers execute legal instructions.

2. A general-purpose microprocessor, characterized in that: The general-purpose microprocessor includes a processor, a cache disk, a scheduling disk, a black area disk, and registers, wherein: The cache disk is used to cache data generated by out-of-order execution and branch prediction. The scheduling disk is used to receive legitimate instructions after they have been validated, and to record the time point B of the instruction. The black disk is used to receive and isolate cached data sent by the cache disk, record time node A, and match the corresponding time node A according to the time node B sent by the scheduling disk, so as to extract and send the cached data to the register.

3. A general-purpose microprocessor according to claim 2, characterized in that: After receiving instruction data from an external device, the processor processes it using out-of-order execution and branch prediction.

4. A general-purpose microprocessor according to claim 2, characterized in that: The black disk isolates the cached data and generates time node A. The isolated cached data is in an unreadable state. The black disk is equipped with a firewall and a cleanup program.

5. A general-purpose microprocessor according to claim 2, characterized in that: The scheduling disk adopts a one-way read-write method. The scheduling only accepts legal instructions that have passed the legal detection and generates time node B for them.

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