Device module and manufacturing method thereof and inductor and capacitor array

Abstract

The present invention relates to a device module and a manufacturing method thereof and an inductor and capacitor array, wherein the device module comprises a first conductive layer, a second conductive layer, and a first functional layer and a second functional layer arranged between the first conductive layer and the second conductive layer, wherein the first functional layer provides a plurality of capacitors and a plurality of through-hole electrodes isolated from the plurality of capacitors, and a plurality of inductors are formed in the second functional layer, each of the inductors is arranged along the thickness direction of the second functional layer so that the first terminal of the inductor is electrically connected to the first conductive layer through the corresponding through-hole electrode, and the second terminal of the inductor is electrically connected to the second conductive layer. The device module of the present invention greatly simplifies the layout and wiring of a multi-phase circuit by directly installing a driver on a multi-inductor array with pins arranged longitudinally, and improves the effective use of inductor and capacitor materials.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply equipment, and more particularly to a device module and a manufacturing method thereof, and an inductor and capacitor array. Background Art

[0002] The rapid development of computer technology has led mankind into the information society, and has also promoted the rapid development of power module technology. In the 1980s, computers fully adopted switching power supplies, taking the lead in completing the computer power supply upgrade. Then switching power supply technology has successively entered the fields of electronic and electrical equipment.

[0003] The rapid development of the communications industry has greatly promoted the development of communications power supplies. High-frequency, miniaturized switching power supplies and their technologies have become the mainstream of modern communications power supply systems. The application of multi-phase power supply technology is also increasing, and the corresponding modular integration of multi-phase power supplies is also a focus. In the prior art, the main methods for integrating power modules are: putting inductors, capacitors and integrated circuits into a package to make a power module; or using the inductor as a base to install integrated circuits and capacitor components.

[0004] However, due to the limitation of module size, the size of the inductor element in the module is greatly limited when performing modular integration of multi-phase power supply in the integration method in the prior art. Inductance is an important factor affecting the power usage in the power module. The limitation of inductor size will seriously affect the power usage of the power module. At the same time, the existing integration method has the problem of difficult wiring, which increases the complexity of the multi-phase power module and even causes problems such as inefficient utilization of inductor and capacitor materials, affecting the accuracy and cost of the integrated power supply. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a device module and a manufacturing method thereof and an inductor and capacitor array, which simplifies the implementation of a multi-phase power supply, effectively utilizes inductor and capacitor materials, and is conducive to improving the power usage of the power module.

[0006] According to a first aspect of the present invention, a device module is provided, comprising: a first conductive layer, a second conductive layer, and a first functional layer and a second functional layer arranged between the first conductive layer and the second conductive layer, wherein the first functional layer provides a plurality of capacitors and a plurality of through-hole electrodes isolated from the plurality of capacitors; a plurality of inductors are formed in the second functional layer, each of the inductors is arranged along the thickness direction of the second functional layer so that a first terminal of the inductor is electrically connected to the first conductive layer through a corresponding through-hole electrode, and a second terminal of the inductor is electrically connected to the second conductive layer.

[0007] Optionally, the device module further includes: a driving chip placed above the first conductive layer, wherein the driving chip is electrically connected to the plurality of capacitors in the first functional layer and the plurality of inductors in the second functional layer through the first conductive layer.

[0008] Optionally, the driving chip includes a multi-phase switching power supply chip.

[0009] Optionally, the first functional layer includes: an upper electrode plate arranged below the first conductive layer; a lower electrode plate arranged above the second functional layer; and a capacitor dielectric layer arranged between the upper electrode plate and the lower electrode plate, wherein the first electrode plate of each capacitor is formed in the upper electrode plate, the second electrode plate of each capacitor is formed in the lower electrode plate, and each through-hole electrode passes through the upper electrode plate, the capacitor dielectric layer and the lower electrode plate.

[0010] Optionally, the device module further includes: a plurality of pins arranged above the first conductive layer, the plurality of pins being respectively located on both sides of the driving chip; and a packaging layer, the packaging layer covering the driving chip and an exposed portion of the first conductive layer.

[0011] According to a second aspect of the present invention, an inductor and capacitor array is provided, comprising: a first conductive layer, a second conductive layer, and a stacked structure arranged between the first conductive layer and the second conductive layer, the stacked structure comprising an inductor layer and a capacitor layer, wherein the capacitor layer provides a plurality of capacitors and a plurality of through-hole electrodes isolated from the plurality of capacitors; a plurality of inductors are formed in the inductor layer, each of the inductors is arranged along the thickness direction of the inductor layer so that a first terminal of the inductor is electrically connected to the first conductive layer through a corresponding through-hole electrode, and a second terminal of the inductor is electrically connected to the second conductive layer.

[0012] Optionally, the capacitor layer includes: an upper plate arranged below the first conductive layer; a lower plate arranged above the inductive layer; and a capacitor dielectric layer arranged between the upper plate and the lower plate, wherein the first plate of each capacitor is formed in the upper plate, the second plate of each capacitor is formed in the lower plate, and each through-hole electrode passes through the upper plate, the capacitor dielectric layer and the lower plate.

[0013] Optionally, the inductor layer includes: a core body; and a plurality of coils located in the core body, each coil is wound around an axis along the thickness direction of the core body, and two ends of the coil are respectively led out from opposite end surfaces in the thickness direction of the core body.

[0014] Optionally, the core body is formed by sealing the plurality of coils with a sealing material through a resin molding method or an integral die-casting method.

[0015] Optionally, the inductor and capacitor array further includes a plurality of first scribe lanes extending along a first direction and a plurality of second scribe lanes extending along a second direction, wherein the first scribe lanes and the second scribe lanes intersect each other to divide the stacked structure into a plurality of sub-regions, each sub-region including a plurality of inductor and capacitor combinations.

[0016] Optionally, the inductor and capacitor array further includes a plurality of driving chips, which are respectively placed in the plurality of sub-areas, and the plurality of inductor and capacitor combinations in each sub-area are electrically connected to the associated driving chip through the first conductive layer.

[0017] Optionally, the inductor and capacitor array further includes at least one pin disposed on the first scribing street or the second scribing street, and the at least one pin is used to be electrically connected to the first conductive layer.

[0018] Optionally, adjacent sub-areas share at least one pin.

[0019] Optionally, the inductor and capacitor array may be divided into a plurality of device modules according to a first scribing lane and a second scribing lane between adjacent sub-regions.

[0020] According to a third aspect of the present invention, there is provided a method for manufacturing a device module, comprising: forming a stacked structure, the stacked structure comprising a stacked inductor layer and a capacitor layer; forming a first conductive layer on a first surface of the stacked structure; forming a second conductive layer on a second surface of the stacked structure opposite to the first surface; dividing the stacked structure into a plurality of sub-regions by means of a first scribing path and a second scribing path, each sub-region comprising a plurality of inductor and capacitor combinations; and separating adjacent sub-regions to obtain a plurality of device modules.

[0021] Optionally, the step of forming the stacked structure includes: providing a capacitor dielectric layer, the capacitor dielectric layer including a third surface and a fourth surface opposite to each other; forming a plurality of through holes on the capacitor dielectric layer; forming an upper electrode plate and a lower electrode plate on the third surface and the fourth surface of the capacitor dielectric layer, respectively, the plurality of through holes passing through the upper electrode plate, the capacitor dielectric layer and the lower electrode plate; providing the inductor layer, and bonding the inductor layer to the lower electrode plate, a plurality of inductors being formed in the inductor layer, each of the inductors being arranged along the thickness direction of the inductor layer; and making a conductive material above the upper electrode plate, the conductive material filling the plurality of through holes to form a plurality of through-hole electrodes, the through-hole electrodes being used to realize electrical connection between the first conductive layer and the first terminals of the plurality of inductors.

[0022] Optionally, after forming a second conductive layer on a second surface of the stacked structure opposite to the first surface, the method further includes: placing a plurality of driver chips above the first conductive layer, the plurality of driver chips being respectively placed in the plurality of sub-areas, and the plurality of inductor-capacitor combinations in each sub-area being electrically connected to the associated driver chip through the first conductive layer.

[0023] Optionally, after placing multiple driver chips above the first conductive layer, the method further includes: setting at least one pin on the first scribe line or the second scribe line, the at least one pin being used to be electrically connected to the first conductive layer, and at least one pin being shared between adjacent sub-areas; and forming a packaging layer, the packaging layer covering the multiple driver chips and the exposed portions of the first conductive layer.

[0024] The beneficial effects of the present invention are as follows: the present invention utilizes an integrated process to manufacture a multi-inductor array with longitudinally arranged pins, and then uses the multi-inductor array as a substrate to stack a capacitor layer and a driver chip thereon, thereby increasing the proportion of inductance of the multi-phase power module, which is beneficial to increasing the power usage of the power module. In addition, the solution of directly installing the driver on the multi-inductor array with longitudinally arranged pins greatly simplifies the layout and wiring of the multi-phase circuit, and improves the effective utilization of inductor and capacitor materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0026] Figure 1 shows the circuit schematic of the multiphase power module;

[0027] Figure 2 shows a schematic diagram of the overall structure of the device module in the first embodiment of the present invention;

[0028] Figure 3a to Figure 3h Schematic cross-sectional views of various stages of a method for manufacturing a device module according to a second embodiment of the present invention are respectively shown;

[0029] Figure 4 Show Figure 3c Schematic diagram of the plan view of the inductor and capacitor array obtained in . DETAILED DESCRIPTION

[0030] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0031] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0032] If the purpose is to describe the situation of being directly on another layer or another area, this article will use the expression "directly on..." or "on... and adjacent to...".

[0033] Figure 1 shows the circuit schematic of the multiphase power module;

[0034] The present invention mainly relates to the integrated packaging of a multi-phase power supply module. The multi-phase power supply is to combine multiple single-phase power supply circuits together, and distinguish the working time of each phase on the basis of parallel connection to form a multi-phase power supply module. Among them, the multiple output paths of the multi-phase power supply are turned on in turn in a certain time sequence.

[0035] like Figure 1 As shown: Taking 4 phases as an example, the multi-phase power supply module includes: capacitors, inductors, driver chips and loads. Among them, the capacitors C1~C2 are filter capacitors for filtering the input Vin signal of the driver chip; the inductors L1~L4 are used as energy conversion devices on each output channel of the multi-phase power supply; the capacitors C11~C12 are filter capacitors for filtering the output Vout signal; the driver chip is used to control the conduction time and sequence of each output channel of the multi-phase power supply module to the load.

[0036] Preferably, on the driving chip, IN1 to IN4 are four signal input terminals of the driving chip, and S1 to S4 are four signal output terminals of the driving chip.

[0037] Preferably, when the multi-phase power module is packaged, if the overall material remains unchanged, the resistance of each channel increases by 4 times and the current is shared by 1 / 4. Since the resistive loss is proportional to the square of the current and proportional to the resistance, the resistive loss of each phase of the 4-phase architecture is reduced to 1 / 4 of that of the single phase, reducing the peak current of a single inductor and making it feasible. When the 4 phases are evenly staggered, the ripple frequency increases by 4 times, reducing the filtering pressure.

[0038] At the same time, since the inductance is in a square relationship with the winding length, if no magnetic material is added, the inductance is reduced to 1 / 16 of a single inductor. In order to reduce ripple, the multi-phase architecture requires more magnetic materials and the switching frequency is increased as much as possible to ensure performance improvement. For example, the amount of magnetic material must be increased by 4 times to keep the original inductance of each branch inductor. From a mechanistic point of view, multi-phase circuits use more magnetic materials and occupy a larger wiring layout area at the expense of more area.

[0039] Figure 2 A schematic structural diagram of a device module in a first embodiment of the present invention is shown.

[0040] like Figure 2 As shown, the power module provided in the embodiment of the present invention includes: a driving chip 1, a first conductive layer 2, a first functional layer 3, a second functional layer 4, a second conductive layer 5 and at least one pin 6. The first functional layer 3 and the second functional layer 4 are arranged between the first conductive layer 2 and the second conductive layer 5, the first functional layer 3 provides a plurality of capacitors and a plurality of through-hole electrodes (not shown in the figure) isolated from the plurality of capacitors, and the second functional layer 4 is formed with a plurality of inductors, each of which is arranged along the thickness direction of the second functional layer 4 so that the first terminal of the inductor is electrically connected to the first conductive layer 2 through the corresponding through-hole electrode, and the second terminal of the inductor is electrically connected to the second conductive layer 5.

[0041] The driver chip 1 is disposed above the first conductive layer 2, and the driver chip 1 is electrically connected to a plurality of capacitors in the first functional layer 3 and a plurality of inductors in the second functional layer 4 through the first conductive layer. The driver chip is, for example, a multi-phase switching power supply chip, and the device module is, for example, a multi-phase power supply module.

[0042] At least one pin 6 is disposed above the first conductive layer 2 and located on both sides of the driver chip. Further, the device module further includes a packaging layer (not shown in the figure), which covers the exposed parts of the driver chip 1 and the first conductive layer 2. At least one pin 6 is used to provide electrical connection between the driver chip 1 and the first functional layer 3 and the second functional layer 4 and the outside.

[0043] Preferably, the first functional layer 3 includes an upper plate 31, a capacitor dielectric layer 32 and a lower plate 33. The upper plate 31 is arranged below the first conductive layer 2, the lower plate 33 is arranged above the second functional layer 4, the capacitor dielectric layer 32 is arranged between the upper plate 31 and the lower plate 33, the first plate of each capacitor is formed in the upper plate, the second plate of each capacitor is formed in the lower plate, and each through-hole electrode penetrates the upper plate 31, the capacitor dielectric layer 32 and the lower plate 33. Preferably, the upper plate 31 and the lower plate 32 can be formed by coating a thick low-capacitance dielectric on the capacitor dielectric layer 32, but the present invention is not limited thereto.

[0044] Preferably, the second functional layer 4 includes a plurality of coils 41 and a core 42, wherein the plurality of coils 41 are located in the core 42, and each of the coils 41 is wound along the thickness direction of the core 42, and the two ends of the coils 41 are respectively led out from opposite end surfaces in the thickness direction of the core 42.

[0045] Preferably, the plurality of coils 41 may be wound with enameled wires or metal wires, and the coils may be spiral coils, which may be circular spirals, polygonal spirals or zigzag lines.

[0046] Preferably, the core 42 is formed by sealing the plurality of coils 41 with a sealing material by resin molding or integral die casting. In this embodiment, as the sealing material, a sealing material obtained by mixing and granulating iron-based metal magnetic powder and / or epoxy resin into a powder form is used. The plurality of coils 41 are placed in a die-casting groove, with both ends of the coils extending out of the die-casting groove, and then the sealing material is added to the die-casting groove for die-casting to obtain the second functional layer 4.

[0047] It should be noted that the method for forming the second functional layer 4 of this embodiment is not limited to the above embodiment, and those skilled in the art may select other manufacturing methods according to specific circumstances.

[0048] Figure 3a to Figure 3h The schematic cross-sectional views of each step of a method for manufacturing a device module according to the second embodiment of the present invention are respectively shown.

[0049] like Figure 3a As shown, a capacitor dielectric layer 101 is provided, and an etching process is first used to form electrodes and multiple through holes 111 on the capacitor dielectric layer 101, and multiple through holes 111 penetrate the capacitor dielectric layer 101, and then an upper plate 102 and a lower plate 103 are formed on the upper and lower surfaces of the capacitor dielectric layer 101, respectively. For example, a resist layer can be formed on the surface of the capacitor dielectric layer 101, and a pattern including an opening is formed in the resist layer using a photolithography process. With the resist layer as a mask, a selective etchant is used to remove the exposed portion of the capacitor dielectric layer 101, thereby forming an electrode image and through holes 111 on the surface of the capacitor dielectric layer 101. For example, a thick low-capacitance dielectric material can be coated on the upper and lower surfaces of the capacitor dielectric layer 101 to obtain the upper plate 102 and the lower plate 103. The upper plate 102, the lower plate 103 and the capacitor dielectric layer 101 between the upper plate 102 and the lower plate 103 constitute the entire capacitor layer 104, the first plate of each capacitor is formed in the upper plate 102, the second plate of each capacitor is formed in the lower plate 103, and multiple through holes 111 penetrate the upper plate 102, the capacitor dielectric layer 101 and the lower plate 103 to isolate the multiple capacitors from each other.

[0050] like Figure 3bAs shown, an inductor layer 105 is provided, and the lower plate 103 of the capacitor layer 104 is bonded to the inductor layer 105, and a conductive material is made above the upper plate 102, and the conductive material fills the multiple through holes 111 to form multiple through-hole electrodes. The inductor layer 105 includes multiple inductors, each of which is arranged along the thickness direction of the inductor layer 105 so that the first terminal of the inductor is electrically connected to the corresponding through-hole electrode. For example, the inductor layer 105 can be formed by a resin molding method or an integral die-casting method, and the conductive material can be formed above the upper plate 102 by an evaporation or deposition process.

[0051] like Figure 3c As shown, a first conductive layer 106 and a second conductive layer 107 are formed on the upper and lower surfaces of the laminated structure composed of the capacitor layer 104 and the inductor layer 105, respectively, to form an inductor and capacitor array. For example, a conductive material is formed on the upper and lower surfaces of the laminated structure by evaporation or deposition process, and then patterned by photolithography and etching process to etch out the electrode shape, thereby forming the first conductive layer 106 and the second conductive layer 107. The first terminals of the multiple inductors in the inductor layer 105 are electrically connected to the first conductive layer 106 through the through-hole electrode, and the second terminals of the multiple inductors are electrically connected to the second conductive layer 107.

[0052] Preferably, if Figure 4 As shown, the stacked structure is reserved with a plurality of first scribing lanes 161 extending along a first direction and a plurality of second scribing lanes 162 extending along a second direction, the first scribing lanes 161 and the second scribing lanes 162 intersect each other to divide the stacked structure into a plurality of sub-regions 163, each of the sub-regions 163 including a plurality of inductor and capacitor combinations 164. The first scribing lanes 161 and the second scribing lanes 162 are reserved scribing slots for dividing the plurality of sub-regions 163.

[0053] like Figure 3d As shown, at least one pin 108 and a plurality of driver chips 109 are formed on the first conductive layer 106, and the at least one pin 108 is used to be electrically connected to the first conductive layer 106. For example, the at least one pin 108 is arranged on the first scribe line or the second scribe line. Figure 4 The plurality of sub-areas are divided, and at least one pin 108 is shared between adjacent sub-areas. For example, at least one pin 108 can be formed on the first conductive layer 106 by depositing a metal material and performing an etching process. Then, a plurality of driver chips 109 are mounted on the first conductive layer 106. For example, Figure 4 The multiple sub-areas are mounted with the multiple driving chips 109 , and the driving chips 109 are separated from each other. The multiple inductor and capacitor combinations in each sub-area are electrically connected to the associated driving chip 109 through the first conductive layer 106 .

[0054] like Figure 3e As shown, after mounting a plurality of driver chips 109 on the first conductive layer 106, a packaging layer 110 is formed, and the packaging layer 110 covers the plurality of driver chips 109 and the exposed parts of the first conductive layer 106. For example, a casting method can be used to shape the molding material according to a preset shape, so as to form a packaging layer 110 on the obtained inductor and capacitor array. Wherein, the casting method includes casting, injection molding, transfer molding and compression molding. Preferably, after forming the packaging layer 110, the obtained inductor and capacitor array is thinned from the top of the packaging layer 110. For example, the surface of the inductor and capacitor array is flattened by chemical mechanical polishing (CMP) or isotropic etching after coating, and the obtained inductor and capacitor array is thinned.

[0055] like Figure 3f As shown, after forming the packaging layer 110 and performing the thinning operation, a first dividing groove 121 is formed along the axis A between adjacent sub-areas in the inductor and capacitor array, and the axis A extends along the thickness direction of the inductor and capacitor array. For example, the first dividing groove 121 is formed by sawing, etching or laser separation, and the first dividing groove 121 extends from the surface of the second conductive layer 107 away from the inductor layer 105 to the surface of the first conductive layer 106 away from the capacitor layer 104. At this time, the pins 108 shared between the adjacent sub-areas serve as a connection part and a mechanical fixation.

[0056] For example, before forming the first dividing grooves 121, a blue film is attached to the upper surface of the stacked structure, and then the first dividing grooves are formed along the axis A between adjacent sub-areas in the inductor and capacitor array. The "blue film" is a PE film commonly used when slicing a wafer.

[0057] like Figure 3g As shown, the first dividing grooves 121 are at least partially filled with a filling material 122. For example, the filling material 122 is a polymer material such as silicone or epoxy resin.

[0058] like Figure 3h As shown, after the filling material 122 fills the first dividing grooves 121, the inductor and capacitor array is divided into separate device modules 100 along the axis A again by sawing, etching or laser separation. For example, during separation, the filling material 122 is only partially removed along the axis A, and the filling material 122 located on the side of the device module 100 is retained.

[0059] In the device module and manufacturing method thereof provided by the present invention, the driving chip, capacitor, multi-phase inductor and other devices are made on one chip, and the chip is layered so that the driving chip, capacitor and multi-phase inductor are stacked, thereby reducing the chip area, improving the integration of the multi-phase power supply, and reducing the chip cost.

[0060] In addition, the connection relationship between the connection points of each part of the device module is connected through a conductive channel that penetrates the material layer. Through the vertical connection of the conductive channel, the layout and connection of the multi-phase power supply are optimized, and the problem of parasitic capacitance generated between the connection points is reduced to a certain extent, and the connection complexity of the multi-phase power supply is reduced.

[0061] In addition, the present application manufactures an inductor and capacitor array of optimized size through lamination bonding, sintering and packaging processes of the capacitor layer and the multi-phase inductor layer, and then cuts and divides the inductor and capacitor array into multiple device modules as needed. The process is simple and the manufacturing cost is effectively reduced.

[0062] The embodiments of the present invention are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A device module, comprising: a first conductive layer, a second conductive layer, and a first functional layer and a second functional layer disposed between the first conductive layer and the second conductive layer, Wherein, the first functional layer provides a plurality of capacitors and a plurality of through-hole electrodes isolated from the plurality of capacitors; A plurality of inductors are formed in the second functional layer, each of the inductors is arranged along the thickness direction of the second functional layer so that a first terminal of the inductor is electrically connected to the first conductive layer through a corresponding through-hole electrode, and a second terminal of the inductor is electrically connected to the second conductive layer; Wherein, the device module further includes: A driving chip is placed above the first conductive layer, and the driving chip is electrically connected to the plurality of capacitors in the first functional layer and the plurality of inductors in the second functional layer through the first conductive layer; a plurality of pins disposed above the first conductive layer, wherein the plurality of pins are respectively located on two sides of the driving chip; and A packaging layer covers the driving chip and the exposed portion of the first conductive layer.

2. The device module according to claim 1, wherein: The driving chip includes a multi-phase switching power supply chip.

3. The device module according to claim 1, wherein the first functional layer comprises: an upper electrode plate disposed below the first conductive layer; a lower electrode plate disposed above the second functional layer; as well as A capacitor dielectric layer is provided between the upper plate and the lower plate, Among them, the first electrode plate of each capacitor is formed in the upper electrode plate, the second electrode plate of each capacitor is formed in the lower electrode plate, and each through-hole electrode passes through the upper electrode plate, the capacitor dielectric layer and the lower electrode plate.

4. An inductor and capacitor array, comprising: a first conductive layer, a second conductive layer, and a stacked structure disposed between the first conductive layer and the second conductive layer, wherein the stacked structure includes an inductor layer and a capacitor layer, Wherein, the capacitor layer provides a plurality of capacitors and a plurality of through-hole electrodes isolated from the plurality of capacitors; A plurality of inductors are formed in the inductor layer, each of which is arranged along the thickness direction of the inductor layer so that a first terminal of the inductor is electrically connected to the first conductive layer through a corresponding through-hole electrode, and a second terminal of the inductor is electrically connected to the second conductive layer. Wherein, the inductor and capacitor array further includes: A plurality of first scribing lanes extending along a first direction and a plurality of second scribing lanes extending along a second direction, wherein the first scribing lanes and the second scribing lanes intersect each other to divide the stacked structure into a plurality of sub-regions, each sub-region comprising a plurality of inductor and capacitor combinations; a plurality of driving chips, wherein the plurality of driving chips are respectively placed in the plurality of sub-areas, and a plurality of inductor-capacitor combinations in each sub-area are electrically connected to the associated driving chip through the first conductive layer; and At least one pin is disposed on the first scribe line or the second scribe line, and the at least one pin is used to be electrically connected to the first conductive layer.

5. The inductor and capacitor array according to claim 4, wherein the capacitor layer comprises: an upper electrode plate disposed below the first conductive layer; A lower electrode plate disposed above the inductor layer; as well as A capacitor dielectric layer is provided between the upper plate and the lower plate, Among them, the first electrode plate of each capacitor is formed in the upper electrode plate, the second electrode plate of each capacitor is formed in the lower electrode plate, and each through-hole electrode passes through the upper electrode plate, the capacitor dielectric layer and the lower electrode plate.

6. The inductor-capacitor array according to claim 4, wherein: The inductor layer comprises: a core; and A plurality of coils are located in the core body, each coil is wound around an axis along the thickness direction of the core body, and two ends of the coil are respectively led out from opposite end surfaces in the thickness direction of the core body.

7. The inductor-capacitor array according to claim 6, wherein: The core body is formed by sealing the plurality of coils with a sealing material by a resin molding method or an integral die casting method.

8. The inductor-capacitor array according to claim 4, wherein: Adjacent sub-areas share at least one pin.

9. The inductor-capacitor array according to claim 8, wherein: The inductor and capacitor array may be divided into a plurality of device modules according to first dicing lanes and second dicing lanes between adjacent sub-regions.

10. A method for manufacturing the device module according to any one of claims 1 to 3, comprising: forming a stacked structure, the stacked structure comprising a stacked inductor layer and a capacitor layer; forming a first conductive layer on a first surface of the stacked structure; forming a second conductive layer on a second surface of the stacked structure opposite to the first surface; Dividing the stacked structure into a plurality of sub-regions by a first scribe line and a second scribe line, each sub-region comprising a plurality of inductor and capacitor combinations; and Adjacent sub-areas are separated to obtain a plurality of device modules.

11. The manufacturing method according to claim 10, wherein: The step of forming the stacked structure comprises: Providing a capacitor dielectric layer, the capacitor dielectric layer comprising a third surface and a fourth surface facing each other; forming a plurality of through holes on the capacitor dielectric layer; An upper electrode plate and a lower electrode plate are respectively formed on the third surface and the fourth surface of the capacitor dielectric layer, and the plurality of through holes penetrate the upper electrode plate, the capacitor dielectric layer and the lower electrode plate; Providing the inductor layer, and attaching the inductor layer to the lower electrode plate, wherein a plurality of inductors are formed in the inductor layer, and each of the inductors is arranged along the thickness direction of the inductor layer; and A conductive material is fabricated above the upper electrode plate. The conductive material fills the plurality of through holes to form a plurality of through-hole electrodes. The through-hole electrodes are used to realize electrical connection between the first conductive layer and the first terminals of the plurality of inductors.

12. The manufacturing method according to claim 11, after forming a second conductive layer on a second surface of the stacked structure opposite to the first surface, further comprising: A plurality of driving chips are placed above the first conductive layer. The plurality of driving chips are placed in the plurality of sub-areas respectively. A plurality of inductor-capacitor combinations in each sub-area are electrically connected to the associated driving chip through the first conductive layer.

13. The manufacturing method according to claim 12, wherein: After placing a plurality of driving chips on the first conductive layer, the method further comprises: Disposing at least one pin on the first scribing street or the second scribing street, the at least one pin being used to be electrically connected to the first conductive layer, and at least one pin being shared between adjacent sub-areas; and A packaging layer is formed, where the packaging layer covers the plurality of driving chips and the exposed portion of the first conductive layer.

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