A comparator control circuit

Abstract

The application discloses a comparator control circuit and belongs to the field of integrated circuits. The comparator control circuit mainly comprises a polarity selection module, a window control module, a low-pass filter module, a clock control module and a main control module. The comparator control circuit can provide a register software controllable, power consumption controllable, comparison hysteresis controllable, output polarity controllable, window controllable, low-pass filter comparator control with flexible sampling rate; wherein, the rising edge of the bus clock triggers the sampling of the window control; the window / sampling signal or the rising edge from the clock control module triggers the sampling of the low-pass filter module, and the consistency of the continuous sampling is checked, and finally the filtering operation is completed and the comparison result is output.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a comparator control circuit. BACKGROUND

[0002] With the rapid development of semiconductor technology, the integration of chip industry is increasingly mature, and SOC (System on Chip) and other integrated circuits have entered people's production and life. Smartwatches and supercomputers are increasingly widely used. Integrated circuits are the core components. The comparator is one of the basic modules of the integrated circuit, and its function is to compare the high and low of the input voltage, and then obtain the comparison result after certain processing.

[0003] For the existing comparator control circuit in the SOC, if the voltage value of the input end needs to be compared and processed to obtain the comparison result, there are mainly two methods: 1. Configure the working mode of the comparator control circuit, mainly including the configuration of the comparison hysteresis time, the configuration of the comparison time or the comparison speed, and after the configuration is completed, the corresponding level is directly generated as the conversion result; 2. Configure the working mode of the comparator control circuit, mainly including the configuration of the comparison hysteresis time, the configuration of the comparison time or the comparison speed, the input result flip configuration, and after the configuration is completed, the comparator comparison result is flipped according to the configuration, and the interrupt processing is generated when the enable interrupt is monitored according to the edge.

[0004] The above two methods can realize the basic analog input voltage comparison function, but for the output result of the comparator, on the one hand, it only has the result flip function, which is too single, and cannot meet various application requirements; on the other hand, when the hysteresis function is lacking or the configurable hysteresis voltage is insufficient to meet the use demand, when the input voltage difference is less than the offset voltage of the differential comparator, the final output of the comparator will produce high-frequency oscillation. SUMMARY

[0005] The purpose of the present application is to provide a comparator control circuit to solve the problems in the background art.

[0006] To solve the above technical problems, the present application provides a comparator control circuit, which comprises a polarity selection module, a window control module, a low-pass filter module, a clock control module, a selector, an analog comparator and a master control module.

[0007] The input end of the polarity selector is connected to the output end of the analog comparator, and the output end of the polarity selector is connected to the input end of the window control module.

[0008] The window control module is driven by a bus clock and controlled by a control signal from a window / sampling terminal, and its output terminal is connected to a low-pass filter module;

[0009] The clock driving signal of the low-pass filter module is selected by a selector, and the output of the selector is the final output result of the comparator control circuit;

[0010] The first input terminal of the clock control module is connected to a bus clock, and the second input terminal is connected to a frequency division control of a master module;

[0011] The input terminal of the master module receives the output result of the comparator control circuit, and the output terminal is connected to an analog comparator, a polarity selection module, a window control module and a low-pass filter module respectively.

[0012] Optionally, the polarity selection module inverts the output level of the analog comparator to change the output polarity.

[0013] Optionally, the window control module performs window control, is driven by a bus clock, and is controlled by a control signal from a window / sampling terminal to selectively transmit an input signal to the low-pass filter module.

[0014] Optionally, the low-pass filter module is a digital low-pass filter, which has two selectable clock sources to perform filtering to determine a sampling time; according to a configurable filter number, the consistency of consecutive sampling samples is judged to realize the function of digital filtering.

[0015] Optionally, the clock control module is used to generate the clock of the low-pass filter module, and according to a configurable frequency division coefficient, the bus clock is divided into a frequency division clock for filtering.

[0016] Optionally, the master module includes signals of 9 control or state registers: EN, PWRMD, HYSTCTR, POL, WINEN, FILT_DIV, FILT_CNT, SMPEN and CMPOUT; wherein EN is an enable switch of the analog comparator, used to start the comparison of analog quantities; PWRMD is a control switch of the analog comparator, used to control the comparison operation of the analog comparator in a low-power mode; HYSTCTR is a hysteresis control of the analog comparator, used to select a hysteresis voltage of the analog comparator; POL is used for the comparison result inversion control of the polarity selection module; WINEN is used for the enable of the window control module; FILT_DIV is used to set the frequency division coefficient of the clock control module; FILT_CNT is used to configure the filter number of the low-pass filter module; SMPEN is used to select the sampling clock of the low-pass filter module as the control signal of the window / sampling terminal; and CMPOUT is used to save the comparison result of the last analog comparator.

[0017] Optionally, the main control module adopts AMBA bus protocol, and controls the operation of the whole comparator control circuit through a bus interface register.

[0018] Optionally, the comparator control circuit has the functions of register software controllability, power consumption controllability, comparison hysteresis controllability, output polarity controllability, window control, and low-pass filtering at a flexible sampling rate, thereby avoiding high-frequency oscillation caused by hysteresis.

[0019] Optionally, the clock driving signal of the low-pass filtering module comes from a control signal of a window / sampling terminal or a clock after frequency division of the clock control module, and is selected through a selector.

[0020] The comparator control circuit provided by the application is used for analog comparator comparison process and result control, and comprises a polarity selection module, a window control module, a low-pass filtering module, a clock control module and a main control module. The comparator control circuit can provide register software controllability, power consumption controllability, comparison hysteresis controllability, output polarity controllability, window control, and low-pass filtering at a flexible sampling rate. The rising edge of a bus clock triggers sampling of the window control. A control signal of a window / sampling terminal or a clock after frequency division of the clock control module triggers sampling of the low-pass filtering module, and the consistency of continuous sampling is checked, and finally filtering operation is completed, and a comparison result is output. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a structure schematic diagram of the comparator control circuit provided by the application;

[0022] Figure 2 is a bypass control logic schematic diagram of the low-pass filtering module;

[0023] Figure 3 is a conduction timing diagram of output signals of each module in the comparator control circuit. DETAILED DESCRIPTION

[0024] The application provides a comparator control circuit, which is used for providing a configurable and reliable comparison result output for an integrated circuit such as an SOC. The comparator control circuit can perform polarity control, window control, and can avoid high-frequency oscillation caused by hysteresis.

[0025] The application provides a comparator control circuit, which is used for providing a configurable and reliable comparison result output for an integrated circuit such as an SOC. The comparator control circuit can perform polarity control, window control, and can avoid high-frequency oscillation caused by hysteresis.

[0026] The structure of the comparator control circuit is as follows Figure 1As shown, including polarity selection module, window control module, low pass filter module, clock control module, and master control module. The input end of the polarity selector is connected to the output end of the analog comparator, the output end of the polarity selector is connected to the input end of the window control module; the window control module is driven by the bus clock, and the window / sampling end input control signal is connected to the output end of the low pass filter module; the clock driving signal of the low pass filter module is selected by the selector, from the window / sampling end, or the clock control module, and the output of the low pass filter module is the final output result of the comparator control circuit; the first input end of the clock control module is connected to the bus clock, and the second input end is connected to the frequency division control of the master control module; the input end of the master control module receives the output result of the comparator control circuit, and the output end is connected to the analog comparator, the polarity selection module, the window control module and the low pass filter module respectively.

[0027] The polarity selection module can control the comparison result to be reversed, that is, the output level of the analog comparator is flipped, and the combination logic is between the comparison from the analog comparator and the completion of the level flip; the window control module can sample the analog comparator output only when the control signal of the input window / sampling end is valid, and the sampling signal is driven by the bus clock, this function can be used to ignore the analog comparator output during the period when the input voltage is invalid, and to realize the zero-crossing detection in some PWM application cases; the low pass filter module operates on the unfiltered and non-synchronous and optional inverted analog comparator output, and generates a filtered and synchronous output CMPOUT, and the synchronous and edge detection is always used to determine the state register bit value, in addition, it is also suitable for CMPOUT in all sampling and window modes; the filtering can be performed using the internal time base defined by FILT_DIV and the bus clock or using the external window / sampling end control signal input to determine the sampling time; the clock control module is used to generate the sampling clock of the low pass filter module, and the frequency division clock is obtained by using the frequency division coefficient FILT_DIV of the bus clock; the master control module contains all control and state registers, and the operation of the module uses AMBA protocol for reading and writing.

[0028] The master module includes 9 control or state register signals: EN, PWRMD, HYSTCTR, POL, WINEN, FILT_DIV, FILT_CNT, SMPEN and CMPOUT; wherein EN is an enable switch of the analog comparator, used to start the comparison of analog quantity; PWRMD is a control switch of the analog comparator, used to control the comparison operation of the analog comparator in low power mode; HYSTCTR is a hysteresis control of the analog comparator, used to select the hysteresis voltage of the analog comparator; POL is used for the comparison result flip control of the polarity selection module; WINEN is used for the enable of the window control module; FILT_DIV is used for setting the frequency division coefficient of the clock control module; FILT_CNT is used for configuring the filter number of the low pass filter module; SMPEN is used for selecting the sampling clock of the low pass filter module as the control signal of the window / sampling end; and CMPOUT is used for saving the comparison result of the last analog comparator.

[0029] Figure 2 The bypass control logic block for the low pass filter module in the comparator control circuit is shown in the figure. In the case of SMPEN=1, if FILT_PER=0x00 or FILT_CNT=0x00, the low pass filter module is bypassed.

[0030] Figure 3 The signal conduction timing diagram for the output signals of the modules in the comparator control circuit is shown in the figure. The negative end of the analog comparator is a fixed voltage value, and the positive end is periodically changed in the form of a triangular wave to generate a periodically changed analog comparator result. Since the polarity selection module is a combinational logic circuit, the delay of the combinational circuit is not considered, so the polarity selection module is synchronized with the output of the analog comparator. When the control signal of the window / sampling end is high, the input signal of the window control module is transmitted to the output, otherwise the output of the window control module will remain in the original state. If FILT_CNT of the low pass filter module is set to 0x01, the low pass filter module acts as a simple sampler. When the low pass filter module is bypassed and FILT_CNT is set to greater than 0x01, the low pass filter module filters based on multiple samples. If the multiple sample levels are consistent, the output is performed. If SMPEN is set to 1, the control signal input of the external window / sampling end is used as the sampling clock. If SMPEN is set to 0, the frequency division bus clock from the clock control module is used as the sampling clock.

[0031] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or modification of the present application by a person skilled in the art based on the above disclosure is within the protection scope of the claims.

Claims

1. A comparator control circuit, characterized by, The comparator control circuit comprises a polarity selection module, a window control module, a low-pass filter module, a clock control module, a selector, an analog comparator and a master control module; The input end of the polarity selection module is connected with the output end of the analog comparator, and the output end of the polarity selection module is connected with the input end of the window control module; The window control module is driven by a bus clock and is input with a control signal from a window / sampling end, and the output end of the window control module is connected with the low-pass filter module; The clock driving signal of the low-pass filter module is selected by the selector, and the output of the low-pass filter module is the final output result of the comparator control circuit; The first input end of the clock control module is connected with the bus clock, and the second input end is connected with the frequency division control of the master control module; The input end of the master control module receives the output result of the comparator control circuit, and the output end is connected with the analog comparator, the polarity selection module, the window control module and the low-pass filter module respectively; The polarity selection module inverts the output level of the analog comparator to change the output polarity; The window control module performs window control, is driven by the bus clock and is controlled by the control signal from the window / sampling end, and selectively transmits the input signal to the low-pass filter module; The low-pass filter module is a digital low-pass filter, has two selectable clock sources to perform filtering to determine the sampling time, and is used for realizing digital filtering by judging the consistency of continuous sampling samples according to the configurable filtering quantity; The clock control module is used for generating the clock of the low-pass filter module, and divides the bus clock into a frequency division clock used for filtering according to the configurable frequency division coefficient; The clock driving signal of the low-pass filter module is selected by the selector from the control signal from the window / sampling end or the clock after frequency division of the clock control module.

2. The comparator control circuit of claim 1, wherein, The master control module comprises the signals of 9 control or state registers, namely EN, PWRMD, HYSTCTR, POL, WINEN, FILT_DIV, FILT_CNT, SMPEN and CMPOUT. The EN is an enable switch of the analog comparator, used for starting the comparison of the analog quantity. The PWRMD is a control switch of the analog comparator, used for controlling the comparison operation of the analog comparator in the low-power mode. The HYSTCTR is a hysteresis control of the analog comparator, used for selecting the hysteresis voltage of the analog comparator. The POL is used for the comparison result inversion control of the polarity selection module. The WINEN is used for the enable of the window control module. The FILT_DIV is used for setting the frequency division coefficient of the clock control module. The FILT_CNT is used for configuring the filtering quantity of the low-pass filter module. The SMPEN is used for selecting the sampling clock of the low-pass filter module as the control signal from the window / sampling end. The CMPOUT is used for saving the comparison result of the analog comparator last time.

3. The comparator control circuit of claim 1, wherein, The master control module adopts the AMBA bus protocol and controls the work of the entire comparator control circuit through the bus interface register.

4. The comparator control circuit of claim 3, wherein, The comparator control circuit is provided with a register software controllable, power consumption controllable, comparison hysteresis controllable, output polarity controllable, window controllable, and low-pass filterable comparator control with flexible sampling rate, thereby avoiding high-frequency oscillation caused by hysteresis.

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