Control structure and method for accumulator buffered data accumulation offload
By introducing a first buffer and a second buffer that work alternately in the accumulator buffer, the problem of low accumulator buffer efficiency is solved, and the continuous caching and unloading of accumulation results is realized, thereby improving the working efficiency of the accumulator buffer.
Patent Information
- Application Number
- CN202210966617.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-12
- Publication Date
- 2026-01-09
- Estimated Expiration
- 2042-08-12
AI Technical Summary
The accumulator buffer is inefficient because after the accumulation operation is completed, it needs to wait for the data to be unloaded before the next round of caching operations can be performed, which increases the waiting time.
The data accumulation and unloading control structure using accumulator buffers includes accumulator buffer control logic and a buffer module. By alternating the operation of the first buffer and the second buffer, the continuous caching and unloading of accumulation results are achieved. The first control logic unit and the second control logic unit generate accumulation result caching signals and unloading signals to ensure that the buffer module can immediately enter the next round of operation after the end of one round of operation.
By alternating between the first and second buffers, the time the accumulator buffer spends waiting for data to be unloaded is reduced, improving the efficiency of the accumulator buffer and enabling it to continuously perform caching and unloading operations of the accumulation results.
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Figure CN115268836B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of accumulator buffering technology, specifically to a control structure and method for data accumulation and unloading from an accumulator buffer. Background Technology
[0002] Systolic arrays (SSAs) are two-dimensional computational structures that accelerate computation through a data-driven approach. Each computational unit in a SSA can transfer data between adjacent units, reducing the number of input / output data accesses through data reuse, thereby lowering memory access bandwidth requirements. SSAs can achieve high computational throughput with relatively low memory access bandwidth, solving the memory access bottleneck problem faced by most processors, and showing significant advantages, especially in high-intensity computation and memory access processing such as neural networks.
[0003] The matrix multiplication acceleration unit is a two-dimensional pulsating array, whose two-dimensional size is flexibly configurable and can be tailored to performance and application requirements. For example... Figure 1 As shown, the matrix multiplication acceleration unit consists of multiple isomorphic operation units. Northbound data is transmitted from north to south in the pulsating array and cached in each operation unit of the pulsating array as needed. Westbound data is transmitted from west to east in the pulsating array. After the westbound data arrives at the operation unit, it is multiplied with the northbound data cached inside the operation unit. The multiplication result is added with the accumulated data transmitted from the north operation unit, thus completing the multiplication-addition operation. The multiplication-addition result is then transmitted to the south operation unit, realizing the transmission of the multiplication-addition result from north to south.
[0004] For example Figure 1 As shown, the accumulator buffer is located at the south exit of the matrix multiplication acceleration unit. It receives the multiplication-accumulation results transmitted from the matrix multiplication acceleration unit, accumulates the results, and caches them. When the accumulator buffer receives an unload signal, the current round of accumulation operation ends, and the data in the accumulator buffer is written back to the local data memory. Then, the data in the accumulator buffer needs to be unloaded. Only after the unload operation is completed can the accumulator buffer start the next round of accumulation and caching operations. This makes the accumulator buffer inefficient. Summary of the Invention
[0005] This invention addresses the problems existing in the prior art by proposing a control structure and method for data accumulation and unloading of an accumulator buffer. This structure and method can continuously cache the accumulation results through a first buffer and a second buffer, effectively improving the working efficiency of the accumulator buffer.
[0006] The technical solution adopted by this invention to solve its technical problem is: a control structure for data accumulation and unloading of an accumulator buffer, comprising...
[0007] an accumulator buffer control logic, comprising a first control logic unit for generating an accumulate result cache signal and a second control logic unit for generating an accumulate result unload signal;
[0008] a buffer module, comprising
[0009] a control register, electrically connected with the accumulator buffer control logic, for receiving and temporarily storing the accumulate result cache signal and the accumulate result unload signal;
[0010] a double buffer unit, electrically connected with the control register, and the double buffer unit comprises a first buffer and a second buffer; the first buffer enters an accumulate result cache state according to the accumulate result cache signal, while the second buffer enters an accumulate result unload state according to the accumulate result unload signal; or, the second buffer enters the accumulate result cache state according to the accumulate result cache signal, while the first buffer enters the accumulate result unload state according to the accumulate result unload signal.
[0011] Preferably, the first control logic unit comprises
[0012] a buffer determination unit one, for determining that the first buffer or the second buffer enters the accumulate result cache state;
[0013] a buffer entry start address determination unit one, electrically connected with the buffer determination unit one, for determining an entry start address of the first buffer or the second buffer which enters the accumulate result cache state;
[0014] a buffer entry end address determination unit one, electrically connected with the buffer determination unit one, for determining an entry end address of the first buffer or the second buffer which enters the accumulate result cache state;
[0015] a buffer entry current address determination unit one, electrically connected with the buffer entry start address determination unit one and the buffer entry end address determination unit one, for determining an entry current address of the first buffer or the second buffer.
[0016] Preferably, the second control logic unit comprises
[0017] a buffer determination unit two, electrically connected with the buffer determination unit one; when the buffer determination unit one determines that the first buffer enters the accumulate result cache state, the buffer determination unit two determines that the second buffer enters the accumulate result unload state; when the buffer determination unit one determines that the second buffer enters the accumulate result cache state, the buffer determination unit two determines that the first buffer enters the accumulate result unload state;
[0018] A buffer entry start address determining unit two is electrically connected with the buffer determining unit two, and is configured to determine an entry start address of the first buffer or the second buffer in the accumulation result offloading state.
[0019] A buffer entry end address determining unit two is electrically connected with the buffer determining unit two, and is configured to determine an entry end address of the first buffer or the second buffer in the accumulation result offloading state.
[0020] A buffer entry current address determining unit two is electrically connected with the buffer entry start address determining unit two and the buffer entry end address determining unit two, and is configured to determine a current entry address of the first buffer or the second buffer.
[0021] Preferably, the buffer module further comprises
[0022] A first data register is electrically connected with an operation unit at an exit of the matrix multiplication acceleration unit, and is configured to obtain and temporarily store a multiplication-addition result corresponding to an output of the operation unit.
[0023] A second data register is electrically connected with the double buffer unit, and is configured to obtain an accumulation result corresponding to the current entry address in the first buffer or the second buffer.
[0024] An adder has a first input electrically connected with the first data register, and has a second input electrically connected with the second data register, and is configured to add the multiplication-addition result in the first data register and the accumulation result in the second data register.
[0025] A third data register is electrically connected with an output of the adder and the double buffer unit, and is configured to obtain and temporarily store an accumulation result output by the adder, and the double buffer unit caches the accumulation result in the third data register to the first buffer or the second buffer corresponding to the current entry address.
[0026] Preferably, the buffer module further comprises
[0027] A result offloading write 0 unit offloads and writes 0 to the accumulation result in the first buffer or the second buffer in the accumulation result offloading state according to the accumulation result offloading signal.
[0028] A control method of data accumulation offloading of an accumulator buffer, comprising the following steps
[0029] A first control logic unit of L1 accumulator buffer control logic generates an accumulation result caching signal, and a second control logic unit of the accumulator buffer control logic generates an accumulation result offloading signal.
[0030] The control register of the L2 buffer module receives and temporarily stores the accumulation result cache signal and the accumulation result unload signal;
[0031] The first buffer of the L3 buffer module performs accumulation result cache operation according to the accumulation result cache signal, while the second buffer of the buffer module performs accumulation result unload operation according to the accumulation result unload signal; or, the second buffer of the buffer module performs accumulation result cache operation according to the accumulation result cache signal, while the first buffer of the buffer module performs accumulation result unload operation according to the accumulation result unload signal.
[0032] As a preferred, the L1 specifically comprises
[0033] The L11 buffer determination unit determines that the first buffer or the second buffer enters the accumulation result cache state;
[0034] The L12 buffer entry start address determination unit determines the entry start address of the first buffer or the second buffer which enters the accumulation result cache state;
[0035] The L13 buffer entry end address determination unit determines the entry end address of the first buffer or the second buffer which enters the accumulation result cache state;
[0036] The L14 buffer entry current address determination unit determines the entry current address of the first buffer or the second buffer.
[0037] As a preferred, the L1 also specifically comprises
[0038] The L15 buffer determination unit two determines that the second buffer enters the accumulation result unload state when the buffer determination unit one determines that the first buffer enters the accumulation result cache state; the buffer determination unit two determines that the first buffer enters the accumulation result unload state when the buffer determination unit one determines that the second buffer enters the accumulation result cache state;
[0039] The L16 buffer entry start address determination unit two determines the entry start address of the first buffer or the second buffer which enters the accumulation result unload state;
[0040] The L17 buffer entry end address determination unit two determines the entry end address of the first buffer or the second buffer which enters the accumulation result unload state;
[0041] The L18 buffer entry current address determination unit two determines the entry current address of the first buffer or the second buffer.
[0042] As a preferred, the L3 specifically comprises
[0043] L31 The first data register acquires and temporarily stores the multiplication-addition result output by the operation unit at the exit of the matrix multiplication acceleration unit;
[0044] L32 The adder adds the multiplication-addition result in the first data register and the accumulated result in the second data register;
[0045] L33 The third data register acquires and temporarily stores the accumulated result output by the adder;
[0046] L34 The double buffering unit buffers the accumulated result in the third data register to the first buffer or the second buffer corresponding to the current address of the entry and in the accumulated result buffering state;
[0047] L35 The second data register acquires the accumulated result corresponding to the current address of the entry in the first buffer or the second buffer.
[0048] As a preferred, the L3 specifically further comprises
[0049] L36 The result unload write 0 unit unloads and writes 0 the accumulated result in the first buffer or the second buffer in the accumulated result unloading state according to the accumulated result unloading signal.
[0050] Beneficial effects
[0051] In the embodiment of the present application, the buffering module can buffer the accumulated result through the first buffer, and meanwhile, can unload the accumulated result buffered in the second buffer. When one round of accumulated result buffering ends, the buffering module can directly enter the buffering of the next round of accumulated result, buffers the accumulated result through the second buffer, and meanwhile, unloads the accumulated result buffered in the first buffer. Such a continuous cycle saves the time for waiting for the unloading of the accumulated result in the prior art, and thus effectively improves the working efficiency of the accumulator buffer. BRIEF DESCRIPTION OF DRAWINGS
[0052] Figure 1 The working principle diagram of the matrix multiplication acceleration unit and the accumulator buffer in the prior art;
[0053] Figure 2 The structural schematic diagram of the accumulator buffer control logic in the embodiment of the present application;
[0054] Figure 3 The structural schematic diagram of the buffering module in the embodiment of the present application. DETAILED DESCRIPTION
[0055] The technical solutions of the present application will be further described below in combination with the drawings and through specific embodiments.
[0056] Embodiment 1: as Figure 2 and Figure 3As shown, a control structure for data accumulation and unloading of an accumulator buffer includes an accumulator buffer control logic and multiple buffer modules. The number of buffer modules is the same as the number of columns in the matrix multiplication acceleration unit. One column of operation unit corresponds to one buffer module, and all buffer modules are synchronously controlled through the accumulator buffer control logic.
[0057] Specifically, the accumulator buffer control logic includes a first control logic unit for generating an accumulation result buffer signal and a second control logic unit for generating an accumulation result unload signal.
[0058] The buffer module includes a control register and a double buffer unit. The control register is electrically connected to the accumulator buffer control logic and is used to receive and temporarily store the accumulation result buffer signal and the accumulation result unload signal. The double buffer unit is electrically connected to the control register and includes a first buffer and a second buffer, wherein the first buffer and the second buffer have the same structure.
[0059] The first buffer enters the accumulation result cache state according to the accumulation result cache signal, while the second buffer enters the accumulation result unload state according to the accumulation result unload signal; or, the second buffer enters the accumulation result cache state according to the accumulation result cache signal, while the first buffer enters the accumulation result unload state according to the accumulation result unload signal. In short, when the first buffer is in the accumulation result cache state, the second buffer must be in the accumulation result unload state; when the first buffer is in the accumulation result unload state, the second buffer must be in the accumulation result cache state. The states of the first and second buffers are always opposite.
[0060] In this embodiment, when the accumulator buffer performs its current accumulation caching operation, the buffer module can cache the accumulation result through the first buffer and simultaneously unload the cached accumulation result from the second buffer. After unloading, the second buffer is in a standby state. Thus, when the accumulator buffer performs the next accumulation caching operation, the buffer module can directly cache the accumulation result through the second buffer and simultaneously unload the cached accumulation result from the first buffer. The buffer module in this embodiment can continuously cycle in this way (unlike existing technologies, which require waiting for the accumulator buffer to unload all its internal data before performing the next round of data accumulation caching after receiving a data unloading signal), saving the time spent waiting for data (i.e., accumulation result) to unload, thereby effectively improving the working efficiency of the accumulator buffer in this embodiment.
[0061] Furthermore, such as Figure 2 As shown, the first control logic unit includes a buffer determination unit 1, a buffer entry start address determination unit 1, a buffer entry end address determination unit 1, and a buffer entry current address determination unit 1.
[0062] The buffer determination unit one is configured to determine whether the first buffer or the second buffer enters the accumulated result cache state. The buffer entry start address determination unit one is electrically connected with the buffer determination unit one and configured to determine the entry start address of the first buffer or the second buffer entering the accumulated result cache state. The buffer entry end address determination unit one is electrically connected with the buffer determination unit one and configured to determine the entry end address of the first buffer or the second buffer entering the accumulated result cache state. The buffer entry current address determination unit one is electrically connected with the buffer entry start address determination unit one and the buffer entry end address determination unit one and configured to determine the entry current address of the first buffer or the second buffer.
[0063] The accumulated result cache signal includes the buffer working state, the entry start address, the entry end address and the entry current address.
[0064] For example, during the first round of accumulated result cache operation, the buffer determination unit one determines that the buffer working state is that the first buffer enters the accumulated result cache state. The buffer entry start address determination unit one determines the entry start address of the first buffer, the buffer entry end address determination unit one determines the entry end address of the first buffer, and the buffer entry current address determination unit one determines the entry current address of the first buffer. During the first round of accumulated result cache operation, the buffer working state, the entry start address and the entry end address of each accumulated result cache signal are fixed, while the entry current address gradually changes from the entry start address to the entry end address (i.e. the entry current address in the first accumulated result cache signal is the entry start address, the entry current address in the second accumulated result cache signal is the next entry address of the entry start address, and the entry current address in the last accumulated result cache signal is the entry end address). When the entry current address is the entry end address, it indicates that the first round of accumulated result cache operation is completed and the next round of accumulated result cache operation is needed.
[0065] Then, in the second round of accumulation result cache operation process, the buffer determination unit one determines the buffer working state as the second buffer entering the accumulation result cache state. The buffer entry start address determination unit one determines the entry start address of the second buffer, and the buffer entry end address determination unit one determines the entry end address of the second buffer. The buffer entry current address determination unit one determines the entry current address of the second buffer. In the second round of accumulation result cache operation process, the buffer working state, the entry start address and the entry end address of each accumulation result cache signal are fixed, and the entry current address gradually changes from the entry start address to the entry end address (i.e. the entry current address in the first accumulation result cache signal is the entry start address, the entry current address in the second accumulation result cache signal is the next entry address of the entry start address, and the entry current address in the last accumulation result cache signal is the entry end address). When the entry current address is the entry end address, it indicates that the second round of accumulation result cache operation process is completed, and the next round of accumulation result cache operation process is needed.
[0066] Then, in the third round of accumulation result cache operation process, the buffer determination unit one determines the buffer working state as the first buffer entering the accumulation result cache state, and the process is repeated.
[0067] Further, as shown in Figure 2 The second control logic unit includes a buffer determination unit two, a buffer entry start address determination unit two, a buffer entry end address determination unit two and a buffer entry current address determination unit two.
[0068] The buffer determination unit two is electrically connected with the buffer determination unit one. When the buffer determination unit one determines that the first buffer enters the accumulation result cache state, the buffer determination unit two determines that the second buffer enters the accumulation result unload state. When the buffer determination unit one determines that the second buffer enters the accumulation result cache state, the buffer determination unit two determines that the first buffer enters the accumulation result unload state. The buffer entry start address determination unit two is electrically connected with the buffer determination unit two, and is used to determine the entry start address of the first buffer or the second buffer entering the accumulation result unload state. The buffer entry end address determination unit two is electrically connected with the buffer determination unit two, and is used to determine the entry end address of the first buffer or the second buffer entering the accumulation result unload state. The buffer entry current address determination unit two is electrically connected with the buffer entry start address determination unit two and the buffer entry end address determination unit two, and is used to determine the entry current address of the first buffer or the second buffer.
[0069] The accumulation result unload signal also includes the buffer working state, the entry start address, the entry end address and the entry current address.
[0070] For example, during the first round of accumulation result unloading operation, the buffer determination unit II determines that the buffer working state is to enter the accumulation result unloading state for the second buffer. The buffer entry start address determination unit II determines the entry start address of the second buffer, the buffer entry end address determination unit II determines the entry end address of the second buffer. The buffer entry current address determination unit II determines the entry current address of the second buffer. And during the first round of accumulation result unloading operation, the buffer working state, the entry start address and the entry end address of each accumulation result unloading signal are fixed, while the entry current address gradually changes from the entry start address to the entry end address (i.e. the entry current address in the first accumulation result unloading signal is the entry start address, the entry current address in the second accumulation result unloading signal is the next entry address of the entry start address, and so on, the entry current address in the last accumulation result unloading signal is the entry end address). When the entry current address is the entry end address, it indicates that the first round of accumulation result unloading operation is completed, and the next round of accumulation result unloading operation needs to be entered. And each round of accumulation result unloading operation is synchronized with the corresponding round of accumulation result buffer operation, i.e. after the first round of accumulation result unloading operation is completed, the first round of accumulation result buffer operation needs to be waited for before entering the next round of operation together.
[0071] Then, during the second round of accumulation result unloading operation, the buffer determination unit II determines that the buffer working state is to enter the accumulation result unloading state for the first buffer. The buffer entry start address determination unit II determines the entry start address of the first buffer, the buffer entry end address determination unit II determines the entry end address of the first buffer. The buffer entry current address determination unit II determines the entry current address of the first buffer. And during the second round of accumulation result buffer operation, the buffer working state, the entry start address and the entry end address of each accumulation result buffer signal are fixed, while the entry current address gradually changes from the entry start address to the entry end address (i.e. the entry current address in the first accumulation result buffer signal is the entry start address, the entry current address in the second accumulation result buffer signal is the next entry address of the entry start address, and so on, the entry current address in the last accumulation result buffer signal is the entry end address). When the entry current address is the entry end address, it indicates that the second round of accumulation result unloading operation is completed, and the next round of accumulation result unloading operation needs to be entered.
[0072] Then, during the second round of accumulation result unloading operation, the buffer determination unit II determines that the buffer working state is to enter the accumulation result unloading state for the first buffer. The buffer entry start address determination unit II determines the entry start address of the first buffer, the buffer entry end address determination unit II determines the entry end address of the first buffer. The buffer entry current address determination unit II determines the entry current address of the first buffer. And during the second round of accumulation result buffer operation, the buffer working state, the entry start address and the entry end address of each accumulation result buffer signal are fixed, while the entry current address gradually changes from the entry start address to the entry end address (i.e. the entry current address in the first accumulation result buffer signal is the entry start address, the entry current address in the second accumulation result buffer signal is the next entry address of the entry start address, and so on, the entry current address in the last accumulation result buffer signal is the entry end address). When the entry current address is the entry end address, it indicates that the second round of accumulation result unloading operation is completed, and the next round of accumulation result unloading operation needs to be entered.
[0073] The accumulator buffer control logic of the embodiment can generate the accumulation result cache signal and the accumulation result unload signal simultaneously through the first control logic unit and the second control logic unit, the entry current address of the accumulation result cache signal and the accumulation result unload signal can change in order one by one, so that the double buffer unit can simultaneously perform the accumulation result cache operation and the accumulation result unload operation according to the accumulation result cache signal and the accumulation result unload signal.
[0074] Further, as shown in Figure 3 The buffer module further includes a first data register, a second data register, an adder and a third data register.
[0075] The first data register is electrically connected with the operation unit at the exit of the matrix multiplication acceleration unit, for obtaining and temporarily storing the multiplication-addition result output by the corresponding operation unit. The second data register is electrically connected with the double buffer unit, for obtaining the accumulation result corresponding to the entry current address in the first buffer or the second buffer. The first input end of the adder is electrically connected with the first data register, and the second input end of the adder is electrically connected with the second data register, for adding the multiplication-addition result in the first data register and the accumulation result in the second data register. The third data register is electrically connected with the output end of the adder and the double buffer unit, for obtaining and temporarily storing the accumulation result output by the adder, and the double buffer unit caches the accumulation result in the third data register into the first buffer or the second buffer corresponding to the entry current address.
[0076] In the first round of accumulation result cache operation, the first control logic unit first generates a first accumulation result cache signal, and sends the first accumulation result cache signal to the control register. The control register receives and temporarily stores the first accumulation result cache signal (assuming that the first accumulation result cache signal determines that the first buffer enters the accumulation result cache state). At this time, the entry current address of the accumulation result cache signal is the starting address of the entry of the first buffer.
[0077] The corresponding multiply-accumulate result accumulation buffer process is as follows: firstly, the first data register acquires and temporarily stores the multiply-accumulate result output by the operation unit connected thereto, then the adder adds the multiply-accumulate result in the first data register and the accumulation result in the second data register (the initial accumulation result in the second data register is 0) to obtain a new accumulation result, then the third data register acquires and temporarily stores the accumulation result output by the adder, then the double buffer unit buffers the accumulation result in the third data register to the corresponding entry in the first buffer according to the first accumulation result buffer signal (the address of the entry corresponds to the entry current address of the first accumulation result buffer signal), and finally the second data register acquires and temporarily stores the accumulation result buffered in the first buffer (corresponding to the entry current address).
[0078] Then the first control logic unit generates a second accumulation result buffer signal, the buffer working state, the entry start address and the entry end address of the second accumulation result buffer signal remain unchanged, only the entry current address advances by one in order. At this time, the first data register acquires and temporarily stores the next multiply-accumulate result output by the operation unit connected thereto, and the accumulation buffer operation of the multiply-accumulate result is the same as the above process. This continues to circulate until the entry current address of the accumulation result buffer signal generated by the first control logic unit first is the same as the entry end address, when the accumulation result buffer operation of the entry current address is completed, the first round of accumulation result buffer operation process is ended, and then the accumulator buffer enters the next round of accumulation result buffer operation process.
[0079] The first data register, the second data register, the adder, the third data register, the double buffer unit, and the control register are used in cooperation to enable the buffer module to continuously and continuously accumulate and buffer the multiply-accumulate result transmitted by the matrix multiplication acceleration unit, thereby realizing high working efficiency of the accumulator buffer.
[0080] Further, as shown in Figure 3 The buffer module further includes a result unload write 0 unit. The result unload write 0 unit unloads and writes 0 to the accumulation result in the first buffer or the second buffer in the accumulation result unloading state according to the accumulation result unload signal.
[0081] In the first round of accumulation result unloading operation process corresponding to the first round of accumulation result buffer operation process, the second control logic unit first generates a first accumulation result unload signal and sends the accumulation result unload signal to the control register, and the control register receives and temporarily stores the accumulation result unload signal (assuming that the accumulation result unload signal determines that the second buffer enters the accumulation result unloading state). At this time, the entry current address of the accumulation result unload signal is the entry start address of the second buffer.
[0082] The corresponding accumulation result unloading cache process is: according to the entry current address in the first accumulation result unloading signal, the result unloading write 0 unit performs unloading write 0 operation on the accumulation result in the corresponding entry (the address of the entry corresponds to the entry current address in the first accumulation result unloading signal) in the second buffer buffer, at this time, the unloading operation of the first accumulation result is completed.
[0083] Then the second control logic unit generates the second accumulation result unloading signal, the buffer working state, the entry start address and the entry end address of the second accumulation result unloading signal remain unchanged, only the entry current address advances by one in order. At this time, the result unloading write 0 unit performs unloading write 0 operation on the accumulation result in the corresponding entry in the second buffer buffer. This continues to circulate until the entry current address in the accumulation result unloading signal generated by the second control logic unit first is the same as the entry end address, when the unloading operation of the accumulation result of the entry current address is completed, the first round of accumulation result unloading operation process is ended, then it needs to wait for the end of the first round of accumulation result cache operation process and then enter the next round of accumulation result unloading operation process together.
[0084] The embodiment enables the buffer module to continuously and continuously unload the accumulation result in the double buffer unit by the result unloading write 0 unit, thereby realizing high working efficiency of the accumulator buffer.
[0085] In addition, before the second buffer performs the unloading of the accumulation result, the accumulation result in the second buffer needs to be written back to the local data storage first. Specifically, the accumulator buffer of the embodiment further includes a result write back module. One accumulator buffer includes one result write back module, the input end of the result write back module is electrically connected with all double buffer units of all buffer modules, and the output end of the result write back module is connected with the local data storage. Through the result write back module, the accumulation result in the second buffer in all double buffer units can be written into the local data storage at the same time.
[0086] Embodiment 2: a control method of data accumulation unloading of an accumulator buffer, comprising the following steps
[0087] The first control logic unit of the L1 accumulator buffer control logic generates an accumulation result cache signal, and the second control logic unit of the accumulator buffer control logic generates an accumulation result unloading signal.
[0088] The first control logic unit in the L1 generates the accumulated result cache signal, which specifically includes an L11 buffer determination unit that determines that the first buffer or the second buffer enters an accumulated result cache state. An L12 buffer entry start address determination unit determines the entry start address of the first buffer or the second buffer that enters the accumulated result cache state. An L13 buffer entry end address determination unit determines the entry end address of the first buffer or the second buffer that enters the accumulated result cache state. An L14 buffer entry current address determination unit determines the entry current address of the first buffer or the second buffer.
[0089] For example, during the first round of accumulated result cache operation, the buffer determination unit determines that the buffer working state is to determine that the first buffer enters the accumulated result cache state. The buffer entry start address determination unit determines the entry start address of the first buffer, the buffer entry end address determination unit determines the entry end address of the first buffer, and the buffer entry current address determination unit determines the entry current address of the first buffer. During the first round of accumulated result cache operation, the buffer working state, the entry start address, and the entry end address of each accumulated result cache signal are fixed, and the entry current address gradually changes from the entry start address to the entry end address (i.e., the entry current address in the first accumulated result cache signal is the entry start address, the entry current address in the second accumulated result cache signal is the next entry address of the entry start address, and the entry current address in the last accumulated result cache signal is the entry end address). When the entry current address is the entry end address, it indicates that the first round of accumulated result cache operation is completed, and the next round of accumulated result cache operation needs to be entered.
[0090] Then, during the second round of accumulated result cache operation, the buffer determination unit determines that the buffer working state is to determine that the second buffer enters the accumulated result cache state. The buffer entry start address determination unit determines the entry start address of the second buffer, the buffer entry end address determination unit determines the entry end address of the second buffer, and the buffer entry current address determination unit determines the entry current address of the second buffer. During the second round of accumulated result cache operation, the buffer working state, the entry start address, and the entry end address of each accumulated result cache signal are fixed, and the entry current address gradually changes from the entry start address to the entry end address (i.e., the entry current address in the first accumulated result cache signal is the entry start address, the entry current address in the second accumulated result cache signal is the next entry address of the entry start address, and the entry current address in the last accumulated result cache signal is the entry end address). When the entry current address is the entry end address, it indicates that the second round of accumulated result cache operation is completed, and the next round of accumulated result cache operation needs to be entered.
[0091] Then, in the third round of the accumulation result cache operation process, the buffer determination unit determines that the first buffer enters the accumulation result cache state, and the process is repeated.
[0092] In the L1, the second control logic unit generates the accumulation result unloading signal, which specifically includes: when the buffer determination unit one determines that the first buffer enters the accumulation result cache state, the buffer determination unit two determines that the second buffer enters the accumulation result unloading state; when the buffer determination unit one determines that the second buffer enters the accumulation result cache state, the buffer determination unit two determines that the first buffer enters the accumulation result unloading state. The buffer entry start address determination unit two determines the entry start address of the first buffer or the second buffer in the accumulation result unloading state. The buffer entry end address determination unit two determines the entry end address of the first buffer or the second buffer in the accumulation result unloading state. The buffer entry current address determination unit two determines the entry current address of the first buffer or the second buffer.
[0093] For example, in the first round of the accumulation result unloading operation process, the buffer determination unit two determines that the second buffer enters the accumulation result unloading state. The buffer entry start address determination unit two determines the entry start address of the second buffer, the buffer entry end address determination unit two determines the entry end address of the second buffer, and the buffer entry current address determination unit two determines the entry current address of the second buffer. In the first round of the accumulation result unloading operation process, the buffer working state, the entry start address, and the entry end address of each accumulation result unloading signal are fixed, and the entry current address gradually changes from the entry start address to the entry end address (i.e., the entry current address in the first accumulation result unloading signal is the entry start address, the entry current address in the second accumulation result unloading signal is the next entry address of the entry start address, and the entry current address in the last accumulation result unloading signal is the entry end address). When the entry current address is the entry end address, it indicates that the first round of the accumulation result unloading operation process is completed, and the next round of the accumulation result unloading operation process needs to be entered. Each round of the accumulation result unloading operation process is synchronized with the corresponding round of the accumulation result cache operation process, that is, after the first round of the accumulation result unloading operation process is completed, the first round of the accumulation result cache operation process needs to be completed before entering the next round of operation.
[0094] Then, during the second round of accumulation result unloading operation, the buffer determination unit two determines that the buffer working state is determined to be the first buffer entering the accumulation result unloading state. The buffer entry start address determination unit two determines the entry start address of the first buffer, and the buffer entry end address determination unit two determines the entry end address of the first buffer. The buffer entry current address determination unit two determines the entry current address of the first buffer. During the second round of accumulation result caching operation, the buffer working state, the entry start address and the entry end address of each accumulation result caching signal are fixed, and the entry current address gradually changes from the entry start address to the entry end address (i.e., the entry current address in the first accumulation result caching signal is the entry start address, the entry current address in the second accumulation result caching signal is the next entry address of the entry start address, and the entry current address in the last accumulation result caching signal is the entry end address). When the entry current address is the entry end address, it indicates that the second round of accumulation result unloading operation process is completed, and the next round of accumulation result unloading operation process needs to be entered.
[0095] Then, during the third round of accumulation result unloading operation, the buffer determination unit two determines that the buffer working state is determined to be the second buffer entering the accumulation result unloading state, and the process is repeated.
[0096] The accumulator buffer control logic of the embodiment can generate accumulation result caching signals and accumulation result unloading signals through the first control logic unit and the second control logic unit, and the entry current addresses of the accumulation result caching signals and the accumulation result unloading signals can change in order one by one, so that the double buffer unit can perform accumulation result caching operation and accumulation result unloading operation according to the accumulation result caching signals and the accumulation result unloading signals.
[0097] The control register of the L2 buffer module receives and temporarily stores the accumulation result caching signals and the accumulation result unloading signals.
[0098] The first buffer of the L3 buffer module performs accumulation result caching operation according to the accumulation result caching signals, and the second buffer of the buffer module performs accumulation result unloading operation according to the accumulation result unloading signals; or the second buffer of the buffer module performs accumulation result caching operation according to the accumulation result caching signals, and the first buffer of the buffer module performs accumulation result unloading operation according to the accumulation result unloading signals.
[0099] The L3 specifically comprises an L31 first data register which acquires and temporarily stores the multiply-add result output by the operation unit at the exit of the matrix multiplication acceleration unit. An L32 adder adds the multiply-add result in the first data register with the accumulated result in a second data register. An L33 third data register acquires and temporarily stores the accumulated result output by the adder. An L34 double buffering unit caches the accumulated result in the third data register into the first buffer or the second buffer corresponding to the entry current address in the accumulated result cache state. An L35 second data register acquires the accumulated result corresponding to the entry current address in the first buffer or the second buffer.
[0100] In the first round of accumulated result cache operation, the first control logic unit first generates a first accumulated result cache signal and sends the signal to the control register, which receives and temporarily stores the signal (assuming that the signal determines that the first buffer enters the accumulated result cache state). At this time, the entry current address of the accumulated result cache signal is the entry start address of the first buffer.
[0101] The corresponding multiply-add result accumulation cache process is as follows: first, the first data register acquires and temporarily stores the multiply-add result output by the operation unit connected thereto, then the adder adds the multiply-add result in the first data register with the accumulated result in the second data register (the initial accumulated result of the second data register is 0) to obtain a new accumulated result, then the third data register acquires and temporarily stores the accumulated result output by the adder, then the double buffering unit caches the accumulated result in the third data register into the entry corresponding to the first buffer according to the first accumulated result cache signal (the address of the entry corresponds to the entry current address of the first accumulated result cache signal), and finally the second data register acquires and temporarily stores the accumulated result cached in the first buffer (corresponding to the entry current address), at which time the accumulation cache operation of the first multiply-add result is completed.
[0102] Then the first control logic unit first generates a second accumulated result cache signal, the buffer working state, entry start address and entry end address of the second accumulated result cache signal remain unchanged, only the entry current address advances by one in order. At this time, the first data register acquires and temporarily stores the next multiply-add result output by the operation unit connected thereto, and the accumulation cache operation of the multiply-add result is the same as the above process. This continues to circulate until the entry current address of the accumulated result cache signal generated first by the first control logic unit is the same as the entry end address, when the entry current address completes the accumulation cache operation, the entire first round of accumulated result cache operation process is completed, and then the entire accumulator buffer enters the next round of accumulated result cache operation process.
[0103] Meanwhile, the L3 specifically further comprises an L36 result offload write 0 unit configured to offload and write 0 the accumulated result in the first buffer or the second buffer in the accumulated result offload state according to the accumulated result offload signal.
[0104] In the first round accumulated result offload operation process corresponding to the first round accumulated result cache operation process, the second control logic unit first generates a first accumulated result offload signal and sends the accumulated result offload signal to the control register, and the control register receives and temporarily stores the accumulated result offload signal (assuming that the accumulated result offload signal is configured to determine that the second buffer enters the accumulated result offload state). At this time, the entry current address of the accumulated result offload signal is the entry start address of the second buffer.
[0105] The corresponding accumulated result offload cache process is that the result offload write 0 unit offloads and writes 0 the accumulated result in the corresponding entry (the address of the entry corresponds to the entry current address of the first accumulated result offload signal) in the second buffer according to the entry current address in the first accumulated result offload signal, and at this time, the offload operation of the first accumulated result is completed.
[0106] Then, the second control logic unit first generates a second accumulated result offload signal, and the buffer working state, the entry start address and the entry end address of the second accumulated result offload signal remain unchanged, only the entry current address advances by one in order. At this time, the result offload write 0 unit offloads and writes 0 the accumulated result in the corresponding entry in the second buffer. This continues to circulate until the entry current address of the accumulated result offload signal generated by the second control logic unit first is the same as the entry end address, and when the offload operation of the accumulated result of the entry current address is completed, the first round accumulated result offload operation process is ended, and then the first round accumulated result cache operation process needs to be ended before entering the next round of accumulated result offload operation process.
[0107] The embodiment can continuously and continuously accumulate and cache the multiplication and addition results transmitted by the matrix multiplication acceleration unit through the first data register, the second data register, the adder, the third data register and the double buffer unit, the control register, and can continuously and continuously offload the accumulated result in the double buffer unit through the result offload write 0 unit, thereby realizing high working efficiency of the accumulator buffer.
[0108] The above-described embodiments are only used to describe the preferred embodiments of the present application and are not used to limit the concept and scope of the present application. Various modifications and improvements to the technical solutions of the present application made by those skilled in the art without departing from the design concept of the present application shall fall within the protection scope of the present application, and the technical content claimed by the present application has been fully recorded in the claims.
Claims
1. A control device for unloading data accumulation from an accumulator buffer, characterized in that: comprising accumulator buffer control logic, comprising a first control logic unit for generating an accumulation result cache signal and a second control logic unit for generating an accumulation result unload signal; a buffer module, comprising a control register, electrically connected with the accumulator buffer control logic, for receiving and temporarily storing the accumulation result cache signal and the accumulation result unload signal; a double buffer unit, electrically connected with the control register, and the double buffer unit comprises a first buffer and a second buffer; the first buffer enters an accumulation result cache state according to the accumulation result cache signal, while the second buffer enters an accumulation result unload state according to the accumulation result unload signal; or, the second buffer enters an accumulation result cache state according to the accumulation result cache signal, while the first buffer enters an accumulation result unload state according to the accumulation result unload signal; the buffer module further comprises a first data register, electrically connected with an operation unit at an exit of a matrix multiplication acceleration unit, for obtaining and temporarily storing a multiply-add result output by the operation unit; a second data register, electrically connected with the double buffer unit, for obtaining an accumulation result corresponding to a current address of an entry in the first buffer or the second buffer; an adder, a first input terminal of which is electrically connected with the first data register, and a second input terminal of which is electrically connected with the second data register, for adding the multiply-add result in the first data register and the accumulation result in the second data register; a third data register, electrically connected with an output terminal of the adder and the double buffer unit, for obtaining and temporarily storing an accumulation result output by the adder, and the double buffer unit caches the accumulation result in the third data register into the first buffer or the second buffer corresponding to the current address of the entry; a result unload write 0 unit, for unloading and writing 0 to the accumulation result in the first buffer or the second buffer in the accumulation result unload state according to the accumulation result unload signal.
2. The control device of claim 1, wherein: the first control logic unit comprises a buffer determination unit one, for determining that the first buffer or the second buffer enters the accumulation result cache state; a buffer entry start address determination unit one, electrically connected with the buffer determination unit one, for determining a start address of an entry of the first buffer or the second buffer entering the accumulation result cache state; a buffer entry end address determination unit one, electrically connected with the buffer determination unit one, for determining an end address of the entry of the first buffer or the second buffer entering the accumulation result cache state; a buffer entry current address determination unit one, electrically connected with the buffer entry start address determination unit one and the buffer entry end address determination unit one, for determining a current address of the entry of the first buffer or the second buffer.
3. The control device of claim 2, wherein: the second control logic unit comprises A second buffer determination unit is electrically connected with the first buffer determination unit. When the first buffer determination unit determines that the first buffer enters the accumulation result caching state, the second buffer determination unit determines that the second buffer enters the accumulation result unloading state. When the first buffer determination unit determines that the second buffer enters the accumulation result caching state, the second buffer determination unit determines that the first buffer enters the accumulation result unloading state. A second buffer entry start address determination unit is electrically connected with the second buffer determination unit, and is configured to determine the entry start address of the first buffer or the second buffer in the accumulation result unloading state. A second buffer entry end address determination unit is electrically connected with the second buffer determination unit, and is configured to determine the entry end address of the first buffer or the second buffer in the accumulation result unloading state. A second buffer entry current address determination unit is electrically connected with the second buffer entry start address determination unit and the second buffer entry end address determination unit, and is configured to determine the entry current address of the first buffer or the second buffer.
4. A method of controlling an accumulator buffered data accumulation offload, the method comprising: The method comprises the following steps The first control logic unit of the L1 accumulator buffer control logic generates an accumulation result caching signal, and the second control logic unit of the accumulator buffer control logic generates an accumulation result unloading signal; The control register of the L2 buffer module receives and temporarily stores the accumulation result caching signal and the accumulation result unloading signal; The first buffer of the L3 buffer module performs accumulation result caching operation according to the accumulation result caching signal, and the second buffer of the buffer module performs accumulation result unloading operation according to the accumulation result unloading signal; Or, the second buffer of the buffer module performs accumulation result caching operation according to the accumulation result caching signal, and the first buffer of the buffer module performs accumulation result unloading operation according to the accumulation result unloading signal; The L3 specifically comprises The L31 first data register obtains and temporarily stores the multiplication and addition result output by the operation unit at the exit of the matrix multiplication acceleration unit; The L32 adder adds the multiplication and addition result in the first data register and the accumulation result in the second data register; The L33 third data register obtains and temporarily stores the accumulation result output by the adder; The L34 double buffer unit caches the accumulation result in the third data register into the first buffer or the second buffer in the accumulation result caching state and corresponding to the entry current address; The L35 second data register obtains the accumulation result corresponding to the entry current address in the first buffer or the second buffer; The L36 result unloading write 0 unit unloads and writes 0 to the accumulation result in the first buffer or the second buffer in the accumulation result unloading state according to the accumulation result unloading signal.
5. The method of claim 4, wherein: The L1 specifically comprises The L11 first buffer determination unit determines that the first buffer or the second buffer enters the accumulation result caching state; The L12 first buffer entry start address determination unit determines the entry start address of the first buffer or the second buffer in the accumulation result caching state; The L13 first buffer entry end address determination unit determines the entry end address of the first buffer or the second buffer in the accumulation result caching state; L14 The L14 buffer entry current address determination unit determines the entry current address of the first buffer or the second buffer.
6. The method of claim 5, wherein: The L1 further comprises L15 When the L15 buffer determination unit one determines that the first buffer enters the accumulation result cache state, the L15 buffer determination unit two determines that the second buffer enters the accumulation result offload state; when the L15 buffer determination unit one determines that the second buffer enters the accumulation result cache state, the L15 buffer determination unit two determines that the first buffer enters the accumulation result offload state. L16 The L16 buffer entry start address determination unit two determines the entry start address of the first buffer or the second buffer which enters the accumulation result offload state. L17 The L17 buffer entry end address determination unit two determines the entry end address of the first buffer or the second buffer which enters the accumulation result offload state. L18 The L18 buffer entry current address determination unit two determines the entry current address of the first buffer or the second buffer.
Citation Information
Patent Citations
Variable-order pipeline serial multiply-accumulator
CN103699355A
Intelligent acceleration chip suitable for power system edge calculation
CN109947573A