A semiconductor termination structure and a method of fabricating the same

Abstract

This invention provides a semiconductor terminal structure and its fabrication method. The fabrication method includes the following steps: providing a semiconductor structure comprising a substrate, an epitaxial layer, and a trench structure, wherein the trench structure includes a trench, a dielectric layer, and a shielding gate layer; etching the dielectric layer to a predetermined depth of the trench to obtain a gate trench; performing acoustic cleaning on the semiconductor structure after the gate trench is formed, and performing pre-cleaning before batch cleaning; forming a gate dielectric layer on the inner wall and bottom surface of the gate trench; forming a gate conductive layer filling the gate trench in the gate trench; forming an interlayer dielectric layer above the epitaxial layer, forming a contact hole penetrating the interlayer dielectric layer, and the interlayer dielectric layer covering the upper surface of the gate conductive layer. This invention reduces the breakage rate of the shielding gate layer by performing pre-cleaning before batch cleaning during the cleaning process after the gate trench is formed and before the gate dielectric layer is formed, and by selecting an appropriate acoustic cleaning power value based on the cleaning effect.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a semiconductor terminal structure and its preparation method. Background Technology

[0002] As the cell size of shielded trench field-effect transistors (SGTs) shrinks, the width of the source poly in the SGT structure also shrinks accordingly. The structural strength of the small-sized source poly decreases sharply, making it prone to breakage in subsequent processes, thus affecting product yield.

[0003] Currently, during chip probing (CP), random gate-source leakage current (IGSS) failures are observed. Failure analysis (FA) reveals that the short circuit is caused by the conductive plug in the source poly contact of the terminal region connecting to the gate poly layer. Specifically, the conductive plug connecting the shielding gate layer to the gate poly layer short-circuits the source and gate, resulting in a gate-source short circuit. This is exacerbated by the possibility of water rinsing or megasonic wave impact during wafer cleaning before the gate dielectric and gate poly layers pass through the furnace tube, causing the shielding gate layer to fracture and its upper surface to be lower than the upper surface of the epitaxial layer. Figure 1 , Figure 2 and Figure 3 The diagrams shown are cross-sectional views of the shielding gate layer after acoustic cleaning fracture, the gate conductive layer formed after the shielding gate layer fracture, and the contact hole formed after the shielding gate layer fracture. The structure includes a semiconductor structure 01, a substrate 011, an epitaxial layer 012, a trench structure 013, a trench 0131, a dielectric layer 0132, a shielding gate layer 0133, a gate trench 0134, a gate dielectric layer 014, a gate conductive layer 015, an interlayer dielectric layer 02, and a contact hole 021. Because the upper surface of the shielding gate layer is lower than the epitaxial layer, the gate conductive layer deposited above the shielding gate layer cannot be completely etched during etching, resulting in residue. This residue causes the gate conductive layer to connect with the conductive plug filling the shielding gate contact hole in the terminal region, leading to random failure of the gate-source leakage current.

[0004] Therefore, there is an urgent need to find a method for fabricating semiconductor terminal structures that improves the breakage ratio of the shielding gate layer. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor terminal structure and its fabrication method, which solves the problem of severe shielding gate layer breakage caused by cleaning after forming the gate trench in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor terminal structure, comprising the following steps:

[0007] A semiconductor structure is provided, the semiconductor structure including a substrate, an epitaxial layer and a trench structure, the trench structure including a trench, a dielectric layer and a shielding gate layer, the trench being embedded in the upper surface layer of the epitaxial layer, the dielectric layer being located on the inner wall and bottom surface of the trench, the shielding gate layer being located in the trench, and the dielectric layer enclosing the sidewalls and bottom surface of the shielding gate layer;

[0008] The dielectric layer is etched to a predetermined depth of the trench to obtain a gate trench;

[0009] The semiconductor structure after the gate trench is formed is subjected to acoustic cleaning, and a preset number of semiconductor structures are pre-cleaned before the batch cleaning of the semiconductor structure to determine the power value for the batch acoustic cleaning.

[0010] A gate dielectric layer is formed on the inner wall and bottom surface of the gate trench, and a gate conductive layer is formed in the gate trench to fill the gate trench. The gate dielectric layer covers the exposed surface of the shielding gate layer, and the upper surface of the gate conductive layer is lower than the upper surface of the epitaxial layer.

[0011] An interlayer dielectric layer is formed above the epitaxial layer, and a contact hole is formed that penetrates the interlayer dielectric layer and exposes the bottom of the shielding gate layer. The interlayer dielectric layer covers the upper surface of the gate conductive layer.

[0012] Optionally, the acoustic cleaning includes one of ultrasonic acoustic cleaning and mega-sonic acoustic cleaning.

[0013] Optionally, the power range of the acoustic cleaning is 0W to 1200W.

[0014] Optionally, the power values ​​for acoustic cleaning vary depending on the size of the semiconductor structure.

[0015] Optionally, the pre-cleaning includes the steps of setting different power values ​​for the acoustic cleaning multiple times and performing yield improvement scanning on the cleaned semiconductor structure.

[0016] Optionally, the power value of the acoustic cleaning for batch cleaning is selected based on the yield improvement scan results.

[0017] Optionally, the gate dielectric layer also covers the upper surface of the epitaxial layer.

[0018] Optionally, the upper surface of the gate conductive layer is lower than the upper surface of the shielding gate layer.

[0019] Optionally, the bottom of the contact hole extends into the shielded gate layer.

[0020] The present invention also provides a semiconductor terminal structure, which is prepared by the semiconductor terminal structure preparation method described above.

[0021] As described above, the semiconductor terminal structure and its fabrication method of the present invention, after etching the dielectric layer to obtain the gate trench and before forming the gate conductive layer, uses the acoustic cleaning method to clean the semiconductor structure after forming the gate trench. Before batch cleaning, the semiconductor structure undergoes pre-cleaning. The power value of the acoustic cleaning is adjusted multiple times according to the size and material of each batch of devices. After adjusting the power value, a preset number of semiconductor structures are cleaned. Taking into account the curve trends of the number of impurity particles on the cleaned semiconductor structure and the breakage ratio of the shielding gate layer, a suitable acoustic cleaning power value is selected for batch cleaning while ensuring that the semiconductor structure meets the cleaning standard after acoustic cleaning and reducing the breakage ratio of the shielding gate layer. This ensures the effectiveness of the acoustic cleaning, reduces the breakage ratio of the shielding gate layer during the acoustic cleaning process, improves device yield, and reduces production losses and costs. Furthermore, after batch acoustic cleaning with a suitable acoustic cleaning power value, the breakage ratio of the shielding gate layer is reduced by 5%, and the fluctuation of the breakage ratio of the shielding gate layer in each time period is relatively small, demonstrating high industrial application value. Attached Figure Description

[0022] Figure 1 The diagram shows a cross-sectional view of the shielding grid layer after acoustic cleaning, indicating a fracture.

[0023] Figure 2 The diagram shows a cross-sectional view of the conductive layer formed after the shielding gate layer breaks.

[0024] Figure 3 The diagram shows a cross-sectional view of the contact hole formed after the shielding grid layer breaks.

[0025] Figure 4 The diagram shows a process flow chart of the method for fabricating the semiconductor terminal structure of the present invention.

[0026] Figure 5 The diagram shows a cross-sectional view of the semiconductor structure used in the fabrication method of the semiconductor terminal structure of the present invention.

[0027] Figure 6 The diagram shows a cross-sectional view of the semiconductor structure after acoustic cleaning, which is a method for preparing the semiconductor terminal structure of the present invention.

[0028] Figure 7 The diagram shows a cross-sectional structure after the formation of the gate conductive layer, which is a method for fabricating the semiconductor terminal structure of the present invention.

[0029] Figure 8 The diagram shows a cross-sectional structure after the formation of contact holes in the method for fabricating the semiconductor terminal structure of the present invention.

[0030] Figure 9 The graph shows the statistical results of the shielding gate breakage rate of the semiconductor terminal structure fabrication method and the semiconductor terminal structure fabrication method of the present invention.

[0031] Component designation explanation

[0032] 01 Semiconductor Structure

[0033] 011 Substrate

[0034] 012 Epitaxial Layer

[0035] 013 Trench Structure

[0036] 0131 Trench

[0037] 0132 Dielectric layer

[0038] 0133 Shielding Grid Layer

[0039] 0134 Gate Trench

[0040] 014 Gate dielectric layer

[0041] 015 Gate conductive layer

[0042] 02 Interlayer Dielectric Layer

[0043] 021 Shielding grid contact hole

[0044] 1. Semiconductor Structure

[0045] 11 Substrate

[0046] 12 Epitaxial Layers

[0047] 13. Trench Structure

[0048] 131 Trench

[0049] 132 Dielectric Layer

[0050] 133 Shielding Grid Layer

[0051] 134 Gate Trench

[0052] 14 Gate dielectric layer

[0053] 15 Gate conductive layer

[0054] 2 Interlayer dielectric layer

[0055] 21 Contact Hole Detailed Implementation

[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] Please see Figures 4 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0058] Example 1

[0059] This embodiment provides a method for fabricating a semiconductor terminal structure, such as... Figure 4 The diagram shown is a process flow chart of the fabrication method for the semiconductor terminal structure, including the following steps:

[0060] S1: A semiconductor structure is provided, the semiconductor structure including a substrate, an epitaxial layer and a trench structure, the trench structure including a trench, a dielectric layer and a shielding gate layer, the trench being embedded in the upper surface layer of the epitaxial layer, the dielectric layer being located on the inner wall and bottom surface of the trench, the shielding gate layer being located in the trench, and the dielectric layer wrapping the sidewalls and bottom surface of the shielding gate layer;

[0061] S2: Etch the dielectric layer to a predetermined depth of the trench to obtain a gate trench;

[0062] S3: Perform acoustic cleaning on the semiconductor structure after the gate trench is formed, and before performing batch cleaning on the semiconductor structure, perform pre-cleaning on a preset number of semiconductor structures to determine the power value for batch acoustic cleaning;

[0063] S4: A gate dielectric layer is formed on the inner wall and bottom surface of the gate trench, and a gate conductive layer is formed in the gate trench to fill the gate trench. The gate dielectric layer covers the exposed surface of the shielding gate layer, and the upper surface of the gate conductive layer is lower than the upper surface of the epitaxial layer.

[0064] S5: An interlayer dielectric layer is formed above the epitaxial layer, and a contact hole is formed that penetrates the interlayer dielectric layer and exposes the bottom of the shielding gate layer. The interlayer dielectric layer covers the upper surface of the gate conductive layer.

[0065] Please see Figures 5 to 6 The following steps are performed: Step S1, Step S2, and Step S3: A semiconductor structure 1 is provided, the semiconductor structure 1 including a substrate 11, an epitaxial layer 12, and a trench structure 13. The trench structure 13 includes a trench 131, a dielectric layer 132, and a shielding gate layer 133. The trench 131 is embedded in the upper surface of the epitaxial layer 12. The dielectric layer 132 is located on the inner wall and bottom surface of the trench 131. The shielding gate layer 133 is located in the trench 131. The dielectric layer 132 covers the sidewall and bottom surface of the shielding gate layer 133. The dielectric layer 131 is etched to a predetermined depth of the trench 131 to obtain a gate trench 134. The semiconductor structure 1 after forming the gate trench 134 is subjected to acoustic cleaning. Before batch cleaning of the semiconductor structure 1, a predetermined number of semiconductor structures 1 are pre-cleaned to determine the power value for batch acoustic cleaning.

[0066] Specifically, such as Figure 5 The diagram shown is a cross-sectional view of the semiconductor structure 1. The thickness of the semiconductor structure 1 can be selected according to actual conditions, and is not limited here.

[0067] Specifically, the substrate 11 is made of silicon, silicon germanium, silicon carbide, or other suitable semiconductor materials.

[0068] Specifically, while ensuring device performance, the thickness of the substrate 11 can be set according to actual conditions, and is not limited here.

[0069] Specifically, the conductivity type of the epitaxial layer 12 can be P-type or N-type.

[0070] Specifically, while ensuring device performance, the thickness of the epitaxial layer 12 can be set according to actual conditions and is not limited here; the doping concentration of the epitaxial layer 12 can be selected according to actual conditions and is not limited here.

[0071] Specifically, while ensuring device performance, the depth and opening size of the trench 131 can be selected according to the actual situation, and are not limited here.

[0072] Specifically, while ensuring device performance, the thickness of the dielectric layer 132 can be selected according to the actual situation, and is not limited here.

[0073] Specifically, the dielectric layer 132 is made of silicon oxide, silicon nitride, or other suitable high-dielectric materials. In this embodiment, silicon oxide is used as the dielectric layer 132.

[0074] Specifically, the method for forming the gate trench 134 includes dry etching, wet etching, or other suitable methods, i.e., etching the dielectric layer 132.

[0075] Specifically, while ensuring device performance, the depth of the gate trench 134 can be selected according to the actual situation, and is not limited here. The depth here refers to the distance between the bottom surface of the gate trench 134 and the upper surface of the epitaxial layer 12.

[0076] As an example, the acoustic cleaning includes one of ultrasonic acoustic cleaning and mega-sonic acoustic cleaning, or other suitable cleaning methods.

[0077] Specifically, the acoustic cleaning includes the following steps: providing an acoustic cleaning instrument containing cleaning fluid, placing the semiconductor structure after the gate trench 134 is formed in the cleaning fluid; setting the frequency of acoustic cleaning, switching different power values ​​multiple times, and performing acoustic cleaning on a preset number of different batches of the semiconductor structure; and setting an appropriate acoustic cleaning power value based on the cleaning results.

[0078] Specifically, the cleaning solution is a conventional wafer cleaning solution, which can be an aqueous solution composed of sulfuric acid, hydrogen peroxide and deionized water, or other suitable cleaning solutions for removing impurity particles.

[0079] As an example, the power range of the acoustic cleaning is 0W to 1200W.

[0080] Specifically, such as Figure 6 The diagram shows a cross-sectional view of the semiconductor structure 1 after acoustic cleaning. Setting the power value of acoustic cleaning to 0W to 1200W can reduce the intensity of the acoustic waves, weaken the damage of the acoustic waves to the shielding gate layer 133, and greatly reduce the breakage rate of the shielding gate layer 133.

[0081] As an example, the power values ​​for acoustic cleaning of semiconductor structures 1 of different sizes are different, where different sizes refer to different size values ​​within the size range of semiconductor structures 1 that can be cleaned by acoustic waves.

[0082] As an example, the pre-cleaning includes the steps of setting different power values ​​for the acoustic cleaning multiple times and performing a yield improvement scan on the cleaned semiconductor structure 1.

[0083] Specifically, since the size of the shielding gate layer 133 varies depending on the size of the semiconductor structure 1, the acoustic wave resistance of the shielding gate layer 133 also varies. While ensuring device performance, when the size of the semiconductor structure 1 is large, the size of the shielding gate layer 133 is also large, allowing for an appropriate increase in the power value of the acoustic cleaning to enhance the particle removal capability and cleaning effect. Conversely, when the size of the semiconductor terminal device is small, the size of the shielding gate layer 133 is also small, allowing for an appropriate decrease in the power value of the acoustic cleaning to reduce the impact of acoustic waves on the shielding gate layer 133.

[0084] Specifically, for semiconductor structures 1 of the same size but different materials, the power of the acoustic cleaning is different. Since the inherent physical properties of the materials of semiconductor structures 1 are different, the acoustic resistance of the shielding gate layer 133 of the same size is also different. Therefore, the acoustic cleaning power value of semiconductor structures of the same size but different materials can be determined by performing the pre-cleaning based on the inherent physical properties of the materials.

[0085] Specifically, before performing batch cleaning of the semiconductor structure 1, different power values ​​are set multiple times. After each adjustment of the power value of the acoustic cleaning, a preset number of semiconductor structures 1 are pre-cleaned. Then, a yield improvement scan is performed on the cleaned semiconductor structures 1. Based on the scan results, combined with the cleaning effect of the acoustic cleaning and the breakage rate of the shielding gate layer 133 during the acoustic cleaning process, under the condition that the impurity particles on the semiconductor structure 1 after cleaning meet the cleaning standard and the breakage rate of the shielding gate layer 133 is low, a suitable power value for batch cleaning of the acoustic cleaning is selected by comprehensively considering the trend of the statistical curve of the cleaning effect and the breakage ratio of the shielding gate layer 133, so as to reduce the breakage ratio of the shielding gate layer 133.

[0086] Specifically, in order to obtain the optimal power value of the acoustic cleaning, the preset number is not less than 100, so as to avoid the cleaning effect and the breakage ratio of the shielding grid layer 133 being affected by chance.

[0087] Please see again Figures 7 to 9The following steps are performed: Step S3, Step S4, and Step S5: A gate dielectric layer 14 is formed on the inner wall and bottom surface of the gate trench 134; a gate conductive layer 15 is formed in the gate trench 134 to fill the gate trench 134; the gate dielectric layer 14 covers the exposed surface of the shielding gate layer 133; the upper surface of the gate conductive layer 15 is lower than the upper surface of the epitaxial layer 12; an interlayer dielectric layer 2 is formed above the epitaxial layer 12; a contact hole 21 is formed that penetrates the interlayer dielectric layer 2 and exposes the bottom of the shielding gate layer 133; the interlayer dielectric layer 2 covers the upper surface of the gate conductive layer 15.

[0088] As an example, the gate dielectric layer 14 also covers the upper surface of the epitaxial layer 12.

[0089] Specifically, the method for forming the gate dielectric layer 14 includes chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods.

[0090] Specifically, while ensuring device performance, the thickness of the gate dielectric layer 14 can be selected according to the actual situation, and is not limited here.

[0091] As an example, the upper surface of the gate conductive layer 15 is lower than the upper surface of the shielding gate layer 133.

[0092] Specifically, such as Figure 7 The diagram shown is a cross-sectional view of the gate conductive layer 15 after it has been formed. The method for forming the gate conductive layer 15 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0093] Specifically, the gate conductive layer 15 fills the gate trench 134, and the upper surface of the gate conductive layer 15 is lower than the upper surface of the epitaxial layer 12.

[0094] Specifically, the method for forming the interlayer medium layer 2 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0095] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer 2 can be selected according to the actual situation, and is not limited here.

[0096] Specifically, the material of the interlayer dielectric layer 2 includes silicon oxide, silicon nitride, or other suitable dielectric materials.

[0097] As an example, such as Figure 8 The diagram shows a cross-sectional view of the contact hole 21 after it is formed. The bottom of the contact hole 21 extends into the shielding grid layer 133.

[0098] Specifically, while ensuring device performance, the depth to which the contact hole 21 extends into the shielding gate layer 133 can be selected according to actual conditions, and is not limited here. The depth to which it extends into the shielding gate layer 133 refers to the distance between the bottom surface of the contact hole 21 and the upper surface of the shielding gate layer 133.

[0099] Specifically, the method for forming the contact hole 21 includes dry etching, wet etching, or other suitable methods.

[0100] Specifically, while ensuring device performance, the size of the contact hole 21 can be selected according to the actual situation, and is not limited here.

[0101] Specifically, after forming the contact hole 21, the method further includes the step of forming a conductive plug that fills the contact hole 21.

[0102] Specifically, the conductive plug formed is made of one of the following materials: titanium, titanium nitride, silver, gold, copper, aluminum, and tungsten, or other suitable conductive materials.

[0103] Specifically, the method for forming the conductive plug includes one of sputtering, evaporation, chemical vapor deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, or atomic layer deposition, or other suitable methods.

[0104] Specifically, such as Figure 9 The figure shows the statistical results of the shielding gate fracture rate of the semiconductor terminal structure fabrication method and the semiconductor terminal structure fabrication method of the present invention. As can be seen from the figure, when the semiconductor terminal structure is fabricated without using the semiconductor terminal structure fabrication method of the present invention, the fracture rate of the shielding gate layer 133 is relatively high, and the fluctuation range of the fracture ratio of the shielding gate layer 133 is large. After the semiconductor terminal device is fabricated using the fabrication method of the present invention, the fracture rate of the shielding gate layer 133 in the device has decreased significantly, with a decrease of about 5%, and the fluctuation of the fracture ratio of the shielding gate layer 133 in each time period is small.

[0105] The semiconductor terminal structure fabrication method of this embodiment involves a pre-cleaning process during the cleaning process after the formation of the gate trench 134 and before the formation of the gate dielectric layer 14. The power value of the acoustic cleaning is adjusted multiple times, and a predetermined number of semiconductor structures 1 are cleaned after each adjustment. Based on the number of impurity particles on the cleaned semiconductor structures 1 and the breakage ratio of the shielding gate layer 133, and considering both the cleaning effect and the statistical trend of the breakage ratio of the shielding gate layer 133, a suitable power value is selected as the acoustic cleaning power value for batch cleaning. This reduces the breakage ratio of the shielding gate layer 133 and improves the device yield. Furthermore, using the semiconductor terminal structure fabrication method of this invention reduces the breakage ratio of the shielding gate layer 133 by 5%, and the fluctuation of the breakage ratio of the shielding gate layer 133 in each time period is relatively small.

[0106] Example 2

[0107] This embodiment provides a semiconductor terminal structure, such as Figure 8 The diagram shown is a cross-sectional view of the semiconductor terminal structure, which is prepared using the method described in Example 1.

[0108] Specifically, the semiconductor terminal structure includes a semiconductor structure 1, a gate trench 134, a gate dielectric layer 14, a gate conductive layer 15, an interlayer dielectric layer 2, and a contact hole 21. The semiconductor structure includes a substrate 11, an epitaxial layer 12, and a trench structure 13. The trench structure 13 includes a trench 131, a dielectric layer 132, and a shielding gate layer 133. The trench 131 is embedded in the upper surface of the epitaxial layer 12. The dielectric layer is located on the inner wall and bottom surface of the trench 131, and the upper surface of the dielectric layer 132 is lower than the upper surfaces of the epitaxial layer 12 and the shielding gate layer 133. The shielding gate layer 133 is located in the trench 131, and the dielectric layer 132 covers the sidewalls and bottom surface of the shielding gate layer 133. The gate trench 134 is located above the dielectric layer 132, and the bottom surface of the gate trench 134 is the upper surface of the dielectric layer 132. The inner wall of the trench 131 not covered by the dielectric layer 132 and the side wall of the shielding gate layer 133 serve as the side walls of the gate trench 134. The gate dielectric layer 14 covers the inner wall and bottom surface of the gate trench 134. The gate conductive layer 15 fills the gate trench 134, and the gate dielectric layer 14 wraps the side walls and bottom surface of the gate conductive layer 15. The interlayer dielectric layer 2 is located above the epitaxial layer 12, and the interlayer dielectric layer covers the gate conductive layer 15. The contact hole 21 penetrates the interlayer dielectric layer 2 and exposes the shielding gate layer 133 at its bottom.

[0109] Specifically, the gate dielectric layer 14 also covers the upper surface of the epitaxial layer 12.

[0110] Specifically, the gate dielectric layer 14 is made of silicon nitride, silicon oxide, or other suitable dielectric materials. In this embodiment, a silicon oxide layer is used as the gate dielectric layer 14.

[0111] Specifically, the gate conductive layer 15 is made of polycrystalline silicon or other suitable conductive materials.

[0112] Specifically, the semiconductor terminal structure is prepared using the semiconductor terminal structure preparation method described in Example 1. During the cleaning process of the semiconductor structure after the formation of the gate trench 134 and before the formation of the gate conductive layer, the power of the acoustic cleaning is adjusted. Based on the detection structure and the detection results, while ensuring that the impurity particles on the semiconductor structure 1 do not affect the device performance and the breakage rate of the shielding gate layer 133 is low after the acoustic cleaning, the acoustic power of the acoustic cleaning is comprehensively considered to obtain the optimal process effect, ensure the device performance, and improve the device yield.

[0113] The semiconductor terminal structure of this embodiment is prepared by using the semiconductor terminal structure preparation method described in Embodiment 1, which reduces the breakage rate of the shielding gate layer 133 from a process perspective, improves the device yield, and reduces production costs.

[0114] In summary, the semiconductor terminal structure and its fabrication method of the present invention, through acoustic cleaning of the semiconductor structure after the formation of the gate trench and before the formation of the gate dielectric layer, and pre-cleaning before batch cleaning, adjusts the acoustic cleaning power value multiple times according to the size and material of each batch of devices, and cleans a predetermined number of semiconductor structures after adjusting the power value. Based on the proportion of impurity particles and shielding gate layer fracture on the semiconductor structure after adjusting the acoustic cleaning power value, and considering the trend of the statistical curve of the cleaning effect and the shielding gate layer fracture ratio while ensuring the cleaning effect, a suitable acoustic cleaning power value for batch cleaning is selected to reduce the shielding gate layer fracture ratio and improve the device yield. Furthermore, by selecting a suitable acoustic cleaning power value, the shielding gate layer fracture ratio is reduced by 5%, and the fluctuation range of the shielding gate layer fracture ratio in each time period after batch cleaning is reduced. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0115] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor terminal structure, characterized in that, Includes the following steps: A semiconductor structure is provided, the semiconductor structure including a substrate, an epitaxial layer and a trench structure, the trench structure including a trench, a dielectric layer and a shielding gate layer, the trench being embedded in the upper surface layer of the epitaxial layer, the dielectric layer being located on the inner wall and bottom surface of the trench, the shielding gate layer being located in the trench, and the dielectric layer enclosing the sidewalls and bottom surface of the shielding gate layer; The dielectric layer is etched to a predetermined depth of the trench to obtain a gate trench; The semiconductor structure after the gate trench is formed is subjected to acoustic cleaning, and before the semiconductor structure is batch cleaned, a preset number of semiconductor structures are pre-cleaned to determine the power value for batch acoustic cleaning. The pre-cleaning includes setting different acoustic cleaning power values ​​multiple times and performing yield improvement scanning on the cleaned semiconductor structure. The power value of the acoustic cleaning for batch cleaning is selected based on the yield improvement scanning results. A gate dielectric layer is formed on the inner wall and bottom surface of the gate trench, and a gate conductive layer is formed in the gate trench to fill the gate trench. The gate dielectric layer covers the exposed surface of the shielding gate layer, and the upper surface of the gate conductive layer is lower than the upper surface of the epitaxial layer. An interlayer dielectric layer is formed above the epitaxial layer, and a contact hole is formed that penetrates the interlayer dielectric layer and exposes the bottom of the shielding gate layer. The interlayer dielectric layer covers the upper surface of the gate conductive layer.

2. The method for fabricating a semiconductor terminal structure according to claim 1, characterized in that: The acoustic cleaning includes one of ultrasonic acoustic cleaning and mega-sonic acoustic cleaning.

3. The method for fabricating a semiconductor terminal structure according to claim 1, characterized in that: The power range of the acoustic cleaning is 0 W to 1200 W.

4. The method for fabricating a semiconductor terminal structure according to claim 1, characterized in that: The power values ​​for acoustic cleaning vary depending on the size of the semiconductor structure.

5. The method for fabricating a semiconductor terminal structure according to claim 1, characterized in that: The gate dielectric layer also covers the upper surface of the epitaxial layer.

6. The method for fabricating a semiconductor terminal structure according to claim 1, characterized in that: The upper surface of the gate conductive layer is lower than the upper surface of the shielding gate layer.

7. The method for fabricating a semiconductor terminal structure according to claim 1, characterized in that: The bottom of the contact hole extends into the shielded grid layer.

8. A semiconductor terminal structure, characterized in that, The semiconductor terminal structure is fabricated using the method for fabricating a semiconductor terminal structure as described in any one of claims 1 to 7.

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