Module reset circuit, reset module and system on chip reset architecture
By using a module-level reset circuit and an Idle signal mechanism, the problem of low efficiency in SOC chip exception handling is solved, achieving precise module-level reset and reducing performance impact.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING TENAFE ELECTRONIC TECHNOLOGY CO LTD
- Filing Date
- 2022-08-11
- Publication Date
- 2026-05-15
AI Technical Summary
In existing technologies, SOC chips have difficulty determining clear reset boundaries when handling abnormal events, resulting in low efficiency in abnormal handling and limited application scenarios.
A module-level reset circuit is adopted, which generates a module-level reset signal through a signal receiving unit, a signal generating unit, and a processing unit to reset abnormal timing devices individually, and shuts down the clock signal in the same clock domain through the Idle signal to reduce the impact on other modules.
It achieves more precise module-level reset, reduces the number of reset modules, reduces the impact on SOC chip performance, and solves the asynchronous edge propagation problem caused by asynchronous reset.
Smart Images
Figure CN115309248B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of chip technology, and in particular to a module reset circuit, a reset module, and a system-on-a-chip reset architecture. Background Technology
[0002] To handle various abnormal events during operation, related technologies use global reset mechanisms or clock domain-based reset mechanisms to reset the timing devices in the chip. However, based on these reset mechanisms, when an abnormality occurs, it is difficult to determine a clear reset boundary, making it difficult for the firmware to cleanly handle the abnormal event during chip operation. Therefore, the entire chip needs to be reset, resulting in low efficiency of abnormal handling and limited application scenarios of the abnormal handling mechanism.
[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of this disclosure is to provide a module reset circuit, device, storage device, and computer system-on-a-chip reset architecture, which at least to some extent overcomes the problems of low efficiency of exception handling and application scenarios of exception handling mechanisms in related technologies.
[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.
[0006] According to one aspect of this disclosure, a module reset circuit is provided, comprising: a signal receiving unit for receiving a reset configuration signal for an abnormal timing device in a functional module and outputting a corresponding trigger signal; a first signal generating unit electrically connected to the signal receiving unit for generating an idle signal based on the trigger signal, the idle signal being used to configure a shutdown signal, the shutdown signal being used to shut down the clock signal of the abnormal timing device and other clock signals within the same clock domain as the clock signal of the abnormal timing device; a second signal generating unit electrically connected to the signal receiving unit for generating a reset enable signal based on the trigger signal; and a calculation unit electrically connected to the second signal generating unit for performing calculations based on the reset enable signal and generating a functional module-based reset signal based on the calculation result, the functional module-based reset signal being used to reset the abnormal timing device in the functional module.
[0007] In one embodiment of this disclosure, the signal receiving unit includes: a synchronization pulse generator for receiving the reset configuration signal and configuring the reset configuration signal as a synchronization pulse; and a counter electrically connected to the synchronization pulse generator for counting based on the synchronization pulse and outputting the trigger signal when the count value reaches a threshold.
[0008] In one embodiment of this disclosure, the first signal generation unit includes an Idle signal generator, which is electrically connected to the counter and is used to output the Idle signal based on the trigger signal, wherein the shutdown signal is configured when the Idle signal is in a high-level state.
[0009] In one embodiment of this disclosure, the second signal generation unit includes a reset signal generator, which is electrically connected to the counter and is used to output the reset enable signal based on the trigger signal.
[0010] In one embodiment of this disclosure, the arithmetic unit includes an AND gate, which is used to perform an AND operation on the reset enable signal and the received clock-based reset signal to generate the functional module-based reset signal based on the operation result. When the functional module-based reset signal is in a low-level state, the abnormal timing device performs a reset operation.
[0011] In one embodiment of this disclosure, it further includes: a synchronous reset unit, electrically connected to the reset signal generator or the logic AND gate, for receiving the reset enable signal and clock signals of other clock domains in the functional module, and generating reset signals for timing devices in other clock domains in the functional module based on the reset enable signal and the clock signals of the clock domains.
[0012] In one embodiment of this disclosure, the reset configuration signal includes a first reset configuration signal and a second reset configuration signal, wherein the first reset configuration signal is used to reset the logic flip-flop and the configurable flip-flop; and the second reset configuration signal is used to reset the logic flip-flop.
[0013] According to another aspect of this disclosure, a reset module is provided, comprising: a module reset circuit as described in any of the preceding embodiments, the module reset circuit including a first signal generation unit for generating an idle signal; and a clock and reset management module electrically connected to the module reset circuit for receiving the idle signal and generating a shutdown signal based on the idle signal, the shutdown signal being used to shut down the clock signal of the abnormal timing device.
[0014] In one embodiment of this disclosure, the clock and reset management module is further configured to: input a clock-based reset signal to the module reset circuit; the module reset circuit further includes an arithmetic unit, the arithmetic unit including a logic AND gate, the logic AND gate being configured to perform an AND operation on the reset enable signal and the received clock-based reset signal to generate a module-based reset signal based on the operation result, wherein when the module-based reset signal is in a low-level state, the abnormal timing device performs a reset operation.
[0015] According to another aspect of this disclosure, a system-on-a-chip reset architecture is provided, comprising: a bus; a plurality of processors electrically connected to the system bus; and a reset module as described in the above embodiments, electrically connected to the plurality of processors via the system bus.
[0016] In one embodiment of this disclosure, a bus timeout protection module is disposed on the system bus and electrically connected to the functional module. The bus timeout protection module is used to generate a false response signal and send the false response signal to the processor when no response is received from the functional module within a preset time period.
[0017] In one embodiment of this disclosure, the bus includes an AHB bus and an AXI bus; the bus timeout protection module includes an AHB bus timeout protection module and an AXI bus timeout protection module.
[0018] The address mapping table processing scheme provided in the embodiments of this disclosure generates a reset enable signal input to the timing device by setting a module-level reset circuit. The module-level reset mechanism is executed based on the module-level reset circuit. The module-level reset mechanism can reset abnormal timing devices in the module individually. Compared with the traditional clock-based reset mechanism, it can reduce the number of reset modules during abnormal handling and reset the abnormal module more accurately, thereby helping to reduce the impact of reset operation on the performance of the SOC chip.
[0019] In addition, by setting up a module reset circuit and configuring a shutdown signal based on the Idle signal, all clock signals synchronized with the clock of this functional module are turned off during the module-level reset signal transition. This helps to solve the problem of asynchronous edge propagation caused by the asynchronous reset of some circuits in the synchronous clock domain, thus avoiding negative impacts on the timing convergence of complex SOC chips.
[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0022] Figure 1 This illustration shows a schematic diagram of the architecture of a system-on-a-chip (SoC) according to an embodiment of the present disclosure.
[0023] Figure 2 A schematic block diagram of a module reset circuit according to an embodiment of the present disclosure is shown;
[0024] Figure 3 A circuit diagram of a module reset circuit according to an embodiment of this disclosure is shown;
[0025] Figure 4 This diagram illustrates the timing signals in the module reset circuit of an embodiment of the present disclosure.
[0026] Figure 5 This diagram illustrates a reset module according to an embodiment of the present disclosure;
[0027] Figure 6 This diagram shows a circuit schematic of a reset module according to an embodiment of the present disclosure;
[0028] Figure 7 This diagram illustrates a reset architecture for a system-on-a-chip (SoC) according to an embodiment of the present disclosure. Detailed Implementation
[0029] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0030] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0031] To facilitate understanding, the following is an explanation of several terms used in this application.
[0032] SoC (System on Chip): is an integrated circuit with a specific purpose that contains a complete system and all embedded software.
[0033] AHB (Advanced High-performance Bus): An advanced high-performance bus, which is a type of bus interface.
[0034] AXI (Advanced eXtensible Interface): An advanced eXtensible interface, which is an on-chip bus designed for high performance, high bandwidth, and low latency.
[0035] System bus: It includes three different buses: data bus (DB), address bus (AB), and control bus (CB).
[0036] Clock domain: refers to the area in a circuit that is controlled by the same clock signal. Only one clock signal can exist in a clock domain.
[0037] A Finite State Machine (FSM) is a mathematical model that represents a finite number of states and the behaviors such as transitions and actions between these states.
[0038] The solutions provided in this application involve technologies such as storage, which are specifically illustrated through the following embodiments.
[0039] Figure 1 A schematic block diagram of a SOC chip system according to an embodiment of the present disclosure is shown.
[0040] like Figure 1 The SOC chip system shown may include: a system bus (including AXI and AHB), multiple CPUs (such as CPU0, CPU1 and CPU2), multiple functional modules (such as functional module 1 and functional module 2), and a clock and reset management module. The clock and reset management module is used to input clock signals (such as clk0 and clk1) and clock-based reset signals (such as clk0_reset and clk1_reset) to the functional modules. When functional module 1 malfunctions, it needs to be reset based on the clock domain of clk0. This reset method causes functional module 2 to also need to be reset.
[0041] In order to achieve a reset for a specific functional module, Figure 2A schematic block diagram of a module reset circuit according to an embodiment of this disclosure is shown.
[0042] like Figure 2 As shown, the module reset circuit 200 according to an embodiment of this disclosure specifically includes:
[0043] The signal receiving unit 202 is used to receive the reset configuration signal for the abnormal timing device in the functional module and output the corresponding trigger signal.
[0044] The reset configuration signal for abnormal timing devices in the functional module can be a reset configuration signal sent by the processor. When an abnormal timing device is detected, the processor inputs the reset configuration signal to the signal receiving module that resets the abnormal timing device, and processes the reset configuration signal accordingly to obtain a trigger signal.
[0045] In addition, taking SOC chips as an example, based on different functions, functional modules can include power management modules, communication modules, computing modules, etc. Taking the digital circuit module in the computing module as an example, the timing devices mainly include registers and combinational logic circuits.
[0046] The first signal generation unit 204 is electrically connected to the signal receiving unit 202 and is used to generate an idle signal based on a trigger signal. The idle signal is used to configure a shutdown signal, which is used to shut down the clock signal of the abnormal timing device and other clock signals that are in the same clock domain as the clock signal of the abnormal timing device.
[0047] The first signal generation unit 204 is used to generate an Idle signal based on the received trigger signal. The Idle signal is specifically a state signal that switches from a low level to a high level. By outputting the Idle signal to the clock signal management module, specifically the clock and reset management module, the management module controls the shutdown of the clock signal of the abnormal timing device and other clock signals in the same clock domain as the clock signal of the abnormal timing device, that is, all clock signals in this clock domain. In this way, the clock signals of other functional modules in the same clock domain as this functional module can be shut down. Since no clock signal is transmitted to other functional modules, even if other functional modules receive asynchronous signals, there will be no problem, thus avoiding additional timing convergence burden on the SOC chip.
[0048] The second signal generation unit 206 is electrically connected to the signal receiving unit 202 and is used to generate a reset enable signal based on the trigger signal.
[0049] The second signal generation unit 206 generates a corresponding operation unit 208 based on the received trigger signal. The operation unit 208 is electrically connected to the second signal generation unit 206 and is used to perform operations based on the reset enable signal. Based on the operation result, a reset signal based on the functional module is generated. The reset signal based on the functional module is used to reset the abnormal timing device in the functional module.
[0050] As will be understood by those skilled in the art, the number of the units mentioned above, except for the first signal generation unit that generates the Idle signal, can correspond to the number of groups of timing devices that need to be recovered. For example, if the functional module has two groups of timing devices, then it has two signal receiving units, two second signal generation units, and two arithmetic units.
[0051] In this embodiment, by setting up a module-level reset circuit, a reset enable signal is generated and input to the timing device. The module-level reset mechanism is executed based on the module-level reset circuit. The module-level reset mechanism can reset abnormal timing devices in the module individually. Compared with the traditional clock-based reset mechanism, it can reduce the number of reset modules during abnormal handling and reset the abnormal module more accurately, thereby helping to reduce the impact of reset operation on the performance of the SOC chip.
[0052] In addition, by setting up a module reset circuit and configuring a shutdown signal based on the Idle signal, all clock signals synchronized with the clock of this functional module are turned off during the module-level reset signal transition. This helps to solve the problem of asynchronous edge propagation caused by the asynchronous reset of some circuits in the synchronous clock domain, thus avoiding negative impacts on the timing convergence of complex SOC chips.
[0053] like Figure 3 As shown, in one embodiment of this disclosure, the signal receiving unit 202 includes:
[0054] The SYNC_PULSE synchronous pulse generator is used to receive the reset configuration signal and configure the reset configuration signal as a synchronous pulse.
[0055] The SYNC_PULSE synchronous pulse generator is used to ensure that the transmit and receive ends of the reset circuit can maintain consistency.
[0056] The counters (RST1_OP_CNT and RST2_OP_CNT) are electrically connected to the synchronization pulse generator and are used to count based on the synchronization pulse. When the count value reaches the threshold, a trigger signal is output.
[0057] Among them, such as Figure 3As shown, the counter is also used to receive the external input counting threshold gate_thrsh. By counting the synchronization pulses, when the detected technical value reaches the counting threshold, the corresponding trigger signal is output to trigger the execution of the reset operation.
[0058] In this embodiment, configuring a synchronization pulse generator and a counter in the signal receiving module helps to ensure the timeliness and reliability of the trigger signal output by the signal receiving unit.
[0059] like Figure 3 As shown, in one embodiment of this disclosure, the first signal generation unit includes an Idle signal generator Idle gen, which is electrically connected to a counter and is used to output an Idle signal based on a trigger signal, wherein a shutdown signal is configured when the Idle signal is in a high-level state.
[0060] Specifically, the Idle signal generator is a device that can pull a low level high.
[0061] In this embodiment, an Idle signal generator is configured to generate a high-level Idle signal in response to a trigger signal. The Idle signal is then input into a management module for managing functional modules, so that the management module generates a clock signal to disable the clock signal in the synchronous clock domain based on the Idle signal, thereby preventing asynchronous edge propagation caused by asynchronous reset of some circuits.
[0062] Specifically, when the reset operation is in an active or wireless state, other clocks in the same clock domain are disabled based on the shutdown signal. This makes it easy for the SOC to disable the reset timing without additional cost. As a preferred implementation, a clock and reset management module connected to the module reset circuit can be used to generate a shutdown signal based on the Idle signal, so as to disable other clocks in the same clock domain based on the shutdown signal.
[0063] like Figure 3 As shown, in one embodiment of this disclosure, the second signal generation unit includes a reset signal generator (Rst1_n_vld gen and Rst2_n_vld gen), which generates corresponding reset enable signals based on different trigger signals. The reset signal generator is electrically connected to the counter and is used to output the reset enable signal based on the trigger signal.
[0064] In this embodiment, by setting a reset signal generator as the second signal generation unit, the reset enable signal generated by the reset signal generator can ensure the specificity of the reset of abnormal timing devices, so as to reduce the impact of the reset operation of this functional module on other functional modules.
[0065] like Figure 3As shown, in one embodiment of this disclosure, the arithmetic unit includes a first logic AND gate AND1. The first logic AND gate AND1 is used to perform an AND operation on a reset enable signal and a received clock-based reset signal to generate a function module-based reset signal based on the operation result. When the function module-based reset signal is in a low-level state, the abnormal timing device performs a reset operation.
[0066] In this embodiment, by setting a first logic AND gate, the reset enable signal and the received clock-based reset signal can be ANDed. In this way, when both signals indicate a reset, a functional module-based reset signal is obtained. The functional module-based reset signal can ensure that the timing devices in the module are reset, so that it is not necessary to reset multiple functional modules in the same clock domain. Furthermore, based on the reset signal, the timing devices can be returned from an erroneous state to a normal state.
[0067] In one embodiment of this disclosure, it further includes: a synchronous reset unit electrically connected to a reset signal generator or a logic AND gate, for receiving a reset enable signal and clock signals from other clock domains in the functional module, and generating reset signals for timing devices in other clock domains in the functional module based on the reset enable signal and the clock signals from the clock domains.
[0068] like Figure 3 As shown, the synchronous reset unit includes a synchronous reset processor SYNC_RESET and a second logic AND gate AND2. The synchronous reset processor SYNC_RESET receives the reset enable signal output by the reset signal generator and the clock signal of the corresponding clock domain. Based on the reset enable signal and the clock signal of the corresponding clock domain, it can generate the corresponding reset enable signal for the functional module using other clock domains. Combined with the input clock-based reset signal i_clka_rstn[], it realizes the reset of the timing device driven by the i_clka[] clock signal, thereby realizing the reset of the timing device in the entire functional module.
[0069] The numbers in brackets [] represent the number of clock signals belonging to different clock domains.
[0070] like Figure 3 As shown, in one embodiment of this disclosure, the reset configuration signal includes a first reset configuration signal i_sft_rst1_n and a second reset configuration signal i_sft_rst2_n. The first reset configuration signal is used to reset the logic flip-flop and the configurable flip-flop; the second reset configuration signal is used to reset the logic flip-flop.
[0071] In this embodiment, two reset configuration signals are input. The first reset configuration signal is used to generate a module-based reset signal o_clk_csr_rstn to reset all logic triggers and configuration triggers within the block. The second reset configuration signal is used to generate a module-based reset signal o_clk_rstn to reset all logic triggers within the block. Since resetting configurable triggers requires the processor to re-execute initialization, the reset sequence of configurable triggers is relatively long and time-consuming. Therefore, it can be determined whether to reset configurable triggers based on the operating conditions. If only logic triggers need to be reset, only the first reset configuration signal needs to be input. If all logic triggers and configuration triggers need to be reset, both the first and second reset configuration signals need to be input.
[0072] like Figure 4 As shown, a reset module according to an embodiment of the present disclosure includes: a module reset circuit 200 as described in any of the above embodiments, the module reset circuit including a first signal generation unit 204, the first signal generation unit being used to generate an idle signal.
[0073] The clock and reset management module 300 is electrically connected to the module reset circuit 200. It is used to receive the Idle signal and generate a shutdown signal based on the Idle signal. The shutdown signal is used to shut down the clock signal of the abnormal timing device.
[0074] The clock and reset management module 300 is responsible for generating clock signals and clock-based reset signals for each module.
[0075] The clock and reset management module 300 is used to generate clock-based resets. Assuming that the functional module 400 has two clock signals clk0 and clk1, two clock reset signals are required. That is, the clk0_rstn signal is used to manage the reset of timing devices under clk0, and the clk1_rstn signal is used to manage the reset of all timing units under clk1.
[0076] By setting up the module reset circuit 200, combined with the clock-based reset signal sent by the clock and reset management module 300, module-level reset can be achieved. This means that regardless of whether it is clock0 or clock1, as long as they belong to the same functional module, they can be reset.
[0077] Furthermore, by inputting this signal to the clock and reset management module, the clock and reset management module can disable the clock signal i_clk based on the l2_idle signal.
[0078] In this embodiment, by setting up a module-level reset circuit and a clock and reset management module, a reset enable signal is generated and input to the timing device. The module-level reset mechanism is executed based on the module-level reset circuit. The module-level reset mechanism can reset abnormal timing devices in the module individually. Compared with the traditional clock-based reset mechanism, it can reduce the number of reset modules during abnormal handling and reset the abnormal module more accurately, thereby helping to reduce the impact of reset operation on the performance of the SOC chip.
[0079] In addition, by setting up a module reset circuit, the Idle signal is sent to the clock and reset management module, which then configures the clock signal to turn off. This means that during the module-level reset signal transition, all clock signals synchronized with the clock of this functional module are turned off. This helps to solve the problem of asynchronous edge propagation caused by the asynchronous reset of some circuits in the synchronous clock domain, thus avoiding any negative impact on the timing convergence of complex SOC chips.
[0080] In one embodiment of this disclosure, the clock and reset management module 300 is further configured to: input a clock-based reset signal to the module reset circuit; the module reset circuit further includes an arithmetic unit, the arithmetic unit including a logic AND gate, the logic AND gate being configured to perform an AND operation on the reset enable signal and the received clock-based reset signal to generate a module-based reset signal based on the operation result, wherein when the module-based reset signal is in a low-level state, the abnormal timing device performs a reset operation.
[0081] Specifically, the timing devices in the module are reset through the coordinated operation between the clock and reset management module and the reset circuit.
[0082] like Figure 5 As shown, the clock and reset management module 300 includes multiple FSM state machines, such as FSM state machine 1, FSM state machine 2 and FSM state machine 3. Based on each FSM state machine and the corresponding logic operation circuit, it outputs a clock signal in a clock domain and a clock-based recovery signal.
[0083] Based on the management characteristics of the clock and reset module 300, it can manage the reset signals of all functional modules.
[0084] like Figure 5As shown, FSM state machine 1 outputs clock signal o_clk1 and clock-based recovery signal o_clk_1_rstn, FSM state machine 2 outputs clock signal o_clk2 and clock-based recovery signal o_clk_2_rstn, and FSM state machine 3 outputs clock signal o_clk3 and clock-based recovery signal o_clk_3_rstn. o_clk1 is used to drive CSR flip-flop 406, o_clk2 is used to drive first logic flip-flop 402, and o_clk3 is used to drive second logic flip-flop 404.
[0085] When a reset is required due to an abnormal phenomenon, the module reset circuit 200 sends an o_Idle signal to the clock and reset module 300. Based on the recovery signals o_clk_1_rstn, o_clk_2_rstn, and o_clk_3_rstn, combined with the module-based reset signal generated by the module reset circuit 200, all other clocks in the same clock domain can be stopped, and the reset signal can be pulled low to reset the flip-flops of the entire functional module.
[0086] like Figure 6 As shown, the clock and reset management module i_clk is the clock signal input to the functional module. The reset circuit receives the reset configuration signal i_sft_rst1_n sent by the processor, pulls the Idle signal o_Idle high, and sends the high Idle signal to the clock and reset management module. Figure 6 As can be seen from the indicator line from o_Idle to i_clk, the clock and reset management module turns off the clock signal i_clk in advance based on the Idle signal, that is, i_clk enters a low level state, and inputs i_clk_l_rstn to the module reset circuit. The sft_rst1_n_vld and i_clk_l_rstn are ANDed to obtain the low-level active reset signals o_clk_csr_rstn and o_clk_rstn, thereby resetting the logic flip-flops and configurable flip-flops in the functional module.
[0087] like Figure 7 As shown, a system-on-a-chip reset architecture according to an embodiment of this disclosure includes:
[0088] The bus is electrically connected to multiple processors (CPUs).
[0089] Specifically, the CPU communicates with other blocks only through the system bus (AHB or AXI). Through AHB and AXI, the system bus and the CPU can be isolated from other blocks.
[0090] The reset module in the above embodiment is electrically connected to multiple processors via a bus.
[0091] like Figure 7 As shown, the clock and reset management module can provide clock-based reset signals Clk0_reset and Clk1_reset (i.e. o_clk_1_rstn mentioned above) in different clock domains. For the module-level reset circuits in different functional modules 1 and 2, Clk0_reset and Clk1_reset can be received respectively.
[0092] In this disclosure, by setting a reset module, the reset function of the system-on-a-chip (SoC) can be realized on a module-by-module basis.
[0093] In one embodiment of this disclosure, a bus timeout protection module is disposed on the bus and electrically connected to the functional module. The bus timeout protection module is used to generate a false response signal and send the false response signal to the processor when no response is received from the functional module within a preset time.
[0094] In this context, a false response signal can be understood as a response signal output by a non-functional module to respond to processor instructions.
[0095] In this embodiment, the architecture of the system-on-a-chip (SoC) chip includes a CPU, a system bus, and functional modules. If a problem occurs on the system bus, it will affect all CPUs in the chip. By setting a bus timeout protection module, the module reset circuit in the bus timeout protection module domain reset module is electrically connected to wait for the response from the functional module. If no response is received within a specified time, a false response can be generated so that the CPU does not wait for a response indefinitely, thus ensuring that the CPU can be in a normal working state. By isolating the bus timeout protection module from the system bus, it can be ensured that the abnormal module will not affect the system bus and CPU, thereby reducing the impact of abnormal handling on performance.
[0096] like Figure 7 As shown, in one embodiment of this disclosure, the bus includes an AHB bus and an AXI bus.
[0097] The bus timeout protection module includes the AHB bus timeout protection module and the AXI bus timeout protection module.
[0098] like Figure 7 As shown, AHB TO is the AHB bus timeout protection module. When the AHB operation exceeds the set time and is not completed, AHB TO can replace the AHB slave device to complete the AHB operation, so that the CPU can normally end the current AHB operation.
[0099] like Figure 7As shown, AXI TO is the AXI bus timeout protection module. When the AXI operation (including the operation of 5 AXI channels) is not completed within the set time, AXI TO can replace the AXI slave device to complete the current AXI operation, so that the CPU can end the current AXI operation normally.
[0100] As a specific implementation, the clock and reset management module is responsible for generating two reset signals, which can reset the logic flip-flops in the functional module, or reset the logic flip-flops and configurable flip-flops in the module.
[0101] In this embodiment, the bus protection function and module-level reset mechanism are new solutions that ensure that abnormal modules will not affect the system bus and CPU. Furthermore, the module-level reset mechanism can accurately reset abnormal modules, thereby reducing the impact of exception handling on performance.
[0102] like Figure 7 As shown, the reset architecture of the SOC based on this disclosure can achieve the following functions:
[0103] (1) Generate a global reset signal based on the clock and reset management module, and provide clock domain base reset function and chip-level global reset function.
[0104] Specifically, by providing clock domain base reset and chip-level global reset functions, the chip-level global reset clarifies intermediate states and many necessary configurations. While this incurs a higher reset cost, the advantage is that a global reset provides a clear state and easily ensures that the silicon can return to its initial power-boot state. Clock domain base reset can provide cross-block reset, ensuring all flip-flops have the same clock.
[0105] (2) System bus timeout mechanism.
[0106] like Figure 7 As shown, by setting the bus timeout protection modules AHB TO and AXI TO, the impact of module-level errors on the system bus and CPU can be isolated. Without this mechanism, module-level errors are likely to cause the system bus or CPU to hang, thus preventing the CPU from having the opportunity to pull the module back to normal.
[0107] (3) Provide a separate reset mechanism for each CPU core.
[0108] like Figure 7 As shown, different CPU reset signals are generated through the clock and reset management module. Each CPU core provides a rate reset mechanism. Through this mechanism, as long as one CPU core of the SOC chip is active, the SOC will be able to pull the CPU core back from an abnormal state.
[0109] (4) Module-level reset mechanism.
[0110] By combining a module-level reset circuit and a clock and reset management module, a module-level reset mechanism is implemented. This mechanism ensures that resets maintain clear reset boundaries, providing a method to minimize the impact when firmware is reset due to error handling. The module-level reset scheme in this disclosure provides two reset methods: the first resets only the logic flip-flops within the module, and the second resets both logic flip-flops and configurable flip-flops within the reset block.
[0111] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”
[0112] The module reset circuit, reset module, and on-chip system-on-a-chip reset architecture provided in this disclosure generate reset enable signals for timing devices by setting up module-level reset circuits. The module-level reset mechanism is executed based on the module-level reset circuit. The module-level reset mechanism can reset abnormal timing devices in the module individually. Compared with the traditional clock-based reset mechanism, it can reduce the number of reset modules during abnormal handling and reset the abnormal module more accurately, thereby helping to reduce the impact of reset operation on the performance of the SOC chip.
[0113] In addition, by setting up a module reset circuit and configuring a shutdown signal based on the Idle signal, all clock signals synchronized with the clock of this functional module are turned off during the module-level reset signal transition. This helps to solve the problem of asynchronous edge propagation caused by the asynchronous reset of some circuits in the synchronous clock domain, thus avoiding negative impacts on the timing convergence of complex SOC chips.
[0114] In this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can mean a fixed connection, a detachable connection, or an integral connection; "link" can mean a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0115] In the description of this application, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0116] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0117] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
[0118] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A module reset circuit, characterized in that, include: The signal receiving unit is used to receive reset configuration signals for abnormal timing devices in the functional module and output corresponding trigger signals; The first signal generation unit is electrically connected to the signal receiving unit and is used to generate an idle signal based on the trigger signal. The idle signal is used to configure a shutdown signal, which is used to shut down the clock signal of the abnormal timing device and other clock signals that are in the same clock domain as the clock signal of the abnormal timing device. The second signal generation unit is electrically connected to the signal receiving unit and is used to generate a reset enable signal based on the trigger signal. The arithmetic unit, electrically connected to the second signal generation unit, is used to perform calculations based on the reset enable signal and generate a reset signal based on the functional module based on the calculation result. The reset signal based on the functional module is used to reset abnormal timing devices in the functional module.
2. The module reset circuit according to claim 1, characterized in that, The signal receiving unit includes: A synchronization pulse generator is used to receive the reset configuration signal and configure the reset configuration signal as a synchronization pulse. A counter, electrically connected to the synchronization pulse generator, is used to count based on the synchronization pulse and output the trigger signal when the count value reaches a threshold.
3. The module reset circuit according to claim 2, characterized in that, The first signal generation unit includes an Idle signal generator, which is electrically connected to the counter and is used to output the Idle signal based on the trigger signal. The shutdown signal is configured when the Idle signal is in a high-level state.
4. The module reset circuit according to claim 2, characterized in that, The second signal generation unit includes a reset signal generator, which is electrically connected to the counter and is used to output the reset enable signal based on the trigger signal.
5. The module reset circuit according to claim 4, characterized in that, The arithmetic unit includes logic AND gates. The logic AND gate is used to perform a bitwise AND operation on the reset enable signal and the received clock-based reset signal, and to generate the functional module-based reset signal based on the operation result. When the reset signal based on the functional module is in a low-level state, the abnormal timing device performs a reset operation.
6. The module reset circuit according to claim 5, characterized in that, Also includes: A synchronous reset unit, electrically connected to the reset signal generator or the logic AND gate, is used to receive the reset enable signal and the clock signals of other clock domains in the functional module, and to generate reset signals for the timing devices of other clock domains in the functional module based on the reset enable signal and the clock signals of the clock domains.
7. A reset module, characterized in that, include: The module reset circuit as described in any one of claims 1 to 6, the module reset circuit includes a first signal generation unit, the first signal generation unit being used to generate an idle signal; The clock and reset management module is electrically connected to the module reset circuit and is used to receive the Idle signal and generate a shutdown signal based on the Idle signal. The shutdown signal is used to shut down the clock signal of the abnormal timing device.
8. The reset module according to claim 7, characterized in that, The clock and reset management module is also used to: input a clock-based reset signal to the module's reset circuit; The module reset circuit further includes an arithmetic unit, which includes an AND gate. The AND gate is used to perform an AND operation on the reset enable signal and the received clock-based reset signal to generate a module-based reset signal based on the operation result. When the reset signal based on the module is in a low-level state, the abnormal timing device performs a reset operation.
9. A system-on-a-chip reset architecture, characterized in that, include: System bus; Multiple processors are electrically connected to the system bus; The reset module as described in claim 7 or 8 is electrically connected to the plurality of processors via the system bus.
10. The on-chip system-on-a-chip reset architecture according to claim 9, characterized in that, A bus timeout protection module is installed on the system bus and electrically connected to the functional module. The bus timeout protection module is used to generate a false response signal and send the false response signal to the processor when no response is received from the functional module within a preset time.