Serial port adaptive switching circuit and communication equipment

Abstract

The present invention provides a serial port adaptive switching circuit and communication equipment, including: a first conversion branch adopts a first conversion chip to convert a first differential pair signal and then outputs it through a first three-state gate circuit; a second conversion branch adopts a second conversion chip to convert a second differential pair signal and then outputs it, and a second / third three-state gate circuit controls the input and output enable of the second chip according to the input signal of the second conversion chip; a third conversion branch adopts a third conversion chip to convert the signal, and receives and sends it through the negative leads of two differential signal pairs; a three-input AND gate circuit performs a logical operation on the outputs of the three conversion branches and then outputs it to a controller, and the controller outputs a signal to the second / third conversion chip. The serial port adaptive switching circuit provided by the present invention can adaptively realize the switching of the serial port according to the enable signal, and can be applicable to a variety of serial port communication protocols by using two sets of differential pair leads to form an external interface.

Description

Technical Field

[0001] The present invention relates to the technical field of serial port communication, and in particular to a serial port adaptive switching circuit and communication equipment. Background Art

[0002] Due to differences in the application environment and the differences in the interface planning of products by various equipment manufacturers, on-site installation and debugging personnel must change the communication medium mode of the serial port according to the actual situation. The equipment shipped by equipment manufacturers on the market has a variety of optional interfaces. For example, the equipment shipped can choose 1 or 2 of RS-232, RS-422, and RS-485. If another communication interface is changed or added on the basis of an already installed interface device, the staff will need to replace the device with the corresponding interface; while wasting manpower and material resources, it also increases the difficulty and risk of debugging new equipment. Even if the product supports RS-232, RS-422, and RS-485 interfaces at the same time, the circuit is often designed separately on the motherboard, and the external interface is output separately, and 3 sets of independent UART buses need to be migrated from the MCU / CPU end. Not only is the cost high, but the structure is also complex, and the connectors used in the interface are relatively large, resulting in a larger case size. It is not conducive to the evolution of products towards miniaturization and low cost. Summary of the invention

[0003] The serial port adaptive switching circuit provided by the present invention can adaptively realize the switching of the serial port according to the enable signal, and adopts two groups of differential pair leads to form an external interface, which can be applicable to various serial port communication protocols.

[0004] In a first aspect, the present invention provides a serial port adaptive switching circuit, characterized in that it includes:

[0005] The first conversion branch comprises a first differential pair lead, a first conversion chip and a first tri-state gate circuit, wherein the first differential pair lead is used to connect the first data transceiver device to the first conversion chip; the first conversion chip is connected to the first tri-state gate circuit, and the first conversion chip is used to convert the first differential pair signal output by the first data transceiver device via the first differential pair lead into a first logic level signal, and the first logic level signal is output after being subjected to a logic operation by the first tri-state gate circuit;

[0006] The second conversion branch has a second differential pair lead, a second conversion chip, a second tri-state gate circuit and a third tri-state gate circuit; the second differential pair lead is used to connect the first data transceiver device with the second conversion chip, and the second conversion chip is connected with the second tri-state gate circuit and the third tri-state gate circuit; the second conversion chip is also used to connect the second data transceiver device, the second conversion chip is used to convert the second differential pair signal output by the first data transceiver device through the second differential pair lead into a second logic level signal and output it to the second data transceiver device, and convert the third logic level signal sent by the second data transceiver device into a second differential pair signal and output it to the second differential pair lead, the second tri-state gate circuit enables the output pin of the second conversion chip according to the third logic level signal, and the third tri-state gate circuit enables the input pin of the second conversion chip according to the third logic level signal;

[0007] The third conversion branch has a third conversion chip and a fourth three-state gate circuit. The third conversion chip is connected to the first differential pair lead and the negative lead of the second differential pair lead. The third conversion chip is also connected to the fourth three-state gate circuit. The third conversion chip is also used to connect to the second data transceiver device. The third conversion chip converts the negative lead signal output by the first data transceiver device through the negative lead of the first differential pair lead into a fourth logic level signal. The fourth logic level signal is output after logic operation by the fourth three-state gate circuit. The third conversion chip converts the third logic level signal sent by the second data transceiver device into a serial port level signal and sends it to the negative lead of the second differential pair lead.

[0008] A three-input AND gate circuit is respectively connected to the first three-state gate circuit, the second conversion chip and the fourth three-state gate circuit, and the three-input AND gate circuit is also used to connect to the second data transceiver device; the three-input AND gate circuit receives the output signals of the first three-state gate circuit, the second conversion chip and the fourth three-state gate circuit, performs an AND operation and then outputs them to the second data transceiver device;

[0009] The control circuit is respectively connected to the first three-state gate circuit, the second three-state gate circuit, the third three-state gate circuit, the fourth three-state gate circuit, the first conversion chip and the third conversion chip; the control circuit is used to output a first enable signal and a second enable signal to match the serial port communication protocol between the first data transceiver device and the second data transceiver device; the first three-state gate circuit, the second three-state gate circuit, the third three-state gate circuit, the first conversion chip and the third conversion chip are enabled by the first enable signal; the fourth three-state gate circuit is enabled by the second enable signal, and the first enable signal and the second enable signal are mutually exclusive enable signals.

[0010] Optionally, the first differential pair lead is connected to the differential pair pins of the first conversion chip;

[0011] An output pin of the first conversion chip is connected to an input interface of the first tri-state gate circuit;

[0012] An output pin of the first tri-state gate circuit is connected to a first input interface of the three-input AND gate circuit;

[0013] The first differential pair leads respectively have a first pull-up resistor and a first pull-down resistor, and the output pin of the first tri-state gate circuit has a second pull-up resistor.

[0014] Optionally, it also includes a first triode;

[0015] The second differential pair leads are connected to the differential pair pins of the second conversion chip;

[0016] The input pin of the second conversion chip is connected to the base of the first transistor, and the input pin of the second conversion chip is also used to connect to the transmission interface of the second data transceiver device; the output pin of the second conversion chip is connected to the second input interface of the three-input AND gate circuit, and the output pin of the second conversion chip has a third pull-up resistor;

[0017] The collector of the first triode is used to be connected to the power supply voltage source via the third pull-up resistor, the collector of the first triode is also connected to the input interface of the second tri-state gate circuit and the third tri-state gate circuit, and the emitter of the first triode is grounded;

[0018] The output pin of the second tri-state gate circuit is connected to the output enable pin of the second conversion chip, and the output pin of the third tri-state gate circuit is connected to the receiving enable pin of the second conversion chip;

[0019] The output pin of the second tri-state gate circuit has a fourth pull-up resistor, and the output pin of the third tri-state gate circuit has a second pull-down resistor; the second differential pair leads respectively have a fifth pull-up resistor and a sixth pull-down resistor.

[0020] Optionally, a receiving pin of the third conversion chip is connected to the negative lead of the first differential pair lead, a transmitting pin of the third conversion chip is connected to the negative lead of the second differential pair lead, an input pin of the third conversion chip is connected to the collector of the first transistor, and an output pin of the third conversion chip is connected to an input pin of the fourth tri-state gate circuit;

[0021] The output pin of the fourth three-state gate circuit is connected to the third input interface of the three-input AND gate circuit;

[0022] Wherein, the output pin of the fourth three-state gate circuit has a sixth pull-up resistor.

[0023] Optionally, the control circuit comprises:

[0024] A first resistor, a first end of the first resistor is grounded;

[0025] A second resistor, a first end of the second resistor is used to be connected to a power supply voltage source;

[0026] A third resistor, wherein a first end of the third resistor has a dip switch, and the dip switch can be connected to the second end of the first resistor or the second end of the second resistor;

[0027] a second triode, wherein the base of the second triode is connected to the second end of the third resistor, and the emitter of the second triode is grounded;

[0028] a fourth resistor, wherein a first end of the fourth resistor is connected to the collector of the second transistor, and a second end of the fourth resistor is used to be connected to a power supply voltage source;

[0029] The first end of the third resistor outputs a first enable signal, and the first end of the fourth resistor outputs a second enable signal.

[0030] Optionally, a first protection circuit is further included; the first protection circuit includes:

[0031] A first transient diode, wherein a first end of the first transient diode is connected to the positive lead of the differential pair lead, and a second end of the first transient diode is grounded;

[0032] A second transient diode, wherein a first end of the second transient diode is connected to the cathode lead of the differential pair lead, and a second end of the second transient diode is grounded;

[0033] A bidirectional Zener diode is provided, wherein a first end of the bidirectional Zener diode is connected to the cathode lead of the differential pair lead, and a second end of the bidirectional Zener diode is grounded.

[0034] Optionally, a second protection circuit and a third protection circuit are also included;

[0035] The second protection circuit comprises:

[0036] A positive electrode protection resistor, the positive electrode protection resistor is connected in series in the positive electrode lead of the differential pair lead, a first end of the positive electrode protection resistor is connected to the physical interface through the lead, and a second end of the positive electrode protection resistor is connected to the first end of the first transient diode;

[0037] A negative electrode protection resistor is connected in series in the negative electrode lead of the differential pair lead, a first end of the negative electrode protection resistor is connected to the physical interface through the lead, and a second end of the negative electrode protection resistor is connected to the first end of the second transient diode.

[0038] The third protection circuit comprises:

[0039] A first varistor, wherein a first end of the first varistor is connected to a first end of the positive electrode protection resistor;

[0040] A second varistor, a first end of the second varistor is connected to a second end of the negative electrode protection resistor;

[0041] A gas discharge tube, wherein a first end of the gas discharge tube is connected to a second end of the first varistor and a second end of the second varistor, and a second end of the gas discharge tube is grounded.

[0042] Optionally, a connection interface is further included, the connection interface includes five pins, four of which are connected to the first differential pair leads and the second differential pair leads in a one-to-one correspondence, and another pin is connected to a grounded lead.

[0043] Optionally, two pins connected to the first differential pair of leads are arranged adjacent to each other, and two pins connected to the second differential pair of leads are arranged adjacent to each other.

[0044] In a second aspect, the present invention provides a communication device, comprising any one of the above-mentioned serial port adaptive switching circuits.

[0045] In the technical solution provided by the present invention, by enabling the first enable signal and the second enable signal, three conversion chips and four three-state gate circuits convert and output signals on different leads, and the lead usage of various serial communication protocols can be distinguished. The entire circuit cooperates with the enable signal to adaptively match various serial communication protocols without the need for controller control or separate setting of multiple protocol interfaces. Based on the technical solution provided by the present invention, the stability, reliability and ease of operation during the serial port switching process can be improved, and the error probability of on-site installation and debugging personnel can be reduced. At the same time, the technical solution provided by the present invention uses fewer types of hardware, low cost, and reduces circuit costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a principle diagram of a serial port adaptive switching circuit according to an embodiment of the present invention;

[0047] Figure 2 A schematic diagram of the voltage range of the RS-232 interface of a serial port adaptive switching circuit according to another embodiment of the present invention;

[0048] Figure 3 A schematic diagram of the voltage range of the RS-485 / RS-422 interface of a serial port adaptive switching circuit according to another embodiment of the present invention;

[0049] Figure 4 A schematic diagram of another embodiment of the present invention in which a serial port adaptive switching circuit limits the voltage range of an RS-232 interface;

[0050] Figure 5 A schematic diagram of a DIP switch control circuit of a serial port adaptive switching circuit according to another embodiment of the present invention;

[0051] Figure 6 FIG. 4 is a schematic diagram of a protection circuit of a serial port adaptive switching circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0054] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0055] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0056] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0057] The embodiment of the present invention provides a serial port adaptive switching circuit, such as Figure 1 As shown, including:

[0058] The first conversion branch comprises a first differential pair lead, a first conversion chip and a first tri-state gate circuit, wherein the first differential pair lead is used to connect the first data transceiver device to the first conversion chip; the first conversion chip is connected to the first tri-state gate circuit, and the first conversion chip is used to convert the first differential pair signal output by the first data transceiver device via the first differential pair lead into a first logic level signal, and the first logic level signal is output after being subjected to a logic operation by the first tri-state gate circuit;

[0059] The second conversion branch has a second differential pair lead, a second conversion chip, a second tri-state gate circuit and a third tri-state gate circuit; the second differential pair lead is used to connect the first data transceiver device with the second conversion chip, and the second conversion chip is connected with the second tri-state gate circuit and the third tri-state gate circuit; the second conversion chip is also used to connect the second data transceiver device, the second conversion chip is used to convert the second differential pair signal output by the first data transceiver device through the second differential pair lead into a second logic level signal and output it to the second data transceiver device, and convert the third logic level signal sent by the second data transceiver device into a second differential pair signal and output it to the second differential pair lead, the second tri-state gate circuit enables the output pin of the second conversion chip according to the third logic level signal, and the third tri-state gate circuit enables the input pin of the second conversion chip according to the third logic level signal;

[0060] The third conversion branch has a third conversion chip and a fourth three-state gate circuit. The third conversion chip is connected to the first differential pair lead and the negative lead of the second differential pair lead. The third conversion chip is also connected to the fourth three-state gate circuit. The third conversion chip is also used to connect to the second data transceiver device. The third conversion chip converts the negative lead signal output by the first data transceiver device through the negative lead of the first differential pair lead into a fourth logic level signal. The fourth logic level signal is output after logic operation by the fourth three-state gate circuit. The third conversion chip converts the third logic level signal sent by the second data transceiver device into a serial port level signal and sends it to the negative lead of the second differential pair lead.

[0061] A three-input AND gate circuit is respectively connected to the first three-state gate circuit, the second conversion chip and the fourth three-state gate circuit, and the three-input AND gate circuit is also used to connect to the second data transceiver device; the three-input AND gate circuit receives the output signals of the first three-state gate circuit, the second conversion chip and the fourth three-state gate circuit, performs an AND operation and then outputs them to the second data transceiver device;

[0062] The control circuit is respectively connected to the first three-state gate circuit, the second three-state gate circuit, the third three-state gate circuit, the fourth three-state gate circuit, the first conversion chip and the third conversion chip; the control circuit is used to output a first enable signal and a second enable signal to match the serial port communication protocol between the first data transceiver device and the second data transceiver device; the first three-state gate circuit, the second three-state gate circuit, the third three-state gate circuit, the first conversion chip and the third conversion chip are enabled by the first enable signal; the fourth three-state gate circuit is enabled by the second enable signal, and the first enable signal and the second enable signal are mutually exclusive enable signals.

[0063] exist Figure 1In the figure, A represents the five signal pins that pass through the protection circuit, including TX+ / -, RX+ / -, GND, and TX / RX are the multiplexed pins of RS232; since there is no direct signal transmission between the ground pin and the conversion circuit, it is not shown in the figure. U1, U2 and U3 are the first conversion chip, the second conversion chip and the third conversion chip respectively, where U1 and U2 can be, for example, SP485EEN. U2 is used as an RS-485 conversion chip alone, and U1 and U2 together constitute an RS-422 conversion circuit; U3 is an RS-232 conversion chip, and its model can be, for example, SP3243EEA. H1, H2, H3 and H4 are the first three-state gate circuit, the second three-state gate circuit, the third three-state gate circuit and the fourth three-state gate circuit inside the chip U4 respectively, and the model of U4 can be, for example, AIP74HC125. U5 is a three-input logic AND gate, model SN74LVC1G11DCKR; U6 is MCU / CPU. Signal REN is the enable control pin of chip U2 RX, which is valid at low level; signal DEN is the enable control pin of chip U2 TX, which is valid at high level; pin 22 of chip U3 is the TX and RX enable pin, which is 1 high level, both TX and RX are enabled, and 0 low level, both TX and RX are disabled. CON and CON-1 represent the first enable signal and the second enable signal respectively.

[0064] In this embodiment, the first differential pair of leads includes RX+ / - leads, the second differential pair of leads includes TX+ / - leads, and the external interface should also include a ground lead. Since the ground lead has no direct signal transmission relationship with the conversion circuit, it is not shown in the figure. According to the technical solution in this embodiment, the pin definitions of various serial ports can be defined according to the following table:

[0065]

[0066] like Figure 2 As shown, when the external access is an RS-232 interface, the RS-232 protocol stipulates that the logic level is: logic 1 = -3V ~ -15V, logic 0 = +3V ~ +15V; Figure 3As shown, when the external access is an RS-485 / RS-422 interface, for the transmitting end: logic 1 is a two-line voltage difference of +2 to +6V, and logic 0 is a two-line voltage difference of -2 to -6V; for the receiving end: (T+)-(T-)≥0.2V, indicating a signal "1", (T+)-(T-)≤0.2V, indicating a signal "0". In the prior art, the TX and RX signals of RX-232 are usually multiplexed with the TX+ and TX- of RS-422. At this time, because the RS-232 working mode is full-duplex, and the TX of RS-422 is a differential line (TX+ and TX-), if RS-232 is transmitting and receiving at the same time, there is a voltage difference of up to 30V between TX and RX. Since the RS-422 transceiver IC is connected to the hardware at the same time, the RS-422 transceiver IC will be damaged or destroyed.

[0067] In order to avoid the above situation, in this embodiment, the multiplexing line sequence is first changed, and the TX and RX of RS-232 are multiplexed with one lead of each of the two differential pairs, which fundamentally prevents the multiplexing of the TX and RX of RS-232 with the TX or RX differential lines of RS-422, so that there will be no high voltage 30V acting on a transceiver at the same time. Then, through the design of the circuit and the design of the enable signal, when the RS-232, RS-422 or RS-485 device is connected, it can adaptively match the corresponding communication protocol to work.

[0068] In the technical solution provided in this embodiment, by enabling the first enable signal and the second enable signal, three conversion chips and four three-state gate circuits convert and output signals on different leads, and the lead usage of various serial communication protocols can be distinguished. The entire circuit cooperates with the enable signal to adaptively match various serial communication protocols without the need for controller control or separate setting of multiple protocol interfaces. Based on the technical solution provided in this embodiment, the stability, reliability and ease of operation during the serial port switching process can be improved, and the error probability of on-site installation and debugging personnel can be reduced. At the same time, the technical solution provided by the present invention uses fewer types of hardware, has low cost, and reduces circuit costs.

[0069] As an optional implementation, continue as Figure 1 As shown, the first differential pair lead is connected to the differential pair pin of the first conversion chip;

[0070] An output pin of the first conversion chip is connected to an input interface of the first tri-state gate circuit;

[0071] An output pin of the first tri-state gate circuit is connected to a first input interface of the three-input AND gate circuit;

[0072] The first differential pair leads respectively have a first pull-up resistor and a first pull-down resistor, and the output pin of the first tri-state gate circuit has a second pull-up resistor.

[0073] In some embodiments, the pull-up resistor and the pull-down resistor of the first differential pair lead can keep the differential voltage of the first differential pair lead when there is no signal, so that its output remains fixed. For example, when the first enable signal CON=0 and the second enable signal CON_1=1, taking the external RS-485 serial bus as an example, the 2nd pin of U1 is low level 0, and the 1st pin can receive data, but because the external wiring RX+ and RX- are suspended and not connected, the signal level of RX+ and RX- is determined by the external pull-up resistors. At this time, RX+ is set to high level 1 by the pull-up resistor R11, and RX- is set to low level 0 by the pull-down resistor R12; because RS-422 / RS-485 are both differential line transmission, when (RX+)-(RX-)>2V, it is high level 1, it can be known that at this time the RXD422 signal is high level 1, RX_422=1. The pull-up resistor of the first tri-state gate circuit can maintain a fixed output when the first tri-state gate circuit is not enabled. For example, when the first enable signal CON=1 and the second enable signal CON_1=0, when the external device is an RS-232 serial port bus, the control pin 1 of the tri-state gate circuit of H1 is at a high level and is in a disabled state. The tri-state gate outputs a high impedance state, and the corresponding signal RX_422 is pulled up by the external resistor R7 and outputs a high level 1, that is, RX_422=1.

[0074] As an optional implementation, continue as Figure 1 As shown, it also includes a first triode;

[0075] The second differential pair leads are connected to the differential pair pins of the second conversion chip;

[0076] The input pin of the second conversion chip is connected to the base of the first transistor, and the input pin of the second conversion chip is also used to connect to the transmission interface of the second data transceiver device; the output pin of the second conversion chip is connected to the second input interface of the three-input AND gate circuit, and the output pin of the second conversion chip has a third pull-up resistor;

[0077] The collector of the first triode is used to be connected to the power supply voltage source via the third pull-up resistor, the collector of the first triode is also connected to the input interface of the second tri-state gate circuit and the third tri-state gate circuit, and the emitter of the first triode is grounded;

[0078] The output pin of the second tri-state gate circuit is connected to the output enable pin of the second conversion chip, and the output pin of the third tri-state gate circuit is connected to the receiving enable pin of the second conversion chip;

[0079] The output pin of the second tri-state gate circuit has a fourth pull-up resistor, and the output pin of the third tri-state gate circuit has a second pull-down resistor; the second differential pair leads respectively have a fifth pull-up resistor and a sixth pull-down resistor.

[0080] In some embodiments, the pull-up resistor and the pull-down resistor of the second differential pair lead can maintain the differential potential when the receiving pin is not enabled. For example, when the first enable signal CON=0 and the second enable signal CON_1=1, for RS-422, when there is no data to be sent, the default 4-pin TXD of U2 is 1, and TXD controls the transistor Q2 to turn on and output a low level 0. At this time, the three-state gates H2 and H3 are in the enabled state, and the signals REN=0 and DEN=0. U2's TX is not enabled, and U2's RX reception is enabled. Since the signal TX+ / A is pulled up and TX- / B is pulled down, for differential transmission RS-422 communication, when (TX+ / A)-(TX- / B)>2V, it is high level 1, that is, RX_485=1; when there is data TXD=1 to send, transistor Q2 is turned on and outputs low level 0, at this time REN=0, DEN=0; U2's TX is not enabled, but since the signal TX+ / A is pulled up and TX- / B is pulled down, for differential transmission RS-422 communication , (TX+ / A)-(TX- / B)>2V, the external output is still high level 1; and U2's RX is enabled, and it can also receive (TX+ / A)-(TX- / B)>2V high level 1, then RX_485=1; when there is data TXD=0 to send, transistor Q2 is cut off and outputs high level 1, at this time REN=1, DEN=1; U2's TX is enabled, and data 0 is sent normally; and U2's RX is not enabled, RX_485 has no data, and is set to high level 1 through the pull-up resistor R15, that is, RX_485=1. The pull-up resistor of the second three-state gate circuit and the pull-down resistor of the third three-state gate are to output the correct signal even in the disabled state. For example, when CON=1, CON_1=0, and the external bus is RS-232, H2 and H3 are not enabled, and the output is in high impedance state. The corresponding signal REN is pulled up by the external resistor R8, and outputs a high level 1 (REN=1). The RX of U2 does not receive, and the RX_485 signal is pulled up by the external resistor R15, and is a high level 1 (RX_485=1). The corresponding signal DEN is pulled down by the external resistor R9, and outputs a low level 0 (DEN=0). The TX of U2 does not send data, that is, no data is sent from pin 4 of U2.

[0081] As an optional implementation, continue as Figure 1As shown, the receiving pin of the third conversion chip is connected to the negative lead of the first differential pair lead, the sending pin of the third conversion chip is connected to the negative lead of the second differential pair lead, the input pin of the third conversion chip is connected to the collector of the first transistor, and the output pin of the third conversion chip is connected to the input pin of the fourth tri-state gate circuit;

[0082] The output pin of the fourth three-state gate circuit is connected to the third input interface of the three-input AND gate circuit;

[0083] Wherein, the output pin of the fourth three-state gate circuit has a sixth pull-up resistor.

[0084] In some embodiments, the output of the fourth tri-state gate has a pull-up resistor, which can output a correct signal to the outside when the fourth tri-state gate is not enabled. For example, when CON=0 and CON_1=1, the 22nd pin of U3 is low level 0, and the corresponding TX and RX of U3 are invalid and cannot send and receive data normally, then the H4 tri-state gate outputs high impedance, and due to the existence of the external pull-up resistor R10, RX_232=1.

[0085] As an optional implementation, Figure 5 As shown, the control circuit includes:

[0086] A first resistor, a first end of the first resistor is grounded;

[0087] A second resistor, a first end of the second resistor is used to be connected to a power supply voltage source;

[0088] A third resistor, wherein a first end of the third resistor has a dip switch, and the dip switch can be connected to the second end of the first resistor or the second end of the second resistor;

[0089] a second triode, wherein the base of the second triode is connected to the second end of the third resistor, and the emitter of the second triode is grounded;

[0090] a fourth resistor, wherein a first end of the fourth resistor is connected to the collector of the second transistor, and a second end of the fourth resistor is used to be connected to a power supply voltage source;

[0091] The first end of the third resistor outputs a first enable signal, and the first end of the fourth resistor outputs a second enable signal.

[0092] In some embodiments, Figure 5In the figure, S1 is a dip switch, R1, R2, R3, R4 are the first resistor, the second resistor, the third resistor and the fourth resistor respectively, and Q1 is a transistor. When the common terminal "3" of the dip switch S1 is turned to the "1" position, the control signal CON is pulled up to a high level through R2, which is recorded as logic "1". At this time, the Q1 transistor is turned on, and the CON_1 signal is pulled low, which is recorded as logic "0"; when the common terminal "3" of the dip switch S1 is turned to the "2" position, the control signal CON is pulled down to a low level through R1, which is recorded as logic "0". At this time, the Q1 transistor is turned off, and the CON_1 signal is pulled up to a high level by R4, which is recorded as logic "1". By controlling the on position of the dip switch, it is defined that when the signal CON=1, CON_1=0, it is an RS-232 communication interface; when the signal CON=0, CON_1=1, it is an RS-485 or RS-422 communication interface according to the on-site wiring conditions; the logic corresponds to the following table:

[0093]

[0094] For each of the above-mentioned embodiments, Figure 1 As shown, the specific data sending and receiving process is analyzed as follows:

[0095] When the code switch control signal CON=1,CON_1=0, the RS-232 interface is selected by default, and the external wiring terminals are correctly wired according to the pin multiplexing instructions in Table 1. At this time, the control pins 1, 4, and 10 of the three tri-state gates H1, H2, and H3 are all high level 1, not enabled, and the tri-state gates output high impedance state. The corresponding signal RX_422 is pulled up by the external resistor R7 and outputs high level 1 (RX_422=1). The corresponding signal REN is pulled up by the external resistor R8 and outputs high level 1 (REN=1). U2's RX does not receive, and the RX_485 signal is pulled up by the external resistor R15 and is high level 1 (RX_485=1); the corresponding signal DEN is pulled down by the external resistor R9 and outputs low level 0 (DEN=0). U2's TX does not send data, that is, U2's 4 pin has no data to send. CON_1=0, the control pin of the tri-state gate H4 is low level 0 valid, and the RXD232 signal is normally output to RX_232. Corresponding to the 22-pin signal CON=1 of U3, both TX and RX of U3 are in the enabled state, and the transceiver U3 works normally in full-duplex mode; at this time, the TXD signal from the MCU / CPU only sends data through the U3 transceiver. At the same time, since RX_422=1, RX_485=1, after passing through the three-input AND gate U5, the level of the RXD signal is completely determined by RX_232, that is, the 17-pin signal RXD232 of U3. Therefore, the RS-232 bus data can be sent and received normally on the physical link. RS-232 communication is completed.

[0096] When the DIP switch control signal CON=0, CON_1=1, the RS-422 or RS-485 interface is selected by default. There are two cases to discuss:

[0097] In one case, if the external bus is RS-485, correctly connect to RS-485 according to the pin multiplexing instructions in Table 1; analysis shows that CON=0, pin 22 of U3 is low level 0, and both TX and RX of U3 are invalid and cannot send and receive data normally, then the H4 tri-state gate outputs high impedance, and due to the existence of the external pull-up resistor R10, RX_232=1. Pin 2 of U1 is low level 0, and pin 1 can receive data. However, due to the external wiring RX+ and RX- being suspended, the signal levels of RX+ and RX- are determined by the external pull-up and pull-down resistors. At this time, RX+ is set to high level 1 by the pull-up resistor R11, and RX- is set to low level 0 by the pull-down resistor R12. Since RS-422 / RS-485 are both differential line transmissions, when (RX+)-(RX-)>2V, it is high level 1. It can be seen that at this time, the RXD422 signal is high level 1, RX_422=1; and for RS-485, since it is half-duplex mode, when there is no data to be sent, the default TXD of U2's 4th pin is 1 high level, and TXD controls the transistor Q2 to conduct and output low level 0. At this time, the three-state gates H2 and H3 are in the enabled state, the signals REN=0, DEN=0, the TX of U2 is invalid and disabled, and the RX is enabled. By default, this state is the RX receiving mode. At the same time, since RX_422 = 1 and RX_232 = 1, after passing through the three-input AND gate U5, the level of the RXD signal is completely determined by RX_485. Therefore, the RX data of the RS-485 bus can be received normally on the physical link.

[0098] When MCU / CPU controls the TX transmission mode of RS-485, there are two cases. When TXD=1, the logic principle is as described above. Although the RX of U2 is enabled, RS-485 works in half-duplex mode, so there is no effect on RX. When TXD=0, TXD controls the transistor Q2 to cut off and outputs a high level 1. At this time, the three-state gates H2 and H3 are in the enabled state, the signal REN=1, DEN=1, at this time, RX is not enabled, TX is enabled, and data can be sent normally.

[0099] In another case, if the external bus is an RS-422 serial port, correctly connect to RS-422 according to the pin multiplexing instructions in Table 1; analysis shows that CON=0, pin 22 of U3 is low level 0, and the corresponding TX and RX of U3 are invalid and cannot send and receive data normally. As mentioned above, RX_232=1; for RS-422, when there is no data to be sent, the default is that pin 4 of U2 is TXD=1, and TXD controls transistor Q2 to turn on and output low level 0. At this time, the three-state gates H2 and H3 are in the enabled state, and the signals REN=0, DEN=0. U2's TX is not enabled, and U2's RX reception is enabled. Since the signal TX+ / A is pulled up and TX- / B is pulled down, for differential transmission RS-422 communication,

[0100] When (TX+ / A)-(TX- / B)>2V, it is high level 1 (RX_485=1); for U1, pin 2 is low level 0 so that pin 1 can receive data normally. The RXD_422 signal level depends entirely on the signal sent from the outside. At the same time, since RX_485=1 and RX_232=1, after passing through the three-input AND gate U5, the level of the RXD signal depends entirely on RX_422. Therefore, the RX data of the RS-422 bus can be received normally on the physical link. In another case, RS-422 is in full-duplex mode. When U2's TX sends data, U1's RX can receive it normally at the same time. Analysis:

[0101] When data TXD=1 is sent, transistor Q2 is turned on and outputs low level 0, at this time REN=0, DEN=0; U2's TX is not enabled, but because the signal TX+ / A is pulled up and TX- / B is pulled down, at this time, for the differential transmission RS-422 communication, (TX+ / A)-(TX- / B)>2V, the external output is still high level 1; and U2's RX is enabled, and it can also receive (TX+ / A)-(TX- / B)>2V high level 1, then RX_485=1; U1's pin 2 is low level 0, enabling RX, RXD422 receives data normally, and at the same time, because RX_485=1, RX_232=1, after passing through the three-input AND gate U5, the level of the RXD signal is completely determined by RX_422. Therefore, RS-422 data can be sent and received normally on the physical link.

[0102] When there is data TXD=0 to be sent, transistor Q2 is cut off and outputs high level 1. At this time, REN=1, DEN=1; U2's TX is enabled and data 0 is sent normally; while U2's RX is not enabled, RX_485 has no data, and is set to high level 1 (RX_485=1) through the pull-up resistor R15. Pin 2 of U1 is low level 0, enabling RX, and RXD422 receives data normally. At the same time, since RX_485=1, RX_232=1, after passing through the three-input AND gate U5, the level of the RXD signal is completely determined by RX_422. Therefore, RS-422 data can be sent and received normally on the physical link.

[0103] Based on the above analysis, when the external wiring correctly follows the pin definition, one of the three communications, RS-232, RS-485, and RS-422, can be selected by controlling the dip switch, truly realizing a three-in-one design. The communication methods corresponding to the above key control signal logic are summarized in the following table:

[0104]

[0105] As an optional implementation, Figure 6 As shown, both the first differential pair lead and the second differential pair lead have a first protection circuit, that is, a three-level protection circuit in the figure; the first protection circuit includes:

[0106] A first transient diode, wherein a first end of the first transient diode is connected to the positive lead of the differential pair lead, and a second end of the first transient diode is grounded;

[0107] A second transient diode, wherein a first end of the second transient diode is connected to the cathode lead of the differential pair lead, and a second end of the second transient diode is grounded;

[0108] A bidirectional Zener diode is provided, wherein a first end of the bidirectional Zener diode is connected to the cathode lead of the differential pair lead, and a second end of the bidirectional Zener diode is grounded.

[0109] In some embodiments, the protection circuit is divided into two cases. The TX+ / A signal does not reuse the RS-232 pin, and only needs to add a bidirectional TVS tube. The TVS tube can absorb the residual voltage after the secondary protection circuit and reliably clamp the voltage within a safe range. Through analysis, it is found that the maximum allowable voltage of the pin of the commonly used RS-482 / RS-422 transceiver conversion chip SP3485 is 12V, so the recommended breakdown voltage specification of TVS1 is about 12V. For the TX- / B signal, because the RS-232 pin is reused, and the maximum voltage to ground is specified in the RS-232 interface level to be up to 15V, TVS2 in the protection circuit is a bidirectional TVS tube like TVS1, but the breakdown voltage is selected to be about 16V, which ensures the normal voltage level when the RS-232 interface is used, and on the other hand, it effectively absorbs the residual voltage after RG2 like TVS1. At the same time, DD1 is added. DD1 is a bidirectional Zener diode, also known as a voltage regulator. The usage specification is about 7V. The main consideration is that the voltage resistance of the SP3485 transceiver conversion chip is between -7V and +12V. Whether it is the signal of the RS-232 interface, the RS-485 interface signal or the RS-422 interface signal, when the voltage level is greater than 7V, it will be stabilized at 7V by the DD1 voltage regulator, which does not affect the normal communication of each interface and effectively protects the subsequent transceiver chip. At this time, if it is connected to the RS-485 / RS-422 interface, it will not affect the logical judgment; if it is connected to RS-232, the voltage will be limited to ±7V, and the limitation is shown as follows Figure 4 As shown, it complies with the RS-232 logic judgment range and will not damage the SP3485 transceiver conversion chip due to excessive voltage.

[0110] As an optional implementation, continue as Figure 6 As shown, it also includes a second protection circuit and a third protection circuit;

[0111] The second protection circuit, i.e. the secondary protection circuit in the figure, includes:

[0112] A positive electrode protection resistor, the positive electrode protection resistor is connected in series in the positive electrode lead of the differential pair lead, a first end of the positive electrode protection resistor is connected to the physical interface through the lead, and a second end of the positive electrode protection resistor is connected to the first end of the first transient diode;

[0113] A negative electrode protection resistor is connected in series in the negative electrode lead of the differential pair lead, a first end of the negative electrode protection resistor is connected to the physical interface through the lead, and a second end of the negative electrode protection resistor is connected to the first end of the second transient diode.

[0114] In some embodiments, positive electrode protection resistors and negative electrode protection resistors are used to limit the inductive peak voltage generated during the transient high current discharge process. The series connection of resistors also prevents the high voltage lightning signal from reaching the TVS tube in the first place to a certain extent.

[0115] As an optional implementation, continue as Figure 6 As shown, the third protection circuit, that is, the first-level protection circuit in the figure, includes:

[0116] A first varistor, wherein a first end of the first varistor is connected to a first end of the positive electrode protection resistor;

[0117] A second varistor, a first end of the second varistor is connected to a second end of the negative electrode protection resistor;

[0118] A gas discharge tube, wherein a first end of the gas discharge tube is connected to a second end of the first varistor and a second end of the second varistor, and a second end of the gas discharge tube is grounded.

[0119] In some embodiments, varistors RV1, RV2 and gas discharge tube GD1 are used to form a primary protection circuit. The varistor itself has a large parasitic capacitance, while the parasitic capacitance of the gas discharge tube is very small. After the varistor is connected in series, the parasitic capacitance is very small. In addition, although the varistor has a fast response time, its leakage current is large, and it can form effective protection when combined with a gas discharge tube with a small leakage current. It provides lightning overvoltage protection between lines and between lines and ground, and its fast response characteristics can be used to quickly discharge the lightning voltage.

[0120] As an optional implementation, it further includes a connection interface, which includes five pins, four of which are connected to the first differential pair leads and the second differential pair leads in a one-to-one correspondence, and another pin is connected to a grounded lead.

[0121] As an optional implementation, two pins connected to the first differential pair of leads are arranged adjacent to each other, and two pins connected to the second differential pair of leads are arranged adjacent to each other.

[0122] In some embodiments, the above-mentioned pin setting method corresponds to the aforementioned pin definition table. According to the aforementioned pin definition table and control signal logic table, when the dip switch outputs a high level, that is, CON=1, CON_1=0, RX-485 and RX-422 of U5 are high levels, and the output signal of U5 is the same as RX-232, that is, the second data transceiver device can receive the data sent by the first data transceiver device via the pin corresponding to RX-. At this time, the DEN pin of U2 is not enabled, and only U3 can convert the signal of TXD of the second data transceiver device and then send it to the first data transceiver device from TX-. When the dip switch outputs a low level, that is, CON=0, CON_1=1, if the RS-485 signal is connected, the RX-232 pin and RX-422 pin of U5 are high levels, and at this time, the output of U5 is the same as the signal of the RX-485 pin. At this time, the differential signal of the first data transceiver device can be sent to the second data transceiver device after conversion by U2. Since the RX+ and RX- pins of RS-485 are floating pins, the first data transceiver device will not receive the information sent by the second data transceiver device. If the RS-422 signal is connected, the RX-232 and RX-485 pins of U5 are both high level, that is, the signal output by U5 to the second data transceiver device is the same as the RS-422 signal. At this time, the differential signal of the first data transceiver device can be sent to the second data device after conversion by U1. Since RX+ and RX- both have corresponding pins at this time, at this time, the signal sent by the second data transceiver device can be sent to the first data transceiver device through RX+ and RX- after conversion by U2.

[0123] An embodiment of the present invention further provides a communication device, comprising any one of the above serial port adaptive switching circuits.

[0124] The communication device is used to connect the first data transceiver device and the second data transceiver device respectively, so that the serial port communication protocol between the first data transceiver device and the second data transceiver device is adaptively matched, thereby supporting data transmission between the first data transceiver device and the second data transceiver device.

[0125] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0126] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0127] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A serial port adaptive switching circuit, characterized in that: include: A first conversion branch, comprising a first differential pair lead, a first conversion chip and a first tri-state gate circuit, wherein the first differential pair lead is used to connect a first data transceiver device to the first conversion chip; the first conversion chip is connected to the first tri-state gate circuit, and the first conversion chip is used to convert a first differential pair signal output by the first data transceiver device via the first differential pair lead into a first logic level signal, and the first logic level signal is output after being subjected to a logic operation by the first tri-state gate circuit; The second conversion branch comprises a second differential pair lead, a second conversion chip, a second tri-state gate circuit and a third tri-state gate circuit; the second differential pair lead is used to connect the first data transceiver device with the second conversion chip, and the second conversion chip is respectively connected to the second tri-state gate circuit and the third tri-state gate circuit; the second conversion chip is also used to connect the second data transceiver device, the second conversion chip is used to convert the second differential pair signal output by the first data transceiver device through the second differential pair lead into a second logic level signal, and output the second logic level signal to the second data transceiver device, and convert the third logic level signal sent by the second data transceiver device into a second differential pair signal, and output the second differential pair signal to the second differential pair lead, the second tri-state gate circuit enables the output pin of the second conversion chip according to the third logic level signal, and the third tri-state gate circuit enables the input pin of the second conversion chip according to the third logic level signal; a third conversion branch, comprising a third conversion chip and a fourth three-state gate circuit, wherein the third conversion chip is respectively connected to the first differential pair lead, the negative lead of the second differential pair lead, and the fourth three-state gate circuit, and the third conversion chip is also used to connect to the second data transceiver device; the third conversion chip converts the negative lead signal output by the first data transceiver device via the negative lead of the first differential pair lead into a fourth logic level signal, and the fourth logic level signal is output after logic operation by the fourth three-state gate circuit; The third conversion chip converts the third logic level signal sent by the second data transceiver device into a serial port level signal, and sends the serial port level signal to the negative lead of the second differential pair lead; A three-input AND gate circuit, connected to the first three-state gate circuit, the second conversion chip and the fourth three-state gate circuit respectively, and the three-input AND gate circuit is also used to connect the second data transceiver device; the three-input AND gate circuit receives the output signals of the first three-state gate circuit, the second conversion chip and the fourth three-state gate circuit, performs an AND operation and then outputs to the second data transceiver device; A control circuit is respectively connected to the first three-state gate circuit, the second three-state gate circuit, the third three-state gate circuit, the fourth three-state gate circuit, the first conversion chip and the third conversion chip; the control circuit is used to output a first enable signal and a second enable signal to match the serial port communication protocol between the first data transceiver device and the second data transceiver device; the first three-state gate circuit, the second three-state gate circuit, the third three-state gate circuit, the first conversion chip and the third conversion chip are enabled by the first enable signal; the fourth three-state gate circuit is enabled by the second enable signal, and the first enable signal and the second enable signal are mutually exclusive enable signals.

2. The serial port adaptive switching circuit according to claim 1, characterized in that: The first differential pair leads are connected to the differential pair pins of the first conversion chip; The output pin of the first conversion chip is connected to the input interface of the first tri-state gate circuit; The output pin of the first tri-state gate circuit is connected to the first input interface of the three-input AND gate circuit; The first differential pair leads respectively have a first pull-up resistor and a first pull-down resistor, and the output pin of the first tri-state gate circuit has a second pull-up resistor.

3. The serial port adaptive switching circuit according to claim 1, characterized in that: Also included is a first triode; The second differential pair leads are connected to the differential pair pins of the second conversion chip; The input pin of the second conversion chip is connected to the base of the first transistor, and the input pin of the second conversion chip is also used to connect to the transmission interface of the second data transceiver device; the output pin of the second conversion chip is connected to the second input interface of the three-input AND gate circuit, and the output pin of the second conversion chip has a third pull-up resistor; The collector of the first triode is used to be connected to the power supply voltage source via the third pull-up resistor, the collector of the first triode is also connected to the input interfaces of the second tri-state gate circuit and the third tri-state gate circuit respectively, and the emitter of the first triode is grounded; The output pin of the second tri-state gate circuit is connected to the output enable pin of the second conversion chip, and the output pin of the third tri-state gate circuit is connected to the receiving enable pin of the second conversion chip; The output pin of the second tri-state gate circuit has a fourth pull-up resistor, and the output pin of the third tri-state gate circuit has a second pull-down resistor; the second differential pair leads respectively have a fifth pull-up resistor and a sixth pull-down resistor.

4. The serial port adaptive switching circuit according to claim 3, characterized in that: The receiving pin of the third conversion chip is connected to the negative lead of the first differential pair lead, the sending pin of the third conversion chip is connected to the negative lead of the second differential pair lead, the input pin of the third conversion chip is connected to the collector of the first transistor, and the output pin of the third conversion chip is connected to the input pin of the fourth three-state gate circuit; The output pin of the fourth tri-state gate circuit is connected to the third input interface of the three-input AND gate circuit; Wherein, the output pin of the fourth three-state gate circuit has a sixth pull-up resistor.

5. The serial port adaptive switching circuit according to claim 1, characterized in that: The control circuit comprises: a first resistor, wherein a first end of the first resistor is grounded; a second resistor, wherein a first end of the second resistor is used to be connected to a power supply voltage source; a third resistor, wherein a first end of the third resistor has a dip switch, and the dip switch can be connected to the second end of the first resistor or the second end of the second resistor; a second triode, wherein a base of the second triode is connected to the second end of the third resistor, and an emitter of the second triode is grounded; a fourth resistor, wherein a first end of the fourth resistor is connected to the collector of the second transistor, and a second end of the fourth resistor is used to be connected to the power supply voltage source; The first end of the third resistor outputs the first enable signal, and the first end of the fourth resistor outputs the second enable signal.

6. The serial port adaptive switching circuit according to claim 1, characterized in that: Also includes a first protection circuit; the first protection circuit includes: A first transient diode, wherein a first end of the first transient diode is connected to a positive lead in the differential pair of leads, and a second end of the first transient diode is grounded; A second transient diode, wherein a first end of the second transient diode is connected to a cathode lead of the differential pair leads, and a second end of the second transient diode is grounded; A bidirectional Zener diode, wherein a first end of the bidirectional Zener diode is connected to the cathode lead of the differential pair leads, and a second end of the bidirectional Zener diode is grounded.

7. The serial port adaptive switching circuit according to claim 6, characterized in that: Also includes a second protection circuit and a third protection circuit; The second protection circuit comprises: A positive electrode protection resistor, wherein the positive electrode protection resistor is connected in series in the positive electrode lead of the differential pair lead, a first end of the positive electrode protection resistor is connected to the physical interface through the lead, and a second end of the positive electrode protection resistor is connected to the first end of the first transient diode; A negative electrode protection resistor, wherein the negative electrode protection resistor is connected in series in the negative electrode lead of the differential pair lead, a first end of the negative electrode protection resistor is connected to the physical interface through a lead, and a second end of the negative electrode protection resistor is connected to the first end of the second transient diode; The third protection circuit comprises: a first varistor, wherein a first end of the first varistor is connected to a first end of the positive electrode protection resistor; a second varistor, wherein a first end of the second varistor is connected to a second end of the negative electrode protection resistor; A gas discharge tube, wherein a first end of the gas discharge tube is connected to a second end of the first varistor and a second end of the second varistor, and a second end of the gas discharge tube is grounded.

8. The serial port adaptive switching circuit according to any one of claims 1 to 7, characterized in that: It also includes a connection interface, which includes five pins, four of which are connected to the first differential pair leads and the second differential pair leads in a one-to-one correspondence, and another pin is connected to a grounded lead.

9. The serial port adaptive switching circuit according to claim 8, characterized in that: The two pins connected to the first differential pair of leads are arranged adjacent to each other, and the two pins connected to the second differential pair of leads are arranged adjacent to each other.

10. A communication device, characterized in that: The invention comprises the serial port adaptive switching circuit as claimed in any one of claims 1 to 9.

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