Automatic power supply noise sensitivity test system for storage devices

Abstract

An automatic power supply noise sensitivity test system for a storage device is provided. A system includes a host, a storage device, and a plurality of noise injection modules. Each noise injection module includes first through third relays coupled to a first path or a second path. The first path includes an operational amplifier to generate a high noise function, a first variable regulator to generate a first regulated supply voltage or a second regulated supply voltage, and a capacitor injection circuit to generate a low noise function and a first power supply noise. The second path includes a second variable regulator to generate a third regulated supply voltage or a fourth regulated supply voltage and a power amplifier injection circuit to generate a second power supply noise. The third relay selectively provides the first power supply noise or the second power supply noise to the storage device.

Description

Technical Field

[0001] This invention relates to a power supply noise sensitivity testing scheme for a storage device. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices (i.e., data storage devices). Data storage devices serve as either primary or secondary storage for portable electronic devices.

[0003] For many years, power supply noise sensitivity testing, or power supply noise injection testing, has been used to screen storage devices such as hard disk drives (HDDs) and solid-state drives (SSDs). It is in this context that embodiments of the present invention have emerged. Summary of the Invention

[0004] Aspects of the present invention include a system for automatically testing the power supply noise sensitivity of one or more storage devices.

[0005] In one aspect of the invention, a power supply noise sensitivity testing system includes: a host computer including a power supply configured to provide a power supply voltage; a plurality of storage devices coupled to the host computer via a Multiple High-Speed ​​Peripheral Component Interconnect (PCIe) link; and multiple noise injection modules for testing the power supply noise sensitivity of the plurality of storage devices. Each noise injection module includes: a first relay configured to receive the power supply voltage and, in response to a frequency selection signal, output the power supply voltage to a first path or a second path; a second relay configured to receive a noise function and, in response to the frequency selection signal, output the noise function to the first path or the second path; and a third relay coupled to the first path or the second path and the storage device. The first path includes: an operational amplifier configured to receive a noise function and generate a high noise function in response to a power supply voltage; a first variable regulator configured to receive and regulate the power supply voltage to generate a first regulated power supply voltage or a second regulated power supply voltage in response to a voltage selection signal; and a capacitor injection circuit configured to receive the first regulated power supply voltage or the second regulated power supply voltage, the noise function, and the high noise function, and generate a low noise function and a first power supply noise, the first power supply noise corresponding to the sum of the first regulated power supply voltage or the second regulated power supply voltage and the high noise function. The second path includes: a second variable regulator configured to receive and regulate the power supply voltage to generate a third regulated power supply voltage or a fourth regulated power supply voltage in response to a voltage selection signal; and a power amplifier injection circuit configured to receive the third regulated power supply voltage or the fourth regulated power supply voltage and the low noise function, and generate a second power supply noise corresponding to the sum of the third regulated power supply voltage or the fourth regulated power supply voltage and the low noise function. A third relay selectively receives the first power supply noise and the second power supply noise in response to a frequency selection signal, and provides the selectively received power supply noise to a storage device.

[0006] In another aspect of the invention, a system for testing the power supply noise sensitivity of a storage device includes: a first relay configured to receive a power supply voltage and, in response to a frequency selection signal, output the power supply voltage to a first path or a second path; a second relay configured to receive a noise function and, in response to the frequency selection signal, output the noise function to the first path; and a third relay coupled to the first path or the second path and the storage device. The first path includes: an operational amplifier configured to receive the noise function and, in response to the power supply voltage, generate a high noise function; and a capacitor injection circuit configured to receive the power supply voltage, the noise function, and the high noise function, and generate a low noise function and a first power supply noise, the first power supply noise corresponding to the sum of the power supply voltage and the high noise function. The second path includes: a regulator configured to receive the power supply voltage and regulate the power supply voltage to generate a regulated power supply voltage; and a power amplifier injection circuit configured to receive the regulated power supply voltage and the low noise function, and generate a second power supply noise corresponding to the sum of the power supply voltage and the low noise function. The third relay selectively receives the first power supply noise and the second power supply noise in response to the frequency selection signal, and provides the selectively received power supply noise to the storage device.

[0007] In another aspect of the invention, a system for testing the power supply noise sensitivity of a storage device includes: a first relay configured to receive a power supply voltage and, in response to a frequency selection signal, output the power supply voltage to a first path or a second path; a second relay configured to receive a noise function and, in response to the frequency selection signal, output the noise function to the first path or the second path; and a third relay coupled to the first path or the second path and the storage device. The first path includes: a first regulator configured to receive the power supply voltage and regulate the power supply voltage to generate a first regulated power supply voltage; an operational amplifier configured to receive the noise function and, in response to the first regulated power supply voltage, generate a high noise function; and a capacitor injection circuit configured to receive the power supply voltage, the noise function, and the high noise function, and generate a low noise function and a first power supply noise, the first power supply noise corresponding to the sum of the power supply voltage and the high noise function. The second path includes: a second regulator configured to receive the power supply voltage and regulate the power supply voltage to generate a second regulated power supply voltage; and a power amplifier injection circuit configured to receive the second regulated power supply voltage and the low noise function, and generate a second power supply noise corresponding to the sum of the power supply voltage and the low noise function. The third relay responds to the frequency selection signal to selectively receive the first power supply noise and the second power supply noise, and provides the selectively received power supply noise to the storage device.

[0008] Additional aspects of the invention will become apparent from the following description. Attached Figure Description

[0009] Figures 1 to 3This is a diagram illustrating an example of a power supply noise sensitivity testing system for storage devices.

[0010] Figure 4 This is a diagram illustrating a power supply noise sensitivity testing system according to an embodiment of the present invention.

[0011] Figure 5 This is a diagram illustrating a power supply noise sensitivity testing system according to an embodiment of the present invention.

[0012] Figure 6 This is a diagram illustrating multiple power supply noise sensitivity testing systems according to embodiments of the present invention.

[0013] Figure 7 This is a diagram illustrating a power supply noise injection module according to an embodiment of the present invention. Detailed Implementation

[0014] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. However, the invention may be implemented in different forms and therefore should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. Throughout this disclosure, the same reference numerals refer to the same parts in the drawings and embodiments of the invention.

[0015] This invention can be implemented in many ways, including: processes; apparatus; systems; computer program products implemented on computer-readable storage media; and / or processors, such as processors adapted to execute instructions stored in and / or provided by memory coupled to the processor. In this specification, these embodiments or any other forms in which the invention may take may be referred to as technical solutions. Generally, the order of steps of the disclosed processes can be changed within the scope of this invention. Unless otherwise stated, components described as suitable for performing a task, such as processors or memory, may be implemented as general components temporarily configured to perform that task at a given time or manufactured as specific components to perform that task. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores suitable for processing data such as computer program instructions.

[0016] The following detailed description of embodiments of the invention is provided in conjunction with the accompanying drawings illustrating aspects of the invention. The invention is described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention is defined only by the claims. The invention is covered by numerous alternatives, modifications, and equivalents within the scope of the claims. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes; the invention may be practiced without some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0017] For many years, power supply noise sensitivity testing, or power supply noise injection testing, has been used to screen storage devices such as hard disk drives (HDDs) and solid-state drives (SSDs). This test involves injecting sinusoidal or square wave noise with a specific amplitude and frequency into the power rails of the storage device. Furthermore, it checks whether the storage device can function properly without errors, malfunctions, or performance degradation. When these tests are applied to different computer or server platforms with a wide range of power quality and integrity, they ensure the quality and reliability of the storage devices.

[0018] Figures 1 to 3 An example of a power supply noise sensitivity testing system for storage devices is shown in the figure.

[0019] like Figures 1 to 3 As shown, the power supply noise sensitivity test system may include: a power supply 51 or 71, a function generator 52 or 72, a storage device under test (hereinafter referred to as storage device) 54 or 74, an oscilloscope 55 or 75, and a test computer 56 or 76. Further, the power supply noise sensitivity test system may include a power supply noise injection component. Various methods can be used to implement the power supply noise injection component.

[0020] exist Figure 1 In this embodiment, the power supply noise injection component can be implemented using the transformer induction component 53. Figure 2 In this embodiment, the power supply noise injection component can be implemented using capacitor 61 and inductor 62. Figure 3In one embodiment, the power supply noise injection component can be implemented using the power amplifier direct injection component 73. These embodiments are described in U.S. Patent Application Serial No. 16 / 834,464, entitled "Noise Injection for Power Noise Susceptibility Test for Memory Systems," which is incorporated herein by reference in its entirety.

[0021] Power supply 51 or 71 can generate a power supply voltage (e.g., +5V or +8 to 12V). Function generator 52 or 72 can generate noise or a noise function (e.g., noise + or {+1V offset + noise}). Oscilloscope 55 or 75 can measure voltages that vary over time (a combination of positive power supply voltage and power supply noise). Test computer 56 or 76 can be coupled to storage device 54 or 74.

[0022] As mentioned above, Figures 1 to 3 Three different power noise injection methods are shown in power noise sensitivity testing for storage devices, such as solid-state drives (SSDs). Because these methods have different bandwidth limitations, no single method can fully cover the bandwidth required by many SSD users (e.g., test bandwidth from DC to 30MHz).

[0023] Figure 1 and Figure 3 The method works at lower frequency bands. Figure 1 The method typically operates at frequencies below 100 kHz. Figure 3 This method works best at frequencies below 500kHz, but compared to... Figure 1 Compared to transformer induction methods, this method offers better performance and a stronger linear response. In contrast, Figure 2 The method operates at higher frequency bands (e.g., greater than or equal to 100 kHz and up to approximately 50 MHz). At lower frequencies below 100 kHz, little noise may couple to the power supply (i.e., power supply 51) due to the low-frequency blocking characteristics of capacitor 61.

[0024] In the embodiments described above, power supply noise sensitivity tests for storage devices must be performed separately on different test benches to cover noise frequencies ranging from low (DC to 100 kHz) to high (100 kHz to 20–30 MHz, and in some cases up to 50 MHz) as needed.

[0025] To cover the entire frequency band, the operator only needs to use Figure 1 or Figure 2The connection settings are used to test noise sensitivity below 100kHz. Testing noise sensitivity from 100kHz to 50MHz requires manual adjustment. Figure 3 Connection settings are configured. Noise frequency and amplitude scanning can be done manually or remotely via test scripts. Result monitoring and recording can also be done manually or automatically.

[0026] The implementation methods described above are easy to build and use. However, they have several drawbacks: 1) Manual operation means slower testing speeds and a higher risk of human error; 2) Test circuit settings need to be changed during testing, which takes a long time and carries the risk of human error; 3) Only one SSD can be tested at a time, making it difficult to use for large-scale SSD testing; 4) Many circuit boards are needed to cover different SSD form factors: 12V for U.2 SSDs and 3.3V for M.2 SSDs; and 5) An external power supply is required and manual adjustment is necessary. Therefore, it is desirable to provide an automated power noise sensitivity testing platform (or system) that supports the entire frequency band.

[0027] The embodiments can provide two automated full-bandwidth power supply noise sensitivity testing systems. Figure 4 and Figure 5 These embodiments are described herein. They are by way of example and without any limitation. Figure 4 The embodiments are for SSD form factors such as U.2, U.3, or enterprise and data center SSD form factors (EDSFF), while Figure 5 Examples of these embodiments are used for SSD form factors such as M.2. Furthermore, these embodiments can provide a modular, automated full-bandwidth power noise sensitivity testing system. Utilizing Figure 6 and Figure 7 This embodiment is described. As shown in Listing 1, some acronyms and abbreviations are used in the description. Figures 4 to 7 The testing system.

[0028] List 1:

[0029]

[0030] Figure 4 This is a diagram illustrating a power supply noise sensitivity testing system 400 according to an embodiment of the present invention. Although Figure 4 Not shown, but the power supply noise sensitivity test system 400 may include, for example, Figures 1 to 3 The diagram shows a function generator, the storage device under test, an oscilloscope, and a test computer. However, because this test platform uses direct data from sources such as... Figure 6 The PCIe-based host or server shown receives a 12V power supply voltage, therefore no external power supply is required.

[0031] Reference Figure 4The power supply noise sensitivity testing system 400 may include a first relay 410, a second relay 420, and a third relay 430. The first relay 410 and the third relay 430 may be coupled via a first path Path1 or a second path Path2.

[0032] The first relay 410 can receive a power supply voltage (e.g., 12V) and output the power supply voltage (12V) to either the first path Path1 or the second path Path2 in response to a frequency selection signal LF / HFSELECT. In some embodiments, the power supply voltage can be received freely. Figure 6 The power supply of the host shown.

[0033] The second relay 420 can receive the noise function FG IN and output the noise function FG IN to the first path Path1 in response to the frequency selection signal LF / HF SELECT.

[0034] The third relay 430 can be coupled to the first path Path1 or the second path Path2 and the storage device (e.g., U.2 SSD).

[0035] The first path, Path1, may include an operational amplifier OPAMP 442 and a capacitor injection circuit 444. OPAMP 442 may receive a noise function FGIN and generate a high noise function HFNOISE in response to a supply voltage (12V). The capacitor injection circuit 444 may receive the supply voltage (12V), the noise function FGIN, and the high noise function HFNOISE, and generate a low noise function LF NOISE and a first supply noise, the first supply noise corresponding to the sum of the supply voltage and the high noise function (12V + HF NOISE).

[0036] In some embodiments, the capacitor injection circuit 444 may utilize, for example, Figure 2 This is achieved using capacitor 61 and inductor 62 as shown. In this embodiment, inductor 62 can receive the supply voltage (12V) instead of... Figure 2 The voltage (5V) in the capacitor 61 is such that it can receive either a noise function FGIN from the second relay 420 or a high noise function (HF NOISE) from the operational amplifier 442. For example, the noise function FGIN is received from the second relay 420 in response to a frequency selection signal LF / HFSELECT corresponding to a low frequency band (e.g., logic "0"). In another example, the high noise function (HF NOISE) is received from the operational amplifier 442 in response to a frequency selection signal LF / HF SELECT corresponding to a high frequency band (e.g., logic "1").

[0037] The second path, Path2, may include a regulator 452 and a power amplifier injection circuit 454. The regulator 452 may receive a power supply voltage (12V) and regulate it to generate a regulated power supply voltage (15V) that is larger than the power supply voltage (12V). The power amplifier injection circuit PWR AMP 454 may receive the regulated power supply voltage (15V) and a low noise function (LF NOISE), and generate a second power supply noise corresponding to the sum of the power supply voltage and the LF NOISE (12V + LF NOISE).

[0038] In some embodiments, such as Figure 3 As shown, the power amplifier injection circuit PWR AMP 454 can be implemented using a power amplifier, resistor R1, and resistor R2. Figure 3 As shown, resistor R1 is coupled between the inverting terminal and the ground terminal of the power amplifier, and resistor R2 is coupled between the inverting terminal and the output terminal of the power amplifier. In this embodiment, the power amplifier can receive a regulated supply voltage (15V) from the regulator 452, instead of... Figure 3 The voltage in the circuit is (8-12V). Furthermore, the power amplifier can receive the low-noise function LF NOIISE from the capacitor injection circuit 444 via the non-inverting terminal.

[0039] The third relay 430 responds to the frequency selection signal LF / HF SELECT to selectively receive the first power supply noise (12V+HF NOISE) and the second power supply noise (12V+LF NOISE), and provides the selectively received power supply noise to the storage device (U.2SSD).

[0040] In some embodiments, the first relay 410 may include a single-pole double-throw (SPDT) power relay having a single pole configured to receive a power supply voltage (12V), a first throw coupled to a first path Path1, and a second throw coupled to a second path Path2. The SPDT power relay may supply the power supply voltage (12V) to either the first path Path1 or the second path Path2 in response to a frequency selection signal LF / HFSELECT.

[0041] In some embodiments, the second relay 420 may include a single-pole double-throw (SPDT) signal relay having a single pole configured to receive a noise function FGIN, a first throw coupled to operational amplifier 442, and a second throw coupled to capacitor injection circuit 444. The SPDT signal relay may provide the noise function FGIN to operational amplifier 442 or capacitor injection circuit 444 in response to a frequency selection signal LF / HF SELECT.

[0042] In some embodiments, the third relay 430 may include a single-pole double-throw (SPDT) power relay having a first throw coupled to a capacitor injection circuit 444, a second throw coupled to a power amplifier injection circuit 454, and a single pole coupled to a storage device (U.2SSD). The SPDT power relay may selectively supply a first power supply noise (12V+HF NOISE) and a second power supply noise (12V+LFNOISE) to the storage device in response to a frequency selection signal LF / HF SELECT.

[0043] In some embodiments, the detailed selection and design of relays 410 to 430, operational amplifier 442, regulator 452, and power amplifier injection circuit 454 can vary depending on the test platform specifications. In one embodiment, a heat sink may be used for the power amplifier injection circuit 454.

[0044] In some embodiments, Figure 6 The function generator and host in the system can be used in the power supply noise sensitivity test system 400. Figure 2 and Figure 3 Remote control of the function generator in the context can be as follows: Figure 6 The example shown uses a single software suite (e.g., LabVIEW) or custom scripts via GPIB, USB, or Ethernet (ETHER NET). The host can run custom I / O test scripts, FIO, or an IOmeter with logging capabilities.

[0045] In some embodiments, the LF / HF SELECT signal can be received freely. Figure 6 The host shown has an expansion USB I / O card (e.g., a GPIO card).

[0046] When the signal LF / HF SELECT equals logic level "0", it drives three SPDT relays 410, 420, and 430 to the normally closed (NC) position. Noise FGIN is supplied to the power amplifier injection circuit 454, and the power supply voltage (12V) is also supplied to the power amplifier injection circuit 454. Therefore, as... Figure 3 The power amplifier injection circuit 454 shown for low-frequency testing is enabled, and the output of the power amplifier injection circuit 454 is provided to the storage device via the SPDT relay 430.

[0047] When the signal LF / HF SELECT equals logic level "1", it drives three SPDT relays 410, 420, and 430 to the normally open (NO) position. Noise FGIN is supplied to operational amplifier 442, and the power supply voltage (12V) is supplied to operational amplifier 442 and capacitor injection circuit 444. Therefore, as... Figure 2 The capacitor injection circuit 444 shown for high-frequency testing is enabled, and the output of the capacitor injection circuit 444 is provided to the storage device via the SPDT relay 430.

[0048] As described above, the power supply noise sensitivity test system 400 utilizes three remotely controlled SPDT relays to automatically switch between low and high test frequencies. The test platform eliminates risky manual operation and significantly reduces overall test time. This test platform can be cost-effective for small-scale testing using workstations or low-end servers.

[0049] Figure 5 This is a diagram illustrating a power supply noise sensitivity testing system 500 according to an embodiment of the present invention.

[0050] Reference Figure 5 The structure and operation of the power supply noise sensitivity test system 500 can be similar to those of the power supply noise sensitivity test system 400. The difference is that the power supply noise sensitivity test system 500 uses the power supply voltage (3.3V) from an external power source of the storage device (e.g., an M.2 SSD), instead of the power supply voltage (12V) from the host power source of the storage device (e.g., a U.2 SSD). Furthermore, the power supply noise sensitivity test system 500 includes a first path Path1, which includes a regulator 542.

[0051] Specifically, the power supply noise sensitivity testing system 500 may include a first relay 510, a second relay 520, and a third relay 530. The first relay 510 and the third relay 530 may be coupled via a first path Path1 or a second path Path2. The first relay 510, the second relay 520, and the third relay 530 may each have... Figure 4 The first relay 510, the second relay 520 and the third relay 530 have the same structure and operation.

[0052] The first path Path1 may include a first regulator 542, an operational amplifier OPAMP 544, and a capacitor injection circuit 546. The operational amplifier OPAMP 544 and the capacitor injection circuit 546 respectively correspond to... Figure 4The circuit includes an operational amplifier OPAMP 442 and a capacitor injection circuit 444. A first regulator 542 receives a power supply voltage (3.3V) and regulates it to generate a first regulated power supply voltage (12V) greater than the power supply voltage (3.3V). The operational amplifier 544 receives a noise function FGIN and generates a high noise function HF NOISE in response to the first regulated power supply voltage (12V). The capacitor injection circuit 546 receives the power supply voltage (3.3V), the noise function FGIN, and the high noise function HF NOISE, and generates a low noise function LF NOISE and a first power supply noise, the first power supply noise corresponding to the sum of the power supply voltage and the high noise function {3.3V + HF NOISE}.

[0053] The second path Path2 may include a second regulator 552 and a power amplifier injection circuit 554. The second regulator 552 and the power amplifier injection circuit 554 respectively correspond to... Figure 4 The second regulator 552 receives a power supply voltage (3.3V) and adjusts it to generate a second regulated power supply voltage (8V) that is larger than the power supply voltage (3.3V). The power amplifier injection circuit 554 receives the second regulated power supply voltage (8V) and a low noise function (LF NOISE), and generates a second power supply noise corresponding to the sum of the power supply voltage and the low noise function {3.3V + LF NOISE}.

[0054] The third relay 530 responds to the frequency selection signal LF / HF SELECT to selectively receive the first power supply noise {3.3V+HF NOISE} and the second power supply noise {3.3V+LF NOISE}, and provides the selectively received power supply noise to the storage device (M.2 SSD).

[0055] As mentioned above, the M.2 SSD test platform uses Figure 5 The different power supply noise injections are shown. Although the signal LF / HF SELECT is used in conjunction with... Figure 4 The three SPDT relays operate and control in the same way, but with the following differences. First, there is an additional regulator that boosts the 3.3V to 12V to generate HF noise via operational amplifier 544. The power amplifier injection circuit 554 in this test platform uses the boosted 8V to reduce the voltage across the input and output of the amplifier to reduce heat dissipation. Figure 5 The rated current of the SPDT relay should be higher than Figure 4 The rated current in the circuit. The power amplifier injection circuit 554 also requires a heatsink. Remote control functionality remains the same as the U.2 SSD test platform 400. This M.2 test platform offers the same advantages as the U.2 test platform.

[0056] Figure 6 This is a diagram illustrating a plurality of power supply noise sensitivity testing systems 600 according to an embodiment of the present invention. Figure 4 and Figure 5 The main upgrade of the single SSD test platform described herein lies in the hardware (HW) architecture of the Test System 600, which enables the simultaneous testing of multiple storage devices (e.g., 4, 8, 16, or 32 SSDs). This test platform may be ideal for large-scale SSD power noise sensitivity screening.

[0057] Reference Figure 6 The multi-supply noise sensitivity testing system 600 may include a host 610, a function generator 620, an input / output (I / O) card 630, multiple storage devices (e.g., SSDs) 641 to 64N, and a multi-noise injection backplane 650. The host 610 may include a power supply (not shown) configured to provide a supply voltage (e.g., 12V) to the multi-noise injection backplane 650.

[0058] In some embodiments, host 610 may be a high-performance server with multiple PCIe lanes. For example, for 32 SSDs, it has at least one x16, and preferably two x16 lanes from host 610. Host 610 may be able to output high current at 12V (up to 100A for 32 SSDs), which would otherwise require an external high-current power supply. Figure 6 The power sequence and protection circuit are not shown.

[0059] Function generator 620 can be coupled to host 610 via a setup bus (e.g., GPIB, USB, or Ethernet) to generate a noise function (or noise) and provide the noise function to multi-noise injection backplane 650. Input / output (I / O) card 630, acting as a signal generator, can be coupled to host 610 via a setup bus (e.g., USB) to generate various operating signals and provide the operating signals to multi-noise injection backplane 650. In some embodiments, the operating signals may include a frequency selection signal LF / HF SELECT and a storage device selection signal U.2 12V / M.2 3.3VSELECT.

[0060] Multiple storage devices 641 to 64N can be coupled to a multi-noise injection backplane 650 via one or more multi-connectors 680 and one or more multi-SSD adapters 690. Further, the multi-noise injection backplane 650 can be coupled to a host 610 via multiple high-speed peripheral component interconnect (PCIe) links. In the example shown, the host 610 can be coupled to the multi-noise injection backplane 650 via 16 PCIe links.

[0061] The multi-noise injection backplane 650 may include multi-noise injection modules 701 to 70N for testing the power supply noise sensitivity of multiple storage devices 641 to 64N. Further, the multi-noise injection backplane 650 may include a buffer array 660, an N-channel PCIe multiplexer (MUX) 670, a multi-connector 680, and a multi-SSD adapter 690. In other words, the multi-noise injection backplane 650 has a complex modular backplane design with PCIe MUX circuitry, typically used in server system designs to link multiple SSDs.

[0062] A power supply voltage (12V) from the host 610 can be provided to each of the multiple noise injection modules 701 to 70N. Each of the multiple noise injection modules 701 to 70N can receive a frequency selection signal LF / HF SELECT and a storage device selection signal U.2 12V / M.2 3.3V SELECT from the I / O card 630. Each of the multiple noise injection modules 701 to 70N can receive a noise function from the function generator 620 through a buffer array 660. In some embodiments, the buffer array 660 may include multiple buffers between the function generator 620 and the multiple noise injection modules 701 to 70N, and each buffer corresponds to a corresponding one of the multiple noise injection modules 701 to 70N. Each buffer can receive and store the noise function and output the noise function to the corresponding noise injection module among the multiple noise injection modules 701 to 70N. Therefore, each of the multiple noise injection modules 701 to 70N can receive a noise function from the function generator 620 through the corresponding buffer of the buffer array 660.

[0063] Each of the multiple noise injection modules 701 to 70N can be coupled to a corresponding storage device among the multiple storage devices 641 to 64N via a corresponding multiple connector 680 and a corresponding multiple SSD adapter 690. Furthermore, each of the multiple noise injection modules 701 to 70N can provide power supply noise {PWR+NOISE} for testing to a corresponding storage device among the multiple storage devices 641 to 64N.

[0064] The Multi-Noise Injection Backplane 650 offers the following advantages: 1) Fully automated with minimal risk of human error; 2) Full-bandwidth testing using only one function generator; 3) Simultaneous testing of one to thirty-two drives, saving total testing time; 4) Independent and replaceable noise injection modules for each drive; 5) Independent and replaceable SSD adapters for each drive; 6) Noise injection modules can handle different SSD form factors; 7) Ideal for large-scale SSD screening, where a drive failure will not affect other drives; and 8) Works even with only one drive.

[0065] Figure 7This is a diagram illustrating a power supply noise injection module 700 according to an embodiment of the present invention. The power supply noise injection module 700 may be... Figure 6 Any one of the multiple noise injection modules 701 to 70N in the system.

[0066] Reference Figure 7 The power supply noise injection module 700 can have a similar Figure 4 The structure and operation of the power supply noise sensitivity testing system 400 are described below. The difference lies in that the power supply noise injection module 700 generates a first power supply noise in the high-frequency band (i.e., high power supply noise) {PWR+HF NOISE}, namely {3.3V+HF NOISE} or {12V+HF NOISE}, and generates a second power supply noise in the low-frequency band (i.e., low power supply noise) {PWR+LF NOISE}, namely {3.3V+LF NOISE} or {12V+LFNOISE}. For this operation, the power supply noise injection module 700 may include variable regulators 742 and 745.

[0067] Specifically, the power supply noise injection module 700 may include a first relay 710, a second relay 720, and a third relay 730. The first relay 710 and the third relay 730 may be coupled via a first path Path1 or a second path Path2. The first relay 710, the second relay 720, and the third relay 730 may each have... Figure 4 The first relay 510, the second relay 520 and the third relay 530 have the same structure and operation.

[0068] The first path, Path1, may include an operational amplifier OPAMP 744 and a capacitor injection circuit 746. The operational amplifier OPAMP 744 and the capacitor injection circuit 746 respectively correspond to... Figure 4 The operational amplifier OPAMP 442 and capacitor injection circuit 444 are included. Further, the first path Path1 may include a first variable regulator 742.

[0069] The first variable regulator 742 can receive and adjust the power supply voltage (12V) to generate a first regulated power supply voltage (3.3V or 12V) in response to the storage device selection signal U.2 12V / M.2 3.3V SELECT. For example, the first variable regulator 742 can generate a first regulated power supply voltage (3.3V) in response to the storage device selection signal M.2 3.3V SELECT, and a first regulated power supply voltage (12V) in response to the storage device selection signal U.2 12V SELECT.

[0070] Operational amplifier 744 can receive the noise function FGIN and generate a high noise function HF NOISE in response to a first regulated supply voltage (12V). Capacitor injection circuit 746 can receive the supply voltage (3.3V or 12V), the noise function FGIN, and the high noise function HF NOISE, and generate a low noise function LF NOISE and a first supply noise, the first supply noise corresponding to the sum of the supply voltage and the high noise function {(3.3V + HF NOISE) or (12V + HF NOISE)}.

[0071] The second path, Path2, may include a second variable regulator 752 and a power amplifier injection circuit 754. The power amplifier injection circuit 754 corresponds to... Figure 4 The power amplifier injection circuit 454 in the middle.

[0072] The second variable regulator 752 can receive and adjust the power supply voltage (12V) to generate a second regulated power supply voltage (8V or 15V) in response to the storage device select signal U.2 12V / M.2 3.3V SELECT. For example, the second variable regulator 752 can generate a second regulated power supply voltage (8V) in response to the storage device select signal M.2 3.3V SELECT, and a second regulated power supply voltage (15V) in response to the storage device select signal U.2 12V SELECT. The power amplifier injection circuit 754 can receive the second regulated power supply voltage (8V or 15V) and the low noise function LF NOISE, and generate a second power supply noise corresponding to the sum of the power supply voltage and the low noise function {(3.3V + LF NOISE) or (12V + LF NOISE)}.

[0073] The third relay 530 responds to the frequency selection signal LF / HF SELECT to selectively receive a first power supply noise {3.3V+HF NOISE} or {12V+HF NOISE} and a second power supply noise {3.3V+LF NOISE} or {12V+LFNOISE}, and provides the selectively received power supply noise to the storage device (M.2 SSD).

[0074] As described above, the embodiments provide a system for testing the power supply noise sensitivity of one or more storage devices. The embodiments automatically test the power supply noise sensitivity of one or more storage devices and support full-bandwidth testing.

[0075] While the foregoing embodiments have been shown and described in considerable detail for clarity and understanding, the invention is not limited to the details provided. As will be understood by those skilled in the art based on the foregoing disclosure, many alternatives exist for implementing the invention. Therefore, the disclosed embodiments are illustrative and not restrictive. The invention is intended to cover all modifications falling within the scope of the appended claims.

Claims

1. A power supply noise sensitivity testing system, comprising: The host unit, including the power supply that provides the power voltage; Multiple storage devices are coupled to the host via multiple high-speed peripheral component interconnect links, i.e., multiple PCIe links; as well as A multi-noise injection module is used to test the power supply noise sensitivity of the multiple storage devices. Each noise injection module includes: The first relay receives the power supply voltage and, in response to a frequency selection signal, outputs the power supply voltage to a first path or a second path. A second relay receives a noise function and, in response to the frequency selection signal, outputs the noise function to either the first path or the second path; and A third relay is coupled to either the first path or the second path and the storage device. The first path includes: An operational amplifier receives the noise function and generates a high noise function in response to the power supply voltage; A first variable regulator receives and regulates the power supply voltage to generate a first regulated power supply voltage or a second regulated power supply voltage in response to a voltage selection signal; and A capacitor injection circuit receives the first regulated power supply voltage or the second regulated power supply voltage, the noise function, and the high noise function, and generates a low noise function and a first power supply noise, wherein the first power supply noise corresponds to the sum of the first regulated power supply voltage or the second regulated power supply voltage and the high noise function. The second path includes: A second variable regulator receives and regulates the power supply voltage to generate a third or fourth regulated power supply voltage in response to the voltage selection signal; and The power amplifier injection circuit receives the third regulated power supply voltage or the fourth regulated power supply voltage and the low noise function, and generates a second power supply noise corresponding to the sum of the third regulated power supply voltage or the fourth regulated power supply voltage and the low noise function. The third relay selectively receives the first power supply noise and the second power supply noise in response to the frequency selection signal, and provides the selectively received power supply noise to the storage device.

2. The system of claim 1, wherein the first relay comprises a single-pole double-throw relay, i.e., an SPDT relay, and in response to the frequency selection signal, provides the power supply voltage to the first path or the second path, the SPDT relay having a single pole for receiving the power supply voltage, a first throw coupled to the first path, and a second throw coupled to the second path.

3. The system of claim 1, wherein the second relay comprises a single-pole double-throw relay, i.e., an SPDT relay, and provides the noise function to the operational amplifier or the capacitor injection circuit in response to the frequency selection signal, the SPDT relay having a single pole for receiving the noise function, a first throw coupled to the operational amplifier, and a second throw coupled to the capacitor injection circuit.

4. The system of claim 1, wherein the third relay comprises a single-pole double-throw relay, i.e., an SPDT relay, and selectively provides the first power supply noise and the second power supply noise to the storage device in response to the frequency selection signal, the SPDT relay having a first throw coupled to the capacitor injection circuit, a second throw coupled to the power amplifier, and a single-pole coupled to the storage device.

5. The system of claim 1, wherein one of the plurality of storage devices includes a U.2 solid-state drive, i.e., a U.2 SSD, and another of the plurality of storage devices includes an M.2 SSD.

6. The system of claim 1, wherein the power supply voltage and the second regulated power supply voltage have a first voltage level, and the first regulated power supply voltage has a second voltage level that is lower than the first voltage level.

7. The system of claim 1, wherein the power supply voltage has a first voltage level, the third regulated power supply voltage has a second voltage level lower than the first voltage level, and the fourth regulated power supply voltage has a third voltage level higher than the first voltage level.

8. The system according to claim 1, further comprising: A function generator generates the noise function.

9. The system according to claim 8, further comprising: The buffer array includes multiple buffers coupled between the function generator and the multiple noise injection module, each buffer receiving and storing the noise function and outputting the noise function to a corresponding noise injection module in the multiple noise injection module.

10. The system according to claim 1, further comprising: A signal generator generates the frequency selection signal and the voltage selection signal.

11. A system for testing the power supply noise sensitivity of a storage device, the system comprising: The first relay receives the power supply voltage and, in response to a frequency selection signal, outputs the power supply voltage to either the first path or the second path. The second relay receives the noise function and, in response to the frequency selection signal, outputs the noise function to the first path; as well as A third relay is coupled to either the first path or the second path and the storage device. The first path includes: An operational amplifier that receives the noise function and generates a high noise function in response to the power supply voltage; and A capacitor injection circuit receives the power supply voltage, the noise function, and the high noise function, and generates a low noise function and a first power supply noise, the first power supply noise corresponding to the sum of the power supply voltage and the high noise function. The second path includes: A regulator that receives the power supply voltage and regulates the power supply voltage to generate a regulated power supply voltage; and The power amplifier injection circuit receives the regulated power supply voltage and the low-noise function, and generates a second power supply noise corresponding to the sum of the power supply voltage and the low-noise function. The third relay selectively receives the first power supply noise and the second power supply noise in response to the frequency selection signal, and provides the selectively received power supply noise to the storage device.

12. The system of claim 11, wherein the first relay comprises a single-pole double-throw relay, i.e., an SPDT relay, and in response to the frequency selection signal, provides the power supply voltage to the first path or the second path, the SPDT relay having a single pole for receiving the power supply voltage, a first throw coupled to the first path, and a second throw coupled to the second path.

13. The system of claim 11, wherein the second relay comprises a single-pole double-throw relay, i.e., an SPDT relay, and provides the noise function to the operational amplifier or the capacitor injection circuit in response to the frequency selection signal, the SPDT relay having a single pole for receiving the noise function, a first throw coupled to the operational amplifier, and a second throw coupled to the capacitor injection circuit.

14. The system of claim 11, wherein the third relay comprises a single-pole double-throw relay, i.e., an SPDT relay, and selectively provides the first power supply noise and the second power supply noise to the storage device in response to the frequency selection signal, the SPDT relay having a first throw coupled to the capacitor injection circuit, a second throw coupled to the power amplifier, and a single-pole coupled to the storage device.

15. The system of claim 11, wherein the power supply voltage is received from the power supply of the host, and the storage device includes a U.2 solid-state drive, i.e., a U.2 SSD.

16. A system for testing the power supply noise sensitivity of a storage device, the system comprising: The first relay receives the power supply voltage and, in response to a frequency selection signal, outputs the power supply voltage to either the first path or the second path. The second relay receives the noise function and, in response to the frequency selection signal, outputs the noise function to the first path or the second path; as well as A third relay is coupled to either the first path or the second path and the storage device. The first path includes: A first regulator receives the power supply voltage and adjusts the power supply voltage to generate a first regulated power supply voltage; An operational amplifier that receives the noise function and generates a high noise function in response to the first regulated power supply voltage; and A capacitor injection circuit receives the power supply voltage, the noise function, and the high noise function, and generates a low noise function and a first power supply noise, the first power supply noise corresponding to the sum of the power supply voltage and the high noise function. The second path includes: A second regulator receives the power supply voltage and adjusts the power supply voltage to generate a second regulated power supply voltage; and The power amplifier injection circuit receives the second regulated power supply voltage and the low-noise function, and generates a second power supply noise corresponding to the sum of the power supply voltage and the low-noise function. The third relay selectively receives the first power supply noise and the second power supply noise in response to the frequency selection signal, and provides the selectively received power supply noise to the storage device.

17. The system of claim 16, wherein the first relay comprises a single-pole double-throw relay, i.e., an SPDT relay, and in response to the frequency selection signal, provides the power supply voltage to the first path or the second path, the SPDT relay having a single pole for receiving the power supply voltage, a first throw coupled to the first path, and a second throw coupled to the second path.

18. The system of claim 16, wherein the second relay comprises a single-pole double-throw relay, i.e., an SPDT relay, and provides the noise function to the operational amplifier or the capacitor injection circuit in response to the frequency selection signal, the SPDT relay having a single pole for receiving the noise function, a first throw coupled to the operational amplifier, and a second throw coupled to the capacitor injection circuit.

19. The system of claim 16, wherein the third relay comprises a single-pole double-throw relay, i.e., an SPDT relay, and selectively provides the first power supply noise and the second power supply noise to the storage device in response to the frequency selection signal, the SPDT relay having a first throw coupled to the capacitor injection circuit, a second throw coupled to the power amplifier, and a single-pole coupled to the storage device.

20. The system of claim 16, wherein the power supply voltage is received from an external power source, and the storage device includes an M.2 solid-state drive, i.e., an M.2 SSD.

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