A method for optimizing shallow trench etching morphology

Abstract

The invention provides a method for optimizing the morphology of shallow trench etching. The semiconductor structure comprises a silicon substrate and a first material layer located on the silicon substrate. The first material layer forms a groove on the silicon substrate. The bottom of the groove exposes the upper surface of the silicon substrate. A second material layer is formed on the surface in the groove and the upper surface of the first material layer structure on both sides of the groove; the second material layer and the silicon substrate are etched downward along the surface of the second material layer on the inner side wall of the groove, and a deep trench is formed after the silicon substrate is etched; the deep trench is filled, and nitride is etched back along the side wall of the deep trench until a part of the side wall of the deep trench is exposed; an oxide film is deposited, and the oxide films on the upper surfaces of the first and second material layers and the upper surface of the remaining nitride are etched away, and the oxide films on the side walls of the silicon substrate and the side walls of the second material layer are retained; the remaining nitride is removed; epitaxial silicon is grown to fill the position of the removed nitride; after the epitaxial silicon is grown, a shallow trench is formed between the upper surface of the epitaxial silicon and the exposed side wall of the silicon substrate.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for optimizing shallow trench etching morphology. Background Art

[0002] In the Super Flash process, there are very high requirements for the shallow trench etching process. In the cell area (CELL area), since titanium nitride (TiN) exists as a floating gate in the SF process, electrons are stored through the channel and discharged through the top tip. When TiN is deposited, if the previous trench profile is recessed, it will affect the performance of the entire CELL, and it may even be easily connected to the CG (control gate) tungsten (W) in the subsequent process to cause a short circuit and breakdown, making the entire CELL function unable to work. When the trench depth is shallow (less than 20nm), the side wall profile is required to be vertical (greater than 88 degrees) and the bottom profile is required to be horizontal; the current process cannot meet this requirement.

[0003] In the prior art, in the super flash process, the silicon sidewall morphology cannot be made vertical during shallow trench etching (less than 20nm), and micro trench protrusions are easily formed at the bottom and the surface is not flat enough. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for optimizing the shallow trench etching morphology, so as to solve the problem that the bottom of the trench is prone to unevenness after shallow trench etching in the prior art.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a method for optimizing shallow trench etching morphology, which at least comprises:

[0006] Step 1, providing a semiconductor structure, the semiconductor structure comprising a silicon substrate, a first material layer located on the silicon substrate, the first material layer forming a groove on the silicon substrate, the bottom of the groove exposing the upper surface of the silicon substrate, and a second material layer formed on the surface inside the groove and the upper surface of the first material layer structure on both sides of the groove;

[0007] Step 2: etching the second material layer and the silicon substrate downward along the surface of the second material layer on the inner side wall of the groove, so that a deep groove is formed on the silicon substrate after etching;

[0008] Step 3: Filling the deep trench with nitride until the deep trench covers the upper surfaces of the first material layer and the second material layer;

[0009] Step 4: etching back the nitride along the sidewall of the deep trench until a portion of the sidewall of the deep trench is exposed; the depth from the bottom of the exposed sidewall of the silicon substrate to the upper surface of the silicon substrate is the depth of the shallow trench;

[0010] Step 5: depositing a layer of oxide film, wherein the oxide film covers the remaining upper surface of the nitride, the exposed sidewalls of the silicon substrate, the sidewalls and top of the second material layer, and the upper surface of the first material layer;

[0011] Step 6: removing the oxide film on the upper surfaces of the first and second material layers and the remaining upper surface of the nitride by high selectivity etching, and retaining the oxide film on the side wall of the silicon substrate and the side wall of the second material layer;

[0012] Step 7, removing the remaining nitride; then epitaxially growing silicon to fill the position of the removed nitride; after the epitaxial silicon, a shallow groove is formed between the upper surface and the exposed side wall of the silicon substrate; the contour formed by the oxide film attached to the side wall of the second material layer constitutes an opening;

[0013] Step 8: forming a sidewall attached to the oxide film on the sidewall in the shallow trench, the sidewall extending from the sidewall at the upper end of the opening to the sidewall at the bottom of the shallow trench;

[0014] Step nine: filling tungsten in the shallow trench and filling it up to the opening that penetrates the shallow trench.

[0015] Preferably, the second material layer in step one is silicon oxide.

[0016] Preferably, the depth of the deep trench in step 2 is the depth from the upper surface of the silicon substrate to the bottom of the deep trench; the depth of the deep trench is greater than 50 nm.

[0017] Preferably, the depth of the shallow groove in step 4 is less than 20 nm.

[0018] Preferably, the nitride in step 4 is silicon nitride.

[0019] Preferably, the oxide in step five is silicon oxide.

[0020] Preferably, the thickness of the oxide film in step six is ​​2 nm.

[0021] Preferably, the high selectivity etching in step six means that the etching selectivity ratio of the oxide and the nitride is 7:1 to 10:1.

[0022] Preferably, in step seven, the remaining nitride is removed by phosphoric acid.

[0023] Preferably, the depth of the shallow trench in step seven is: the distance from the upper surface of the epitaxial silicon to the upper surface of the silicon substrate, and the depth of the shallow trench is less than 20 nm.

[0024] As described above, the method for optimizing the shallow trench etching morphology of the present invention has the following beneficial effects: the present invention first etches a deep trench, fills a nitride film, then etches back to a certain depth, deposits oxide, and retains the oxide sidewall by high selectivity etching. Nitride is removed by a high selectivity chemical solution, and an epitaxial silicon process grows on the silicon surface to complete the trench filling and form a shallow trench with good morphology. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 9 It is a schematic diagram of the cross-sectional structure of each process stage of forming a shallow trench in the present invention;

[0026] Fig.10 Shown is a schematic flow chart of the method for optimizing shallow trench etching morphology in the present invention. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] See also Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0029] The present invention provides a method for optimizing shallow trench etching morphology, such as Fig.10 As shown, Fig.10 The flowchart of the method for optimizing the shallow trench etching morphology in the present invention is shown, and the method at least comprises the following steps:

[0030] Step 1, providing a semiconductor structure, the semiconductor structure comprising a silicon substrate, a first material layer located on the silicon substrate, the first material layer forming a groove on the silicon substrate, the bottom of the groove exposing the upper surface of the silicon substrate, and a second material layer formed on the surface inside the groove and the upper surface of the first material layer structure on both sides of the groove;

[0031] According to the present invention, the second material layer in step 1 of this embodiment is silicon oxide.

[0032] like Figure 1 As shown, in step 1, the semiconductor structure is provided, and the semiconductor structure includes a silicon substrate 01, and a first material layer 02 located on the silicon substrate 01, wherein the first material layer 02 forms a groove on the silicon substrate, and the bottom of the groove exposes the upper surface of the silicon substrate, and the surface inside the groove and the upper surface of the first material layer structure 02 on both sides of the groove are formed with a second material layer 03;

[0033] According to the present invention, the second material layer in step 1 of this embodiment is silicon oxide.

[0034] Step 2: etching the second material layer and the silicon substrate downward along the surface of the second material layer on the inner side wall of the groove, so that a deep groove is formed on the silicon substrate after etching;

[0035] The present invention further has a depth of the deep trench in step 2 of this embodiment of the present invention, which is the depth from the upper surface of the silicon substrate to the bottom of the deep trench; and the depth of the deep trench is greater than 50 nm.

[0036] like Figure 2 As shown, in step 2, the second material layer 03 and the silicon substrate 01 are etched downward along the surface of the second material layer 03 on the inner side wall of the groove, and a deep groove is formed on the silicon substrate 01 after etching;

[0037] The present invention further has a depth of the deep trench in step 2 of this embodiment of the present invention, which is the depth from the upper surface of the silicon substrate to the bottom of the deep trench; and the depth of the deep trench is greater than 50 nm.

[0038] Step three, filling the deep trench with nitride until the deep trench covers the upper surface of the first material layer and the second material layer; Figure 3 As shown, in step three, the deep trench is filled with nitride 04 until the deep trench covers the upper surfaces of the first material layer 02 and the second material layer 03 .

[0039] Step 4: etching back the nitride along the sidewall of the deep trench until a portion of the sidewall of the deep trench is exposed; the depth from the bottom of the exposed sidewall of the silicon substrate to the upper surface of the silicon substrate is the depth of the shallow trench;

[0040] According to the present invention, the depth of the shallow groove in step 4 of this embodiment is less than 20 nm.

[0041] According to the present invention, the nitride in step 4 of this embodiment is silicon nitride.

[0042] like Figure 4 As shown, in step 4, the nitride 04 is etched back along the sidewall of the deep trench until a portion of the sidewall of the deep trench is exposed; the depth from the bottom of the exposed silicon substrate sidewall to the upper surface of the silicon substrate is the depth of the shallow trench; the depth of the shallow trench in step 4 of this embodiment is less than 20nm. The nitride 04 in step 4 of this embodiment is silicon nitride.

[0043] Step 5: depositing a layer of oxide film, wherein the oxide film covers the remaining upper surface of the nitride, the exposed sidewalls of the silicon substrate, the sidewalls and top of the second material layer, and the upper surface of the first material layer;

[0044] According to the present invention, the oxide in step five of this embodiment is silicon oxide.

[0045] like Figure 5 As shown, in step five, a layer of oxide film 05 is deposited, and the oxide film 05 covers the remaining upper surface of the nitride 04, the exposed side walls of the silicon base 01, the side walls and top of the second material layer 03, and the upper surface of the first material layer 02; the oxide film 05 in step five of this embodiment is silicon oxide.

[0046] Step 6: removing the oxide film on the upper surfaces of the first and second material layers and the remaining upper surface of the nitride by high selectivity etching, and retaining the oxide film on the side wall of the silicon substrate and the side wall of the second material layer;

[0047] According to the present invention, the thickness of the oxide film in step six of this embodiment is 2 nm.

[0048] Further, the high selectivity etching in step six of this embodiment of the present invention refers to an etching selectivity ratio of the oxide and the nitride of 7:1 to 10:1.

[0049] like Figure 6 As shown, in step 6, the oxide film 05 on the upper surface of the first and second material layers and the remaining upper surface of the nitride 04 is removed by high selectivity etching, and the oxide film 05 on the side wall of the silicon substrate 01 and the side wall of the second material layer 03 is retained; the thickness of the oxide film 05 in step 6 of this embodiment is 2nm. The high selectivity etching in step 6 of this embodiment means that the etching selectivity ratio of the oxide film 05 and the nitride 04 is 7:1 to 10:1.

[0050] Step 7, removing the remaining nitride; then epitaxially growing silicon to fill the position of the removed nitride; after the epitaxial silicon, a shallow groove is formed between the upper surface and the exposed side wall of the silicon substrate; the contour formed by the oxide film attached to the side wall of the second material layer constitutes an opening;

[0051] The present invention further comprises removing the remaining nitride by phosphoric acid in step seven of this embodiment.

[0052] The present invention further has a depth of the shallow trench in step seven of this embodiment: the distance from the upper surface of the epitaxial silicon to the upper surface of the silicon substrate, and the depth of the shallow trench is less than 20 nm.

[0053] like Figure 7 and Figure 8 As shown, in step 7, the remaining nitride is removed; then epitaxial silicon 06 is grown to fill the position of the removed nitride; after epitaxial silicon 06, its upper surface and the exposed side wall of the silicon substrate form a shallow groove; the contour formed by the oxide film 05 attached to the side wall of the second material layer 03 constitutes an opening; in step 7 of this embodiment, the remaining nitride is removed by phosphoric acid. The depth of the shallow groove in step 7 of this embodiment is: the distance from the upper surface of the epitaxial silicon to the upper surface of the silicon substrate, and the depth of the shallow groove is less than 20nm.

[0054] Step 8: forming a TiN sidewall attached to the oxide film on the sidewall of the shallow trench, wherein the TiN sidewall extends from the sidewall of the upper end of the opening to the sidewall of the bottom of the shallow trench; Fig. 9 As shown, in step eight, a TiN sidewall 08 attached to the oxide film is formed on the sidewall in the shallow trench, and the TiN sidewall 08 extends from the sidewall at the upper end of the opening to the sidewall at the bottom of the shallow trench.

[0055] Step nine: fill the shallow trench with tungsten 07 until it reaches the opening that penetrates the shallow trench.

[0056] Therefore, from Fig. 9 It can be seen that the shallow groove formed by the present invention has two side walls perpendicular to the bottom, and the bottom of the shallow groove does not bulge and cause unevenness, so a shallow groove with good morphology is formed.

[0057] In summary, the present invention first etches a deep trench, fills a layer of nitride film, and then etches back to a certain depth. A layer of oxide film is deposited, and the oxide sidewalls are retained by high-selectivity etching. The nitride is removed by a high-selectivity chemical solution, and the epitaxial silicon process grows on the silicon surface and does not grow on the oxide surface, completing the filling of the trench. An excellent trench morphology is obtained, and the subsequent TiN / W deposition process is completed, and the excellent morphology is maintained. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0058] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for optimizing shallow trench etching morphology, characterized in that: At least: Step 1, providing a semiconductor structure, the semiconductor structure comprising a silicon substrate, a first material layer located on the silicon substrate, the first material layer forming a groove on the silicon substrate, the bottom of the groove exposing the upper surface of the silicon substrate, and a second material layer formed on the surface inside the groove and the upper surface of the first material layer structure on both sides of the groove; Step 2: etching the second material layer and the silicon substrate downward along the surface of the second material layer on the inner side wall of the groove, so that a deep groove is formed on the silicon substrate after etching; Step 3: Filling the deep trench with nitride until the deep trench covers the upper surfaces of the first material layer and the second material layer; Step 4: etching back the nitride along the sidewall of the deep trench until a portion of the sidewall of the deep trench is exposed; the depth from the bottom of the exposed sidewall of the silicon substrate to the upper surface of the silicon substrate is the depth of the shallow trench; Step 5: depositing a layer of oxide film, wherein the oxide film covers the remaining upper surface of the nitride, the exposed sidewalls of the silicon substrate, the sidewalls and top of the second material layer, and the upper surface of the first material layer; Step 6: removing the oxide film on the upper surfaces of the first and second material layers and the remaining upper surface of the nitride by high selectivity etching, and retaining the oxide film on the side wall of the silicon substrate and the side wall of the second material layer; Step 7, removing the remaining nitride; then epitaxially growing silicon to fill the position of the removed nitride; after the epitaxial silicon, a shallow groove is formed between the upper surface and the exposed side wall of the silicon substrate; the contour formed by the oxide film attached to the side wall of the second material layer constitutes an opening; Step 8: forming a TiN sidewall attached to the oxide film on the sidewall in the shallow trench, wherein the TiN sidewall extends from the sidewall at the upper end of the opening to the sidewall at the bottom of the shallow trench; Step nine: filling the shallow trench with tungsten until it reaches the opening that penetrates the shallow trench.

2. The method for optimizing shallow trench etching morphology according to claim 1, characterized in that: The second material layer in step one is silicon oxide.

3. The method for optimizing shallow trench etching morphology according to claim 1, characterized in that: The depth of the deep trench in step 2 is the depth from the upper surface of the silicon substrate to the bottom of the deep trench; the depth of the deep trench is greater than 50 nm.

4. The method for optimizing shallow trench etching morphology according to claim 1, characterized in that: The depth of the shallow groove in step 4 is less than 20 nm.

5. The method for optimizing shallow trench etching morphology according to claim 1, characterized in that: The nitride in step 4 is silicon nitride.

6. The method for optimizing shallow trench etching morphology according to claim 1, characterized in that: The oxide film in step five is silicon oxide.

7. The method for optimizing shallow trench etching morphology according to claim 1, characterized in that: The thickness of the oxide film in step six is ​​2 nm.

8. The method for optimizing shallow trench etching morphology according to claim 1, characterized in that: The high selectivity etching in step six means that the etching selectivity ratio between the oxide film and the nitride is 7:1 to 10:

1.

9. The method for optimizing shallow trench etching morphology according to claim 1, characterized in that: In step seven, the remaining nitride is removed by phosphoric acid.

10. The method for optimizing shallow trench etching morphology according to claim 1, characterized in that: The depth of the shallow trench in step seven is: the distance from the upper surface of the epitaxial silicon to the upper surface of the silicon substrate, and the depth of the shallow trench is less than 20 nm.

Images