A charge pump circuit structure with low power consumption and low starting current PWM modulation for AMOLED

Abstract

The present invention proposes a charge pump circuit structure of low-power and low-startup current PWM modulation for AMOLED, including a charge pump module (chargepump), a pulse width modulation module 1 (PWM1), a pulse width modulation module 2 (PWM2), a slope generation module (slope_gen), a logic module 1 (logic1), a logic module 2 (logic2) and a driver module (driver). The structure has the advantages of low power consumption, low startup current, high efficiency and small area.

Description

Technical Field

[0001] The present invention relates to the technical field of charge pumps, and in particular to a charge pump circuit structure with low power consumption and low starting current PWM modulation for AMOLED. Background Art

[0002] AMOLED stands for Active Matrix Organic Light Emitting Device display. Advantages of this display over traditional LCDs include low power consumption, manufacturing flexibility, and faster refresh rates. Compared to traditional LCDs, AMOLED displays do not have a backlight, so each pixel consists of a different color OLED that emits light independently. OLEDs emit light based on the current provided through a drive transistor, which is controlled by a programmed voltage.

[0003] The transistor itself is a nonlinear device and will show a certain resistance effect in the circuit. The resistance value of this resistor changes nonlinearly and varies according to the size of the current passing through. Studies have shown that when a MOSFET with lower on-resistance (RDSON) replaces a diode, the forward voltage drop is much lower than the forward voltage drop of a diode rectifier, so the conduction loss of the rectifier is greatly reduced.

[0004] Since the PWM modulator is used to generate adjustment signals to adjust the brightness of each OLED light-emitting unit, when the load is heavy, a charge pump circuit is required to provide a high voltage or negative voltage higher than the external power supply voltage. However, according to the charge pump characteristics: when the charge pump duty cycle is from 0 to 50%, the output voltage is from low to high, and when it is from 50% to 100%, the output voltage is from high to low. Even if the charge pump reaches the maximum output energy, it cannot meet the load requirements, and the output energy of the charge pump will decrease. The above two reasons will lead to unstable performance and high power consumption of the PWM modulation circuit.

[0005] The present invention designs a charge pump circuit structure of AMOLED with low power consumption and low starting current PWM modulation, which can obtain low starting current through logic control and can effectively avoid energy loss on RDSON tube. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a charge pump circuit structure of AMOLED with low power consumption and low starting current PWM modulation, including: a charge pump module, a pulse width modulation module 1, a pulse width modulation module 2, a ramp generation module, a logic module 1, a logic module 2 and a driving module.

[0007] The charge pump module consists of five Pmos tubes, namely Pmos2, Pmos3, Pmos4, Pmos5 and Pmos6, plus a flying capacitor C2 and a capacitor C3. The positive end of the flying capacitor C2 is connected to the drain end of Pmos2, the drain end of Pmos6 and the source end of Pmos3, and the negative end of the flying capacitor C2 is connected to the drain end of Pmos5 and the source end of Pmos4; the driving signal PH1_s is connected to the gate of Pmos2. The terminal is connected to the gate terminal of Pmos5, the driving signal PH1 is connected to the gate terminal of Pmos6, the driving signal PH2 is connected to the gate terminal of Pmos3 and the gate terminal of Pmos4, the input signal AVDD is connected to the source terminal of Pmos2 and the source terminal of Pmos6, the input signal vicb is connected to the drain terminal of Pmos4, the ground signal gnd is connected to the source terminal of Pmos5, the output signal vgh is connected to the drain terminal of pmos3 and the positive terminal of the filter capacitor C3, and the negative terminal of the filter capacitor C3 is connected to the ground signal gnd.

[0008] Among them, the pulse width modulation module 1 is composed of a voltage-dividing resistor R2, a voltage-dividing resistor R3, a voltage-dividing resistor R4, an error amplifier EA1 and a comparator COMP1, the charge pump output signal vgh is connected to one end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R2 is connected to the signal FB2 and one end of the voltage-dividing resistor R3, the other end of the voltage-dividing resistor R3 is connected to the signal FB1 and one end of the voltage-dividing resistor R4, the other end of the voltage-dividing resistor R4 is connected to the ground signal gnd, the positive input of the error amplifier EA1 is connected to the input signal vref that is independent of temperature, the negative input of the error amplifier EA1 is connected to the signal FB1, the output end VC1 of the error amplifier EA1 is connected to the negative input end of the comparator COMP1, the positive input end of the comparator COMP1 is connected to the slope signal slope, and the output end of the comparator COMP1 is connected to the input end R of the RS trigger, providing the R1 signal for the RS trigger 1 in the logic module 1.

[0009] Among them, the pulse width modulation module 2 is composed of an error amplifier EA2 and a comparator COMP2, the positive input of the error amplifier EA2 is connected to the input signal vref that is independent of temperature, the negative input of the error amplifier EA2 is connected to the signal FB2, the output terminal VC2 of the error amplifier EA2 is connected to the negative input terminal of the comparator COMP2, the positive input terminal of the comparator COMP2 is connected to the slope signal slope, and the output terminal of the comparator COMP2 is connected to the input terminal R of the RS trigger, providing the R2 signal for the RS trigger 2 in the logic module 2.

[0010] Among them, the slope signal slope is generated by the slope generation module, and the slope generation module is composed of an inverter inv, an nmos tube nmos1, a Pmos tube Pmos1, a resistor R1 and a capacitor C1. The clock signal CK2_A with a 50% duty cycle is connected to the input end of the inverter, the output end of the inverter is connected to the gate end of Pmos1 and the gate end of nmos1, and the output end of the inverter outputs the signal CK2_B. The source end of Pmos1 is connected to the power signal, the drain end of Pmos1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the positive end of the capacitor C1 and the drain end of nmos1. The node signal at the connection is the slope signal slope with a 50% duty cycle input to the positive end of the comparator COMP, the negative end of the capacitor C1 is grounded, and the source end of nmos1 is grounded.

[0011] Among them, the logic module 1 is composed of a D trigger, a rising edge capture module, an RS trigger 1 and a NAND gate. The clock input signal CLK is connected to the input clk terminal of the D trigger. The input terminal D and the output terminal QB of the D trigger are short-circuited together. The output terminal Q outputs a divided clock signal CK2_A with a duty cycle of 50%. The divided clock signal CK2_A is used as the input signal of the rising edge capture module. The rising edge capture module outputs the rising edge signal CK2 of the divided clock signal CK2_A. The input terminal S of RS trigger 1 is connected to the rising edge signal CK2. The input terminal R of RS trigger 1 is connected to the output terminal of the comparator COMP1 in the pulse width modulation module 1. The output terminal of RS trigger 1 is connected to one input terminal PH1_ii_s of the NAND gate. The other input terminal of the NAND gate is connected to the divided clock signal CK2_A with a duty cycle of 50%. The output terminal PH1_i_s of the NAND gate is connected to the input terminal of the driving module.

[0012] Among them, the logic module 2 is composed of an RS trigger 2, an OR gate and an inverter inv1. The input end S of the RS trigger 2 is connected to the rising edge signal CK2, the input end R of the RS trigger 2 is connected to the output end of the comparator COMP2 in the pulse width modulation module 2, the output end of the RS trigger 2 is connected to the input end ph1_ii of the inverter inv1, the output end of the inverter inv1 is connected to one input end of the OR gate, the other input end of the OR gate is connected to the drive signal PH1_s signal, and the output end PH1_i signal of the OR gate is used as the input end of the drive module.

[0013] The driving module is composed of three driving devices and a group of staggered clock generators. The output end PH1_i_s signal of the NAND gate of the logic module 1 is connected to the input end of the staggered clock generator to generate two groups of non-overlapping staggered clock signals. The two groups of signals are respectively connected to the input ends of the first and second driving devices. The output ends of the first and second driving devices output driving signals PH1_s and PH2 respectively. The output end PH1_i signal of the OR gate of the logic module 2 is connected to the input end of the third driving device. The output end of the third driving device outputs the driving signal PH1. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Shown is a circuit diagram of the present invention;

[0015] Figure 2 Shown is a working timing diagram of the PWM modulation of the present invention. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] See also Figure 1 The present invention provides a charge pump circuit structure of low power consumption and low starting current PWM modulation for AMOLED, comprising: a charge pump module (chargepump), a pulse width modulation module 1 (PWM1), a pulse width modulation module 2 (PWM2), a slope generation module (slope_gen), a logic module 1 (logic1), a logic module 2 (logic2) and a driver module (driver).

[0018] Among them, the charge pump module (chargepump) is composed of five Pmos tubes, namely Pmos2, Pmos3, Pmos4, Pmos5 and Pmos6, plus a flying capacitor C2 and a capacitor C3, the positive end of the flying capacitor C2 is connected to the drain end of Pmos2, the drain end of Pmos6 and the source end of Pmos3, and the negative end of the flying capacitor C2 is connected to the drain end of Pmos5 and the source end of Pmos4; the driving signal PH1_s is connected to the gate end of Pmos2 and the gate end of Pmos5, the driving signal PH1 is connected to the gate end of Pmos6, the driving signal PH2 is connected to the gate end of Pmos3 and the gate end of Pmos4, the input signal AVDD is connected to the source end of Pmos2 and the source end of Pmos6, and the input signal vicb is connected to the drain end of Pmos4. The ground signal gnd is connected to the source terminal of Pmos5, the output signal vgh is connected to the drain terminal of pmos3 and the positive terminal of the filter capacitor C3, and the negative terminal of the filter capacitor C3 is connected to the ground signal gnd.

[0019] Wherein, the pulse width modulation module 1 (PWM1) is composed of a voltage-dividing resistor R2, a voltage-dividing resistor R3, a voltage-dividing resistor R4, an error amplifier EA1 and a comparator COMP1, the charge pump output signal vgh is connected to one end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R2 is connected to the signal FB2 and one end of the voltage-dividing resistor R3, the other end of the voltage-dividing resistor R3 is connected to the signal FB1 and one end of the voltage-dividing resistor R4, the other end of the voltage-dividing resistor R4 is connected to the ground signal gnd, the positive input of the error amplifier EA1 is connected to the input signal vref that is independent of temperature, the negative input of the error amplifier EA1 is connected to the signal FB1, the output end VC1 of the error amplifier EA1 is connected to the negative input end of the comparator COMP1, the positive input end of the comparator COMP1 is connected to the slope signal slope, and the output end of the comparator COMP1 is connected to the input end R of the RS trigger, providing the R1 signal for the RS trigger 1 in the logic module 1.

[0020] Among them, the pulse width modulation module 2 (PWM2) is composed of an error amplifier EA2 and a comparator COMP2, the positive input of the error amplifier EA2 is connected to the input signal vref that is independent of temperature, the negative input of the error amplifier EA2 is connected to the signal FB2, the output terminal VC2 of the error amplifier EA2 is connected to the negative input terminal of the comparator COMP2, the positive input terminal of the comparator COMP2 is connected to the slope signal slope, and the output terminal of the comparator COMP2 is connected to the input terminal R of the RS trigger, providing the R2 signal for the RS trigger 2 in the logic module 2.

[0021] Among them, the slope signal slope is generated by a slope generating module (slope_gen), and the slope generating module is composed of an inverter inv, an nmos tube nmos1, a Pmos tube Pmos1, a resistor R1 and a capacitor C1. The clock signal CK2_A with a 50% duty cycle is connected to the input end of the inverter, and the output end of the inverter is connected to the gate end of Pmos1 and the gate end of nmos1. The output end of the inverter outputs the signal CK2_B, the source end of Pmos1 is connected to the power signal, the drain end of Pmos1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the positive end of the capacitor C1 and the drain end of nmos1. The node signal at the connection is the slope signal slope with a 50% duty cycle input to the positive end of the comparator COMP, the negative end of the capacitor C1 is grounded, and the source end of nmos1 is grounded.

[0022] Among them, the logic module 1 (logic1) is composed of a D trigger, a rising edge capture module (posedge), an RS trigger 1 and a NAND gate. The clock input signal CLK is connected to the input clk terminal of the D trigger. The input terminal D and the output terminal QB of the D trigger are short-circuited together. The output terminal Q outputs a divided clock signal CK2_A with a duty cycle of 50%. The divided clock signal CK2_A is used as the input signal of the rising edge capture module. The rising edge capture module outputs the rising edge signal CK2 of the divided clock signal CK2_A. The input terminal S of the RS trigger 1 is connected to the rising edge signal CK2. The input terminal R of the RS trigger 1 is connected to the output terminal of the comparator COMP1 in the pulse width modulation module 1. The output terminal of the RS trigger 1 is connected to an input terminal PH1_ii_s of the NAND gate. The other input terminal of the NAND gate is connected to the divided clock signal CK2_A with a duty cycle of 50%. The output terminal PH1_i_s of the NAND gate is connected to the input terminal of the driving module.

[0023] Among them, the logic module 2 (logic2) is composed of RS trigger 2, OR gate and inverter inv1, the input end S of RS trigger 2 is connected to the rising edge signal CK2, the input end R of RS trigger 2 is connected to the output end of comparator COMP2 in pulse width modulation module 2, the output end of RS trigger 2 is connected to the input end Ph1_ii of inverter inv1, the output end of inverter inv1 is connected to one input end of the OR gate, the other input end of the OR gate is connected to the driving signal PH1_s signal, and the output end PH1_i signal of the OR gate is used as the input end of the driving module.

[0024] The driver module (driver) is composed of three driver devices (dr) and a group of staggered-phase clock generators (phase_gen). The output terminal PH1_i_s signal of the NAND gate of the logic module 1 is connected to the input terminal of the staggered-phase clock generator to generate two groups of non-overlapping staggered-phase clock signals. The two groups of signals are respectively connected to the input terminals of the first and second driver devices. The output terminals of the first and second driver devices output driving signals PH1_s and PH2 respectively. The output terminal PH1_i signal of the OR gate of the logic module 2 is connected to the input terminal of the third driver device. The output terminal of the third driver device outputs the driving signal PH1.

[0025] How it works:

[0026] 1. ClK generation: ring oscillator generation;

[0027] 2. CK2_A generates: the divided frequency signal of CLK, whose duty cycle is fixed at 50%;

[0028] 3. Generation of CK2: Capture the rising edge of CK2_A;

[0029] 4. Generation of FB1: voltage division of vgh, FB = K1*vgh;

[0030] 5. Generation of FB2: voltage division of vgh, FB=K2*vgh, FB2 voltage is greater than FB1;

[0031] 6. Generation of VC1: Output of the error amplifier, vc = K*(VREF-FB1);

[0032] 7. Generation of VC2: Output of the error amplifier, vc = K*(VREF-FB2);

[0033] 8. Generation of Slope signal: fixed slope signal with a duty cycle of 50% (controlled by CK2_A);

[0034] 9. Generation of R1 (R2) signal: VC1 (VC2) is compared with the slope signal. When VC1 (VC2) is higher, the R1 (R2) signal moves further back, away from CK2. The lower VC is, the R1 (R2) signal moves forward, closer to CK2.

[0035] 10. Generation of PH1_s (PH1) signal: PH1_s controls the small charging MOS transistor, and PH1 controls the large charging MOS transistor. Its low-level time is from the rising edge of the CK2 signal to the rising edge of the R1 (R2) signal, and its high-level time is from the rising edge of the R1 (R2) signal to the rising edge of the CK2 signal. Since the rising edge of CK2 is fixed and VC1 (VC2) controls the rising edge of the R1 (R2) signal, the duty cycle of the PH1_s (PH1) signal can be changed through VC1 (VC2) (the maximum duty cycle is 50%, because when the duty cycle of the charge pump ranges from 0 to 50%, the output voltage increases from low to high; when it ranges from 50% to 100%, the output voltage decreases from high to low. Therefore, the duty cycle is linearly adjusted within the range of 0 to 50%) to change the corresponding ratio of the charge and discharge of the charge pump and control the vgh voltage. At startup, only the small charging MOS transistor is turned on to reduce the startup current. When stable, the duty cycles of the large and small transistors are automatically determined according to the load conditions to achieve the effect of low power consumption. The automatic process is as follows: when the load is heavy, that is, FB1 < VREF, VC1 outputs high. Even if the duty cycle of PH1_s reaches 50%, it still cannot meet the requirements. At this time, vgh gradually decreases, FB2 gradually decreases, VC2 changes from low to high, and the duty cycle of PH1 increases from 0, causing vgh to increase, achieving the automatic adjustment process;

[0036] 11. Generation of PH2 signal: Opposite to PH1_s.

[0037] Working process of feedback control:

[0038] The driving signal PH1_s controls the small charging MOS transistor, and the driving signal PH1 controls the large charging MOS transistor. Its low-level time is from the rising edge of the CK2 signal to the rising edge of the R1 (R2) signal, and its high-level time is from the rising edge of the R1 (R2) signal to the rising edge of the CK2 signal. Since the rising edge of CK2 is fixed and VC1 (VC2) controls the rising edge of the R1 (R2) signal, the duty cycle of the PH1_s (PH1) signal can be changed through VC1 (VC2) (the maximum duty cycle is 50%, because when the duty cycle of the charge pump ranges from 0 to 50%, the output voltage increases from low to high; when it ranges from 50% to 100%, the output voltage decreases from high to low. Therefore, the duty cycle is linearly adjusted within the range of 0 to 50%) to change the corresponding ratio of the charge and discharge of the charge pump and control the vgh voltage. At startup, only the small charging MOS transistor is turned on to reduce the startup current. When stable, according to the load conditions, the duty cycles of the large and small transistors are automatically determined to achieve the effect of low power consumption. The automatic process is as follows: when the load is heavy, that is, FB1 < VREF, VC1 outputs high, then PH1_s maintains the highest efficiency of 50%, but even when PH1_s reaches a 50% duty cycle, it still cannot meet the vgh set voltage requirement. At this time, vgh slowly decreases, FB2 slowly decreases, VC2 changes from low to high, and the duty cycle of PH1 increases from 0, causing vgh to increase, achieving an automatic adjustment process.

[0039] Please refer to Figure 2 , the ring oscillator always generates a clock CIK with a fixed frequency. It is divided by two by a D flip-flop to generate a clock signal CK2_A with a fixed duty cycle of 50%. The rising edge extraction module extracts the rising edge clock signal CK2 of CK2_A as the S terminal of the RS flip-flop. The CK2_A signal also controls the ramp generation signal module, that is, the slope signal is low for 50% of the time and a triangular wave signal for 50% of the time. When overloaded, the duty cycle of PH1_s reaches 50% but still cannot meet the output requirements. At this time, FB1 << VREF and FB2 is near VREF. When FB2 is lower than VREF, VC2 is high and the duty cycle of PH1 is large. At this time, the load gradually becomes lighter, vgh gradually increases, FB2 slowly increases, the duty cycle of PH1 gradually decreases, and vgh decreases. When the duty cycle of ph1 decreases to 0, vgh is still higher than the preset value. At this time, FB2 >> VREF, VC2 outputs low, FB1 is slightly higher than VREF, and VC1 gradually decreases from high, that is, the duty cycle of ph1_s gradually decreases and vgh continues to decrease until VREF = FB1, completing the process of switching from overload to light load.

[0040] The charge pump circuit structure with AMOLED low-power and low-startup-current PWM modulation provided by the present invention has the following advantages:

[0041] 1. Low power consumption: When lightly loaded, low power consumption can be achieved through 0% duty cycle;

[0042] 2. Low starting current;

[0043] 3. High efficiency and small area: Compared with a fixed duty cycle, changing rdson means one less rdson regulating tube, thus reducing the area and avoiding energy loss on the rdson tube.

[0044] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0045] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is limited by the appended claims and their equivalents.

Claims

1. A charge pump circuit structure with low power consumption and low starting current PWM modulation for AMOLED, characterized in that: include: Charge pump module, pulse width modulation module 1, pulse width modulation module 2, ramp generation module, logic module 1, logic module 2 and drive module; The charge pump module is composed of five Pmos tubes, namely Pmos2, Pmos3, Pmos4, Pmos5 and Pmos6, plus a flying capacitor C2 and a capacitor C3, the positive end of the flying capacitor C2 is connected to the drain end of the Pmos2, the drain end of the Pmos6 and the source end of the Pmos3, the negative end of the flying capacitor C2 is connected to the drain end of the Pmos5 and the source end of the Pmos4; the driving signal PH1_s is connected to the gate end of the Pmos2 and the gate end of the Pmos5 e terminal, the driving signal PH1 is connected to the gate terminal of Pmos6, the driving signal PH2 is connected to the gate terminal of Pmos3 and the gate terminal of Pmos4, the input signal AVDD is connected to the source terminal of Pmos2 and the source terminal of Pmos6, the input signal vicb is connected to the drain terminal of Pmos4, the ground signal gnd is connected to the source terminal of Pmos5, the output signal vgh is connected to the drain terminal of Pmos3 and the positive terminal of the filter capacitor C3, and the negative terminal of the filter capacitor C3 is connected to the ground signal gnd; The pulse width modulation module 1 is composed of a voltage-dividing resistor R2, a voltage-dividing resistor R3, a voltage-dividing resistor R4, an error amplifier EA1 and a comparator COMP1, the charge pump output signal vgh is connected to one end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R2 is connected to the signal FB2 and one end of the voltage-dividing resistor R3, the other end of the voltage-dividing resistor R3 is connected to the signal FB1 and one end of the voltage-dividing resistor R4, the other end of the voltage-dividing resistor R4 is connected to the ground signal gnd, the positive input of the error amplifier EA1 is connected to the input signal vref that is independent of temperature, the negative input of the error amplifier EA1 is connected to the signal FB1, the output end VC1 of the error amplifier EA1 is connected to the negative input end of the comparator COMP1, the positive input end of the comparator COMP1 is connected to the slope signal slope, the output end of the comparator COMP1 is connected to the input end R of the RS trigger, and provides an R1 signal for the RS trigger 1 in the logic module 1; The pulse width modulation module 2 is composed of an error amplifier EA2 and a comparator COMP2, the positive input of the error amplifier EA2 is connected to an input signal vref that is independent of temperature, the negative input of the error amplifier EA2 is connected to the signal FB2, the output terminal VC2 of the error amplifier EA2 is connected to the negative input terminal of the comparator COMP2, the positive input terminal of the comparator COMP2 is connected to the slope signal slope, and the output terminal of the comparator COMP2 is connected to the input terminal R of the RS trigger to provide an R2 signal for the RS trigger 2 in the logic module 2; The slope signal slope is generated by the slope generating module, which is composed of an inverter inv, an nmos tube nmos1, a Pmos tube Pmos1, a resistor R1 and a capacitor C1. The clock signal CK2_A with a 50% duty cycle is connected to the input end of the inverter, the output end of the inverter is connected to the gate end of the Pmos1 and the gate end of the nmos1, the output end of the inverter outputs the signal CK2_B, the source end of the Pmos1 is connected to the power signal, the drain end of the Pmos1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the positive end of the capacitor C1 and the drain end of the nmos1, and the node signal at the connection is the slope signal slope with a 50% duty cycle input to the positive end of the comparator COMP, the negative end of the capacitor C1 is grounded, and the source end of the nmos1 is grounded; The logic module 1 is composed of a D trigger, a rising edge capture module, an RS trigger 1 and a NAND gate. The clock input signal CLK is connected to the input clk terminal of the D trigger. The input terminal D and the output terminal QB of the D trigger are short-circuited together. The output terminal Q outputs a divided clock signal CK2_A with a duty cycle of 50%. The divided clock signal CK2_A serves as the input signal of the rising edge capture module. The rising edge capture module outputs the rising edge signal CK2 of the divided clock signal CK2_A. The input terminal S of the RS trigger 1 is connected to the rising edge signal CK2. The input terminal R of the RS trigger 1 is connected to the output terminal of the comparator COMP1 in the pulse width modulation module 1. The output terminal of the RS trigger 1 is connected to one input terminal PH1_ii_s of the NAND gate. The other input terminal of the NAND gate is connected to the divided clock signal CK2_A with a duty cycle of 50%. The output terminal PH1_i_s of the NAND gate is connected to the input terminal of the driving module.

2. According to claim 1, a charge pump circuit structure of low power consumption and low starting current PWM modulation for AMOLED, characterized in that: The logic module 2 is composed of an RS trigger 2, an OR gate and an inverter inv1. The input end S of the RS trigger 2 is connected to the rising edge signal CK2, the input end R of the RS trigger 2 is connected to the output end of the comparator COMP2 in the pulse width modulation module 2, the output end of the RS trigger 2 is connected to the input end ph1_ii of the inverter inv1, the output end of the inverter inv1 is connected to one input end of the OR gate, the other input end of the OR gate is connected to the drive signal PH1_s signal, and the output end PH1_i signal of the OR gate serves as the input end of the drive module.

3. The charge pump circuit structure of low power consumption and low startup current PWM modulation for AMOLED according to claim 2, characterized in that: The driving module is composed of three driving devices and a group of staggered clock generators. The output end PH1_i_s signal of the NAND gate of the logic module 1 is connected to the input end of the staggered clock generator to generate two groups of non-overlapping staggered clock signals. The two groups of signals are respectively connected to the input ends of the first and second driving devices, and the output ends of the first and second driving devices output driving signals PH1_s and PH2 respectively. The output end PH1_i signal of the OR gate of the logic module 2 is connected to the input end of the third driving device, and the output end of the third driving device outputs the driving signal PH1.

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