Voltage regulating device and memory employing the same

Abstract

The application provides a voltage regulating device and a memory using the same. The voltage regulating device can regulate the voltage at a preset sampling point according to the feedback of the preset sampling point, so as to keep the voltage stable, improve the voltage stability and consistency of the preset sampling point. The memory can clamp the voltage of the preset sampling point by the voltage regulating device, so that the voltage of the preset sampling point is kept stable, the common source end voltage of the memory array is kept stable, the stability and consistency of the common source end voltage are improved, and the reading accuracy of the memory is improved.

Description

[0001] This invention is a divisional application of Chinese patent application No. 202011470668.4, filed on December 15, 2020, entitled "Voltage Regulation Device and Memory Using the Same". Technical Field

[0002] This invention relates to the field of voltage regulation, and more particularly to a voltage regulation device and a memory using the same. Background Technology

[0003] In 3D NAND flash memory, information in a cell is stored in the cell in the form of a threshold voltage (Vth). The process of reading stored information is the process of determining the threshold voltage (Vth). In this process, the bit line (BL) is first pulled up, then the word line (WL) is enabled. A read voltage (Vrd) is applied to the selected word line (select WL), and a conduction voltage (Vpass) is applied to the unselected word line (unselect WL). The common source terminal (ACS) is pulled to ground (GND) to form a current path to discharge the bit line.

[0004] At this point, the threshold voltage of the programmed memory cell is higher, and the difference between the gate-source voltage (Vgs) and the threshold voltage (Vth) is lower, resulting in a slower discharge rate. Conversely, the threshold voltage of the unprogrammed memory cell is lower, and the difference between the gate-source voltage (Vgs) and the threshold voltage (Vth) is higher, resulting in a faster discharge rate. After a discharge period, the bit line voltage is checked, and whether the stored information in the memory cell is "0" or "1" is determined based on whether the bit line voltage is lower than the reference voltage. During this process, the magnitude of the discharge current depends on the difference between the gate-source voltage (Vgs) and the threshold voltage (Vth). Therefore, the discharge current is related to both the gate voltage and the threshold voltage, as well as the source voltage (i.e., ACS).

[0005] In existing technologies, during reading, the common source terminal is connected to the ground terminal via a switching transistor. As chip storage capacity and area increase, due to limitations in the chip's ground network strength, the ground voltage at different locations on the chip may differ when read current flows, and even the ground voltage at the same location may differ at different times. Since the ground voltage directly affects the gate-source voltage (Vgs), it can impact read accuracy.

[0006] In TLC (Trinary-Level Cell) / QLC (Quad-Level Cell) 3D NAND, the threshold voltage of a storage cell is divided into several intervals to store as much information as possible. For example, in TLC 3D NAND, the threshold voltage of a storage cell is divided into 8 intervals, with each interval storing 3 bits of information. In QLC 3D NAND, the threshold voltage of a storage cell is divided into 16 intervals, with each interval storing 4 bits of information. Therefore, the accuracy requirements for threshold voltage (Vth) determination become increasingly higher, and higher requirements are also placed on the stability and consistency of the grounding voltage. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a voltage regulation device and a memory using the same.

[0008] To address the aforementioned problems, this invention provides a voltage regulation device for regulating the voltage at a preset sampling point. The device includes: an operational amplifier with an inverting input, a non-inverting input, and an output; the inverting input receives a reference voltage, and the non-inverting input is electrically connected to the preset sampling point to input the voltage at the preset sampling point, forming a feedback loop; a pull-up transistor with a control terminal, a first terminal, and a second terminal; the control terminal is electrically connected to the output of the operational amplifier, the first terminal is electrically connected to a power supply, and the second terminal is electrically connected to the preset sampling point; and a pull-down transistor with a control terminal, a first terminal, and a second terminal; the control terminal is electrically connected to the output of the operational amplifier, the first terminal is electrically connected to ground, and the second terminal is electrically connected to the preset sampling point.

[0009] Furthermore, the pull-up transistor is a PMOS transistor, and the pull-down transistor is an NMOS transistor.

[0010] Furthermore, the pull-down capability of the pull-down transistor is greater than the pull-up capability of the pull-up transistor.

[0011] Furthermore, under pull-up or light load conditions, the voltage regulator operates in Class AB mode, while under heavy load conditions, the voltage regulator operates in Class A mode.

[0012] Furthermore, the pull-up transistor and the pull-down transistor are low-voltage transistors.

[0013] Furthermore, the voltage regulation device also includes a switching transistor, and the second terminal of the pull-up transistor and the second terminal of the pull-down transistor are connected to the switching transistor.

[0014] Furthermore, the preset sampling point is set on the path connecting the second terminal of the pull-up transistor and the second terminal of the pull-down transistor to the switching transistor, or the second terminal of the pull-up transistor and the second terminal of the pull-down transistor are electrically connected to the preset sampling point through the switching transistor.

[0015] Furthermore, the switching transistor is a high-voltage transistor.

[0016] Furthermore, the voltage regulation device also includes a level converter, which is electrically connected to the switching transistor and is used to convert the voltage signal into a level and use it as a control signal for the switching transistor.

[0017] The present invention also provides a memory comprising: a memory array having a common source terminal; a voltage regulation device as described above, electrically connected to the common source terminal for connecting the common source terminal to a ground terminal, wherein the preset sampling point is set on the connection path between the common source terminal and the voltage regulation device or on the connection path between the common source terminal and the memory array.

[0018] One advantage of the present invention is that the voltage regulating device can adjust the voltage at the preset sampling point according to the feedback of the preset sampling point, so as to keep it stable and improve the voltage stability and consistency of the preset sampling point.

[0019] Another advantage of the present invention is that the memory of the present invention can clamp the voltage of the preset sampling point through the voltage adjustment device to keep it stable, thereby keeping the common source extreme voltage of the memory array stable, improving the stability and consistency of the common source extreme voltage, and thus improving the read accuracy of the memory. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the common source terminal grounding circuit of a memory in the prior art;

[0021] Figure 2 This is a circuit diagram of the voltage regulation device according to the first embodiment of the present invention;

[0022] Figure 3 This is another circuit diagram of the voltage regulation device according to the first embodiment of the present invention;

[0023] Figure 4 This is a circuit diagram of the voltage regulation device according to the second embodiment of the present invention;

[0024] Figure 5 This is a circuit diagram of the memory of the present invention;

[0025] Figure 6 This is a circuit diagram of the storage array of the memory of the present invention. Detailed Implementation

[0026] The following detailed description, with reference to the accompanying drawings, describes embodiments of the voltage regulation device and the memory using the same as provided in this invention.

[0027] Figure 1 This is a schematic diagram of the common source terminal grounding circuit for a memory in existing technology. Please refer to [link / reference]. Figure 1 In existing technology, the common source terminal ACS of the memory array 100 is connected to the ground terminal VSS_PAD via a switch S. The inventors discovered that the voltage instability of the common source terminal ACS is caused by several resistors present on the path from the common source terminal ACS to the ground terminal VSS_PAD. Specifically, these resistors include: the wiring resistance R1 from VSS_PAD to the switch S, the on-resistance of the switch S, and the wiring resistance R2 from the common source terminal ACS to the switch S. When the operating current of the memory chip flows through these resistors, a corresponding voltage drop is generated. For example, the current I1 from the memory array 100 is collected at the common source terminal ACS, and the operating current I2 from other operating modules of the memory chip, etc. The voltage drop across these resistors makes the voltage of the common source terminal ACS unstable, not an ideal "ground," but varying with different locations and times of the memory chip. This affects the discharge current of the memory array, ultimately affecting the read accuracy.

[0028] Therefore, the present invention provides a voltage regulation device that can regulate the voltage at the common source terminal ACS and clamp it to a set value, thereby improving the stability and consistency of the voltage at the common source terminal ACS.

[0029] The voltage regulating device of the present invention is used to regulate the voltage at a preset sampling point. Figure 2 This is a circuit diagram of the voltage regulation device according to the first embodiment of the present invention. Please refer to [link / reference]. Figure 2 The voltage regulation device includes an operational amplifier OPAMP, a pull-up transistor MP1, and a pull-down transistor MN1.

[0030] The operational amplifier (OPAMP) includes an inverting input, a non-inverting input, and an output. A reference voltage Vref is input to the inverting input, and the non-inverting input is electrically connected to a preset sampling point A to input the voltage Va at that point, forming a feedback loop.

[0031] The reference voltage Vref can be set according to the required voltage of the preset sampling point A, and the reference voltage Vref can be equal to the required voltage of the preset sampling point A.

[0032] In this embodiment, the pull-up transistor MP1 is a PMOS transistor. The pull-up transistor MP1 includes a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the output terminal of the operational amplifier OPAMP, the first terminal is electrically connected to the power supply VCC, and the second terminal is electrically connected to the preset sampling point A. That is, the output signal Vout of the operational amplifier OPAMP serves as the input signal to the control terminal of the pull-up transistor MP1, and the output signal of the second terminal of the pull-up transistor MP1 serves as the voltage signal for the preset sampling point A.

[0033] In this embodiment, the pull-down transistor MN1 is an NMOS transistor. The pull-down transistor MN1 includes a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the output terminal of the operational amplifier OPAMP, the first terminal is electrically connected to the ground terminal VSS, and the second terminal is electrically connected to the preset sampling point A. That is, the output signal Vout of the operational amplifier OPAMP serves as the input signal to the control terminal of the pull-down transistor MN1, and the output signal of the second terminal of the pull-down transistor MN1 serves as the voltage signal at the preset sampling point A.

[0034] In the voltage regulation device of the present invention, the control terminals of the pull-up transistor MP1 and the pull-down transistor MN1 are both connected to the output terminal of the operational amplifier OPAMP. Therefore, the output signal of the operational amplifier OPAMP serves as the control signal for the pull-up transistor MP1 and the pull-down transistor MN1. The second terminal (i.e., the output terminal) of the pull-up transistor MP1 and the second terminal (i.e., the output terminal) of the pull-down transistor MN1 are both connected to the preset sampling point A. Therefore, the output signal of the pull-up transistor MP1 and the output signal of the pull-down transistor MN1 together serve as the voltage signal for the preset sampling point A.

[0035] The working process of the voltage regulating device of the present invention is described as follows:

[0036] When the voltage at the preset sampling point A decreases, the voltage Va at the non-inverting input of the operational amplifier OPAMP becomes less than the voltage Vref at the inverting input. Consequently, the output voltage Vout at the output of the operational amplifier OPAMP decreases, altering the conduction capability of the pull-up transistor MP1 and the pull-down transistor MN1. Specifically, the voltage at the control terminal of the pull-up transistor MP1 decreases, strengthening its pull-up capability; conversely, the voltage at the control terminal of the pull-down transistor MN1 decreases, weakening its pull-down capability. The combined effect of MP1 and MN1 causes the output voltage to rise, thus increasing the voltage at the preset sampling point A. This allows for the adjustment of the voltage at the preset sampling point A, preventing it from decreasing and maintaining stability.

[0037] When the voltage at the preset sampling point A increases, the voltage Va at the non-inverting input of the operational amplifier OPAMP becomes greater than the voltage Vref at the inverting input. Consequently, the output voltage Vout at the output of the operational amplifier OPAMP increases, altering the conduction capability of the pull-up transistor MP1 and the pull-down transistor MN1. Specifically, an increase in the voltage at the control terminal of the pull-up transistor MP1 weakens its pull-up capability; an increase in the voltage at the control terminal of the pull-down transistor MN1 strengthens its pull-down capability. The combined effect of MP1 and MN1 causes a decrease in the output voltage, thus lowering the voltage at the preset sampling point A. This allows for the adjustment of the voltage at the preset sampling point A, preventing it from rising and maintaining stability.

[0038] The voltage regulation device of the present invention can adjust the voltage at the preset sampling point A according to the feedback of the preset sampling point A, so as to keep it stable and improve the voltage stability and consistency of the preset sampling point.

[0039] Furthermore, when the voltage regulation device serves as a connection between the common source terminal and the ground terminal of the memory array, it primarily absorbs current rather than provides it. This current-absorbing mode corresponds to the reading operation of the memory array, which requires higher speed, i.e., a higher pull-down capability and a lower pull-up capability. Therefore, in this embodiment, the pull-down capability of the pull-down transistor MN1 is greater than the pull-up capability of the pull-up transistor MP1 to suit its operating mode. In other words, in this embodiment, the pull-down transistor MN1 and the pull-up transistor MP1 are asymmetrical. This asymmetry can be achieved by changing the width-to-length ratio of the pull-down transistor MN1 and the pull-up transistor MP1.

[0040] Furthermore, the voltage regulator operates in pseudo-Class AB mode. Specifically, under pull-up or light load conditions, the voltage regulator operates in Class AB mode; under heavy load conditions, the voltage regulator operates in Class AB mode. For details, please refer to [link to relevant documentation]. Figure 3This is another circuit diagram of the first embodiment of the present invention. The operational amplifier (OPAMP) includes a transconductance stage (Gm stage), a class AB bias circuit, and current mirrors Ia and Ib. These structures are conventional structures of the operational amplifier (OPAMP) and will not be described in detail. When the voltage regulation device is used as a connection device between the common source terminal and the ground terminal of the memory array, because the pull-down current needs to be large, the gate voltage (vg_MN1) of the pull-down transistor MN1 will be pulled very high during reading, while Vbn and Vbp in the class AB bias circuit are preset fixed voltages. When the gate voltage (vg_MN1) of the pull-down transistor MN1 is high, the NMOS transistor (MNb) in the Class AB bias circuit will be turned off, causing the circuit to operate in Class A amplifier mode. Conversely, when the pull-down current is low, the gate voltage (vg_MN1) of the pull-down transistor MN1 will not be high, and the NMOS transistor (MNb) in the Class AB bias circuit will not be turned off, causing the circuit to operate in Class AB amplifier mode. Therefore, in pull-up or light-load mode, the voltage regulation device operates in Class AB mode; in heavy-load mode, it operates in Class A mode.

[0041] Furthermore, the operational amplifier OPAMP, pull-up transistor MP1, and pull-down transistor MN1 are all fabricated in the low-voltage power domain (Vcc domain). Therefore, both the pull-up transistor MP1 and the pull-down transistor MN1 are low-voltage transistors, which simplifies the layout design and saves layout area while realizing the function.

[0042] In some cases, such as during a memory erase operation, it is not necessary to connect the voltage regulator to the ground terminal; that is, the voltage regulator does not need to be connected to the memory circuitry. Therefore, to solve this problem, the present invention provides a second embodiment. The difference between the second embodiment and the first embodiment is that the voltage regulator further includes a switching transistor. The differences between the second embodiment and the first embodiment will be described in detail below.

[0043] Please see Figure 4 This is a circuit diagram of a voltage regulating device according to a second embodiment of the present invention. The voltage regulating device further includes a switching transistor S. The second terminal of the pull-up transistor MP1 and the second terminal of the pull-down transistor MN1 are electrically connected to the switching transistor S. The switching transistor S is used as a switch for the voltage regulating device. When the switching transistor S is turned on, the voltage regulating device operates; when the switching transistor S is turned off, the voltage regulating device does not operate.

[0044] Furthermore, since the switching transistor S also experiences a voltage drop, which affects the voltage at the memory's output terminal (common source terminal), in this embodiment, the second terminals of the pull-up transistor MP1 and the pull-down transistor MN1 are electrically connected to the preset sampling point A via the switching transistor S. That is, in the second embodiment, the switching transistor S is also covered by a feedback loop, ensuring that the voltage drop of the switching transistor S has no effect on the voltage at the preset sampling point A, further improving the voltage stability and consistency at the preset sampling point A. In this embodiment, when the voltage regulation device needs to regulate the voltage at the preset sampling point A, the switching transistor S is turned on; when the voltage regulation device does not need to regulate the voltage at the preset sampling point A, the switching transistor S is turned off, allowing the voltage regulation device to selectively regulate the voltage at the preset sampling point A.

[0045] Furthermore, in other embodiments of the present invention, if the on-resistance of the switch S is small and the voltage drop across it can be ignored, or if the voltage drop of the switch S has little effect on the voltage of the output terminal (common source terminal) of the memory, then the preset sampling point A can also be set on the path connecting the second terminal of the pull-up transistor MP1 and the second terminal of the pull-down transistor MN1 to the switch S.

[0046] Furthermore, in the second embodiment, the switching transistor S is fabricated in the high-voltage domain, therefore it is a high-voltage transistor. In this embodiment, the switching transistor S is a high-voltage NMOS transistor. When the voltage regulation device is not required to regulate the voltage of the preset sampling point A, a low-level signal is input to the control terminal of the switching transistor S to turn it off, thereby disconnecting the voltage regulation device from the preset sampling point A; when the voltage regulation device is required to regulate the voltage of the preset sampling point A, a high-level enable signal is input to the control terminal of the switching transistor S to turn it on, thereby connecting the voltage regulation device to the preset sampling point A.

[0047] Furthermore, when the voltage regulator is used as a connection device between the common source terminal and the ground terminal of the memory array, a high voltage is generated under certain operating states of the common source terminal, such as during an erase operation. In these cases, the voltage regulator does not need to be connected to the common source terminal. Therefore, to protect the internal circuitry of the voltage regulator, the switch S needs to be turned off. At this time, the switch S receives a high-level signal. If this high-level signal is directly used as the control signal for the switch S, it will turn on the switch S. Therefore, the voltage regulator of this invention also includes a level shifter LS, which is electrically connected to the switch S and is used to convert the voltage signal to a higher level before using it as the control signal for the switch S, thereby enabling the switch S to be turned on and off.

[0048] The present invention also provides a memory employing the above-described voltage regulation device. Please refer to [link / reference needed]. Figure 5 This is a circuit diagram of the memory of the present invention, which includes a storage array 100 and the voltage regulation device 500 described above.

[0049] Please see Figure 6 This is a schematic diagram of the memory array 100, which includes multiple memory cells arranged in a three-dimensional space to form multiple memory strings. The channels of memory cells within the same memory string are physically connected. The transistor at the top of each memory string is an upper select transistor (TSG), which is connected to the bit line BL. The transistor at the bottom of the memory string is a lower select transistor (BSG). Different memory strings are distinguished by the upper select transistor (TSG) and the lower select transistor (BSG). Multiple memory cells located in the same layer form a memory row. The gates of memory cells located in different memory strings but within the same memory row are physically connected and all connected to the same word line WL.

[0050] The storage array 100 also includes a common source terminal (ACS). The common source terminal (ACS) is used to electrically connect the storage array 100 to a ground terminal.

[0051] The process of reading stored information involves determining the threshold voltage (Vth). In this process, the bit line BL is first pulled up, then the word line WL is enabled. A read voltage is applied to the selected word line (select WL), and a conduction voltage (Vpass) is applied to the unselected word line (unselect WL). The common source terminal ACS is pulled to ground (GND), thus forming a current path to discharge the bit line. However, as the chip's storage capacity and area increase, due to the limitations of the chip's grounding network strength, the grounding voltage at different locations on the chip may differ when read current flows. Even at the same location, the grounding voltage may differ at different times, leading to instability in the voltage of the common source terminal ACS, which affects the performance and reliability of the memory array.

[0052] Please continue reading. Figure 5 To address the aforementioned issues, the voltage regulator 500 is electrically connected to the common source terminal ACS, thereby connecting the common source terminal ACS to the ground. The preset sampling point A is located on the connection path between the common source terminal ACS and the voltage regulator 500.

[0053] The present invention's memory can clamp the voltage of the preset sampling point A through the voltage adjustment device 500, thereby keeping it stable, thus keeping the common source extreme ACS voltage of the storage array 100 stable, improving the stability and consistency of the common source extreme ACS voltage, and thus improving the read accuracy of the memory.

[0054] Furthermore, the closer the preset sampling point A is to the storage array 100, the better, so that the voltage drop on the current path between the output terminal and the ground terminal of the storage array is included in the feedback loop as much as possible, thereby improving the stability of the voltage at the output terminal of the storage array.

[0055] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A voltage regulating device, characterized in that, include: An operational amplifier includes an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal is connected to the input terminal of a reference voltage, and the non-inverting input terminal is electrically connected to a preset sampling point to form a feedback loop. A pull-up transistor includes a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the output terminal of the operational amplifier, the first terminal is electrically connected to a power supply, and the second terminal is electrically connected to the preset sampling point. A pull-down transistor includes a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected to the output terminal of the operational amplifier, the first terminal is electrically connected to the ground terminal, and the second terminal is electrically connected to the preset sampling point. Wherein, the pull-down capability of the pull-down transistor is greater than the pull-up capability of the pull-up transistor; and the aspect ratio of the pull-down transistor is greater than the aspect ratio of the pull-up transistor.

2. The voltage regulating device according to claim 1, characterized in that, The pull-up transistor is a P-type transistor, and the pull-down transistor is an N-type transistor.

3. The voltage regulating device according to claim 2, characterized in that, When the voltages at the control terminals of both the pull-up transistor and the pull-down transistor decrease, the total voltage output by the output terminals of the pull-up transistor and the pull-down transistor increases.

4. The voltage regulating device according to claim 2, characterized in that, When the voltages at the control terminals of both the pull-up transistor and the pull-down transistor increase, the total voltage output by the output terminals of the pull-up transistor and the pull-down transistor decreases.

5. The voltage regulating device according to claim 1, characterized in that, When under load or light load, the voltage regulator operates in Class AB mode; when under heavy load, the voltage regulator operates in Class A mode.

6. The voltage regulating device according to claim 1, characterized in that, The voltage regulation device further includes a switching transistor, and the second terminal of the pull-up transistor and the second terminal of the pull-down transistor are electrically connected to one end of the switching transistor.

7. The voltage regulating device according to claim 6, characterized in that, The pull-up transistor and the pull-down transistor are of the first type of transistor; the switching transistor is of the second type of transistor; In this case, the power domain of the first type of transistor is lower than that of the second type of transistor.

8. The voltage regulating device according to claim 7, characterized in that, The preset sampling point is set on the path connecting the second terminal of the pull-up transistor and the second terminal of the pull-down transistor to the switching transistor, or the second terminal of the pull-up transistor and the second terminal of the pull-down transistor are electrically connected to the preset sampling point through the switching transistor.

9. The voltage regulating device according to claim 7, characterized in that, The voltage regulation device further includes a level converter, which is electrically connected to the gate of the switching transistor and is used to convert the output signal of the pull-up transistor and the output signal of the pull-down transistor together into a control signal for the switching transistor.

10. A memory, characterized in that, include: Storage array; The common source terminal is connected to the storage array and is used to electrically connect the storage array to the ground terminal; A voltage regulating device, electrically connected to the common source terminal, is used to connect the common source terminal to the ground terminal; The voltage regulation device includes: a pull-up transistor, a pull-down transistor, and a switching transistor; The output terminal of the pull-up transistor and the output terminal of the pull-down transistor are connected together to one of the source or drain of the switching transistor; The remaining one of the source or drain terminals of the switching transistor is connected to the common source terminal; the switching transistor is used to control the voltage drop at the common source terminal. Wherein, the pull-down capability of the pull-down transistor is greater than the pull-up capability of the pull-up transistor; and the aspect ratio of the pull-down transistor is greater than the aspect ratio of the pull-up transistor.

11. The memory according to claim 10, characterized in that, The voltage regulation device further includes: an operational amplifier; The operational amplifier includes an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal is connected to the input terminal of the reference voltage, and the non-inverting input terminal is electrically connected to a preset sampling point to form a feedback loop. The control terminals of the pull-up transistor and the pull-down transistor are both connected to the output terminal of the operational amplifier. The preset sampling point is set on the connection path between the common source end and the switching transistor.

12. The memory according to claim 11, characterized in that, The voltage regulation device further includes a level converter, which is connected to the gate of the switching transistor and is used to convert the output signal of the pull-up transistor and the output signal of the pull-down transistor together into a control signal for the switching transistor.

Images