Wafer holder, semiconductor manufacturing device, and method for manufacturing semiconductor device

Abstract

Provided is a wafer holder capable of suppressing contact between a semiconductor wafer and a wafer holder at unexpected locations when placing and taking a semiconductor wafer relative to a carrier. Also disclosed is a semiconductor manufacturing device and a method for manufacturing a semiconductor device. At the wafer holder, two supporting parts are arranged in a first direction, the two supporting parts are connected via a joint, the two supporting parts each extend from the joint to a second direction orthogonal to the first direction, the spacing between the sides of the two supporting parts facing the direction intersecting the second direction and facing each other is greater than or equal to 170 mm, the spacing between the sides of the two supporting parts facing the direction intersecting the second direction and facing each other is less than or equal to 280 mm, and when the distance between the inner side surfaces of the two supporting parts is set to A (mm), and the length of the inner side surfaces of the two supporting parts in the second direction is set to L (mm), L≥(300 2 ‑A 2 ) 0 . 5 The relationship is established.

Description

Technical Field

[0001] The present invention relates to a wafer holder, a semiconductor manufacturing device and a method for manufacturing a semiconductor device. Background Art

[0002] A wafer holder is used to transfer semiconductor wafers. For example, Patent Document 1 discloses a wafer holder.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2013-151035

[0004] In a carrier that holds semiconductor wafers, the semiconductor wafers are supported and held by grooves formed in multiple layers in the vertical direction on the left and right inner walls. The semiconductor wafers held in the carrier are supported only at their outer periphery, so the unsupported center portion bends downward due to its own weight. Wafers that have been thinned, such as those with steps, bend significantly. To remove semiconductor wafers held in multiple layers in the vertical direction from the carrier, a wafer holder must be inserted between the semiconductor wafers. However, if the gap for inserting the wafer holder becomes smaller due to the bending of the semiconductor wafers, the semiconductor wafer and the wafer holder may come into contact in unexpected locations. Summary of the Invention

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a wafer holder that can prevent the semiconductor wafer from contacting the wafer holder at unexpected locations when the semiconductor wafer is placed in and out of a carrier.

[0006] The wafer holder of the present invention comprises a joint portion and two supporting portions, the two supporting portions are arranged in a first direction, the two supporting portions are connected via the joint portion, the two supporting portions each extend from the joint portion in a second direction perpendicular to the first direction, the spacing between the side surfaces of the two supporting portions facing the direction intersecting the second direction and facing each other is greater than or equal to 170 mm, the spacing between the side surfaces of the two supporting portions facing the direction intersecting the second direction and facing each other is less than or equal to 280 mm, and when the distance between the inner side surfaces of the two supporting portions is set to A and the length of the inner side surfaces of the two supporting portions in the second direction is set to L, L ≥ (300 2 -A 2 ) 0.5 The relationship holds true, where the units of A and L are mm.

[0007] Effects of the Invention

[0008] According to the present invention, there is provided a wafer receptacle capable of preventing the semiconductor wafer from coming into contact with the wafer receptacle at an unexpected location when the semiconductor wafer is placed in and out of a carrier. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a top view of the wafer holder according to the first embodiment.

[0010] Figure 2 yes Figure 1 Cross-sectional view at the α1-β1 line.

[0011] Figure 3 It is a diagram showing the warping of a wafer with a step accommodated in a carrier.

[0012] Figure 4 This is a diagram showing a state where the wafer holder according to the first embodiment is inserted between wafers accommodated in a carrier.

[0013] Figure 5 It is a diagram showing the warping of a wafer with a step accommodated in a carrier.

[0014] Figure 6 It is a diagram showing a state where wafers are accommodated in a carrier.

[0015] Figure 7 yes Figure 6 Cross-sectional view at the α2-β2 line.

[0016] Figure 8 This is a top view of an example of a wafer holder according to the second embodiment.

[0017] Figure 9 yes Figure 8 Cross-sectional view at line α3-β3.

[0018] Figure 10 This is a diagram showing the relationship between the position of the placement portion and the curvature of a wafer with a step.

[0019] Figure 11 This is a top view of another example of the wafer holder according to the second embodiment.

[0020] Figure 12 yes Figure 11 Cross-sectional view at the α4-β4 line.

[0021] Figure 13 This is a flowchart showing a method for manufacturing a semiconductor device according to a third embodiment.

[0022] Figure 14 It is a top view of a wafer holder of a comparative example.

[0023] Figure 15 This is a diagram showing a state where a wafer holder of a comparative example is inserted between wafers accommodated in a carrier.

[0024] Figure 16 This is a diagram showing a semiconductor device manufactured according to the third embodiment.

[0025] Figure 17 It is a diagram showing a semiconductor manufacturing apparatus of Embodiment 1. Detailed implementation manners

[0026] <A. Embodiment 1>

[0027] <A-1. Structure>

[0028] Figure 1 It is a top view showing a wafer chuck 21 of the present embodiment. Figure 2 It is Figure 1 a cross-sectional view of the wafer chuck 21 at the α1-β1 line of. In Figure 1 and Figure 2 also shown is a stepped wafer 5 placed on the wafer chuck 21. The stepped wafer 5 has a flange 15 at its outer peripheral portion. The thickness of the stepped wafer 5 is thinner at the central portion than at the portion of the flange 15.

[0029] The wafer chuck 21 has two carrying portions 2 (2a, 2b) and a joining portion 3. The two carrying portions 2 are arranged in the first direction ( Figure 1 the x direction of). The two carrying portions 2 extend from the joining portion 3 toward the second direction ( Figure 1 the y direction of). The two carrying portions 2 are connected via the joining portion 3. The first direction and the second direction are orthogonal directions.

[0030] Hereinafter, for each of the two carrying portions 2, the inner side means the side of the other carrying portion 2. That is, the inner side surface of the carrying portion 2a is the side surface of the carrying portion 2b side, and the inner side surface of the carrying portion 2b is the side surface of the carrying portion 2a side.

[0031] Each of the two carrying portions 2 has an inner side surface that extends linearly in the second direction in a top view. In addition, each of the two carrying portions 2 has an outer side surface that extends linearly in the second direction in a top view.

[0032] The wafer chuck 21 is, for example, a wafer chuck for transporting a 300 mm stepped wafer.

[0033] The interval A between the inner side surfaces of the two carrying portions 2 is greater than or equal to 170 mm.

[0034] In addition, the interval B between the outer side surfaces of the two carrying portions 2 is less than or equal to 250 mm.

[0035] Each of the two receiving portions 2 is configured so that the outer side of the receiving portion 2 is shorter than the inner side. That is, the end of the inner side surface in the second direction can be located further to the side in the second direction than the end of the outer side surface in the second direction. By making the outer side of the receiving portion 2 shorter than the inner side, the rigidity of the receiving portion 2 is increased. The front ends of the two receiving portions 2 are each arcuately shaped, for example, to follow the outer circumference of the stepped wafer 5 placed on the wafer holder 21.

[0036] When the distance between the inner side surfaces of the two support parts 2 is A (mm) and the length of the inner side surfaces of the two support parts 2 in the second direction is L (mm), A and L are designed so that L ≥ (300 2 -A 2 ) 0.5 Here, (300 2 -A 2 ) 0.5 This is the length of the portion where the inner side surface of the carrier 2 overlaps the stepped wafer 5 when viewed from above, assuming the diameter of the stepped wafer 5 is 300 mm. Therefore, when the stepped wafer 5 is placed on two carriers 2 without overlapping the inner side surfaces of the two carriers 2 on the bonding portion 3 side, each of the two carriers 2 can reach further in the second direction than the side surface of the stepped wafer 5 in the second direction. Therefore, at a position in the first direction where the carrier 2 is located, the carrier 2 can be securely inserted to support the stepped wafer 5 across the entire second direction.

[0037] Assuming a 300 mm wafer with steps, for example, when the interval A (mm) is greater than or equal to 170 mm and less than 200 mm, L can be greater than or equal to 247 mm. For example, when the interval A (mm) is greater than or equal to 200 mm and less than or equal to 230 mm, L can be greater than or equal to 223 mm.

[0038] The portion of the side surface on the second direction side of the joint portion 3 between the two receiving portions 2 is recessed in the direction opposite to the second direction at the center portion between the two receiving portions 2 when viewed from above. Therefore, even when a stepped wafer 5 is placed on the receiving portion 2 such that the side surface on the side opposite to the second direction of the stepped wafer 5 is located near the boundary between the receiving portion 2 and the joint portion 3, the joint portion 3 and the stepped wafer 5 do not overlap when viewed from above.

[0039] Next, the carrier for accommodating wafers will be described. Figure 6 It is a plan view showing a state where the wafer 5 with a step is accommodated in the carrier 6 . Figure 7 yes Figure 6Cross-sectional view at the α2-β2 line.

[0040] The carrier 6 is adapted for 300 mm wafers and is in accordance with Semi standards.

[0041] The carrier 6 is provided with a support portion 7. The support portion 7 is a protrusion protruding from the side surface of the carrier 6. The protruding length of the support portion 7 is, for example, less than 10 mm.

[0042] The stepped wafer 5 is housed in the carrier 6 in a state where the back surfaces of both end portions in the X direction are supported by the support portions 7 .

[0043] Figure 3 It means that when the chip 5 with steps is Figure 6 and Figure 7 The figure shows the bending state of the stepped wafer 5 in a state where the back surface of the end portions on both end sides in the X direction is supported by the support portion 7 of the carrier 6 .

[0044] exist Figure 3 , the lowest value of the height at each X-direction position is plotted against the height at the support portion 7. The lowest value of the height at a certain X-direction position is the lowest height between different positions in the Y-direction specified by the X-direction position.

[0045] exist Figure 3 In FIG. 1 , the data are shown with the height of the portion where the stepped wafer 5 is supported by the support portion 7 being set to 0 (mm).

[0046] like Figure 3 As shown, the stepped wafer 5 is curved in such a manner that it is high near the support portion 7, i.e., in an area where the horizontal axis value is close to -150 mm or 150 mm, and low in the center portion in the X direction, i.e., near 0 mm.

[0047] Figure 4 It means that a certain layer of carrier 6 is accommodated. Figure 3 The wafer 5 with the step after the measurement is a picture of a state where a semiconductor wafer 4 is stored in the layer below the layer storing the wafer 5 with the step. The semiconductor wafer 4 is a wafer whose central portion is not thinned. Figure 4 Also shown is the carrier 2 of the wafer holder 21 inserted between the semiconductor wafer 4 and the wafer 5 with the step.

[0048] exist Figure 5 5a represents the height of the lower surface of the stepped wafer 5. 4a represents the height of the upper surface of the semiconductor wafer 4. Since the semiconductor wafer 4 is not thinned, the height of the upper surface of the semiconductor wafer 4 is substantially constant regardless of the in-plane position.

[0049] If a chip 5 with a step is accommodated in the upper layer of the upper and lower adjacent layers, and a semiconductor chip 4 that has not been thinned is accommodated in the lower layer, the gap when the chip holder 21 is inserted between the chip accommodated in the upper layer and the chip accommodated in the lower layer becomes smaller.

[0050] The support portions 7 are arranged at intervals of about 10 mm in the height direction. Due to the curvature of the stepped wafer 5, the gap between the lower surface of the stepped wafer 5 and the upper surface of the semiconductor wafer 4 is about 5 mm in the center portion in the X direction.

[0051] When using a wafer holder 21 with a spacing A greater than or equal to 170 mm, as Figure 4 and Figure 5 When the carrier 2 is inserted between the stepped wafer 5 and the semiconductor wafer 4 as shown, the gap between the lower surface of the stepped wafer 5 and the upper surface of the semiconductor wafer 4 at the position in the X direction where the carrier 2 is inserted is approximately 6 mm or greater. This allows for a larger gap C between the carrier 2 and the stepped wafer 5, or between the carrier 2 and the semiconductor wafer 4. For example, if the carrier 2 is 4 mm thick, the gap C between the carrier 2 and the stepped wafer 5, or between the carrier 2 and the semiconductor wafer 4, can each be maintained at least 1 mm at all positions in the Y direction where the carrier 2 is located. This prevents the wafer holder 21 from contacting the semiconductor wafer 4 or the stepped wafer 5 at unexpected locations.

[0052] In addition, in order to be able to Figure 4 When the wafer holder 21 is lifted in the state, the wafer 5 with the step is placed on the wafer holder 21 without contacting the support part 7, for example, the protruding length of one support part 7 is set to be less than 10 mm, and the interval B is, for example, less than or equal to 280 mm.

[0053] In addition, if Figure 6 As shown, in order to support the end of the wafer, the carrier 6 has a side opposite to the side where the wafer holder 21 is inserted (i.e., Figure 6 The width D of the opening 16 in this narrow portion is 250 mm. If the interval B is less than or equal to 250 mm, the wafer holder 21 can be inserted into this narrow portion, and the wafer holder 21 can support the stepped wafer 5 even at the end of the stepped wafer 5 opposite to the side where the wafer holder 21 is inserted.

[0054] Next, a semiconductor manufacturing apparatus including a wafer holder will be described. Figure 17FIG. 0 is a diagram showing an example of a semiconductor manufacturing apparatus according to the present embodiment, namely, a semiconductor manufacturing apparatus 200. The semiconductor manufacturing apparatus 200 is a device for wafer transfer. The semiconductor manufacturing apparatus 200 has a wafer stage 21. The semiconductor manufacturing apparatus 200, for example, has a drive unit 25 that drives the wafer stage 21, and the wafer stage 21 is driven by the drive unit 25 to automatically transfer wafers. The semiconductor manufacturing apparatus according to the present embodiment may be any semiconductor manufacturing apparatus having a wafer stage 21, and the semiconductor manufacturing apparatus according to the present embodiment may also be Figure 17 a semiconductor manufacturing apparatus other than the semiconductor manufacturing apparatus 200 shown.

[0055] <A-2. Operation>

[0056] A method of taking out the stepped wafer 5 using the wafer stage 21 from a state where a plurality of stepped wafers 5 are accommodated in the carrier 6 will be described. The stepped wafer 5 to be taken out is referred to as a stepped wafer 5a, and the stepped wafer 5 accommodated in the lower layer of the stepped wafer 5a is referred to as a stepped wafer 5b.

[0057] When taking out the stepped wafer 5 from the carrier 6, the two carrier portions 2 of the wafer stage 21 are inserted between the stepped wafer 5a to be taken out and the stepped wafer 5 in the lower layer thereof, that is, the stepped wafer 5b.

[0058] At this time, the two carrier portions 2 are inserted into the carrier 6 from the Figure 6 negative Y-direction side toward the Y-direction side in a manner that does not overlap with the central portion of the stepped wafer 5 in the X direction in a plan view. The two carrier portions 2 are inserted into Figure 3 the regions with less bending shown, that is, the regions where the X coordinate is -125 mm to -85 mm and 85 mm to 125 mm. One carrier portion 2 is inserted into the region where the X coordinate is -125 mm to -85 mm, and the other carrier portion 2 is inserted into the region where the X coordinate is 85 mm to 125 mm.

[0059] By inserting the two carrier portions 2 into the carrier 6 in a manner that does not overlap with the central portion of the stepped wafer 5 in the X direction in a plan view, it is easy to insert the two carrier portions 2 between the stepped wafer 5a to be taken out and the stepped wafer 5b in the lower layer thereof.

[0060] The wafer stage 21 is designed as described above so that even in a situation such as Figure 4Even when the stepped wafer 5 is on the upper layer and the unstepped semiconductor wafer 4 is on the lower layer, i.e., when the gap for inserting the wafer holder 21 is minimized, sufficient clearance is ensured to allow the wafer holder 21 to be inserted. Therefore, there is no need to adjust the position of the wafer holder 21 during insertion to match the configuration of the wafers accommodated in the carrier 6. This eliminates the need for positional adjustments, preventing malfunctions caused by incorrectly setting the position for inserting the wafer holder 21. This improves production efficiency and prevents wafer damage caused by incorrect settings.

[0061] After the wafer holder 21 is inserted, the wafer holder 21 is raised until the stepped wafer 5a contacts the two receiving portions 2, so that the stepped wafer 5a is held only by the two receiving portions 2 and not by the supporting portion 7. At this time, the wafer is held by the two receiving portions 2 up to the end opposite to the insertion side of the wafer holder 21. Therefore, the deflection of the end of the stepped wafer 5a held by the two receiving portions 2 opposite to the insertion side is reduced.

[0062] Next, the wafer holder 21 is slightly raised to such an extent that it does not come into contact with the stepped wafer 5 accommodated above the stepped wafer 5a.

[0063] Next, the wafer holder 21 holding the stepped wafer 5a is pulled out from the carrier 6. The stepped wafer 5a pulled out from the carrier 6 is then transported by the wafer holder 21 to a processing station or the like of an apparatus for processing the stepped wafer 5a.

[0064] Next, the operation of transporting the wafer 5 with a step from the processing stage or the like to the carrier 6 and accommodating the wafer 5 with a step in the carrier 6 will be described.

[0065] First, the wafer holder 21 is positioned below the wafer 5 with a step that has been processed (hereinafter referred to as the wafer 5c with a step).

[0066] Next, the wafer holder 21 is gradually raised to bring the stepped wafer 5 c into contact with the two stages 2 , so that the stepped wafer 5 c is held only by the two stages 2 and not by the processing stage.

[0067] Next, move the wafer stage 21 from the processing table to near the carrier 6. Next, position the wafer stage 21 above the support portion 7 at the object receiving position of the carrier 6. Next, insert the wafer stage 21 into a position that satisfies the following condition: the stepped wafer 5c held by the wafer stage 21 does not contact the most curved central portion of the stepped wafer 5 accommodated in the layer above the stepped wafer 5c. After that, gradually lower the wafer stage 21 so that the stepped wafer 5c contacts the support portion 7, and make the stepped wafer 5c be in a state of being held only by the support portion 7 and not by the two carrier portions 2. After that, pull out the wafer stage 21 from the carrier 6 to complete the accommodation.

[0068] <A-3. Modified Example>

[0069] It has been described that each of the two carrier portions 2 of the wafer stage 21 has an inner side surface that linearly extends in the second direction in a plan view, but each of the two carrier portions 2 can also be a more common shape. In addition, the shape of the wafer stage 21 has been described assuming a 300 mm wafer, but wafers of different sizes can also be assumed. For a larger-sized wafer, the bending when accommodated in the carrier is greater, so a wafer stage similar to the wafer stage 21 is useful.

[0070] That is, the wafer stage 21 can also be, for example, a wafer stage that can place an object having a disc shape with a diameter of d (mm) in a manner that satisfies the following conditions (a) and (b).

[0071] By making the wafer stage 21 satisfy condition (a), as Figure 1 shown, it is possible to place the stepped wafer 5 while avoiding the central portion in the x direction of the stepped wafer 5. In addition, by making the wafer stage 21 satisfy condition (a), when taking out the stepped wafer 5 from the carrier 6 through the wafer stage 21, the wafer stage 21 will not catch on the support portion 7. In addition, by making the wafer stage 21 satisfy condition (b), the carrier portion 2 can support the stepped wafer 5 across the entire Y direction.

[0072] The wafer stage 21 can also be, for example, a wafer stage that can place an object having a disc shape with a diameter of d (mm) in a manner that satisfies the following conditions (a), (b), and (c). [[ID=1》

[0073] By satisfying condition (c), the front end of the wafer stage 21 can be inserted into Figure 6 the narrow opening 16 of the carrier 6 as shown.

[0074] In addition, the wafer stage 21 can also be, for example, a wafer stage that can place an object having a disc shape with a diameter of d (mm) in a manner that satisfies the following conditions (d) and (e).

[0075] By satisfying conditions (d) and (e), the same advantages as in the case of satisfying conditions (a), (b), and (c) are obtained.

[0076] (a) In the x-direction, outside the region where the distance from the center of the object is greater than or equal to 85×(d / 300) mm and less than or equal to 140×(d / 300) mm, the two carrying portions 2 and the joint portion 3 do not overlap in a plan view.

[0077] (b) In the x-direction, in each of the two regions where the distance from the center of the object is greater than or equal to 85×(d / 300) mm and less than or equal to 140×(d / 300) mm, each of the two carrying portions 2 extends further on the y-direction side than the side surface of the object on the y-direction side.

[0078] (c) The portions of the two carrying portions 2 that are further on the y-direction side than the side surface of the object on the y-direction side fall within the region where the distance from the center of the object in the x-direction is greater than or equal to 85×(d / 300) mm and less than or equal to 125×(d / 300) mm.

[0079] (d) In the x-direction, outside the region where the distance from the center of the object is greater than or equal to 85×(d / 300) mm and less than or equal to 125×(d / 300) mm, the two carrying portions 2 and the joint portion 3 do not overlap in a plan view.

[0080] (e) In the x-direction, in each of the two regions where the distance from the center of the object is greater than or equal to 85×(d / 300) mm and less than or equal to 125×(d / 300) mm, each of the two carrying portions 2 extends to a further position on the y-direction side than the side surface of the object on the y-direction side.

[0081] The diameter d of the disk-shaped object can also be, for example, greater than or equal to 295 mm. Specifically, the diameter d of the disk-shaped object can be, for example, 300 mm or 450 mm.

[0082] <B. Embodiment 2>

[0083] Figure 8 The wafer carrier 22 of the present embodiment shown is different from the wafer carrier 21 of Embodiment 1 in that it has a mounting portion 8 and a guiding portion 9. The wafer carrier 22 is the same as the wafer carrier 21 in other respects. In addition, Figure 9 is Figure 8 a cross-sectional view taken along the α3-β3 line.

[0084] Regarding the wafer carrier 22, the mounting portion 8 and the guiding portion 9 are provided at both the end on the y-direction side and the end on the side opposite to the y-direction side at each of the two carrying portions 2.

[0085] The wafer holder 22 may be provided with only one of the placement portion 8 and the guide portion 9 .

[0086] The guide portion 9 restricts the position of the stepped wafer 5 in the in-plane direction, thereby suppressing deviation of the stepped wafer 5 from the proper position.

[0087] Each placement portion 8 is used to place a wafer on its top surface. The top surface of each placement portion 8 is not tilted. The tilt of the top surface of each placement portion 8 is, for example, less than 3°. The tilt of the top surface of each placement portion 8 is, for example, less than 1°. The wafer is placed on the two receiving portions 2 via each placement portion 8.

[0088] By providing the placement portion 8, preferably, as Figure 8 and Figure 9 As shown, the wafer holder 22 can hold the stepped wafer 5 in a state where the wafer holder 22 is in contact only with the outer periphery of the stepped wafer 5. This can reduce the contact area between the wafer holder 22 and the stepped wafer 5.

[0089] exist Figure 10 In the case where the wafer 5 with the step on the α3-β3 line is convex downward, the height of the lowest position of the lower surface of the wafer 5 with the step on the α3-β3 line is plotted. In the case where the wafer 5 with the step on the α3-β3 line is convex upward, the height of the highest position of the lower surface of the wafer 5 with the step on the α3-β3 line is plotted. Figure 10 In the embodiment, the height of the upper surface of the placement portion 8 is set to 0 mm.

[0090] Figure 10 The data are obtained by measuring the height of the stepped wafer 5 on the α3-β3 line while using a sufficiently high placement portion and keeping the stepped wafer 5 out of contact with the wafer holder 22 .

[0091] The angle θ related to the configuration of the carrier 8 is the angle opened toward the first direction among the angles formed by the straight line connecting the center of the carrier 8d (for example, the circumferential center of the chip 5 with the step, hereinafter referred to as the circumferential center) and the circumferential center of the carrier 8b and the straight line connecting the circumferential center of the carrier 8a and the circumferential center of the carrier 8c when viewed from above.

[0092] The placement portion 8a is the placement portion 8 at the end of the support portion 2a on the y-direction side. The placement portion 8b is the placement portion 8 at the end of the support portion 2b on the y-direction side. The placement portion 8c is the placement portion 8 at the end of the support portion 2b on the opposite side in the y-direction. The placement portion 8d is the placement portion 8 at the end of the support portion 2a on the opposite side in the y-direction.

[0093] like Figure 10 As shown, when θ is small, the stepped wafer 5 is convex on the line α3-β3. When θ is small, the stepped wafer 5 is supported by the center portion in the second direction, so the front and rear ends in the second direction are lowered. Consequently, the wafer is convex along the line along the second direction.

[0094] In addition, if Figure 10 As shown, as θ increases, the degree of convexity of the wafer 5 having a step on the α3-β3 line increases.

[0095] In order to prevent the portion other than the placement portion 8 of the wafer holder 22 from contacting the wafer 5 with the step, it is preferable to set θ to be small. For example, if the height of the placement portion 8 is set to 1 mm, then when θ is less than or equal to 110°, the wafer 5 will not be moved when the step is maintained. Figure 10 In the case of the wafer 5 having a step after measurement shown in FIG. 1 , the wafer 5 having a step can be prevented from coming into contact with the wafer holder 22 .

[0096] More preferably, θ is less than or equal to 90°. Further preferably, θ is less than or equal to 85°. In the case where θ is less than or equal to 85°, Figure 10 As shown, the stepped wafer 5 is convex along the line α3-β3. Therefore, contact between the stepped wafer 5 and any portion of the wafer holder 22 other than the mounting portion 8 is further suppressed. When θ is small, the stepped wafer 5 is supported by the center portion in the second direction, so both front and rear ends in the second direction drop downward. However, because the stepped wafer 5 is mounted on the wafer holder 22 so that the bonding portion 3 and the stepped wafer 5 do not overlap when viewed from above, even if both ends in the second direction of the stepped wafer 5 drop downward, the stepped wafer 5 does not contact the bonding portion 3.

[0097] By setting θ to be equal to or greater than 67°, for example, the wafer 5 having a step can be stably held.

[0098] Therefore, θ is, for example, greater than or equal to 67° and less than or equal to 110°. More preferably, θ is, for example, greater than or equal to 67° and less than or equal to 85°.

[0099] Figure 11 and Figure 12 Each is with Figure 8 and Figure 9 The corresponding drawings show another example of this embodiment. Figure 12 yes Figure 11 Cross-sectional view of the α4-β4 line. Figure 11 and Figure 12 As shown, the wafer holder 22 may also be provided with suction holes 10. The openings of the suction holes 10 are provided on the upper surface of the mounting portion 8.

[0100] The wafer stage 22 sucks the stepped wafer 5 placed on the placement unit 8 through suction performed through the opening provided on the upper surface of the placement unit 8. Thereby, dropping of the stepped wafer 5 is suppressed. In addition, for example, high-speed movement or flipping of the wafer stage 22 can be performed.

[0101] At this time, it is preferable that the region for sucking the stepped wafer 5 is the flange 15 on the outer peripheral portion of the stepped wafer 5. Since the flange 15 is not polished and is thick, the flange 15 is sucked, thereby suppressing the possibility of damage to the stepped wafer 5 due to suction.

[0102] The semiconductor manufacturing apparatus 200 described in Embodiment 1 may have the wafer stage 22 instead of the wafer stage 21.

[0103] <C. Embodiment 3>

[0104] In the present embodiment, a method for manufacturing a semiconductor device using the wafer stage of any one of Embodiments 1 or 2 will be described.

[0105] <C-1. Structure of Semiconductor Device>

[0106] Figure 16 FIG. shows an example of a semiconductor device, a semiconductor element 50, manufactured by the present embodiment. The semiconductor element 50 is an IGBT (Insulated Gate Bipolar Transistor).

[0107] The semiconductor element 50 has a collector electrode 64 provided on the back side, a p-type collector layer 61 provided on the collector electrode 64, an n-type buffer layer 60 provided on the p-type collector layer 61, an n - -type drift layer 51 provided on the n - -type drift layer 51, a p-type base layer 52 provided on the p-type base layer 52, an n + -type emitter layer 53 provided in a partial region on the p-type base layer 52, a p + -type contact layer 54 provided in a region where the n + -type emitter layer 53 is not provided on the p-type base layer 52, and an emitter electrode 63 electrically connected to the n + -type emitter layer 53 and the p + -type contact layer 54. Here, n + -type or p + -type indicates that the impurity concentration in this region is higher than the impurity concentration in the n-type or p-type region. n - -type or p- The - type indicates that the impurity concentration in this region is lower than that in the n - type or p - type region.

[0108] In the case of the semiconductor device 50, a trench is formed that penetrates the p - type base layer 52 from the surface of the surface including the n - type emitter layer 53 and the p - type contact layer 54 and reaches the n - type drift layer 51. + type emitter layer 53 and p + type contact layer 54 to reach the n - type drift layer 51 through the p - type base layer 52. A trench gate is formed by disposing a buried gate electrode 58 in this trench隔着栅极绝缘膜57. The buried gate electrode 58 faces the n - type drift layer 51隔着栅极绝缘膜57. The gate insulating film 57 contacts the p - type base layer 52 and the n - type emitter layer 53. When a gate drive voltage is applied to the buried gate electrode 58, a channel is formed in the p - type base layer 52 that contacts the gate insulating film 57. An interlayer insulating film 59 is provided between the buried gate electrode 58 and the emitter electrode 63. - type drift layer 51. A trench gate is formed by disposing a buried gate electrode 58 in this trench隔着栅极绝缘膜57. The buried gate electrode 58 faces the n - type drift layer 51隔着栅极绝缘膜57. The gate insulating film 57 contacts the p - type base layer 52 and the n - type emitter layer 53. When a gate drive voltage is applied to the buried gate electrode 58, a channel is formed in the p - type base layer 52 that contacts the gate insulating film 57. An interlayer insulating film 59 is provided between the buried gate electrode 58 and the emitter electrode 63. - type drift layer 51. The gate insulating film 57 contacts the p - type base layer 52 and the n - type emitter layer 53. When a gate drive voltage is applied to the buried gate electrode 58, a channel is formed in the p - type base layer 52 that contacts the gate insulating film 57. An interlayer insulating film 59 is provided between the buried gate electrode 58 and the emitter electrode 63. + type emitter layer 53. When a gate drive voltage is applied to the buried gate electrode 58, a channel is formed in the p - type base layer 52 that contacts the gate insulating film 57. An interlayer insulating film 59 is provided between the buried gate electrode 58 and the emitter electrode 63.

[0109] The semiconductor device manufactured using the wafer holder of Embodiment 1 or 2 is not limited to an IGBT. For example, it can also be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a diode, or an RC - IGBT (Reverse - Conducting IGBT).

[0110] The semiconductor used in the semiconductor device manufactured using the wafer holder of Embodiment 1 or 2 is, for example, any of a silicon semiconductor, a silicon carbide semiconductor, and a gallium nitride semiconductor.

[0111] <C - 2. Manufacturing Method>

[0112] Figure 13 This is a flowchart showing the manufacturing method of the semiconductor device of the present embodiment. Hereinafter, the case of manufacturing the semiconductor element 50 will be described.

[0113] First, a structure on the surface side of the semiconductor element 50 is formed on the surface of the semiconductor wafer 4 (step S1).

[0114] Next, a surface protective film is formed on the surface of the semiconductor wafer 4 (step S2). The surface protective film protects the structure on the surface side of the semiconductor element 50 formed in step S1 when the back side of the semiconductor wafer 4 is processed in subsequent processes.

[0115] Next, the back side of the semiconductor wafer 4 is polished and etched to thin the semiconductor wafer (step S3). In step S3, first, the back side is polished by machining with a polishing stone. At this time, only the central portion of the back side of the semiconductor wafer 4 is polished, and the outer peripheral portion of the back side of the semiconductor wafer 4 is not polished. As a result, a stepped wafer 5 having a flange is formed in the outer peripheral portion. In step S3, thereafter, the back side of the stepped wafer 5 is wet-etched to thin the stepped wafer 5 to an appropriate thickness. In this wet etching, for example, a chemical solution containing hydrofluoric acid or nitric acid is used.

[0116] Next, a structure on the back side of the semiconductor element 50 is formed on the back side of the stepped wafer 5 (step S4). In step S4, an n-type buffer layer 60 and a p-type collector layer 61 are sequentially formed by ion implantation and heat treatment from the back side of the stepped wafer 5, and thereafter, a collector electrode 64 is formed on the back side of the stepped wafer 5.

[0117] The wafer holder 21 or the wafer holder 22 of Embodiment 1 or 2 is used, for example, to convey the semiconductor wafer thinned in step S3. For example, the stepped wafer 5 obtained by thinning the semiconductor wafer 4 in step S3 is accommodated in the carrier 6 by the wafer holder 21 or the wafer holder 22 of Embodiment 1 or 2. Since the stepped wafer 5 is thinned, it is held in a bent state due to its own weight in the carrier 6. Even if the stepped wafer 5 is held in a bent state due to its own weight in the carrier 6, conveyance by the wafer holder of Embodiment 1 or 2 can prevent the bent area of the wafer from contacting the wafer holder and perform conveyance. Feeding into the apparatus performing steps S4 to S6 and conveyance from the apparatus performing steps S4 and S5 into the carrier 6 also use the wafer holder of Embodiment 1 or 2. <F

[0118] The wafer holder 21 or the wafer holder 22 of Embodiment 1 or 2 is not only used after step S3, but can also be used in step S3 and the steps before it.

[0119] The bending mode of the stepped wafer 5 varies corresponding to the thickness of the stepped wafer 5, but by using the wafer holder 21 or the wafer holder 22 of Embodiment 1 or 2, alignment does not need to be performed each time when inserting the wafer into the wafer holder, and productivity can be improved.

[0120] <D. Comparative Example>

[0121] Figure 14 FIG is a view showing a wafer holder 100 of a comparative example. The wafer holder 100 has a shorter carrying portion 2 than the wafer holder of Embodiment 1 or 2. Therefore, when the wafer is placed on the wafer holder 100, the joining portion 3 overlaps with the wafer. Therefore, when taking out the wafer accommodated in the carrier 6, as Figure 15The gap C shown is small, and the wafer holder 100 and the wafer can be easily contacted.

[0122] exist Figure 7 When removing wafers in the situation shown, the wafer below the wafer being removed is also curved. Therefore, adjusting the position of the wafer holder 100 downward can ensure a gap between the upper and lower wafers. However, if the insertion position of the wafer holder 100 is adjusted to correspond to the state of the wafer at the bottom, malfunctions may occur due to, for example, incorrect wafer holder insertion position settings, potentially leading to reduced production efficiency or wafer damage due to incorrect settings. The wafer holder of Embodiment 1 or 2 can avoid such problems.

[0123] Furthermore, the various embodiments may be freely combined, or the various embodiments may be appropriately modified or omitted.

[0124] Description of the label

[0125] 2, 2a, 2b carrying part, 3 bonding part, 4 semiconductor wafer, 5, 5a, 5b, 5c wafer with step, 6 carrier, 7 supporting part, 8, 8a, 8b, 8c, 8d loading part, 9 guiding part, 10 adsorption hole, 15 flange, 16 opening, 21, 22, 100 wafer holder, 50 semiconductor element, 200 semiconductor manufacturing equipment.

Claims

1. A wafer holder comprising a joint portion and two supporting portions. The two supporting parts are arranged in a first direction, The two bearing parts are connected via the joint part, The two supporting portions each extend from the joint portion in a second direction perpendicular to the first direction. The distance between the side surfaces of the two supporting parts facing the direction intersecting the second direction and facing each other is greater than or equal to 170 mm. The distance between the side surfaces of the two supporting portions, each facing a direction intersecting the second direction and facing opposite sides to each other, is less than or equal to 280 mm. When the distance between the inner side surfaces of the two support portions is defined as A and the length of the inner side surfaces of the two support portions in the second direction is defined as L, L≥(300 2 -A 2 ) 0.5 The relationship is established, in which The unit of A and L is mm. The two supporting parts are each configured such that the outer side of the supporting part is shorter than the inner side of the supporting part. On one and the other of the two supporting parts, i.e., the first supporting part and the second supporting part, a placing part is provided at an end portion on the second direction side and an end portion on the side opposite to the second direction side, respectively. In a plan view, an angle of an angle opened toward the first direction among angles formed by a straight line connecting the center of the receiving portion at the end portion of the first supporting portion opposite to the second direction side and the center of the receiving portion at the end portion of the second supporting portion on the second direction side and a straight line connecting the center of the receiving portion at the end portion of the first supporting portion on the second direction side and the center of the receiving portion at the end portion of the second supporting portion on the opposite side to the second direction side is less than or equal to 110°, Each of the two supporting parts, namely the first supporting part and the second supporting part, is provided with a guide part at an end portion on the second direction side and an end portion on the side opposite to the second direction side. The guide portion limits the position of the wafer placed on the wafer holder in the in-plane direction. The guide portion is provided on the placement portion.

2. The wafer holder according to claim 1, wherein: The distance between the side surfaces of the two supporting portions, which face the direction intersecting the second direction and face opposite to each other, is less than or equal to 250 mm.

3. The wafer holder according to claim 1, wherein: The angle of the angle opened toward the first direction is greater than or equal to 67°.

4. The wafer holder according to claim 1 or 3, wherein: A suction hole having an opening is provided on the upper surface of the mounting portion, The wafer placed on the upper surface of the placement portion is adsorbed by suction from the opening.

5. The wafer holder according to claim 1 or 3, wherein: The inclination of the upper surface of the placement portion is less than 3°.

6. A wafer holder comprising a joint portion and two supporting portions. The two supporting parts are arranged in a first direction, The two bearing parts are connected via the joint part, The two supporting portions each extend from the joint portion in a second direction perpendicular to the first direction. A disk-shaped object with a diameter d greater than or equal to 295 mm can be placed in a manner that satisfies both conditions (a) and (b), that is: (a) in the first direction, outside an area greater than or equal to 85 × (d / 300) mm and less than or equal to 140 × (d / 300) mm from the center of the object, the two supporting portions and the joining portion do not overlap when viewed from above; (b) in each of two regions in the first direction at a distance from the center of the object of not less than 85×(d / 300) mm and not more than 140×(d / 300) mm, each of the two supporting portions extends further toward the second direction side than a side surface of the object on the second direction side; On one and the other of the two supporting parts, i.e., the first supporting part and the second supporting part, a placing part is provided at an end portion on the second direction side and an end portion on the side opposite to the second direction side, respectively. In a plan view, an angle of an angle opened toward the first direction among angles formed by a straight line connecting the center of the receiving portion at the end portion of the first supporting portion opposite to the second direction side and the center of the receiving portion at the end portion of the second supporting portion on the second direction side and a straight line connecting the center of the receiving portion at the end portion of the first supporting portion on the second direction side and the center of the receiving portion at the end portion of the second supporting portion on the opposite side to the second direction side is less than or equal to 110°, Each of the two supporting parts, namely the first supporting part and the second supporting part, is provided with a guide part at an end portion on the second direction side and an end portion on the side opposite to the second direction side. The guide portion limits the position of the wafer placed on the wafer holder in the in-plane direction. The guide portion is provided on the placement portion.

7. The wafer holder according to claim 6, wherein: The object can be placed in a manner that satisfies the three conditions (a), (b), and (c), that is, (c) The portion of each of the two supporting parts that is closer to the second direction side than the side surface of the object on the second direction side falls within an area whose distance from the center of the object in the first direction is greater than or equal to 85×(d / 300) mm and less than or equal to 125×(d / 300) mm.

8. The wafer holder according to claim 6, wherein: Instead of (a) and (b), the object may be placed so as to satisfy the two conditions (d) and (e), that is: (d) in the first direction, outside an area where the distance from the center of the object is greater than or equal to 85×(d / 300) mm and less than or equal to 125×(d / 300) mm, the area does not overlap with the two supporting portions and the joining portion when viewed from above; (e) In each of two regions in the first direction at a distance from the center of the object greater than or equal to 85×(d / 300) mm and less than or equal to 125×(d / 300) mm, each of the two supporting portions extends closer to the second direction side than the side surface of the object on the second direction side.

9. The wafer holder according to claim 6, wherein: The angle of the angle opened toward the first direction is greater than or equal to 67°.

10. The wafer holder according to claim 6 or 9, wherein: A suction hole having an opening is provided on the upper surface of the mounting portion, The wafer placed on the upper surface of the placement portion is adsorbed by suction from the opening.

11. The wafer holder according to claim 6 or 9, wherein: The inclination of the upper surface of the placement portion is less than 3°.

12. A semiconductor manufacturing apparatus comprising the wafer holder according to any one of claims 1 to 11.

13. A method for manufacturing a semiconductor device, wherein a semiconductor wafer is transported using a wafer holder. The method for manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thickness thinner at a central portion than at a peripheral portion, The diameter d of the semiconductor wafer is greater than or equal to 295 mm, wherein The unit of d is mm, The wafer holder has two supporting parts extending along the second direction. The method for manufacturing a semiconductor device further comprises the step of conveying the semiconductor wafer by placing it on the two receiving portions in a state where the semiconductor wafer and the wafer holder do not overlap when viewed from above, except for a region greater than or equal to 85×(d / 300) mm and less than or equal to 140×(d / 300) mm from the center of the semiconductor wafer in a first direction orthogonal to the second direction; On one and the other of the two supporting parts, i.e., the first supporting part and the second supporting part, a placing part is provided at an end portion on the second direction side and an end portion on the side opposite to the second direction side, respectively. In a plan view, an angle of an angle opened toward the first direction among angles formed by a straight line connecting the center of the receiving portion at the end portion of the first supporting portion opposite to the second direction side and the center of the receiving portion at the end portion of the second supporting portion on the second direction side and a straight line connecting the center of the receiving portion at the end portion of the first supporting portion on the second direction side and the center of the receiving portion at the end portion of the second supporting portion on the opposite side to the second direction side is less than or equal to 110°, Each of the two supporting parts, namely the first supporting part and the second supporting part, is provided with a guide part at an end portion on the second direction side and an end portion on the side opposite to the second direction side. The guide portion limits the position of the wafer placed on the wafer holder in the in-plane direction. The guide portion is provided on the placement portion.

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