Method for preparing nanoscale patterned substrate and nanoscale patterned substrate

Abstract

The present invention discloses a method for preparing a nanoscale patterned substrate and a nanoscale patterned substrate, the method comprising: providing a substrate, forming a photoresist layer on the substrate; patterning the photoresist layer, forming a plurality of first circular holes penetrating the photoresist layer on the photoresist layer; forming a first sacrificial layer, the first sacrificial layer covers the inner wall of the first circular hole to form a second circular hole with a diameter of nanometers; forming a first etching mask layer, the first etching mask layer fills the second circular hole and forms a cylinder with a diameter of nanometers in the second circular hole; etching the substrate, forming a nanoscale cone array on the surface of the substrate. The present invention can realize the manufacture of a nanoscale patterned substrate with a conical morphology using a micrometer-level process.

Description

Technical Field

[0001] The present invention relates to the field of LED substrate manufacturing, and more specifically, to a method for preparing a nanoscale patterned substrate and the nanoscale patterned substrate. Background Art

[0002] In the field of LED (Light emitting diode), PSS (patterned sapphire substrate) is designed and manufactured on the sapphire substrate by etching (dry etching / wet etching on the C surface of sapphire) to produce micron-level or nano-level patterns with specific microstructure rules, thereby controlling the output light form of the LED device (the concave-convex pattern on the sapphire substrate will produce light scattering or refraction effects to increase the light extraction rate). At the same time, the growth of GaN film on the patterned sapphire substrate will produce a lateral epitaxial effect, reducing the dislocation defects between GaN grown on the sapphire substrate, improving the epitaxial quality, and improving the internal quantum efficiency of the LED and increasing the light extraction efficiency. Compared with LEDs based on general sapphire substrates, the brightness of LEDs based on PSS has increased by more than 70%.

[0003] As the resolution of LED displays continues to increase, the pixel pitch of LED devices continues to decrease, and the chip size has gradually decreased from the early millimeter level to the current micrometer level, and may even reach the nanometer level in the future. It has been proven that the performance of LED devices using nanometer-level patterned sapphire substrates, such as light output power, is better than that of planar sapphire substrates. However, the existing preparation methods of micrometer-level sapphire graphic substrates are limited by factors such as lithography exposure accuracy and cannot be used to obtain nanometer-level PSS substrates. The method of nanometer-level patterned sapphire substrates has high requirements for lithography accuracy and high equipment cost, and there are problems such as uneven distribution of the microstructure of the patterned sapphire surface, or difficulty in producing microscopic cone structures with pointed tips. Summary of the invention

[0004] The purpose of the present invention is to provide a method for preparing a nanoscale patterned substrate and a nanoscale patterned substrate, so as to realize the manufacture of a nanoscale patterned substrate having a conical morphology by using a micron-scale process.

[0005] In a first aspect, the present invention provides a method for preparing a nanoscale patterned substrate, comprising:

[0006] providing a substrate, and forming a photoresist layer on the substrate;

[0007] Patterning the photoresist layer to form a plurality of first circular holes penetrating the photoresist layer on the photoresist layer;

[0008] forming a first sacrificial layer, wherein the first sacrificial layer covers the inner wall of the first circular hole to form a second circular hole with a nanometer-scale diameter;

[0009] forming a first etching mask layer, wherein the first etching mask layer fills the second circular hole and forms a column with a nanometer diameter in the second circular hole;

[0010] The substrate is etched to form a nanoscale cone array on the surface of the substrate.

[0011] Optionally, forming a first sacrificial layer includes:

[0012] forming the first sacrificial layer on the photoresist layer, wherein the first sacrificial layer covers the surface of the photoresist layer, the sidewall of the first circular hole and the bottom of the first circular hole;

[0013] The first sacrificial layer on the inner wall of the first circular hole forms a side wall, and the side wall surrounds the second circular hole;

[0014] The first sacrificial layer at the bottom of the second circular hole is removed.

[0015] Optionally, forming a first etching mask layer includes:

[0016] forming a second sacrificial layer on the substrate, wherein the second sacrificial layer fills the second circular hole and covers the first sacrificial layer above the photoresist layer;

[0017] The first sacrificial layer and the second sacrificial layer above the photoresist layer are removed to expose the photoresist layer; the remaining second sacrificial layer is formed into a column with a nanometer diameter in the second circular hole;

[0018] removing the photoresist layer to expose the sidewall;

[0019] The sidewall spacer is removed, and the remaining second sacrificial layer forms the first etching mask layer.

[0020] Optionally, before removing the first sacrificial layer at the bottom of the first circular hole, the preparation method further includes:

[0021] forming a second sacrificial layer on the substrate, wherein the second sacrificial layer fills the second circular hole and covers the first sacrificial layer above the photoresist layer;

[0022] removing the first sacrificial layer and the second sacrificial layer above the photoresist layer, and exposing the photoresist layer;

[0023] removing the photoresist layer to expose the sidewall;

[0024] forming a third sacrificial layer, wherein the third sacrificial layer covers the substrate and surrounds the sidewalls, and the third sacrificial layer is made of the same material as the first sacrificial layer;

[0025] The second sacrificial layer in the second circular hole is removed.

[0026] Optionally, after removing the first sacrificial layer at the bottom of the second circular hole, forming an etching mask layer includes:

[0027] forming a fourth sacrificial layer, wherein the fourth sacrificial layer fills the second circular hole and forms a nano-scale column in the second circular hole;

[0028] The third sacrificial layer and the sidewall spacer are removed, and the remaining fourth sacrificial layer forms the first etching mask layer.

[0029] Optionally, before forming the photoresist layer on the substrate, the preparation method further comprises: forming a first dielectric layer on the surface of the substrate, and the first etching mask layer is formed on the first dielectric layer.

[0030] Optionally, the material of the fourth sacrificial layer is photoresist, and the material of the first dielectric layer is silicon dioxide.

[0031] Optionally, one of the first sacrificial layer and the second sacrificial layer is silicon nitride, and the other is silicon dioxide; or, one of them is metal, and the other is silicon dioxide or silicon nitride; or both are different metal materials.

[0032] Optionally, the substrate is a sapphire substrate.

[0033] In a second aspect, the present invention provides a nanoscale patterned substrate, wherein the nanoscale patterned substrate is obtained by using the method for preparing the nanoscale patterned substrate described in any one of the first aspects.

[0034] The beneficial effects of the present invention are:

[0035] The present invention first forms a photoresist layer on a substrate, then patterns the photoresist layer, forms a plurality of first circular holes penetrating the photoresist layer on the photoresist layer, then forms a first sacrificial layer to cover the inner wall of the first circular hole, thereby forming a second circular hole with a nanometer diameter in the photoresist layer, then fills the second circular hole with the second sacrificial layer and forms a cylinder with a nanometer diameter in the second circular hole, then removes the side wall formed by the photoresist layer and the first sacrificial layer, so that the second sacrificial layer filling the second circular hole forms a first etching mask layer of a cylinder array on the surface of the substrate, etches the substrate using the first etching mask layer, and forms a nanometer-scale cone array on the surface of the substrate. The method can reduce the size of the circular hole by forming a side wall with a certain thickness on the inner wall of the circular hole in the photoresist layer, so that the diameter of the circular hole reaches the nanometer level, so that a nanometer-scale cylinder mask can be prepared in the subsequent process, and then a nanometer-scale cone array can be etched on the surface of the substrate, and a regular patterned substrate with a nanometer-scale cone morphology can be manufactured using a micrometer-level semiconductor manufacturing process.

[0036] The system of the present invention has other characteristics and advantages, which will be apparent from the drawings incorporated herein and the following detailed description, or will be described in detail in the drawings incorporated herein and the following detailed description, which together serve to explain the specific principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.

[0038] Figure 1 A characterization diagram of the etching process of an existing micron-scale sapphire patterned substrate is shown. Figure 2 A schematic diagram of photoresist patterning in an existing micron-scale sapphire substrate patterning method is shown.

[0039] Figure 3 A step diagram of a method for preparing a nanoscale patterned substrate according to Example 1 of the present invention is shown.

[0040] Figure 4 A schematic diagram of structural changes corresponding to each step of a method for preparing a nanoscale patterned substrate according to Example 1 of the present invention is shown.

[0041] Figure 5 A schematic diagram of photoresist patterning in a method for preparing a nanoscale patterned substrate according to Example 1 of the present invention is shown.

[0042] Figure 6A schematic diagram of structural changes corresponding to each step of a method for preparing a nanoscale patterned substrate according to Example 2 of the present invention is shown. DETAILED DESCRIPTION

[0043] Existing methods for preparing micron-scale sapphire patterned substrates, such as Figure 1 As shown in FIG. 1 , a cross-sectional representation diagram of each process of etching preparation is shown, and finally a conical patterned PSS substrate is obtained. The top view of the photoresist before etching is shown in FIG. Figure 2 As shown in the figure, the black area represents the photoresist left on the wafer surface after photolithography, and the white part represents the photoresist washed away after photolithography, that is, the wafer substrate that exposes this area. Due to the micron-level process, it is limited by factors such as photolithography exposure accuracy and cannot be used to obtain nano-level PSS substrates. In theory, to obtain a nano-level conical patterned substrate, it is only necessary to make the black part of the photoresist pattern nano-level, but this poses a challenge to the resolution of photolithography, especially in the case where a circular pattern is left and most of the area is washed away. The uniformity of each circular pattern after being miniaturized to the nanometer level is difficult to control.

[0044] In this regard, the present invention can realize the manufacture of nanometer-scale patterned substrates by using existing micrometer-scale process equipment without increasing the resolution of the lithography machine, that is, without increasing the equipment cost.

[0045] The present invention will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0046] Example 1

[0047] like Figure 3 and Figure 4 As shown, a method for manufacturing a nanoscale patterned substrate comprises:

[0048] S101: providing a substrate, and forming a photoresist layer 2 on the substrate;

[0049] Specifically, the substrate in this embodiment is a sapphire substrate 1 (wafer), and photoresist can be spin-coated on the substrate to form a photoresist layer 2. Preferably, the thickness of the photoresist layer 2 is 2 to 10 microns, and the spin-coating speed can be determined according to the thickness value.

[0050] S102: patterning the photoresist layer 2, forming a plurality of first circular holes 3 penetrating the photoresist layer 2 on the photoresist layer 2;

[0051] Specifically, in this embodiment, a micron-level photolithography machine can be used to pattern the photoresist layer 2. The method for patterning the photoresist layer 2 includes photolithography exposure and development. In this step, the mask template for patterning the photoresist layer 2 can be designed and processed in advance as needed. After development, the following is obtained: Figure 5 In the photoresist pattern shown, the diameter of the first circular hole 3 on the photoresist layer 2 is less than or equal to 1 micron, wherein the exposure time ranges from 3 to 20 seconds, preferably 6 seconds in this embodiment, the development time ranges from 45 to 120 seconds, preferably 75 seconds in this embodiment, and the fixing time ranges from 60 to 300 seconds, preferably 120 seconds in this embodiment, to pattern the photoresist.

[0052] S103: forming a first sacrificial layer 4, the first sacrificial layer 4 covers the inner wall of the first circular hole 3 to form a second circular hole 5 with a diameter of nanometer level;

[0053] In this embodiment, the method of forming the first sacrificial layer 4 includes:

[0054] A first sacrificial layer 4 is formed on the photoresist layer 2, wherein the first sacrificial layer 4 covers the surface of the photoresist layer 2, the sidewall of the first circular hole 3 and the bottom of the first circular hole 3;

[0055] The first sacrificial layer 4 on the inner wall of the first circular hole 3 forms a side wall 7, and the side wall 7 surrounds the second circular hole 5;

[0056] The first sacrificial layer 4 at the bottom of the second circular hole 5 is removed.

[0057] Specifically, a first sacrificial layer 4 can be formed on the photoresist layer 2 by using a plasma enhanced chemical vapor deposition process, and the first sacrificial layer 4 covers the surface of the photoresist layer 2, the sidewall of the first circular hole 3 and the bottom of the first circular hole 3; wherein the first sacrificial layer 4 covering the inner wall of the circular hole forms a sidewall 7;

[0058] Afterwards, the first sacrificial layer 4 is etched by a dry etching process to remove the first sacrificial layer 4 at the bottom of the circular hole and expose the surface of the substrate.

[0059] In this embodiment, the material of the first sacrificial layer 4 is preferably silicon nitride. A layer of silicon nitride can be grown by plasma enhanced chemical vapor deposition. The process conditions for forming the first sacrificial layer 4 are:

[0060] The chamber temperature range is 300-500 degrees Celsius, preferably 400 degrees Celsius, the intake flow range is 10-10000sccm, preferably 1000sccm, the gas types include one or more of silane, ammonia, and nitrogen, the chamber pressure range is 50-50000mTorr, preferably 650mTorr, the RF power range is 5-50000W, preferably 100W, the thickness is determined according to the diameter of the first circular hole 3 of the lithography so that the remaining circular hole diameter reaches the nanometer level, ranging from 10nm to 1000nm, and the thickness of the deposited silicon nitride is preferably 500nm.

[0061] Afterwards, the silicon nitride is etched by plasma, and stops on the sapphire substrate 1 to remove the first sacrificial layer 4 at the bottom of the first circular hole 3. The etching process conditions are:

[0062] The chamber pressure range is 0.5 to 50 mTorr, the upper electrode power range is 600 to 3000 W, the lower electrode power range is 50 to 3000 W, the chuck temperature range is -15 to 50°C, and the etching gas adopts a carbon fluorine gas, which can be one or more of carbon fluorine gases such as octafluorocyclobutane, hexafluorobutadiene, carbon tetrafluoride, trifluoromethane, difluoromethane, and fluoromethane. Hydrogen or oxygen can also be added to adjust the selection ratio. The etching gas flow range is 10 to 1000 sccm, the wafer back helium pressure range is 1 to 20 Torr, and the process time depends on the thickness of the grown silicon nitride.

[0063] S104: forming a first etching mask layer, the first etching mask layer fills the second circular hole 5 and forms a column with a nanometer diameter in the second circular hole 5;

[0064] Wherein, forming the first etching mask layer comprises:

[0065] forming a second sacrificial layer 6 on the substrate, wherein the second sacrificial layer 6 fills the second circular hole 5 and covers the first sacrificial layer 4 above the photoresist layer 2;

[0066] The first sacrificial layer 4 and the second sacrificial layer 6 on the photoresist layer 2 are removed to expose the photoresist layer 2; the remaining second sacrificial layer 3 forms a column with a diameter of nanometer level in the second circular hole 5;

[0067] Removing the photoresist layer 2 to expose the sidewall 7;

[0068] The spacers 7 are removed, and the remaining second sacrificial layer 6 forms a first etching mask layer.

[0069] Specifically, in this step, a high-density plasma chemical vapor deposition process may be used to deposit the second sacrificial layer 6 on the substrate, and the second sacrificial layer 6 fills the second circular hole 5 and covers the first sacrificial layer 4 above the photoresist layer 2 .

[0070] In this embodiment, the material of the second sacrificial layer 6 is preferably silicon dioxide, and high-density plasma chemical vapor deposition can be used to fill the silicon dioxide. The deposition process conditions are:

[0071] The temperature range is 300 degrees Celsius to 1000 degrees Celsius, preferably 400 degrees Celsius, the intake flow range is 10 to 10000 sccm, preferably 1000 sccm, the process gas types include one or more of silane, oxygen, hydrogen, argon, nitrogen, and nitrogen trifluoride, the chamber pressure range is 5 to 500 mTorr, preferably 7 mTorr, the upper RF power range is 500 to 50000 W, preferably 5000 W, and the lower RF power range is 50 to 50000 W, preferably 5000 W.

[0072] Then, chemical mechanical polishing is used to remove the first sacrificial layer 4 and the second sacrificial layer 6 above the photoresist layer 2, and the photoresist layer 2 is exposed until the top surface of the photoresist layer 2 is exposed, wherein the polishing liquid flow rate in the chemical mechanical polishing process is 50 to 500 mL / min, preferably 200 mL / min, and the pressure applied to the wafer by the grinding head is 0.1 to 10 psi, preferably 50 g / cm 2 , rotation speed 5 to 50 rpm, preferably 10 rpm.

[0073] Then, the photoresist is removed by wet method. A mixed solution of concentrated sulfuric acid and hydrogen peroxide can be used, or an organic solvent such as acetone can be used to wash away the photoresist.

[0074] Afterwards, a plasma dry etching process is used to remove the silicon nitride sidewalls 7 . The etching process conditions refer to the process conditions for etching silicon nitride in step S103 .

[0075] After removing the photoresist and the silicon nitride sidewalls 7 , only the nano-column array composed of silicon dioxide remains on the sapphire substrate 1 . The photoresist nano-column array serves as a mask layer for etching the sapphire substrate 1 .

[0076] S105: Etching the substrate to form a nanoscale cone array on the surface of the substrate.

[0077] Specifically, in this embodiment, the cylindrical array formed by the second sacrificial layer 6 is used as the first etching mask layer, and the sapphire substrate 1 is etched by plasma, and the etching process conditions are:

[0078] The chamber pressure range is 0.5 to 50 mTorr, preferably 2.6 mTorr, the upper electrode power range is 600 to 3000 W, preferably 1200 W, the lower electrode power range is 50 to 3000 W, preferably 500 W, the chuck temperature range is -15 to 50°C, preferably 20°C, the BCl3 flow range is 10 to 1000 sccm, preferably 100 sccm, the back helium pressure range is 1 to 20 Torr, and the process time depends on the etching depth.

[0079] In this step, the silicon dioxide serving as the first etching mask layer is etched together, and a cone of sapphire material is etched under each nanometer-scale silicon dioxide column, thereby forming a nanometer-scale cone array morphology on the surface of the sapphire substrate 1 .

[0080] In this embodiment, after forming the nanoscale cone array, the method further includes:

[0081] Step S106: forming a gallium nitride epitaxial layer 8 covering the cone array on the substrate through an epitaxial process.

[0082] Specifically, the growth method of the gallium nitride epitaxial layer 8 of the present embodiment is as follows: trimethyl indium, trimethyl gallium and ammonia are introduced into the reaction chamber, the temperature is raised to 700°C, the growth rate is controlled at 0.05μm / h, and a 5nm thick InGaN nucleation layer is deposited on the substrate; then, the introduction of trimethyl indium, trimethyl gallium and ammonia is continued, the temperature in the chamber is increased to 800°C, the growth rate is increased to 0.2μm / h, and an InGaN insertion layer is formed; then the introduction of trimethyl indium is stopped, trimethyl gallium and ammonia are continued to be introduced into the reaction chamber, the temperature is raised to 1100°C, and the deposition of the GaN epitaxial layer 8 is continued thereon.

[0083] It should be noted that, in the present embodiment, the materials of the first sacrificial layer 4 and the second sacrificial layer 6 can be interchanged, and the material of the first sacrificial layer 4 is silicon dioxide, and the material of the second sacrificial layer 6 is silicon nitride. In addition to the combination of silicon dioxide and silicon nitride, the materials of the first sacrificial layer 4 and the second sacrificial layer 6 can also be a combination of metal (such as gold, silver, copper, aluminum, titanium, etc.) / silicon dioxide, metal (such as gold, silver, copper, aluminum, titanium, etc.) / silicon nitride or metal / metal (such as copper / aluminum). If different combinations of the first sacrificial layer 4 and the second sacrificial layer 6 materials are selected, specific etching process conditions can be set according to the etching selectivity ratio of the two sacrificial materials.

[0084] Example 2

[0085] like Figure 6 As shown, this embodiment provides another method for manufacturing a nanoscale patterned substrate, comprising: step S201: providing a substrate, and forming a photoresist layer 2 on the substrate;

[0086] In this embodiment, before forming the photoresist layer 2 on the substrate, the preparation method further includes: forming a first dielectric layer 11 on the surface of the substrate, and forming a first etching mask layer formed subsequently on the first dielectric layer 11. In this embodiment, the material of the first dielectric layer 11 is silicon dioxide.

[0087] Specifically, before executing step S201, a sapphire substrate 1 is first provided, and then a layer of silicon dioxide is grown on the sapphire substrate 1 as a first dielectric layer 11. The thickness of the first dielectric layer 11 is 1 to 5 microns, preferably 2 microns. The first dielectric layer 11 can be formed by low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, electron beam evaporation, magnetron sputtering and other processes.

[0088] Then, step S201 is performed to spin-coat photoresist on the first dielectric layer 11 to form a photoresist layer 2 with a thickness of 2 to 10 microns. In this embodiment, the thickness of the photoresist layer 2 is preferably twice the thickness of the previously grown silicon dioxide (first dielectric layer 11), i.e., 6 microns. The spin coating speed is determined according to the thickness value of the photoresist.

[0089] Step S202: patterning the photoresist layer 2, forming a plurality of first circular holes 3 penetrating the photoresist layer 2 on the photoresist layer 2;

[0090] Specifically, the method of patterning the photoresist layer 2 refers to step S102 of embodiment 1.

[0091] Step S203: forming a first sacrificial layer 4, wherein the first sacrificial layer 4 covers the inner wall of the first circular hole 3 to form a second circular hole 5 with a diameter of nanometer level;

[0092] Wherein, forming the first sacrificial layer comprises:

[0093] A first sacrificial layer 4 is formed on the photoresist layer 2, wherein the first sacrificial layer 4 covers the surface of the photoresist layer 2, the sidewall of the first circular hole 3 and the bottom of the first circular hole 3;

[0094] The first sacrificial layer 4 on the inner wall of the first circular hole 3 forms a side wall 7, and the side wall 7 surrounds the second circular hole 5;

[0095] The first sacrificial layer 4 at the bottom of the second circular hole 5 is removed.

[0096] In this embodiment, before removing the first sacrificial layer 4 at the bottom of the first circular hole 3, the preparation method of this embodiment further includes:

[0097] forming a second sacrificial layer 6 on the substrate, wherein the second sacrificial layer 6 fills the second circular hole 5 and covers the first sacrificial layer 4 above the photoresist layer 2;

[0098] removing the first sacrificial layer 4 and the second sacrificial layer 6 above the photoresist layer 2 and exposing the photoresist layer 2;

[0099] Removing the photoresist layer 2 to expose the sidewall 7;

[0100] forming a third sacrificial layer 9, the third sacrificial layer 9 covers the substrate and surrounds the sidewall 7, and the third sacrificial layer 9 is made of the same material as the first sacrificial layer 4;

[0101] The second sacrificial layer 6 in the second circular hole 5 is removed.

[0102] Specifically, the method of forming the first sacrificial layer 4 in this step includes:

[0103] A first sacrificial layer 4 is formed on the photoresist layer 2 by a plasma enhanced chemical vapor deposition process, and the first sacrificial layer 4 covers the surface of the photoresist layer 2, the inner wall of the first circular hole 3, and the substrate surface exposed at the bottom of the first circular hole 3, wherein the first sacrificial layer 4 covering the inner wall of the circular hole forms a side wall 7.

[0104] Preferably, the first sacrificial layer 4 in this embodiment is silicon nitride, and the method for depositing the first sacrificial layer 4 is referred to step S103 of embodiment 1. The thickness of the sidewall 7 in this embodiment ranges from 10nm to 1000nm, preferably 500nm, so that the remaining circular hole diameter reaches nanometer level.

[0105] After forming the first sacrificial layer 4, a second sacrificial layer 6 is formed on the substrate, and the second sacrificial layer 6 fills the second circular hole 5. The method for forming the second sacrificial layer 6 includes:

[0106] A second sacrificial layer 6 is deposited on the substrate by a high-density plasma chemical vapor deposition process. The second sacrificial layer 6 fills the second circular hole 5 and covers the first sacrificial layer 4 above the photoresist layer 2 .

[0107] In this embodiment, the second sacrificial layer 6 is preferably made of silicon dioxide. The method of depositing the second sacrificial layer 6 is as described in Example 1.

[0108] After forming the second sacrificial layer 6, the first sacrificial layer 4 and the second sacrificial layer 6 on the photoresist layer 2 are removed by chemical mechanical polishing to expose the photoresist layer 2. The method of chemical mechanical polishing to expose the photoresist is as described in Example 1.

[0109] After the photoresist layer 2 is exposed, the photoresist is removed by a wet method, using a mixed solution of concentrated sulfuric acid and hydrogen peroxide, or an organic solvent such as acetone.

[0110] After removing the photoresist layer, a third sacrificial layer 9 is formed on the substrate by a plasma enhanced chemical vapor deposition process. The third sacrificial layer 9 is made of the same material as the first sacrificial layer 4. The third sacrificial layer 9 covers the substrate, the second sacrificial layer 6 and the sidewall 7.

[0111] Then, a chemical mechanical polishing process is used to remove the second sacrificial layer 6 and the third sacrificial layer 9 above the sidewall 7 to expose the second sacrificial layer 6 .

[0112] The material of the third sacrificial layer 9 of this embodiment is preferably silicon nitride. A layer of silicon nitride can be grown by plasma enhanced chemical vapor deposition. The deposition process conditions refer to the process conditions for depositing the first sacrificial layer 4 in step S103 of embodiment 1.

[0113] After the third sacrificial layer 9 material is formed, chemical mechanical polishing is used to grind it flat until the second sacrificial layer 6 at the top of the second circular hole 5 is exposed.

[0114] Afterwards, a dry etching process is used to remove the second sacrificial layer 6 in the second circular hole 5 and the first sacrificial layer 4 at the bottom of the second circular hole 5. In other embodiments, the first sacrificial layer 4 at the bottom of the second circular hole 5 can also be removed before the second sacrificial layer 6 is formed.

[0115] In the specific implementation process, plasma etching can be first used to remove the second sacrificial layer 6 (silicon dioxide) in the second circular hole 5. The process conditions for etching the second sacrificial layer 6 are:

[0116] The chamber pressure range is 0.5 to 50 mTorr, the upper electrode power range is 600 to 3000 W, the lower electrode power range is 50 to 3000 W, the chuck temperature range is -15 to 50°C, the etching gas is a carbon fluorine gas (it can be one or more of carbon fluorine gases such as octafluorocyclobutane, hexafluorobutadiene, carbon tetrafluoride, trifluoromethane, difluoromethane, fluoromethane, etc., and hydrogen or oxygen can also be added to adjust the selectivity), the flow range is 10 to 1000 sccm, the back helium pressure range is 1 to 20 Torr, the process time varies with the thickness of silicon dioxide, and this step can also use hydrofluoric acid wet etching of silicon dioxide, but whether dry or wet, it is necessary to pay attention to the selectivity between silicon dioxide and silicon nitride; in this embodiment, the etching selectivity of silicon nitride to silicon dioxide is greater than 10.

[0117] Then, the silicon nitride (first sacrificial layer 4) exposed at the bottom of the second circular hole 5 is continuously etched by plasma, and the etching is stopped on the second mask layer 11 (silicon dioxide layer). The process conditions for etching silicon nitride (removing the first sacrificial layer 4 at the bottom of the second circular hole 5) are:

[0118] The chamber pressure range is 0.5 to 50 mTorr, the upper electrode power range is 600 to 3000 W, the lower electrode power range is 50 to 3000 W, the chuck temperature range is -15 to 50°C, the carbon fluoride gas (which can be one or more of the carbon fluoride gases such as octafluorocyclobutane, hexafluorobutadiene, carbon tetrafluoride, trifluoromethane, difluoromethane, fluoromethane, etc., and hydrogen or oxygen can also be added to adjust the selectivity) flow range is 10 to 1000 sccm, the back helium pressure range is 1 to 20 Torr, and the process time varies with the thickness of the silicon nitride grown in the fourth step.

[0119] After completing this step, only the nanopores (second circular holes 5 ) formed by the second circular holes 5 in the silicon nitride layer remain on the second mask layer 11 .

[0120] Step S204: forming a first etching mask layer, the first etching mask layer fills the second circular hole and forms a column with a nanometer diameter in the second circular hole;

[0121] This step specifically includes: forming a fourth sacrificial layer 10, the fourth sacrificial layer 10 fills the second circular hole 5 and forms a nano-scale column in the second circular hole 5;

[0122] The third sacrificial layer 9 and the spacer 7 are removed, and the remaining fourth sacrificial layer 10 forms a first etching mask layer.

[0123] In this embodiment, the material of the fourth sacrificial layer 10 is preferably photoresist. The photoresist can be dripped to fill the nanopores (second circular holes 5) formed by silicon nitride. The photoresist can also be spin-coated. If the photoresist is too thick after this step, chemical mechanical polishing can be continued to be used to smooth it until the silicon nitride is exposed.

[0124] Afterwards, a wet etching process is used to remove the third sacrificial layer 9 and the sidewall 7. That is, the entire silicon nitride layer around the photoresist nano-column formed by the fourth sacrificial layer 10 in the nano-pore is removed by wet etching.

[0125] In this embodiment, the process conditions for wet etching of silicon nitride are: using 85% concentrated phosphoric acid and 15% deionized water, and the etching temperature is 140 degrees Celsius to 200 degrees Celsius.

[0126] After the silicon nitride is removed, only the nano-column array formed by the fourth sacrificial layer 11 (photoresist) remains on the first dielectric layer 11 (silicon dioxide layer), and the photoresist nano-column array serves as the first mask layer.

[0127] Step S205: etching the substrate and the first dielectric layer to form a nanoscale cone array on the surface of the substrate.

[0128] Specifically, in this step, a plasma dry etching process can be used to etch the silicon dioxide material of the first dielectric layer 11. The specific process conditions can be: a chamber pressure range of 0.5 to 50 mTorr, an upper electrode power range of 600 to 3000 W, a lower electrode power range of 50 to 3000 W, a chuck temperature range of -15 to 50°C, a carbon fluoride gas (which can be one or more of carbon fluoride gases such as octafluorocyclobutane, hexafluorobutadiene, carbon tetrafluoride, trifluoromethane, difluoromethane, fluoromethane, etc., and hydrogen or oxygen can also be added to adjust the selectivity) flow range of 10 to 1000 sccm, a back helium pressure range of 1 to 20 Torr, and the process time varies with the thickness of the silicon dioxide.

[0129] In this step, the photoresist serving as the mask layer is etched together, and a cone structure formed by silicon dioxide and sapphire is etched under each nanoscale cylindrical photoresist, thereby forming a nanoscale cone array morphology on the substrate.

[0130] In this embodiment, after forming the nanoscale cone array, the method further includes:

[0131] Step S206: forming a gallium nitride epitaxial layer 8 covering the cone array on the substrate through an epitaxial process.

[0132] The specific process method for epitaxially growing the gallium nitride epitaxial layer 8 refers to step S106 of embodiment 1.

[0133] Example 3

[0134] This embodiment provides a nanoscale patterned substrate, and the nanoscale patterned substrate is manufactured by using the method for preparing the nanoscale patterned substrate of any of the above embodiments.

[0135] The nanoscale patterned substrate of this embodiment adopts a micron-level manufacturing process to realize a conical nanoscale patterned substrate. The nanoscale patterned substrate can be obtained by using existing lithography equipment, without the need to upgrade the lithography equipment, thereby reducing equipment costs. The tip of the nanoscale cone structure is clear, and the conical nanoscale pattern morphology is regularly arranged. The use of this nanoscale patterned substrate can effectively improve the brightness of the LED device.

[0136] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for preparing a nanoscale patterned substrate, characterized in that: include: providing a substrate, and forming a photoresist layer on the substrate; Patterning the photoresist layer to form a plurality of first circular holes penetrating the photoresist layer on the photoresist layer; forming a first sacrificial layer, wherein the first sacrificial layer covers the inner wall of the first circular hole to form a second circular hole with a nanometer-scale diameter; forming a first etching mask layer, wherein the first etching mask layer fills the second circular hole and forms a column with a nanometer diameter in the second circular hole; The substrate is etched to form a nanoscale cone array on the surface of the substrate.

2. The preparation method according to claim 1, characterized in that: The forming of the first sacrificial layer comprises: forming the first sacrificial layer on the photoresist layer, wherein the first sacrificial layer covers the surface of the photoresist layer, the sidewall of the first circular hole and the bottom of the first circular hole; The first sacrificial layer on the inner wall of the first circular hole forms a side wall, and the side wall surrounds the second circular hole; The first sacrificial layer at the bottom of the second circular hole is removed.

3. The preparation method according to claim 2, characterized in that: The forming of the first etching mask layer comprises: forming a second sacrificial layer on the substrate, wherein the second sacrificial layer fills the second circular hole and covers the first sacrificial layer above the photoresist layer; The first sacrificial layer and the second sacrificial layer above the photoresist layer are removed to expose the photoresist layer; the remaining second sacrificial layer is formed into a column with a nanometer diameter in the second circular hole; removing the photoresist layer to expose the sidewall; The sidewall spacer is removed, and the remaining second sacrificial layer forms the first etching mask layer.

4. The preparation method according to claim 2, characterized in that: Before removing the first sacrificial layer at the bottom of the first circular hole, the preparation method further includes: forming a second sacrificial layer on the substrate, wherein the second sacrificial layer fills the second circular hole and covers the first sacrificial layer above the photoresist layer; removing the first sacrificial layer and the second sacrificial layer above the photoresist layer, and exposing the photoresist layer; removing the photoresist layer to expose the sidewall; forming a third sacrificial layer, wherein the third sacrificial layer covers the substrate and surrounds the sidewalls, and the third sacrificial layer is made of the same material as the first sacrificial layer; The second sacrificial layer in the second circular hole is removed.

5. The preparation method according to claim 4, characterized in that: After removing the first sacrificial layer at the bottom of the second circular hole, forming a first etching mask layer includes: forming a fourth sacrificial layer, wherein the fourth sacrificial layer fills the second circular hole and forms a nano-scale column in the second circular hole; The third sacrificial layer and the sidewall spacer are removed, and the remaining fourth sacrificial layer forms the first etching mask layer.

6. The preparation method according to claim 5, characterized in that: Before forming the photoresist layer on the substrate, the preparation method further includes: forming a first dielectric layer on the surface of the substrate, and the first etching mask layer is formed on the first dielectric layer.

7. The preparation method according to claim 6, characterized in that: The material of the fourth sacrificial layer is photoresist, and the material of the first dielectric layer is silicon dioxide.

8. The preparation method according to any one of claims 3 to 7, characterized in that: One of the first sacrificial layer and the second sacrificial layer is silicon nitride, and the other is silicon dioxide; or one of them is metal, and the other is silicon dioxide or silicon nitride; or both are different metal materials.

9. The preparation method according to claim 3 or 6, characterized in that: The substrate is a sapphire substrate.

10. A nanoscale patterned substrate, characterized in that: The nanoscale patterned substrate is obtained by the method for preparing a nanoscale patterned substrate according to any one of claims 1 to 9.

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