Display Components

Abstract

A backplane for controlling a display is disclosed. The backplane includes a plurality of tiles formed into an array. Each of the plurality of tiles includes a plurality of complementary metal oxide semiconductor backplane dies. The edges of the backplane dies forming the perimeter of the array include electrical connections that direct electrical signals to at least one of the CMOS backplane dies. A display assembly is also disclosed, wherein the display assembly includes a backplane having an array of tiles. Each tile includes a plurality of electrically coupled CMOS backplane dies, wherein the edges of the tiles forming the outer perimeter of the array include electrical connections that direct electrical signals to one or more of the plurality of CMOS backplane dies. The display assembly further includes at least one array of light emitting diodes electrically coupled to at least one tile.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. application serial number 63 / 005,731, filed on April 6, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of the present disclosure are generally directed to various assemblies, and more particularly to assemblies that include a backplate and to assemblies that include a backplate and an array of other elements for forming a display. Background Art

[0004] An overlooked aspect of many displays is the backplane technology used to drive the pixels of the main display panel (e.g., an array of individual pixels and / or optical elements). The backplane is the design, assembly, or arrangement of the various circuits and / or transistors in the display panel that are responsible for turning individual pixels on and off, thus playing an important role in overall display resolution, refresh rate, and power consumption.

[0005] The current challenge is to make a backplane that is highly integrated and can be assembled or packaged with light emitting elements (e.g., light emitting diodes or LEDs) or light reflecting elements and optical elements. Packaging technology for integrated optical and electronic components continues to improve from the packaging technology used in traditional packaging. For example, there are improved technologies for wafer-level chip scale packaging (WLCSP) and for fan-out wafer-level packaging. In addition, the dimensions of the packaging have also improved to enable even denser solutions. Packaging has shifted from one-dimensional (1D) packaging with one chip per package to 2D packaging (e.g., multiple chips per package), to 2.5D packaging with an interposer, and to 3D packaging with chip stacking. Even with all the improvements provided by these technologies, they may not meet the requirements for the types of components needed in high-resolution displays (including light field displays).

[0006] Therefore, new techniques are desirable that enable the design and fabrication of assemblies having backplanes and assemblies having backplanes combined with arrays of other elements forming displays. Summary of the invention

[0007] A simplified summary of one or more aspects is presented below in order to provide a basic understanding of such aspects. The present disclosure is not an extensive overview of all contemplated aspects, and is neither intended to identify the key or decisive elements of all aspects, nor to characterize the scope of any or all aspects. Its purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description presented later.

[0008] In one aspect of the present disclosure, a backplane for controlling light provided by a display is described. The backplane includes a plurality of tiles formed into an array, wherein each tile includes a plurality of complementary metal oxide semiconductor (CMOS) backplane dies, and wherein edges of the tiles forming an outer perimeter of the array include electrical connectors that direct electrical signals to at least one of the CMOS backplane dies.

[0009] In another aspect of the present disclosure, a display assembly is described. The display assembly includes a backplane having an array of tiles, each tile having a plurality of electrically coupled CMOS backplane dies. The edges of the tiles forming the outer perimeter of the array include electrical connections that direct electrical signals to one or more of the plurality of CMOS backplane dies. The display assembly further includes at least one array of light emitting diodes (LEDs) electrically connected to at least one tile. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings illustrate only some implementations and therefore should not be considered limiting in scope.

[0011] Figure 1 Examples of displays and sources of content for the displays in accordance with aspects of the present disclosure are illustrated.

[0012] Figure 2A An example of a display having multiple pixels in accordance with aspects of the present disclosure is illustrated.

[0013] Figure 2B and Figure 2C An example of a light field display having multiple picture elements in accordance with aspects of the present disclosure is illustrated.

[0014] Figure 3A An example of a backplane formed with multiple tiles in accordance with aspects of the present disclosure is illustrated.

[0015] Figure 3B An example of a backplane formed with a single panel in accordance with aspects of the present disclosure is illustrated.

[0016] Figure 4 An example of a reconstituted wafer from which dice are diced in accordance with aspects of the present disclosure is illustrated.

[0017] Figures 5A-5K An example of using wafer level packaging (WLP) to form a backplane and display in accordance with aspects of the present disclosure is illustrated.

[0018] Fig. 6A and Figure 6B An example of forming a component using panel level packaging (PLP) in accordance with aspects of the present disclosure is illustrated.

[0019] Figures 7A-7E Examples of different configurations of CMOS backplane dies, LED arrays, and microlens arrays for WLP and PLP are illustrated in accordance with aspects of the present disclosure.

[0020] Fig. 8A and Figure 8B are flow charts illustrating different methods of manufacturing or fabricating a backplane for controlling light provided by a display in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0021] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein may be practiced. The specific embodiments include specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known components are shown in block diagram form in order to avoid confusing such concepts.

[0022] The number of pixels in future displays is expected to be much larger than in current displays, sometimes by several orders of magnitude. Such displays will present challenges in terms of the type of backplane assembly or display assembly that will ultimately be used, particularly in terms of power consumption and overall bandwidth, as these factors may limit the ability to implement displays with very high resolutions and extremely large pixel counts. Various aspects to be considered in determining an appropriate backplane or display assembly include different technical options as well as different integration options. As used herein, the terms "backplane" and "backplane assembly" may be used interchangeably. Similarly, the terms "display" and "display assembly" may be used interchangeably. In addition, in some implementations, a "display" or "display assembly" may include a "backplane" or "backplane assembly."

[0023] Regarding technology options, various possible semiconductor technologies can be considered, including, for example, amorphous silicon (a-Si), metal oxide, low temperature polysilicon (LTPS), and complementary metal oxide semiconductor (CMOS) wafers. Among these semiconductor technologies, LTPS and CMOS wafers can provide more flexible options for the purpose of backplane bandwidth and density requirements. For example, CMOS wafers can support bandwidths in the range of 1MHz-1,000MHz and drive unit spacings in the range of 1μm-30μm. On the other hand, LTPS can support bandwidths in the range of 1MHz-15 MHz and drive unit spacings in the range of 10μm-10,000μm.

[0024] LTPS backplane design may involve a manufacturing process flow that provides low cost and minimal bonding interfaces. However, custom die placement tools that can serve large areas with high accuracy will be required. In some instances, LTPS may not provide sufficient performance in terms of placement area and accuracy.

[0025] As described in the present disclosure, CMOS backplane design can be implemented using a panel level packaging (PLP) approach or alternatively using wafer tiles as part of a wafer level packaging (WLP) approach. The PLP approach uses a single panel to form a backplane / display assembly, whereas the WLP approach uses an array of wafer tiles to form a backplane / display assembly. Some benefits or advantages of these two approaches include using only known good CMOS bare dies and producing high performance backplanes. Some challenges of the PLP approach are that panel level packaging processes are typically not available for production and require customized or non-standard processes. Customized processes may result in increased production costs and time and possible quality reduction. Some benefits or advantages of the WLP approach include good tool availability including LED bonding tools, laser stripping tools, and microlens replication tools, as well as better yields in the case of known good tiles. The WLP approach can also provide a solution that evolves into the PLP approach. On the other hand, some challenges of the WLP approach are the need for precise tile dicing, the need for extremely precise tiling, the possible need for backside contacts if more than 4 wafer tiles are used in the display (e.g., for a 22 inch diagonal display with 12 inch square wafer tiles), and the possibility that microlens tile seams may be visible (although in some implementations, applying microlenses after the tiling process is completed can reduce or eliminate the appearance of such seams).

[0026] Described below Figure 1-2C A general overview of the types of displays to which the various backplane and display aspects described in this disclosure may be applicable is provided, including PLP and WLP approaches for making a backplane or display (eg, a backplane with LEDs and microlenses added).

[0027] Figure 1 100 is shown, which illustrates an example of a display 110 receiving content / data 125 (e.g., image content, video content, or both) from a source 120. The display 110 may include one or more panels (not shown), wherein each panel in the display 110 is a light emitting element (e.g., such as a Figure 2AEach panel may also include a backplane or backplane assembly for driving the light emitting or light reflecting elements. Each panel may be made of a single CMOS panel (e.g., using a CMOS backplane panel) or may be made of multiple CMOS wafer tiles (e.g., using a CMOS backplane wafer tile). When light emitting panels are used, they may include multiple light emitting elements arranged in an array, which may be referred to herein as "sub-ray pixels" (see, e.g., Figure 2A A plurality of sub-ray pixels may be arranged in a grid or array to form a "sub-ray pixel" 221 (see Figure 2B ). These light emitting elements can be light emitting diodes (LEDs) made of one or more semiconductor materials and these LEDs can be monolithically integrated on a single substrate. These LEDs can be inorganic LEDs. These LEDs can be micro-LEDs, also known as mircoLEDs, mLEDs or LEDs. Other display technologies that can be used to make light emitting elements include liquid crystal display (LCD) technology or organic LED (OLED) technology. The terms "light emitting element", "light emitter" or simply "emitter" can be used interchangeably in this disclosure.

[0028] Display 110 may have capabilities including ultra-high resolution capabilities (e.g., support for 8K and higher resolutions), high dynamic range (contrast) capabilities, or light field capabilities, or a combination of these capabilities. Display 110 may further include light field capabilities and may be used as Figure 2B , 2C To enable such light field capabilities, display 110 may include a plurality of picture elements, also referred to herein as "super light pixels," wherein each super light pixel (e.g., Figure 2B and Figure 2C The super ray pixel 225 in FIG. 2 includes multiple subgroups of sub-ray pixels (e.g., Figure 2B The light pixels 221 in the super light pixel can be monolithically integrated on the same semiconductor substrate. Each light pixel in the super light pixel can be independently activated to emit light from a specific location (e.g., from a specific (x, y) coordinate location) relative to the light steering optical element. By selectively emitting or reflecting light from different locations, multiple views can be supported by a light field display, as will be described below in this article with respect to Figures 2A-2C As discussed.

[0029] Figure 2AThe graphic 200a in FIG. 1 shows a display 210a having a plurality of light emitting elements 220a (also referred to as pixels or display pixels). The light emitting elements 220a, which may be LEDs as discussed above, are typically formed in an array and adjacent to each other to provide a higher pixel density and, therefore, a higher resolution of the display 210a. The display 210a may be Figure 1 An example of a display 110 in graphic 100 is shown.

[0030] exist Figure 2A In the example shown, the light emitting elements 220a can be organized or positioned into a Q×P array on an area of ​​the display 210a, where Q is the number of rows of pixels in the array and P is the number of columns of pixels in the array. An enlarged portion of such an array is shown to the right of the display 210a. Although not shown, the display 210a can include a backplane in addition to the array of light emitting elements 220a, which includes various electrical traces and contacts configured to selectively deliver power to one or more of the light emitting elements 220a. The backplane coupled to the display 210a can be based on the features or configurations described herein.

[0031] Figure 2B The graphic 200b in FIG. 100 shows a light field display 210b having a plurality of picture elements or super light pixels 225. In the present disclosure, the terms “picture element” and the term “super light pixel” may be used interchangeably to describe similar structural units in a light field display. The light field display 210b may be an example of the display 110 with light field capabilities in the graphic 100. The light field display 210b may be used for different types of applications and its size may vary accordingly. For example, the light field display 210b may have different sizes when used as a display for a watch, near-eye application, phone, tablet, laptop, monitor, television, billboard, etc. Therefore, and depending on the application, the picture elements 225 in the light field display 210b may be organized into arrays, grids, or other types of ordered arrangements of different sizes. The picture elements 225 of the light field display 210b may be distributed over one or more display panels.

[0032] exist Figure 2BIn the example shown, the picture elements 225 are organized or positioned in an N×M array, where N is the number of rows of picture elements in the array and M is the number of columns of picture elements in the array. An enlarged portion of such an array is shown to the right of the light field display 210b. When the picture elements or super light pixels 225 include different LEDs that produce red (R) light, green (G) light, and blue (B) light on the same semiconductor substrate as the light emitting elements 220b, the light field display 210b can be said to be made of RGB LED super light pixels. These LEDs of different colors can be monolithically integrated on the same substrate and can vary in size from about 1 micron to about 100 microns.

[0033] Each of the picture elements 225 in the light field display 210b may include a corresponding light redirecting optical element (e.g., Figure 2C 200c in FIG). Picture element 225 represents the minimum picture element size that defines the display resolution. In this regard, the light pixels 221 of picture element 225 (e.g., the array or grid of light emitting elements 220b) can be smaller than the corresponding light redirecting optical element 215 for the picture element. However, in practice, the size of the light pixels of picture element 225 can be similar to the size of the corresponding light redirecting optical element 215 (e.g., the diameter of the microlens or lenslet), which in turn can be similar or the same as the spacing 230b between picture elements 225. In some embodiments, the super light pixel can be smaller than the picture element or approximately the same size as the picture element. Larger super light pixels (e.g., super light pixels having approximately the same size as the picture element) can provide increased angular light resolution

[0034] As mentioned above, the array of light emitting elements 220b can be arranged into "light pixels" 221, as shown in the enlarged version of the picture element 225 shown on the right side of the graphic 200b. The picture element 225 can be an array X×Y of light emitting elements 220b, where X is the number of rows of light emitting elements 220b in the array and Y is the number of columns of light emitting elements 220b in the array. In one example, the picture element 225 is a 9×9 array including 81 light emitting elements or sub-light pixels 220b.

[0035] exist Figure 2C, graphic 200c shows another example of a light field display 210c and a magnified view of a portion of an array of picture elements 225 with corresponding light redirecting optical elements 215 as described above. Spacing 230c can represent the spacing or distance between the centers of adjacent picture elements 225 and can be approximately the size of the light redirecting optical elements 215 (e.g., the size of the microlenses or lenslets) so that the light redirecting optical elements have no gaps or minimal gaps therebetween when arranged in an array to form the light field display 210c. Although in Figure 2C The middle picture elements 225 are shown as being separated from one another, but this is for illustration purposes only and they may be constructed adjacent to one another with no space between them.

[0036] Figure 3A FIG. 300a illustrates an example of a backplane 320a formed with a plurality of tiles 310a, 310b, 310c, 310d in accordance with aspects of the present disclosure. The backplane 320a may be combined with the above Figure 1-2C The backplane 320a, which may also be referred to as a backplane assembly, may be made of four (4) tiles (e.g., tiles 310a, 310b, 310c, and 310d) arranged to form an array. Although Figure 3A The example of has four tiles, but without departing from the scope of this example, the backplane can be made with more or fewer tiles. The electrical connector 330 can be used to transmit signals to and / or from one or more of the tiles 310a-310d. For example, when one or more of the tiles 310a-310d on the backplane 320a include light-emitting elements and / or optical elements or components (e.g., sub-light pixels, light pixels, and / or super light pixels), the backplane 320a can also be referred to as a display or display assembly.

[0037] As in the following about Figure 4Described in more detail, each of the blocks or wafer blocks 310a-310d can be diced or cut from a reconstructed wafer including a plurality of CMOS backplane dies (where each of those dies is known to be a good working die). That is, each block includes a plurality of separate and electrically interconnected CMOS backplane dies (not shown) that are held together in the block. As shown in figure 300a, the block 310 provides an electrical connector 330 at the edge of the outer periphery of the backplane 320a to allow interaction and / or communication with the CMOS backplane die in each of the blocks 310a-310d. Through silicon via (TSV) electrical connections can be used to provide electrical connections between the substrate of the backplane 320a and one or more blocks 310a-310d, replacing or supplementing the electrical connector 330 disposed around the edge of the block. Each CMOS backplane die in the block is a CMOS integrated circuit configured to provide an electrical signal to control a corresponding subset of the light emitting element or light reflecting element electrically coupled thereto.

[0038] Figure 3B Figure 300b illustrates an example of a backplane 320b formed with a single panel 340 in accordance with aspects of the present disclosure. The backplane 320b may be combined with the above Figure 1-2C The backplane 320b may be used with any of the displays described herein. The backplane 320b may also be referred to as a backplane assembly. The electrical connector 330 may be used to transmit signals to and / or from the panel 340. When the backplane 320b is coupled with a light emitting element and / or an optical element or component, the assembly may be referred to as a display or display assembly. Figures 5A-5K Examples of electrical connections between electrical connector 330 and light emitting elements in a display assembly are discussed in further detail.

[0039] As described in more detail below, panel 340 includes a plurality of separate and electrically interconnected CMOS backplane dies (not shown) held together in the panel. Panel 340 may be formed using the same methods used to form a reconstituted wafer but on a larger scale. As shown in diagram 300b, panel 340 provides electrical connectors 330 at the edges in the outer periphery to interact or communicate with one or more of the CMOS backplane dies in the panel. Each CMOS backplane die in the panel is configured to provide signals to control a light emitting element of the display (e.g., one or more sub-light pixels 220b, Figure 2B ) or a CMOS integrated circuit having one or more corresponding subsets of light reflecting elements.

[0040] Figure 4 Graph 400 is shown showing an example of a reconstructed wafer 420 from which a block 430 is diced or cut in accordance with aspects of the present disclosure. Block 430 may represent Figure 3AIn order to use conventional semiconductor manufacturing and processing equipment that generally requires wafers to have a specific size and shape, it is necessary to form or make a block or wafer block (e.g., Figure 3A One method of reconstructing the standard size and shape wafer by placing multiple CMOS backplane dies 410 into an array on a wafer 420 and then cutting or dicing square or rectangular tiles 430 (dashed lines) from the reconstructed wafer 420 after processing the wafer 420 using conventional manufacturing steps. This allows the reconstructed wafer 420 (and therefore the tiles 430) to be processed by various conventional semiconductor manufacturing steps configured to process standard size / shape wafers, because without the wafer 420, the square or rectangular tiles 430 are non-standard in size and shape and are not suitable for conventional semiconductor processing tools and equipment.

[0041] Figures 5A-5I 500a-500i are illustrated, which illustrate a method for forming a backplane assembly (eg, Figure 3A and Figure 3B One or more of the back panels 320a and 320b) and the display components (e.g., Figure 1 , Figure 2A , Figure 2B and Figure 2C Example steps of displays 110, 210a, 210b and 210c).

[0042] Figure 5A Graph 500a in FIG. 5 shows a schematic diagram of a reconstructed wafer (e.g., Figure 4 FIG. 5 is a cross-sectional view of at least a portion of a block 535a diced from a reconstructed wafer 420 in FIG. 5. The block 535a includes a substrate 530 having an adhesive layer 540, a plurality of CMOS backplane dies 510 (eg, Figure 4530) is attached to the adhesive layer 540. The adhesive layer 540 can provide a permanent bond of the CMOS backplane die 510 to the substrate 530, which can mitigate die displacement. In this example, each CMOS backplane die 510 is positioned with the die facing up, wherein the pillars 520 (e.g., die or chip electrical connections) face away from the substrate 530 and are configured to be electrically coupled with an additional display component (not shown). The base 515a of the die located below the pillars 520 (e.g., a portion of the CMOS backplane die 510 including the backplane electronics and circuitry) is adjacent to the adhesive layer 540 and the substrate 530. The pillars 520 can be copper (Cu) pillars, that is, Cu can be used for die electrical connectivity; however, other conductive metals or materials can also be used. The CMOS backplane die 510 is shown as separated for illustration purposes (e.g., with gaps between adjacent CMOS backplane die) but is intended to be tightly packed and can therefore be tightly positioned to adjacent die. In an example, a 100 μm gap between CMOS backplane dies 510 may be desirable, although 300 μm may be currently possible with existing semiconductor assembly and test (OSAT) tools.

[0043] Figure 5B Figure 500b in shows that an overmold 550 (or similar packaging material) is deposited over and around the CMOS backplane die 510 on the block 535b to hold the CMOS backplane die 510 together. In this example, there is an amount (e.g., excess) of overmold 550 covering the top portion of the CMOS backplane die 510. The overmold 550 can be a custom material suitable for the application. One example is a silica-filled epoxy molding compound (EMC), which is rigid when cured but can cause the die to shift. Another example is polyimide, which may be compliant but there may be no current method or process for dispensing it. In some instances, inkjet technology can be used to dispense polyimide.

[0044] Figure 5C Figure 500c in Figure 5 shows a patch 535c illustrating the result of grinding, etching or otherwise removing a portion of the overmold 550 so that the top portion of the CMOS backplane die 510 (e.g., the top of the pillar 520) is exposed (e.g., excess overmold is removed). When polyimide is used for the overmold 550, it is important to note that the polyimide may not always grind well and different approaches may be used to dispense the polyimide, such as deposition with a doctor blade or direct patterning without grinding.

[0045] Figure 5D The figure 500d in FIG. 5 shows the exposed portion of the pillar 520 of the CMOS backplane die 510 (eg Figure 5CAn electrical redistribution layer (RDL) 555, such as a copper (Cu) RDL, is deposited on the die 535d to form interconnections between the CMOS backplane dies 510. In particular, the RDL 555 provides electrical connections between the pillars 520 of different CMOS backplane dies 510 to interconnect the CMOS backplane dies 510. Standard processes can be used to deposit the RDL 555. In one example, adaptive lithography can be used to illustrate die shifting, although the wiring density required in the RDL may be challenging for adaptive lithography techniques.

[0046] Figure 5E Figure 500e in Figure 500e shows a partial cross-sectional view of a tile 535e diced from a reconstituted wafer from which the substrate 530 and adhesive layer 540 have been removed. Alternatively, the tile 535e may have been formed without the use of the substrate 530 and / or adhesive layer 540, whereby the CMOS backplane die 510 is held together by the overmold 550. As shown in figure 500e, the RDL 555 is located on the top of the tile 535e (i.e., above the exposed pillars 520 of one or more CMOS backplane die 510) and the bottom of the CMOS backplane die 510 forms the bottom of the tile 535e.

[0047] Without any additional components (e.g., LED arrays and / or microlens arrays), the block 535e shown in FIG. 500e or the reconstructed wafer from which the block 535e is diced can be considered to be a backplane or backplane assembly. However, additional components or elements (e.g., LED arrays and / or microlens arrays) can be added to the backplane or backplane assembly on the reconstructed wafer (as described in more detail below), and the structure can be considered to be a backplane or backplane assembly that can be combined as described above. Figure 4 The display assembly is diced or cut in the manner described.

[0048] Fig. 5F FIG. 500f in FIG. 500f shows the result of flip-chip bonding of LED array 560 to CMOS backplane die 510. Each of LED array 560 includes, for example, a plurality of LEDs such as the above combination. Figures 2A-2CThe LED array 560 may include electrical contacts or connections 565 electrically connected to portions of the RDL 555 or other electrical connections 570 placed above the RDL 555. Although figure 500f shows a one-to-one correspondence between the LED array 560 and the CMOS backplane die 510, this is for illustration only and not limitation. It is also possible that a single LED array 560 may be electrically coupled to multiple CMOS backplane die 510, or alternatively, multiple LED arrays 560 may be electrically coupled to a single CMOS backplane die 510. The electronics and circuitry of the CMOS backplane die 510 may be selected to control the operation of one or more of the light emitting elements within one or more of the corresponding LED arrays 560. In the following description of Figure 5J and Figure 5K Additional electrical connection schemes for connecting LEDs, CMOS backplane dies, and / or other components within a display assembly using RDL are discussed.

[0049] In another implementation, an array of light reflecting elements such as digital micromirror device (DMD) reflectors may be used in conjunction with or in place of the LED array 560, in which case the electronics and circuitry of the CMOS backplane die 510 may be selected to control the operation of one or more of the light reflecting elements. Fig.5I A display assembly having multiple DMD reflector arrays 590 is shown in FIG. Fig. 5F As shown, one or more of the electrical contacts or connections 565, 570 can electrically couple the RDL 555 to the DMD array 590. One or more DMD arrays 590 can be electrically coupled to each of the CMOS backplane dies 510; alternatively, one or more of the CMOS backplane dies 510 can be electrically coupled to each of the DMD arrays 590.

[0050] Further in conjunction with patterns 500f and 500i, the accuracy of flip chip bonding and the use of laser lift-off (LLO) such as available wafer-scale LLO tools need to be considered to, for example, remove the reconstructed wafer from the substrate 530 and / or separate the LED array 560 or DMD array 590 to be flip chip bonded. Additional considerations include the use of underfill to compensate for the mismatch in the coefficient of thermal expansion (CTE) between the LED array (or DMD reflector array 590) and the CMOS backplane die, the difficulty in feeding the underfill when the gap between the flip chip connections is small, and whether to use underfill instead of pre-applied film. If underfill is not used, it can be considered whether voids may occur in conjunction with the microlens and how to avoid such occurrences.

[0051] Figure 5GFigure 500g in Figure 500g shows a microlens array 575 disposed above and attached to an LED array 560 that has been flip-chip bonded to an RDL 555 on top of a CMOS backplane die 510. The microlens array 575 may include various optical elements, such as the above combined Figure 2C The light redirecting optical element 215 (e.g., a lens or microlens) is depicted. Although the diagram 500g shows a single microlens array 575, this is for illustration only and not limitation. Multiple microlens arrays 575 may also be used. Furthermore, there need not be a one-to-one correspondence between the CMOS backplane die 510, the LED array 560, and the microlens array 575, as shown in more detail below.

[0052] Figure 5H The graph 550h in FIG. 5 shows that the above combination Figure 3A and Figure 4 The results of the described die dicing and die bonding. In this example, Figure 5G At least a portion of the reconstructed wafer is shown cut by high precision dicing to form diced tiles 535h. The cross-sectional view of the diced tiles in this example includes a CMOS backplane die 510, wherein a flip-chip bonded LED array 560 is connected to the CMOS backplane die 510 via electrical connections 565, 570 and RDL 555, and one or more microlens arrays 575 are located above the LED array 560. The diced tiles 535h can be combined with other tiles (see, e.g., Figure 3A ) are bonded together (e.g., by permanent bonding using, for example, an adhesive layer (not shown)) to a rigid substrate 580. Tile bonding may require a high degree of alignment accuracy over a large area. Multiple tiles may be assembled on a backplane to form a display assembly, as described above with respect to FIG. Figure 3A Just as described.

[0053] Figure 5J and Figure 5K Figures 500j and 500k are partial cross-sectional views of tiles 535j, 535k, respectively. Tiles 535j, 535k include LED array 560, CMOS backplane die 510, and optionally example electrical connections between adhesive layer 540 and substrate 530. Figure 5J, block 535j includes a plurality of LED arrays 560 electrically coupled to a plurality of CMOS backplane dies 510 using an RDL 555 disposed therebetween. The RDL 555 is patterned so that portions of the RDL (i.e., connectors 554) can extend between different CMOS backplane dies. For example, connector 554(1) of RDL 555 electrically couples a first CMOS backplane die 510(1) to a second CMOS backplane die 510(2). Similarly, connector 554(2) of RDL 555 electrically couples a second CMOS backplane die 510(2) to a third CMOS backplane die 510(3). Additional CMOS backplane dies can similarly be interconnected using additional connectors in the RDL. Thus, by patterning the RDL so that connections bridge across different backplane dies, the backplane dies 510(2), 510(3), 510(4) centrally located within the tile and their associated LED arrays can be electrically addressed (e.g., from the tile's electrical connector 330).

[0054] Reference together Figure 5J and Figure 5K , the CMOS backplane die 510 is illustrated as having base portions 515j, 515k, respectively. The base portions 515j, 515k may be silicon material. In the embodiments shown in the figures 500j, 500k, the base portions 515j, 515k may include one or more through silicon vias (TSVs) 552 that provide electrical connectivity to the CMOS backplane die 510, and / or in some embodiments, the through silicon vias (TSVs) 552 may extend from the bottom surface of the base portions 515j, 515k to the conductive pillars (e.g., Figure 5A The TSVs 552 are formed of a conductive material and are configured to receive current or signals (e.g., from a different electrical connector, from a power source, or from a control module) and deliver the current or signals to one or more LED arrays 560 directly or indirectly through an intermediate connector.

[0055] Figure 5KFigure 500k in Figure 500k shows additional TSVs 534 extending through the substrate 530 (e.g., extending between its top and bottom surfaces). Without departing from the scope of the present disclosure, the block 353K may have more or fewer TSVs 534 in the substrate 530. In some embodiments, the bottom surface of the TSV 534 (i.e., the surface farthest from the CMOS backplane die 510) can be electrically coupled to a power source or another electrical conduit within the display assembly. The top surface of the TSV 534 (i.e., the surface closest to the CMOS backplane die 510) can be directly coupled to one or more TSVs 558 within the base portion 515k of the CMOS backplane die 510. Alternatively or additionally, the top surface of the TSV 534 can be coupled to an RDL or other printed circuit system to distribute current before delivering the current to one or more TSVs 558 within the CMOS backplane die 510. In embodiments where printed circuitry is disposed on the top surface of substrate 530, adhesive layer 540 may be contoured or otherwise selectively applied so that the printed circuitry is not covered by the adhesive layer. In some embodiments, the printed circuitry may be formed of a material having both conductive and adhesive properties, such as a conductive epoxy or an anisotropic conductive film (ACF) that is selectively applied to create electrical connections.

[0056] Fig. 6A and Figure 6B Figures 600a and 600b respectively illustrate an example of forming a component using panel level packaging (PLP) in accordance with aspects of the present disclosure. Figures 5A-5K Unlike the example in FIG. 6 , FIG. 600 a and FIG. 600 b show forming a single panel over a substrate 530 (which is not removed) by using an adhesive layer 540 to hold a CMOS backplane die 510, depositing an RDL 555, flip-chip bonding an LED array 560 using electrical contacts or connections 565 and 570, and then placing one or more microlens arrays 575 on top (e.g., Figure 6B ). The materials and / or processes used to make a single panel using PLP can be the same or similar to the materials and / or processes used to make a reconstructed wafer from which the pieces are diced in WLP; however, the PLP assembly can be larger in size than the pieces formed using WLP and can be square or rectangular in shape. PLP can therefore be used to make a single panel backplane assembly or a single panel display assembly having not only backplane electronics but also optical and / or optical elements. An assembly formed using PLP can include electrical connectors (not shown) around the perimeter of the assembly.

[0057] Figures 7A-7EExamples of different configurations of CMOS backplane die, LED array, and microlens array for WLP and PLP are illustrated in accordance with aspects of the present disclosure. As described above, different correspondences may exist between the CMOS backplane die, LED array, and microlens array.

[0058] Fig. 7A FIG. 700a in FIG. 700a is a top view showing a configuration or implementation for a tile (e.g., a tile diced or cut from a reconstructed wafer) or panel 730 including a plurality of CMOS backplane dies 710 arranged in an array, and each CMOS backplane die 710 has a corresponding LED array 760 positioned thereon (indicated by dashed lines). In addition, a single microlens array 775 covers the entire set of CMOS backplane dies 710 and LED arrays 760 on the panel 730. However, in FIG. Figure 3A The 2x2 array of tiles shown allows for electrical connectors at the edge of the backplane to connect both sides of each tile, except Fig. 7A None of the die 710 having one or more edges along the perimeter of the array can be directly connected using electrical connectors (not shown) at the edge of the panel 730. Therefore, for electrical addressing Fig. 7A Each CMOS backplane die 710 is electrically connected to an adjacent CMOS backplane die having no edges along the perimeter of the array. Thus, all CMOS backplane die 710 of the panel 730 can be electrically addressed from an electrical connector (not shown) at the edge of the panel 730. Alternatively, or in addition, electrical connections to one or more CMOS backplane dies can be provided, for example, via the panel 730 by using through-holes (not shown) or other mechanisms for forming electrical connections. Conventional methods such as wire bonding can be used to provide electrical connections.

[0059] Figure 7B Figure 700b in Figure 7 shows an example configuration for a tile or panel 730, where there are multiple CMOS backplane dies 710 arranged in an array (e.g., an 8×8 array) and a single corresponding LED array 760 located above the CMOS backplane die 710. In addition, there is a single microlens array 775 covering the entire set of CMOS backplane dies 710 and LED array 760.

[0060] Figure 7CFigure 700c in Figure 700c shows another example configuration for a tile or panel 730, where there are multiple CMOS backplane dies 710 arranged in an array (e.g., an 8×8 array) and multiple LED arrays 760 arranged in a different array (e.g., a 2×2 array) located above the CMOS backplane dies 710. In this example, each LED array 760 covers a subset of the CMOS backplane dies 710 (e.g., a 4×4 array of CMOS backplane dies 710). Although each LED array 760 can cover the same number of CMOS backplane dies 710, this is not necessarily the case. In addition, there is a single microlens array 775 that covers the entire set of CMOS backplane dies 710 and LED arrays 760.

[0061] Fig.7D Figure 700d in Figure 700d shows another possible configuration or implementation for a tile or panel 730, in which there are multiple CMOS backplane dies 710 arranged in an array (e.g., an 8×8 array) and multiple LED arrays 760 arranged in a different array (e.g., a 2×2 array) located above the CMOS backplane dies 710. In this example, each LED array 760 covers a subset of the CMOS backplane dies 710 (e.g., a 4×4 array of CMOS backplane dies 710). Although each LED array 760 can cover the same number of CMOS backplane dies 710, this is not necessarily the case. In addition, there can be multiple microlens arrays 775. In this example, there is a microlens array 775 for each LED array 760 (e.g., a 2×2 array of microlens arrays 775), but this is not necessarily the case.

[0062] Fig. 7E Figure 700e in Figure 700e shows another configuration or implementation for a tile or panel 730, where there are multiple CMOS backplane dies 710 arranged in an array (e.g., an 8×8 array) and a single LED array 760 located above the CMOS backplane die 710. In addition, there may be multiple microlens arrays 775 covering the entire set of CMOS backplane dies 710 and the LED array 760. In this example, the microlens arrays 775 are arranged in a different array (e.g., a 2×2 array) than the CMOS backplane die 710, and each microlens array 775 covers a subset of the CMOS backplane die 710 (e.g., a 4×4 array of CMOS backplane die 710).

[0063] Fig. 8A and Figure 8B are flow charts illustrating different methods of manufacturing or fabricating a backplane for controlling light provided by a display in accordance with aspects of the present disclosure.

[0064] Fig. 8AThe method 800a in corresponds to a method of manufacturing a backplane for controlling light provided by a display.

[0065] The method 800a includes, at 810, providing multiple and separate CMOS backplane dies.

[0066] The method 800a optionally includes testing the CMOS backplane dies using a probing test at 815 and removing those of the CMOS backplane dies that fail the test.

[0067] The method 800a includes forming a reconstructed wafer by holding the CMOS backplane die together at 820. The multiple CMOS backplane die can be held in a fixed position relative to each other using an adhesive layer disposed on a rigid substrate. The CMOS backplane die and substrate assembly can be processed by standard processing equipment rather than custom equipment during subsequent processing steps to reduce manufacturing costs. Further processing steps may include depositing an overmold layer, removing a portion of the overmold layer to expose the conductive pillars, depositing an electrical redistribution layer (RDL) and placing an LED or DMD panel over the RDL.

[0068] The method 800a includes, at 830, dicing tiles from a wafer (also referred to herein as a "reconstituted wafer"), wherein the CMOS backplane dies in the tiles are electrically connected to each other.

[0069] The method 800a includes arranging the tiles, along with other tiles diced from other reconstituted wafers, into a tile array at 840, wherein edges of the tiles in an outer perimeter of the tile array provide electrical connections to interact with a CMOS backplane die in the tiles.

[0070] In one aspect of method 800a, each CMOS backplane die is a CMOS integrated circuit configured to provide signals to control one or more respective subsets of light emitting elements or light reflecting elements within the display assembly.

[0071] In one aspect of method 800a, each CMOS backplane die has passed a wafer level probing test before it is included in its corresponding tile.

[0072] In one aspect of method 800a, a reconstituted wafer is formed over a substrate, and method 800a further includes removing the reconstituted wafer from the substrate by performing a wafer level laser lift off (LLO) process to separate the reconstituted wafer from the substrate.

[0073] In one aspect of method 800a, a substrate is used to form the reconstituted wafer, and the substrate remains part of the reconstituted wafer after the tiles are secured thereto and dicing is completed.

[0074] In one aspect of method 800a, a reconstituted wafer is formed over a substrate, and the CMOS backplane die is held in place in the reconstituted wafer by being permanently attached to the substrate.

[0075] In one aspect of method 800a, the CMOS backplane die in each tile is held together by an overmold, the CMOS backplane die is positioned die-up, and forming the reconstructed wafer further includes removing a top portion of the overmold to expose electrical posts of the CMOS backplane die to electrical interconnections between the CMOS backplane die and the electrical redistribution layer. In addition, removing the top portion of the overmold includes grinding, etching, or otherwise removing the top portion of the overmold.

[0076] In one aspect of method 800a, the CMOS backplane dies in each tile are held together with an overmold, and method 800a further includes disposing the overmold between and around at least the CMOS backplane dies and curing the overmold to form a portion of the reconstructed wafer, the overmold being made of a material including silicon dioxide, aluminum oxide, graphite, ceramic, polymer, or electronic molding compound. The polymer may include polyimide or epoxy.

[0077] In one aspect of method 800a, the size of the tiles diced from the reconstituted wafer ranges from 4 inches up to 18 inches. In some embodiments, the diced tiles may be approximately 11 inches. Other tile sizes are possible without departing from the scope of the present disclosure.

[0078] In one aspect of method 800a, the tiles diced from the reconstituted wafer are rectangular tiles or square tiles.

[0079] In one aspect of the method 800a, the reconstituted wafer is a standard size for wafer level processing, the standard size being one of a 150 mm wafer size, a 200 mm wafer size, a 300 mm wafer size, or a 450 mm wafer size.

[0080] In one aspect of method 800a, an array of tiles is arranged over a rigid base.

[0081] In one aspect of method 800a, an array of tiles is arranged over a flexible substrate.

[0082] Figure 8B Method 800b in corresponds to another method of manufacturing a backplane for controlling light provided by a display.

[0083] The method 800b includes, at 850, providing multiple and separate CMOS backplane dies.

[0084] The method 800b includes forming a panel at 860 by holding the CMOS backplane dies together, wherein the CMOS backplane dies in the panel are electrically interconnected, and wherein edges in an outer perimeter of the panel provide electrical connectors to interface with the CMOS backplane dies.

[0085] In one aspect of method 800b, forming the panel includes holding the CMOS backplate die together by bonding the CMOS backplate die to a substrate.

[0086] In one aspect of method 800b, forming the panel includes holding the CMOS backplane die together with an overmold.

[0087] In one aspect of method 800b, forming the panel includes attaching the CMOS backplane die to the substrate and holding the CMOS backplane die together with an overmold. Method 800b may further include removing the panel with the CMOS backplane die from the substrate by performing a laser lift off (LLO) process to separate the panel from the substrate. Additionally, removing the panel from the substrate may include using a heat, laser, or UV releasable layer between the panel and the substrate.

[0088] In one aspect of method 800b, each CMOS backplane die is a CMOS integrated circuit configured to provide signals to control a respective subset of light emitting elements or light reflecting elements of the display.

[0089] In one aspect of method 800b, each CMOS backplane die has passed a wafer level probing test before it is included in a panel.

[0090] In one aspect of method 800b, the CMOS backplane die is positioned with the die facing up, and forming the panel includes holding the CMOS backplane die together with an overmold, and removing a top portion of the overmold to expose electrical posts of the CMOS backplane die. Further, removing the top portion of the overmold includes grinding the top portion of the overmold. Additionally, the electrical posts of the CMOS backplane die are exposed to electrical interconnections between the CMOS backplane die and the electrical redistribution layer.

[0091] In one aspect of method 800b, forming the panel includes holding the CMOS backplane die together with an overmold, and method 800b further includes disposing the overmold at least between and around the CMOS backplane die and curing the overmold to form the panel, the overmold being made of a material including silicon dioxide, aluminum oxide, graphite, ceramic, polymer, or electronic molding compound. The polymer may include polyimide or epoxy resin.

[0092] This disclosure describes various techniques and devices that enable larger and denser assemblies of backplanes and displays that can be used with high-resolution displays, such as light field displays.

[0093] The following claims are intended to cover all generic and specific features described herein, as well as all statements of the scope of the present methods and systems which, as a matter of language, might be said to fall therebetween. In particular, the following embodiments are specifically contemplated, as are any combinations of such embodiments that are compatible with each other.

[0094] (A) A backplane for controlling a display and comprising a plurality of tiles formed into an array, each tile comprising a plurality of complementary metal oxide semiconductor (CMOS) backplane dies, wherein edges of the tiles forming the outer perimeter of the array have electrical connections for directing electrical signals to at least one of the CMOS backplane dies.

[0095] (B) In the backplane denoted as (A), at least one of the CMOS backplane dies includes a CMOS integrated circuit that generates at least one electrical signal to drive at least one light emitting element of the display.

[0096] (C) In any of the backplanes denoted as (A) or (B), each CMOS backplane die includes a CMOS integrated circuit for generating an electrical signal to at least one light reflecting element of the display.

[0097] (D) In ​​any of the backplanes denoted as (A)-(C), when the plurality of tiles are formed into a 2x2 array, each tile has two edges, each edge having an electrical connection at the outer perimeter of the array.

[0098] (E) In any of the backplanes denoted as (A)-(D), a CMOS backplane die of the plurality of CMOS backplane dies positioned at the edge of the tile provides external electrical connectivity to the remaining CMOS backplane dies of the tile.

[0099] (F) In any one of the backplanes represented as (A)-(E), the plurality of CMOS backplane dies are arranged in a rectangular or square array and each of the plurality of CMOS backplane dies includes a plurality of pillars, and the plurality of pillars are electrically connected to at least one LED array of the display via an electrical redistribution layer (RDL).

[0100] (G) In any of the backplanes denoted as (A)-(F), each of the plurality of tiles further comprises an overmold that fills gaps between the CMOS backplane dies and holds the plurality of CMOS backplane dies together.

[0101] (H) In any of the backplates denoted as (A)-(G), the overmold is formed of a material selected from the group consisting of silica, alumina, graphite, ceramic, and polymer.

[0102] (I) In any of the backplanes denoted as (A)-(H), each of the plurality of tiles further comprises a substrate for firmly supporting the plurality of CMOS backplane dies.

[0103] (J) In any of the backplanes denoted as (A)-(I), the substrate is rigid and includes a plurality of through-silicon vias (TSVs) providing electrical connectivity to at least one of the plurality of CMOS backplane dies.

[0104] (K) A display component comprising: a backplane having an array of tiles, each tile having a plurality of electrically coupled CMOS backplane dies, wherein edges of the tiles forming an outer perimeter of the array include electrical connections for directing electrical signals to one or more of the plurality of CMOS backplane dies; and at least one light emitting diode (LED) array, the at least one LED array being electrically coupled to at least one tile.

[0105] (L) In the display component represented as (K), each of the plurality of tiles further includes an electrical redistribution layer disposed on at least a portion of each of the plurality of CMOS backplane dies to electrically connect a column of at least one of the CMOS backplane dies to the at least one LED array.

[0106] (M) Any of the display components denoted as (K) or (L), further comprising at least one microlens array configured to refract light from the LED array.

[0107] (N) In any of the display assemblies denoted as (K)-(M), the at least one microlens array comprises a single microlens array overlying the tile array.

[0108] (O) In any of the display components represented as (K)-(N), the at least one microlens array includes a plurality of microlens arrays, wherein each of the plurality of microlens arrays covers a different tile of the tile array.

[0109] (P) In any of the display components denoted as (K)-(O), the at least one microlens array comprises a plurality of microlens arrays, and wherein each of the plurality of microlens arrays covers a single CMOS backplane die.

[0110] (Q) In any of the display assemblies denoted as (K)-(P), each tile of the array of tiles further includes a substrate rigidly supporting the plurality of CMOS backplane dies.

[0111] (R) In any of the display assemblies denoted as (K)-(M), the substrate further includes a plurality of through-silicon vias (TSVs) providing electrical connectivity to at least one of the plurality of CMOS backplane dies.

[0112] (S) In any of the display assemblies denoted as (K)-(R), each tile of the tile array further includes an overmold that fills gaps between the CMOS backplane dies therein and rigidly supports the CMOS backplane dies.

[0113] Therefore, although the present disclosure has been provided in accordance with the illustrated implementations, those skilled in the art will readily recognize that there may be variations of the embodiments and those variations will be within the scope of the present disclosure. Therefore, those skilled in the art may make many modifications without departing from the scope of the appended claims.

Claims

1. A back panel for controlling a display, the back panel comprising: electrical connectors on the periphery of the backplane; a plurality of tiles formed into a tile array on the backplane, the plurality of tiles including tiles on a perimeter of the tile array and connected to the electrical connector; as well as a plurality of backplane dies arranged in a die array on the tile, the plurality of backplane dies comprising: a first backplane die having an edge on a perimeter of the die array, and A second backplate die adjacent to the first backplate die and having no edge on the perimeter of the die array, the second backplate die being connected to the electrical connector through the first backplate die.

2. The back plate according to claim 1, wherein: A backplane die of the plurality of backplane dies includes a complementary metal oxide semiconductor (CMOS) integrated circuit that generates electrical signals to drive light emitting elements of the display.

3. The back plate according to claim 1, wherein: A backplane die of the plurality of backplane dies includes a complementary metal oxide semiconductor (CMOS) integrated circuit for generating electrical signals to light reflecting elements of the display.

4. The backplane of claim 1, wherein when the plurality of tiles are formed into a 2x2 tile array, each tile has two edges, each of the two edges having an electrical connection at the perimeter of the tile array.

5. The back plate according to claim 1, wherein: The first of the plurality of backplane dies provides external electrical connectivity to remaining backplane dies in the array of dies on the tile.

6. The back plate according to claim 1, wherein: The plurality of backplane dies are arranged in a rectangular or square die array and a backplane die of the plurality of backplane dies comprises a plurality of pillars electrically connected to an LED array of the display via an electrical redistribution layer (RDL).

7. The back plate according to claim 1, wherein: The tile includes an overmold configured to fill gaps between the plurality of backplate dies and hold the plurality of backplate dies together.

8. The back plate according to claim 7, wherein: The overmold is formed of at least one of a silica material, an alumina material, a graphite material, a ceramic material, or a polymer material.

9. The back plate according to claim 1, wherein: The tile includes a substrate for firmly supporting the plurality of backplane dies.

10. The backplane of claim 9, the substrate being rigid and comprising a plurality of through silicon vias (TSVs) providing electrical connectivity to at least one of the plurality of backplane dies.

11. A display assembly comprising: A back plate, the back plate comprising: electrical connectors on the periphery of the backplane, a tile array including tiles on a perimeter of the tile array and connected to the electrical connector, and a plurality of electrically coupled backplane dies arranged in a die array on the tile, the plurality of backplane dies comprising: a first backplane die having an edge on a perimeter of the die array, and a second backplane die adjacent to the first backplane die and having no edge on the perimeter of the die array, the second backplane die being connected to the electrical connector through the first backplane die; and A light emitting diode (LED) array is electrically coupled to the tile.

12. The display assembly according to claim 11, wherein: The tile includes an electrical redistribution layer disposed on at least a portion of each of the first backplane die and the second backplane die to electrically connect the posts of at least one of the first backplane die or the second backplane die to the LED array.

13. The display assembly of claim 11, further comprising at least one microlens array configured to refract light from the LED array.

14. The display assembly according to claim 13, wherein: The at least one microlens array comprises a single microlens array overlying the tile array.

15. The display assembly according to claim 13, wherein: The at least one microlens array comprises a plurality of microlens arrays, wherein each of the plurality of microlens arrays covers a different tile of the tile array.

16. The display assembly according to claim 13, wherein: The at least one microlens array comprises a plurality of microlens arrays, and wherein each of the plurality of microlens arrays covers a single backplate die of the plurality of backplate dies.

17. The display assembly according to claim 11, wherein: The tile includes a substrate that rigidly supports the plurality of backplane dies. 18 . The display assembly of claim 17 , the substrate further comprising a plurality of through-silicon vias (TSVs) providing electrical connectivity to at least one of the plurality of backplane dies.

19. The display assembly according to claim 11, wherein: The tile includes an overmold configured to fill gaps between the plurality of backplate dies and rigidly support the plurality of backplate dies.

20. The display assembly of claim 19, wherein: The overmold is formed of at least one of a silica material, an alumina material, a graphite material, a ceramic material, or a polymer material.

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