A dual-channel temperature detection layout and its implementation circuit

Abstract

This invention discloses a dual-channel temperature detection layout method and its implementation circuit. The MpA and MnA modules are placed at the top of the chip layout, the digital and analog modules are placed in the middle, and the MpB and MnB modules are placed at the bottom. Qp0 and Qp1 are arranged between the MpA and MnA modules to form channel A; Qp2 and Qp3 are arranged between the MpB and MnB modules to form channel B. By detecting the Vbe values ​​of Qp0, Qp1 and Qp2, Qp3 respectively, the temperature changes of channels A and B can be detected simultaneously. This invention can accurately detect the temperature changes of both channels simultaneously, and compared to the traditional method using a single BJT, it has a faster response speed, avoids untimely over-temperature shutdown of a single channel, and enables normal operation or over-temperature shutdown control of the dual-channel temperature detection system.

Description

Technical Field

[0001] This invention belongs to the field of temperature measurement technology, and relates to a dual-channel temperature detection layout method and its implementation circuit. Background Technology

[0002] Currently, a single BJT is typically used to measure temperature. This method cannot accurately and quickly sample the temperature of both channels simultaneously, which can easily cause single-channel overheating and damage the chip.

[0003] Figure 1 This is a traditional dual-channel layout using a single BJT (Bipolar Junction Transistor) for temperature measurement, typically placed in one of three locations: A, B, or C. Placing it at A allows for accurate measurement of temperature changes in channel A, but due to its distance from channel B, it can easily cause system overheating when channel B operates alone. Placing it at C yields the same results as placing it at A. Placing it at B, with the same distance from both channels, results in insufficient measurement accuracy for both channels. It's clear that using a single BJT for temperature measurement in a dual-channel system always has its limitations. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a dual-channel temperature detection layout method and its implementation circuit. Two sets of BJTs are used to sample the temperature of the two channels respectively, and the temperature change is reflected in the Vbe voltage. The results of the two sets of comparators are then coupled together in a certain way through comparators to output the TSD control signal.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A dual-channel temperature detection layout method, wherein in the dual-channel temperature detection layout, the MpA module and MnA module are laid out at the top of the chip layout, the digital module and analog module are laid out in the middle of the chip layout, and the MpB module and MnB module are laid out at the bottom of the chip layout.

[0007] BJT devices Qp0 and Qp1 are deployed between the MpA module and the MnA module to form the first temperature detection channel channelA.

[0008] BJT devices Qp2 and Qp3 are deployed between the MpB module and the MnB module to form the second temperature detection channel channelB.

[0009] Among them, the MpA module and the MpB module are PMOS transistor modules, and the MnA module and the MnB module are NMOS transistor modules;

[0010] The analog module is used to generate bias currents Iref1 and Iref2, reference voltage Vref, and bias voltage Vbias.

[0011] The digital module includes MOSFETs Mp0, Mp1, Mn0 and Mn1 and comparators CMP1 and CMP2, which are used to generate over-temperature shutdown (TSD) signals for channels A and B based on the signals generated by the analog module.

[0012] By placing BJT devices Qp0, Qp1 and Qp2, Qp3 at the center of the layout of channels A and B respectively, and taking advantage of the characteristic that the Vbe voltage of the BJT devices is inversely proportional to the absolute temperature under a fixed bias current, the temperature changes of channels A and B can be detected simultaneously by detecting the Vbe voltages of BJT devices Qp0, Qp1 and Qp2, Qp3 respectively.

[0013] The present invention further includes the following preferred embodiments:

[0014] Preferably, CMP1 and CMP2 are used to monitor the voltage Vbe1 between the base and emitter of Qp0 and Qp1, and the voltage Vbe2 between the base and emitter of Qp2 and Qp3, respectively, and compare Vbe1 and Vbe2 with the reference voltage Vref, respectively, and realize the normal operation or over-temperature shutdown control of the dual-channel temperature detection system by outputting the results.

[0015] Preferably, CMP1 and CMP2 compare Vbe1 and Vbe2 with the reference voltage Vref respectively, and control the normal operation of the dual-channel temperature detection system by outputting the results. Specifically:

[0016] When the temperature of channel A and channel B does not rise to the point that Vbe1 and Vbe2 are less than or equal to Vref, the corresponding comparators output a low level, turning on Mp1 and Mp0 and turning off Mn1 and Mn0, so that the dual-channel temperature detection system works normally.

[0017] Preferably, CMP1 and CMP2 compare Vbe1 and Vbe2 with the reference voltage Vref respectively, and the output results are used to achieve over-temperature shutdown control of the dual-channel temperature detection system, specifically:

[0018] When the temperature of either or both of channels A and B rises to the point that either or both of Vbe1 and Vbe2 are less than or equal to Vref, the corresponding comparator outputs a high level, thereby enabling the dual-channel temperature detection system to shut down due to over-temperature.

[0019] The present invention also provides an implementation circuit for the dual-channel temperature detection layout method, the circuit including a channel A detection circuit and a channel B detection circuit;

[0020] The channel A detection circuit includes Qp0, Qp1, CMP1, Mp0, and Mn0;

[0021] The emitter sets of Qp0 and Qp1, as well as the negative phase input of CMP1, are connected to one end of the bias current Iref1, and the other end of the bias current Iref1 is connected to the operating voltage Vdd.

[0022] The input signal at the negative phase input terminal of CMP1 is Vbe1;

[0023] The base and collector electrodes of Qp0 and Qp1 are both grounded;

[0024] The input signal at the non-inverting input terminal of CMP1 is Vref, and the output terminal is connected to the gate of Mn0.

[0025] The source of Mn0 is grounded, and its drain is connected to the drain of Mp0 to output a thermal shutdown signal TSD.

[0026] The source of Mp0 is connected to Vdd, and the gate is connected to the bias voltage Vbias.

[0027] Preferably, the channel B detection circuit includes Qp2, Qp3, CMP2, Mp1, and Mn1;

[0028] The emitter sets of Qp2 and Qp3, as well as the negative phase input of CMP2, are connected to the bias current Iref2.

[0029] The input signal at the negative phase input terminal of CMP2 is Vbe2;

[0030] The base and collector electrodes of Qp2 and Qp3 are both grounded;

[0031] The input signal at the non-inverting input terminal of CMP2 is Vref, and the output terminal is connected to the gate of Mn1.

[0032] The source of Mn1 is grounded, and its drain is connected to the drain of Mp1 to output a thermal shutdown signal TSD.

[0033] The source of Mp1 is connected to Vdd, and the gate is connected to the bias voltage Vbias.

[0034] Preferably, when the temperature of channels A and B has not risen to the critical level, and Vbe1 and Vbe2 are greater than Vref, comparators CMP1 and CMP2 both output low level. At this time, Mp1 and Mp0 are in the deep linear region conduction state, Mn1 and Mn0 are cut off, the thermal shutdown signal TSD is high level, and the dual-channel temperature detection system works normally.

[0035] Preferably, when channel A operates alone, as the temperature gradually increases, when Vbe1≤Vref and Vbe2>Vref, comparator CMP1 outputs a high level and CMP2 outputs a low level. Mp1, Mp0, and Mn0 are in the on state, Mn1 is off, and Mn0 is in the deep linear region. The leakage currents of Mp1 and Mp0 flow through Mn0 simultaneously. At this time, the thermal shutdown signal TSD is low, realizing the over-temperature shutdown of the dual-channel temperature detection system.

[0036] Similarly, when channel B operates alone, and Vbe2≤Vref, Vbe1>Vref, the thermal shutdown signal TSD is low, realizing the over-temperature shutdown of the dual-channel temperature detection system.

[0037] Preferably, when channels A and B are working simultaneously, as the temperature gradually increases, Vbe1 and Vbe2 are both less than or equal to Vref. When this occurs, comparators CMP1 and CMP2 both output a high level, and Mp1, Mp0, Mn0, and Mn1 are simultaneously in the on state. Mn1 and Mn0 are in the deep linear region. At this time, the thermal shutdown signal TSD is low, thus realizing the over-temperature shutdown of the dual-channel temperature detection system.

[0038] The beneficial effects of this invention are compared with those of the prior art:

[0039] 1. In this invention, BJT devices Qp0, Qp1 and Qp2, Qp3 are placed at the center of the two sets of temperature detection channel layouts. Each set of channels uses two BJTs, which can simultaneously and accurately detect the temperature changes of the two channels. Compared with the traditional temperature measurement method that uses one BJT, it has a more negative temperature coefficient, resulting in a faster response speed.

[0040] 2. In the dual-channel temperature detection layout, CMP1 and CMP2 are also arranged to monitor the voltage drop Vbe1 between the base and emitter of Qp0 and Qp1, and the voltage drop Vbe2 between the base and emitter of Qp2 and Qp3, respectively. By comparing Vbe1 and Vbe2 with the reference voltage Vref, the dual-channel temperature detection system can be operated normally or controlled to shut down due to over-temperature. Attached Figure Description

[0041] Figure 1 It is a traditional dual-channel layout method that uses a single BJT for temperature measurement;

[0042] Figure 2 This invention relates to a layout method for computer graphics.

[0043] Figure 3 This describes the circuit implementation of the layout method of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this invention.

[0045] Figure 2 This invention relates to a layout method for computer graphics. Figure 3 This describes the circuit implementation of the layout method of the present invention. A thermal shutdown signal (TSD) is provided for the dual-channel simultaneous temperature detection.

[0046] It is known that for a fixed current bias of Iref1, Iref2, the voltage drop Vbe between the base and emitter of a BJT device has a negative temperature coefficient. The magnitude of the negative temperature coefficient is proportional to the emitter area of ​​the BJT. Compared with the traditional temperature measurement method using a single BJT, the present invention uses two BJTs per group, which results in a more negative temperature coefficient and thus a faster response speed.

[0047] refer to Figure 2 Embodiment 1 of the present invention provides a dual-channel temperature detection layout method. In a preferred but non-limiting embodiment of the present invention, in the dual-channel temperature detection layout, the MpA module and MnA module, the digital module and analog module, and the MpB module and MnB module are arranged in parallel and uniformly in three rows in sequence.

[0048] BJT devices Qp0 and Qp1 are deployed between the MpA module and the MnA module to form the first temperature detection channel channelA.

[0049] BJT devices Qp2 and Qp3 are deployed between the MpB module and the MnB module to form the second temperature detection channel channelB.

[0050] Among them, the MpA module and the MpB module are PMOS transistor modules, and the MnA module and the MnB module are NMOS transistor modules;

[0051] The structure and principle of the MpA, MpB, MnA and MnB modules are common knowledge in the field. The channels they form simply represent some power tubes that generate heat sources. They are the objects of this patent's testing, but not the inventive points of this patent, and will not be elaborated upon.

[0052] The analog module is used to generate bias currents Iref1 and Iref2, reference voltage Vref, and bias voltage Vbias.

[0053] The structure and principle of the analog module are not part of the invention of this patent. The methods for generating Iref, Vref, etc. are common knowledge to those skilled in the art and will not be elaborated here.

[0054] The digital module includes MOSFETs Mp0, Mp1, Mn0 and Mn1 and comparators CMP1 and CMP2, which are used to generate over-temperature shutdown (TSD) signals for channels A and B based on the signals generated by the analog module.

[0055] By placing BJT devices Qp0, Qp1 and Qp2, Qp3 at the center of the layout of channels A and B respectively, and taking advantage of the characteristic that the Vbe voltage of the BJT devices is inversely proportional to the absolute temperature under a fixed bias current, the temperature changes of channels A and B can be detected simultaneously by detecting the Vbe voltages of BJT devices Qp0, Qp1 and Qp2, Qp3 respectively.

[0056] CMP1 and CMP2 monitor the voltage drop Vbe1 between the base and emitter of Qp0 and Qp1, and the voltage drop Vbe2 between the base and emitter of Qp2 and Qp3, respectively. They also compare Vbe1 and Vbe2 with the reference voltage Vref to enable the dual-channel temperature detection system to operate normally or shut down due to over-temperature.

[0057] The method of comparing Vbe1 and Vbe2 with the reference voltage Vref to achieve normal operation or over-temperature shutdown control of the dual-channel temperature detection system is as follows:

[0058] When the temperature of channel A and channel B does not rise to the point that Vbe1 and Vbe2 are less than or equal to Vref, the corresponding comparators output a low level, causing Mp1 and Mp0 to be in the deep linear region of conduction, while Mn1 and Mn0 are cut off. The thermal shutdown signal TSD is high, and the dual-channel temperature detection system operates normally. In other cases, over-temperature shutdown is implemented.

[0059] refer to Figure 3Embodiment 2 of the present invention provides an implementation circuit for the dual-channel temperature detection layout method. In a preferred but non-limiting embodiment of the present invention, the circuit includes a channel A detection circuit and a channel B detection circuit.

[0060] The channel A detection circuit includes Qp0, Qp1, CMP1, Mp0, and Mn0;

[0061] The bias current Iref1 is connected to the emitter of Qp0 and Qp1 and the negative phase input of CMP1;

[0062] The input signal at the negative phase input terminal of CMP1 is Vbe1;

[0063] The base and collector electrodes of Qp0 and Qp1 are both grounded;

[0064] The input signal at the non-inverting input terminal of CMP1 is Vref, and the output terminal is connected to the gate of Mn0.

[0065] The source of Mn0 is grounded, and its drain is connected to the drain of Mp0 to output a thermal shutdown signal TSD.

[0066] The source of Mp0 is connected to Vdd, and the gate is connected to the bias voltage Vbias.

[0067] The channel B detection circuit includes Qp2, Qp3, CMP2, Mp1, and Mn1;

[0068] The bias current Iref2 is connected to the emitter of Qp2 and Qp3 and the negative phase input of CMP2;

[0069] The input signal at the negative phase input terminal of CMP2 is Vbe2;

[0070] The base and collector electrodes of Qp2 and Qp3 are both grounded;

[0071] The input signal at the non-inverting input terminal of CMP2 is Vref, and the output terminal is connected to the gate of Mn1.

[0072] The source of Mn1 is grounded, and its drain is connected to the drain of Mp1 to output a thermal shutdown signal TSD.

[0073] The source of Mp1 is connected to Vdd, and the gate is connected to the bias voltage Vbias.

[0074] When the temperature of channel A and channel B does not rise to the point that Vbe1 and Vbe2 are both less than or equal to Vref, comparators CMP1 and CMP2 both output a low level. At this time, Mp1 and Mp0 are in the deep linear region of conduction, Mn1 and Mn0 are cut off, the TSD signal is high, and the dual-channel temperature detection system works normally.

[0075] When channel A operates alone, as the temperature gradually increases, Vbe1≤Vref and Vbe2>Vref, comparator CMP1 outputs a high level and CMP2 outputs a low level. Mp1, Mp0, and Mn0 are in the on state, Mn1 is off, and Mn0 is in the deep linear region. The leakage currents of Mp1 and Mp0 flow through Mn0 simultaneously. At this time, the TSD signal is low, realizing the over-temperature shutdown of the dual-channel temperature detection system.

[0076] Similarly, when channel B works alone, and Vbe2≤Vref, Vbe1>Vref, the TSD signal is low, thus achieving over-temperature shutdown of the dual-channel temperature detection system.

[0077] When channels A and B operate simultaneously, as the temperature gradually increases, Vbe1 and Vbe2 become less than or equal to Vref. Comparators CMP1 and CMP2 both output high levels, and Mp1, Mp0, Mn0, and Mn1 are simultaneously in the on state. Mn1 and Mn0 are in the deep linear region, and the drain-source voltage Vds is very small. At this time, the TSD signal is low, realizing the system over-temperature shutdown.

[0078] The beneficial effects of this invention are compared with those of the prior art:

[0079] 1. This invention places BJT devices Qp0, Qp1 and Qp2, Qp3 at the center of two sets of channel layouts, using two BJTs for each channel. This allows for simultaneous and accurate detection of temperature changes in both channels. Compared to the traditional method using a single BJT, it exhibits a more negative temperature coefficient, resulting in a faster response speed.

[0080] 2. In the dual-channel temperature detection layout, CMP1 and CMP2 are also arranged to monitor the voltage drop Vbe1 between the base and emitter of Qp0 and Qp1, and the voltage drop Vbe2 between the base and emitter of Qp2 and Qp3, respectively. By comparing Vbe1 and Vbe2 with the reference voltage Vref, the dual-channel temperature detection system can be operated normally or controlled to shut down due to over-temperature.

[0081] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0082] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0083] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0084] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0085] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0086] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0087] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0088] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A dual-channel temperature detection layout method, characterized in that: in the dual-channel temperature detection layout, MpA and MnA modules are arranged at the top of the chip layout, digital and analog modules are arranged in the middle of the chip layout, MpB and MnB modules are arranged at the bottom of the chip layout; BJT devices Qp0 and Qp1 are arranged between the MpA and MnA modules to form a first group of temperature detection channels channelA; BJT devices Qp2 and Qp3 are arranged between the MpB and MnB modules to form a second group of temperature detection channels channelB; wherein, the MpA and MpB modules are PMOS tube modules, and the MnA and MnB modules are NMOS tube modules; the analog module is used to generate bias currents Iref1 and Iref2, a reference voltage Vref and a bias voltage Vbias; the digital module includes MOS tubes Mp0, Mp1, Mn0 and Mn1, and comparators CMP1 and CMP2, and is used to generate over-temperature shutdown signals TSD signals of the channelA and channelB based on signals generated by the analog module; the BJT devices Qp0 and Qp1 and the BJT devices Qp2 and Qp3 are respectively arranged at the center of the channelA and channelB layout, and by detecting the Vbe voltages of the BJT devices Qp0, Qp1, Qp2 and Qp3, the temperature changes of the channelA and channelB can be detected at the same time under the condition that the bias current is fixed, by using the characteristic that the Vbe voltage of the BJT device is inversely proportional to the absolute temperature; The implementation circuit of the dual-channel temperature detection layout method includes channelA detection circuit and channelB detection circuit; the channelA detection circuit includes Qp0, Qp1, CMP1, Mp0 and Mn0; the emitter set of Qp0 and Qp1 and the negative phase input end of CMP1 are connected to one end of the bias current Iref1, the other end of the bias current Iref1 is connected to the working voltage Vdd; the input signal of the negative phase input end of CMP1 is Vbe1; the base set and the collector of Qp0 and Qp1 are grounded; the input signal of the positive phase input end of CMP1 is Vref, and the output end is connected to the gate of Mn0; the source of Mn0 is grounded, the drain is connected to the drain of Mp0 and outputs the thermal shutdown signal TSD; the source of Mp0 is connected to Vdd, and the gate is connected to the bias voltage Vbias. 2.The dual-channel temperature detection layout method of claim 1, characterized in that: the CMP1 and CMP2 are used to monitor the voltages Vbe1 between the base and the emitter of Qp0 and Qp1 and the voltages Vbe2 between the base and the emitter of Qp2 and Qp3, respectively, and compare Vbe1 and Vbe2 with the reference voltage Vref, respectively, to realize normal operation or over-temperature shutdown control of the dual-channel temperature detection system through the output results. ​ ​ ​ 3. The double-channel temperature detection layout method according to claim 2, wherein: the CMP1 and CMP2 respectively compare Vbe1 and Vbe2 with the reference voltage Vref, and realize normal working control of the double-channel temperature detection system through output results, specifically: when the temperature of channel A and channel B does not rise to make Vbe1 and Vbe2 less than or equal to Vref, the corresponding comparator outputs low level, and Mp1 and Mp0 are turned on, Mn1 and Mn0 are cut off, and the double-channel temperature detection system works normally.

4. The double-channel temperature detection layout method according to claim 2, wherein: the CMP1 and CMP2 respectively compare Vbe1 and Vbe2 with the reference voltage Vref, and realize over-temperature shutdown control of the double-channel temperature detection system through output results, specifically: when the temperature of either channel A or channel B or both channels rises to make either Vbe1 or Vbe2 or both less than or equal to Vref, the corresponding comparator outputs high level, and the double-channel temperature detection system is over-temperature shutdown.

5. The double-channel temperature detection layout method according to claim 1, wherein: the channel B detection circuit comprises Qp2, Qp3, CMP2, Mp1 and Mn1; the emitter set of Qp2 and Qp3 and the negative phase input end of CMP2 are connected with the bias current Iref2; the input signal of the negative phase input end of CMP2 is Vbe2; the base set and the collector of Qp2 and Qp3 are grounded; the input signal of the positive phase input end of CMP2 is Vref, and the output end is connected with the gate of Mn1; the source of Mn1 is grounded, and the drain is connected with the drain of Mp1 and outputs a thermal shutdown signal TSD; and the source of Mp1 is connected with Vdd, and the gate is connected with the bias voltage Vbias.

6. The double-channel temperature detection layout method according to claim 5, wherein: when the temperature of channel A and channel B does not rise to the critical value, and Vbe1 and Vbe2 are greater than Vref, the comparators CMP1 and CMP2 both output low level, at this time, Mp1 and Mp0 are in the deep linear region conduction state, Mn1 and Mn0 are cut off, the thermal shutdown signal TSD is high level, and the double-channel temperature detection system works normally.

7. The double-channel temperature detection layout method according to claim 5, wherein: when channel A works alone, and the temperature gradually rises to make Vbe1 ≤ Vref, and Vbe2 > Vref, the comparator CMP1 outputs high level and CMP2 outputs low level, Mp1, Mp0 and Mn0 are in the conduction state, Mn1 is cut off, Mn0 is in the deep linear region, the drain current of Mp1 and Mp0 flows through Mn0 at the same time, at this time, the thermal shutdown signal TSD is low level, and the double-channel temperature detection system is over-temperature shutdown.

8. The double-channel temperature detection layout method according to claim 5, wherein: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ When channelB works alone, Vbe2≤Vref, Vbe1>Vref, the thermal shutdown signal TSD is low, and the double-channel temperature detection system is over-temperature shutdown.

9. The double-channel temperature detection layout method according to claim 5, characterized in that: When channelA and channelB work simultaneously, with the temperature gradually increasing, Vbe1, Vbe2 are simultaneously less than or equal to Vref, the comparators CMP1 and CMP2 output high, Mp1, Mp0, Mn0, and Mn1 are simultaneously in the conduction state, Mn1 and Mn0 are in the deep linear region, and the thermal shutdown signal TSD is low, realizing the over-temperature shutdown of the double-channel temperature detection system.

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