Screening method, device and electronic equipment for data retention performance of flash memory chip

Abstract

The application discloses a screening method and device for data retention performance of a flash memory chip and electronic equipment, and the method comprises the following steps: pre-processing a flash memory unit of the flash memory chip; reading a first analog electrical parameter of the flash memory unit after the pre-processing; performing interference processing on the flash memory chip; reading a second analog electrical parameter of the flash memory unit after the interference processing; judging a difference between the first analog electrical parameter and the second analog electrical parameter, and if the difference meets a preset change range, the data retention performance of the flash memory unit is qualified. The technical scheme provided by the application reduces the test period, improves the test efficiency, and reduces the influence on the subsequent programming accuracy.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of memory, and particularly relate to a screening method, device and electronic equipment for data retention performance of a flash memory chip. BACKGROUND

[0002] In recent years, the rapid development of electronic product technology has made consumers' experience requirements for electronic products higher and higher, and the demand for faster and more convenient storage products is also increasing. In applications, sometimes due to external factors or poor data retention capability of the flash memory chip, the configuration information and production information of the flash memory unit change. Therefore, the data retention performance of the flash memory chip needs to be detected during production.

[0003] In the conventional flash memory interference screening test of the prior art, the number of interference tests is large, the cycle is long, the test efficiency is affected, and in a deep programming state, interference processing is easy to produce interface states that affect channel current or gather movable charges (such as ions) at the channel interface of the flash memory unit, thereby affecting the subsequent programming accuracy. SUMMARY

[0004] The present application provides a screening method, device and electronic equipment for data retention performance of a flash memory chip, which reduces the test cycle, improves the test efficiency, and reduces the impact on the subsequent programming accuracy.

[0005] In a first aspect, the present application provides a screening method for data retention performance of a flash memory chip, comprising:

[0006] preprocessing a flash memory unit of the flash memory chip;

[0007] reading a first analog electrical parameter of the flash memory unit after preprocessing;

[0008] interfering with the flash memory chip;

[0009] reading a second analog electrical parameter of the flash memory unit after the interference processing;

[0010] judging a difference between the first analog electrical parameter and the second analog electrical parameter, and if the difference meets a preset change range, the data retention performance of the flash memory unit is qualified.

[0011] Optionally, preprocessing the flash memory chip comprises:

[0012] obtaining a sub-threshold region of the flash memory unit; wherein the sub-threshold region represents a voltage range of a working region of the flash memory chip;

[0013] matching a write voltage in the sub-threshold region according to the first analog electrical parameter;

[0014] According to the write voltage, the flash memory cell is simulated flash programming, and the first analog electrical parameter is written into the flash memory cell.

[0015] Optionally, the flash memory chip is pre-processed, including:

[0016] Erasing the storage data of the flash memory cell.

[0017] Optionally, after erasing the storage data of the flash memory cell, further comprising:

[0018] Determining the detection analog electrical parameter interval of the flash memory cell;

[0019] According to the detection analog electrical parameter interval, the flash memory cell is detected; if the analog parameter of the flash memory cell is in the analog electrical parameter interval, the flash memory cell is erased normally.

[0020] Optionally, the second analog electrical parameter of the flash memory cell after the interference processing is read, including:

[0021] The read voltage is applied to the flash memory cell, and the second analog electrical parameter stored in the flash memory cell is read.

[0022] Optionally, the interference processing on the flash memory chip includes baking the flash memory chip.

[0023] In a second aspect, an embodiment of the present application provides a screening device for data retention performance of a flash memory chip, including:

[0024] A pre-processing module is configured to pre-process a flash memory cell of the flash memory chip.

[0025] A first reading module is configured to read a first analog electrical parameter of the flash memory cell after pre-processing.

[0026] An interference module is configured to interfere with the flash memory chip.

[0027] The first reading module is further configured to read a second analog electrical parameter of the flash memory cell after the interference processing.

[0028] A judging module is configured to judge a difference between the first analog electrical parameter and the second analog electrical parameter; if the difference meets a preset variation range, the data retention performance of the flash memory cell is qualified.

[0029] Optionally, the pre-processing module includes:

[0030] An acquisition unit is configured to acquire a sub-threshold region of the flash memory cell; wherein the sub-threshold region represents a voltage range of a working region of the flash memory chip.

[0031] a matching unit configured to match a write voltage in the sub-threshold region according to the first analog electrical parameter;

[0032] a programming unit configured to perform analog flash programming on the flash memory unit according to the write voltage, and write the first analog electrical parameter into the flash memory unit.

[0033] Optionally, the preprocessing module comprises:

[0034] The erasing unit is configured to erase the flash memory unit.

[0035] In a third aspect, an embodiment of the present application provides an electronic device, which comprises:

[0036] at least one processor; and

[0037] a memory connected with the at least one processor; wherein the memory stores a computer program which can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the screening method for data retention performance of a flash memory chip according to any one of claims 1-6.

[0038] In the prior art, a chessboard programming method is used to perform digital programming on a flash memory unit, and the boundary of a test interval of a defined state "0" and a state "1" is taken as a judgment standard, and the state "0" and the state "1" of the flash memory unit are respectively judged through at least two interference processes. Compared with the prior art, the technical solution provided by the embodiment of the present application can reflect the influence of the interference process on the data retention performance of the flash memory unit through a difference value of changes of analog electrical parameters before and after the interference process, can judge the data retention performance of the flash memory unit through only one interference process, reduce a test period, improve test efficiency, and reduce the influence of subsequent analog flash programming precision. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 FIG. 1 is a schematic diagram of a relationship between a sample number and a storage unit current in a digital data retention test in the prior art.

[0040] Figure 2 FIG. 5 is a flowchart of a screening method for data retention performance of a flash memory chip provided by an embodiment of the present application.

[0041] Figure 3 FIG. 5 is a flowchart of a screening method for data retention performance of a flash memory chip provided by an embodiment of the present application.

[0042] Figure 4 A flow chart of another screening method of data retention performance of a flash memory chip according to an embodiment of the present application.

[0043] Figure 5 A diagram of the relationship between voltage and flash memory cell current according to an embodiment of the present application.

[0044] Figure 6 A flow chart of another screening method of data retention performance of a flash memory chip according to an embodiment of the present application.

[0045] Figure 7 A flow chart of another screening method of data retention performance of a flash memory chip according to an embodiment of the present application.

[0046] Figure 8 A diagram of the relationship between flash memory cell current and sample number according to an embodiment of the present application.

[0047] Figure 9 A flow chart of another screening method of data retention performance of a flash memory chip according to an embodiment of the present application.

[0048] Figure 10 A structural diagram of a screening device of data retention performance of a flash memory chip according to an embodiment of the present application.

[0049] Figure 11 A structural diagram of an electronic device that can be used to implement an embodiment of the present application is presented. DETAILED DESCRIPTION

[0050] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0051] Figure 1 A diagram of the relationship between sample number and storage unit current in a digital data retention test in the prior art, Figure 2 A flow diagram of a digital data retention test in the prior art, see Figure 1 and Figure 2, the flash memory chip is a storage chip capable of storing data files. In an ideal case, when the storage current of the flash memory unit is less than the first limit current Normal, it represents "0" data storage, and when the storage current of the flash memory unit is greater than the first limit current Normal, it represents "1" data storage. However, in the interference screening of the flash memory chip, it is necessary to increase the screening range as a test interval, therefore, it is necessary to define the second limit current Margin1 and the third limit current Margin0 as the boundaries of the test interval, the second limit current Margin1 is the minimum current of "1" data storage, and the third limit current Margin0 is the maximum current of the current of "0" data storage. After interference processing, the storage current of the flash memory unit storing "1" data will decrease and move towards "0", and the storage current of the flash memory unit storing "0" data will increase and move towards "1", therefore, after interference processing, if the current of the flash memory unit storing "0" data is still less than the third limit current Margin0, and the current of the flash memory unit storing "1" data is still greater than the second limit current Margin1, it indicates that the data retention performance is qualified. The test process is as follows: after deep erase of the flash memory chip, for example, the flash memory chip is programmed with "0101..." in a chessboard mode, the programming failure is screened, the screened pass is subjected to interference processing, and the second limit current Margin1 and the third limit current Margin0 are used as the standards for judgment, so as to judge whether the data retention performance of the flash memory chip is qualified. After deep erase again, the flash memory chip is programmed with "1010..." in a flip chessboard mode, and after interference processing, the second limit current Margin1 and the third limit current Margin0 are used as the standards for judgment, so as to judge whether the data retention performance is qualified. The whole test process needs at least 2 times of interference processing, the test period is long, and after deep programming, interference processing is easy to produce interface state affecting channel current or gather movable charges (such as ions) at the channel interface, thereby affecting the subsequent programming accuracy.

[0052] Therefore, Figure 3 A flowchart of a screening method for data retention performance of a flash memory chip is provided for the embodiment of the present application. The embodiment can be applicable to the screening of data retention performance of the flash memory chip. The method can be executed by a screening device for data retention performance of the flash memory chip. The device can be realized in the form of hardware and / or software. The method specifically comprises the following steps:

[0053] S110, pre-processing the flash memory unit of the flash memory chip.

[0054] The flash memory chip includes at least two flash memory units, which are usually arranged in an array. In the data retention performance screening, the entire flash memory chip or the flash memory units in a uniform area of the flash memory chip can be selected for screening test. The pre-treatment is to change the storage state of the flash memory unit through erasing / programming and other processing procedures. In the prior art, the flash memory unit is digitally programmed through chessboard programming, and in the embodiment, the pre-treatment procedure includes erasing the stored data in the flash memory unit, so that the flash memory unit is in a neutral storage state after erasing, or storing an analog value in the flash memory unit through analog programming, and using the analog electrical parameter stored in the pre-treated flash memory unit for subsequent data retention performance screening.

[0055] S120, reading a first analog electrical parameter of the pre-treated flash memory unit.

[0056] Specifically, the first analog electrical parameter is the channel current in the floating gate of the flash memory unit, wherein the flash memory unit has a source electrode, a drain electrode, a floating gate and a control gate. There is a silicon dioxide insulating layer between the floating gate and the silicon substrate, which is used to protect the charge in the floating gate from leaking. With this structure, the flash memory unit has charge retention capability. After pre-treating the flash memory unit, a reading voltage is applied to the flash memory unit to read the first analog electrical parameter of the flash memory unit.

[0057] S130, performing interference treatment on the flash memory chip.

[0058] Specifically, the interference treatment is a process of placing the flash memory chip in a simulated environment that is easy to cause data loss, so as to detect whether the flash memory chip still has good data retention performance after being subjected to the simulated environment. For example, the flash memory chip is subjected to high-temperature baking to simulate the effect of high-temperature environment on data retention.

[0059] S140, reading a second analog electrical parameter of the flash memory unit after the interference treatment.

[0060] Specifically, after the interference treatment, a reading voltage is applied to the flash memory unit to read the second analog electrical parameter of the flash memory unit.

[0061] S150, judging the difference between the first analog electrical parameter and the second analog electrical parameter, and if the difference meets a pre-set change range, the data retention performance of the flash memory unit is qualified.

[0062] Specifically, after interference processing, the channel current of the flash memory cell may increase or decrease depending on the type of stored charge. Therefore, by obtaining the difference between the first and second analog electrical parameters before and after interference processing, the impact of interference processing on the data retention performance of the flash memory cell can be reflected. If, after a long baking period, the difference between the first and second analog electrical parameters is within the normal range, it indicates that the data retention performance of the flash memory cell is stable. If the difference exceeds the normal range, it indicates that the data retention performance of the flash memory cell is defective.

[0063] The technical solution provided by this invention preprocesses the flash memory cells of the flash memory chip, directly reads the first analog electrical parameters of the flash memory cells after preprocessing, performs interference processing, reads the second analog electrical parameters of the flash memory cells after interference processing, and compares the difference in the changes of the analog electrical parameters before and after interference processing. This difference reflects the impact of interference processing on the data retention performance of the flash memory cells. Data retention performance can be determined with only one interference processing, reducing the test cycle and improving test efficiency. Reading is performed after preprocessing, followed by interference processing, thereby reducing the impact on subsequent programming accuracy.

[0064] Figure 4 A flowchart illustrating another method for screening the data retention performance of a flash memory chip according to an embodiment of the present invention is provided. (See attached flowchart.) Figure 4 The method includes the following steps:

[0065] S210. Obtain the subthreshold region of the flash memory cell. The subthreshold region characterizes the voltage range of the operating region of the flash memory chip.

[0066] Specifically, the subthreshold region 'a' is the working region for simulated in-memory computing. Figure 5 A schematic diagram illustrating the relationship between voltage and flash memory cell current is provided in an embodiment of the present invention. See also... Figure 5 The subthreshold region 'a' is a characteristic of the device itself. It is obtained by testing the current and voltage performance of the flash memory cell or through model simulation. The current in the subthreshold region 'a' is typically between tens of pA and hundreds of nA. For example, the current in the subthreshold region 'a' can be assigned a specific number of bits to obtain current weights; for instance, it can be divided into 7 bits based on the current magnitude, resulting in 0-127 weights.

[0067] S220. Match the write voltage within the subthreshold region according to the first analog electrical parameters.

[0068] Specifically, the first simulation parameter is selected as the storage current of the flash memory cell according to the performance of the flash memory cell. For example, when the storage current of the flash memory cell is represented by a weight, the corresponding storage current can correspond to the weight, and the corresponding write voltage is matched in the sub-threshold region according to the first simulation parameter or the weight.

[0069] S230, performing analog flash programming on the flash memory cell according to the write voltage, and writing the first simulation parameter into the flash memory cell.

[0070] Specifically, each flash memory cell is programmed by analog flash programming, and the corresponding write voltage set in the programming can adjust the storage current of the flash memory cell, that is, the first simulation parameter or the weight. For example, in order to simplify the subsequent storage current writing complexity of each flash memory cell, the same first simulation parameter or weight can be written into each flash memory cell.

[0071] S240, reading the first simulation parameter of the flash memory cell after the preprocessing.

[0072] S250, performing interference processing on the flash memory chip.

[0073] S260, reading the second simulation parameter of the flash memory cell after the interference processing.

[0074] S270, judging the difference between the first simulation parameter and the second simulation parameter, and if the difference meets the preset change range, the data retention performance of the flash memory cell is qualified.

[0075] Specifically, the device is subjected to data retention test, and the difference between the first simulation parameter and the second simulation parameter before and after the interference processing on the storage unit according to the application of the analog flash, or the change of the weight before and after the interference processing on the storage unit, is used as the standard of qualification or disqualification. The difference reflects the influence of the interference processing on the data retention performance of the flash memory cell.

[0076] Figure 6 Another flowchart of the screening method of the data retention performance of the flash memory chip provided by the embodiment of the present application is provided, which is shown in Figure 6 The method steps include:

[0077] After other tests are completed, the flash memory unit is deeply erased, and the flash memory unit is in a "1 state" after being erased, and a "1" reading can be performed on each flash memory unit to determine whether each flash memory unit is successfully erased, so as to avoid erasing failure and affecting the detection accuracy of the subsequent test. According to the performance of the storage unit, the sub-threshold region a is obtained, the write-in first analog electrical parameter corresponding to the write-in voltage is determined, the analog flash programming is performed on the flash memory unit, the first analog electrical parameter is written into the flash memory unit by adjusting the write-in voltage, and the programming result is read to obtain the first analog electrical parameter, so as to avoid programming errors or missed programming and thus affect the subsequent programming accuracy. Each flash memory unit is programmed in turn until all the tested flash memory units are programmed, the flash memory unit is subjected to interference processing, for example, the flash memory unit is subjected to high-temperature baking, and the storage current of the flash memory unit, that is, the second analog electrical parameter, is read again. If the difference between the first analog electrical parameter and the second analog electrical parameter obtained after a long baking time is within a normal range, it indicates that the data retention performance of the flash memory unit is stable, and if the difference between the first analog electrical parameter and the second analog electrical parameter exceeds the normal range, it indicates that the data retention performance of the flash memory unit has defects.

[0078] Figure 7 A flowchart of another method for screening the data retention performance of a flash memory chip is provided for the embodiment of the present application, as shown in Figure 7 The method steps include:

[0079] S310, erase the storage data of the flash memory unit.

[0080] Specifically, the injection of charges into the floating gate of the flash memory unit indicates that "0" is written, and no injection of charges indicates that "1" is written, so the data of the flash memory unit is cleared by writing "1". When no charge is injected, the charge of the floating gate of the working interval e of the flash memory unit is close to charge neutrality, that is, the neutral state. Figure 8 A schematic diagram of the relationship between the current of the flash memory unit and the number of samples is provided for the embodiment of the present application, as shown in Figure 8 The difference b between the current of the storage data in the "1" state and the neutral state is greater than the difference c between the current of the storage data in the "0" state and the neutral state, so after the interference processing, the change amount of the retention current of the storage data in the "0" state is small, and the movement amount is small, which is not convenient for collection. Therefore, preferably, the data stable test of the storage data in the "1" state can be retained, and the minimum current of the storage data in the "1" state is defined as.

[0081] S320, read the first analog electrical parameter of the flash memory unit after preprocessing.

[0082] Specifically, the first analog electrical parameter of the storage data in the "1" state is read.

[0083] S330, performing interference processing on the flash memory chip.

[0084] S340, reading a second analog electrical parameter of the flash memory cell after interference processing.

[0085] S350, judging a difference between the first analog electrical parameter and the second analog electrical parameter, and if the difference is within a preset variation range, the data retention performance of the flash memory cell is qualified.

[0086] Specifically, after interference processing, the current of the storage data in the state of '1' is reduced and moves to the state of '0', and the current at this time, i.e. the second analog electrical parameter, is read. According to the difference between the first analog electrical parameter and the second analog electrical parameter, the current variation d of the data in the state of '1' is obtained. The current variation d is a quantity representing the state of '1', i.e. the current and voltage curve of the flash memory cell changes with the change of the floating gate charge when in the saturation region or linear region. If the current variation d is still greater than or equal to a preset value, it indicates that the data retention performance of the flash memory cell is qualified. The selection of the preset value is set according to the tolerance requirement of the change size of the storage current of the flash memory cell. The whole test process only needs one interference processing, the test period is short, and interference processing in a deep erase state is not required, so that the screening of data retention can be realized, the flash memory cells with abnormalities can be excluded, and the subsequent programming accuracy can be reduced.

[0087] Optionally, after erasing the storage data of the flash memory cell, the method further comprises:

[0088] Determining a detection analog electrical parameter interval of the flash memory cell.

[0089] Detecting the flash memory cell according to the detection analog electrical parameter interval. If the analog parameter of the flash memory cell is within the analog electrical parameter interval, the flash memory cell is erased normally.

[0090] Specifically, according to the performance of the flash memory cell, the charge is injected into the floating gate of the flash memory cell to represent that '0' is written, and no charge is injected to represent that '1' is written, so that the data of the flash memory cell is cleared by writing '1'. The detection analog electrical parameter is determined according to the performance of the flash memory cell, and the detection analog electrical parameter is the defined storage current after the flash memory cell is erased. The defined storage current is taken as the detection standard. After the flash memory cell is erased, the first analog electrical parameter is read. If the storage current corresponding to the first analog electrical parameter is greater than the defined storage current, it indicates that the flash memory cell is successfully erased, and the flash memory cell with abnormal erasing is screened.

[0091] Figure 9 The flowchart of another method for screening the data retention performance of the flash memory chip provided by the embodiment of the present application is combined with Figure 8 Referring to Figure 9After other tests are completed, the flash memory unit is deeply erased, and the flash memory unit is in a "1 state" after being erased, and a "1" reading can be performed on each flash memory unit, that is, a first analog electrical parameter is read, and if the storage current of the flash memory unit is greater than an erase standard Margin 3, it is determined that the flash memory unit is successfully erased, and the influence of erasing failure on subsequent detection accuracy is avoided. The flash memory unit is subjected to interference processing, and for example, the flash memory unit is subjected to high-temperature baking, and the storage current of the flash memory unit, that is, a second analog electrical parameter, is read again. After interference processing, the current of the storage data in the "1 state" decreases, and the current at this time, that is, the second analog electrical parameter, is read, and the current change d of the "1 state" data retention is obtained according to the difference between the first analog electrical parameter and the second analog electrical parameter. If the current change d is still greater than a preset value, it indicates that the data retention performance of the flash memory unit is qualified. The selection of the preset value is set according to the tolerance requirement of the change size of the storage current. The entire test process only needs one interference processing, the test period is short, and interference processing in a deep erasing state is not needed, so that the screening of data retention can be realized, the flash memory unit with an abnormality is excluded, and the influence on subsequent programming accuracy is reduced.

[0092] Optionally, the second analog electrical parameter of the flash memory unit after interference processing is read, and the method comprises the following steps.

[0093] The reading voltage is applied to the flash memory unit, and the second analog electrical parameter stored in the flash memory unit is read.

[0094] Specifically, the reading voltage is applied to the flash memory unit, and the storage current of the flash memory unit, that is, the second analog electrical parameter, is read. The process of applying the reading voltage to the flash memory unit is also the process of reading the storage current from each flash memory unit.

[0095] Optionally, the interference processing on the flash memory chip comprises baking the flash memory chip.

[0096] Specifically, the flash memory chip is placed in an analog environment that is easy to cause data loss, for example, baking, and the purpose of baking the flash memory chip is to simulate an environment that may cause the data retention capability of the flash memory unit to decrease in a real environment. In order to prevent the flash memory chip from being oxidized in a high-temperature environment, the flash memory chip can be placed in a nitrogen environment. It should be noted that in the embodiment, the analog environment that is easy to cause data loss is exemplarily a high-temperature environment, but is not limited to this, and is only used for illustration.

[0097] Figure 10 A structure diagram of a screening device for data retention performance of a flash memory chip provided in the embodiment of the application is shown in FIG. 1. Figure 10 , and comprises the following components.

[0098] The preprocessing module 110 is configured to perform preprocessing on the flash memory unit of the flash memory chip.

[0099] The first reading module 120 is configured to read a first analog electrical parameter of the pre-processed flash memory cell.

[0100] The interference module 130 is configured to perform interference processing on the flash memory chip.

[0101] The first reading module 120 is configured to read a second analog electrical parameter of the flash memory cell after the interference processing.

[0102] The judging module 140 is configured to judge a difference between the first analog electrical parameter and the second analog electrical parameter, and if the difference meets a preset variation range, the data retention performance of the flash memory cell is qualified.

[0103] Specifically, the flash memory chip includes at least two flash memory cells, and the flash memory cells are usually arranged in an array form. In the data retention performance screening, the entire flash memory chip or the flash memory cells in a uniform area of the flash memory chip can be selected for screening test. The pre-processing is to change the storage state of the flash memory cell through an erasing / programming process. In the prior art, the flash memory cell is digitally programmed through chessboard programming, and in the embodiment, the pre-processing process of the pre-processing module 110 includes erasing the stored data in the flash memory cell to make the flash memory cell in a neutral storage state, or storing an analog value in the flash memory cell through analog programming, and the analog electrical parameter stored in the pre-processed flash memory cell is used for subsequent screening of the data retention performance.

[0104] The first analog electrical parameter is a channel current in the floating gate of the flash memory cell, wherein the flash memory cell has a source electrode, a drain electrode, a floating gate and a control gate. There is a silicon dioxide insulating layer between the floating gate and the silicon substrate to prevent the charge in the floating gate from leaking. With this structure, the flash memory cell has a charge retention capability. After the pre-processing of the flash memory cell, the first reading module 120 applies a reading voltage to the flash memory cell to read the first analog electrical parameter of the flash memory cell.

[0105] The interference processing is a process of placing the flash memory chip in an analog environment which is easy to cause data loss, so as to detect whether the flash memory chip still has good data retention performance after passing through the analog environment. The interference module bakes the flash memory chip at high temperature to simulate the influence of high temperature environment on data retention. After the interference processing, the first reading module 120 applies a reading voltage on the flash memory unit to read the second analog electrical parameter of the flash memory unit. After the interference processing, according to the type of stored charge, the channel current of the flash memory unit may become larger or smaller, therefore, the judging module 140 obtains the difference between the first analog electrical parameter and the second analog electrical parameter before and after the interference processing, and reflects the influence of the interference processing on the data retention performance of the flash memory unit through the difference. If the difference between the first analog electrical parameter and the second analog electrical parameter obtained after baking for a long time is within the normal range, it indicates that the data retention performance of the flash memory unit is stable, and if the difference between the first analog electrical parameter and the second analog electrical parameter exceeds the normal range, it indicates that the data retention performance of the flash memory unit has defects.

[0106] The technical scheme provided by the embodiment of the application, the preprocessing module pre-processes the flash memory unit of the flash memory chip, the first reading module directly reads the first analog electrical parameter of the flash memory unit after the pre-processing, the interference module performs interference processing, the first reading module reads the second analog electrical parameter of the flash memory unit after the interference processing, and the judging module compares the change difference between the analog electrical parameters before and after the interference processing, reflects the influence of the interference processing on the data retention performance of the flash memory unit through the difference, judges the data retention performance through only one interference processing, reduces the test period and improves the test efficiency, reads after the pre-processing, and then performs interference processing, so as to reduce the influence on the subsequent programming accuracy.

[0107] Optionally, the preprocessing module comprises:

[0108] The obtaining unit is configured to obtain a sub-threshold region a of the flash memory unit. The sub-threshold region a represents a voltage range of a working region of the flash memory chip.

[0109] The matching unit is configured to match a write voltage in the sub-threshold region a according to the first analog electrical parameter.

[0110] The programming unit is configured to perform analog flash programming on the flash memory unit according to the write voltage, and write the first analog electrical parameter into the flash memory unit.

[0111] Specifically, the sub-threshold region a is a working region of analog storage and calculation, and the sub-threshold region a is a characteristic of the device itself. The acquisition unit obtains the sub-threshold region a of each flash memory cell by using current-voltage performance testing of the flash memory cell device or by using model simulation. The current of the sub-threshold region a is approximately between ten pA and several hundred nA. For example, the current of the sub-threshold region a can be appropriately divided by a number of bits, so as to obtain the weight of the current. For example, according to the current size, the current can be divided into 7 bits, so as to obtain 0-127 weights. According to the performance of the flash memory cell, the first simulation parameter is selected as the storage current of the flash memory cell. For example, when the storage current of the flash memory cell is expressed by a weight, the corresponding storage current can correspond to the weight. The matching unit matches the corresponding write voltage in the sub-threshold region a according to the first simulation parameter or the weight. The programming unit programs each flash memory cell by simulating flash programming. In the programming, the corresponding write voltage is set to adjust the storage current of the flash memory cell, that is, the first simulation parameter or the weight. For example, in order to simplify the storage current writing complexity of each flash memory cell, the same first simulation parameter or weight can be written to each flash memory cell.

[0112] Optionally, the preprocessing module comprises:

[0113] The erasing unit is configured to erase the storage data of the flash memory cell.

[0114] Specifically, injecting charges into the floating gate of the flash memory cell indicates that "0" is written, and no charge injection indicates that "1" is written. Therefore, the data of the flash memory cell is cleared by writing "1".

[0115] Figure 11 A structural schematic diagram of an electronic device that can be used to implement an embodiment of the present application is shown in FIG. 1. Figure 11 The electronic device comprises:

[0116] at least one processor; and

[0117] a memory connected in communication with the at least one processor, wherein

[0118] The memory stores a computer program executable by the at least one processor. The computer program is executed by the at least one processor to enable the at least one processor to perform any of the data retention performance screening methods of the flash memory chip in the embodiments of the present application.

[0119] Specifically, electronic devices are intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0120] like Figure 11 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0121] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0122] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as data retention performance filtering methods.

[0123] In some embodiments, the screening method of data retention performance can be implemented as a computer program tangibly embodied in a computer readable storage medium, e.g., storage unit 18. In some embodiments, portions of or all of the computer program can be loaded onto the electronic device 10 via, e.g., ROM 12 and / or communication unit 19. When a computer program is loaded onto the RAM 13 and executed by the processor 11, one or more of the steps of the above-described screening method of data retention performance can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the screening method of data retention performance by other any suitable means, e.g., by means of firmware.

[0124] Finally, it should be noted that the above-mentioned embodiments are merely used to illustrate the technical solutions of the present application, rather than limit the same. Even though the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still make modifications to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for screening the data retention performance of a flash memory chip, characterized in that, The method comprises: preprocessing a flash memory cell of the flash memory chip, the preprocessing comprising storing an analog value in the flash memory cell by analog programming, a first analog electrical parameter of the flash memory cell after the preprocessing being used for screening of data retention performance; reading the first analog electrical parameter of the flash memory cell after the preprocessing; interfering with the flash memory chip; reading a second analog electrical parameter of the flash memory cell after the interference; judging a difference between the first analog electrical parameter and the second analog electrical parameter, and if the difference meets a preset variation range, the data retention performance of the flash memory cell is qualified, wherein the flash memory chip works in a sub-threshold region.

2. The method for screening the data retention performance of flash memory chips according to claim 1, characterized in that, The preprocessing further comprises: obtaining a sub-threshold region of the flash memory cell, wherein the sub-threshold region represents a voltage range of a working region of the flash memory chip; matching a write voltage in the sub-threshold region according to the first analog electrical parameter; performing analog flash programming on the flash memory cell according to the write voltage, and writing the analog value into the flash memory cell.

3. The method of claim 1, wherein the step of determining the data retention performance of the flash memory chip comprises the steps of: applying a first voltage to the flash memory chip; and determining the data retention performance of the flash memory chip based on the first voltage. The preprocessing further comprises: erasing stored data of the flash memory cell.

4. The method for screening the data retention performance of flash memory chips according to claim 3, characterized in that, After erasing the stored data of the flash memory cell, the method further comprises: determining a detection analog electrical parameter interval of the flash memory cell; detecting the flash memory cell according to the detection analog electrical parameter interval, and if an analog parameter of the flash memory cell is within the analog electrical parameter interval, the flash memory cell is erased normally.

5. The method of claim 1, wherein the step of determining the data retention performance of the flash memory chip comprises the steps of: applying a first voltage to the flash memory chip; and determining the data retention performance of the flash memory chip based on the first voltage. The reading of the second analog electrical parameter of the flash memory cell after the interference comprises: applying a read voltage to the flash memory cell, and reading the second analog electrical parameter stored in the flash memory cell.

6. The method of claim 1, wherein the step of determining the data retention performance of the flash memory chip comprises the steps of: applying a first voltage to the flash memory chip; and determining the data retention performance of the flash memory chip based on the first voltage. The interference with the flash memory chip comprises baking the flash memory chip.

7. A screening device for the data retention performance of a flash memory chip, characterized in that, The method comprises: a preprocessing module configured to preprocess a flash memory cell of the flash memory chip, the preprocessing comprising storing an analog value in the flash memory cell by analog programming, a first analog electrical parameter of the flash memory cell after the preprocessing being used for screening of data retention performance; a first reading module configured to read the first analog electrical parameter of the flash memory cell after the preprocessing; an interference module configured to interfere with the flash memory chip; the first reading module is further configured to read a second analog electrical parameter of the flash memory cell after the interference; a judging module configured to judge a difference between the first analog electrical parameter and the second analog electrical parameter, and if the difference meets a preset variation range, the data retention performance of the flash memory cell is qualified, wherein the flash memory chip works in a sub-threshold region.

8. The screening apparatus for data retention performance of a flash memory chip according to claim 7, wherein The preprocessing module comprises: an obtaining unit configured to obtain a sub-threshold region of the flash memory cell, wherein the sub-threshold region represents a voltage range of a working region of the flash memory chip; a matching unit configured to match a write voltage in the sub-threshold region according to the first analog electrical parameter; a programming unit configured to perform analog flash programming on the flash memory cell according to the write voltage, and write the analog value into the flash memory cell.

9. The screening apparatus for data retention performance of a flash memory chip according to claim 7, wherein, The preprocessing module comprises: an erasing unit configured to erase the flash memory cell.

10. An electronic device, comprising: The electronic device comprises: at least one processor; and A memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform a screening method for the data retention performance of a flash memory chip according to any one of claims 1-6.

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