A manufacturing method and processing system for a multi-layer circuit board

Abstract

The present application discloses a manufacturing method and a processing system for a multi-layer circuit board. The manufacturing method of the multi-layer circuit board includes: preparing a sub-board; setting at least two detection marks in the edge area of the sub-board; obtaining the initial positions of at least two detection marks, and obtaining the actual positions of at least two detection marks after performing a preset processing on the sub-board, and obtaining the expansion and contraction rate of the sub-board according to the initial positions and the actual positions; selecting at least two sub-boards with matching expansion and contraction rates for lamination and fixation. Through the above solution, the qualification rate of the multi-layer board formed after lamination can be improved.

Description

Technical Field

[0001] This application belongs to the technical field of printed circuit boards, and particularly relates to a manufacturing method and processing system for multi-layer circuit boards. Background Art

[0002] In existing PCB circuit boards, they can usually be formed by stacking at least two sub-boards, and each sub-board can include a sub-board and a conductive circuit layer provided on the surface of the sub-board.

[0003] When manufacturing multi-layer PCB circuit boards, it is usually necessary to etch the surface of the inner-layer sub-boards to form a preset pattern, and then laminate multiple sub-boards to form the multi-layer PCB circuit board.

[0004] However, during the process of etching the surface of the sub-boards, it usually causes the overall size of the sub-boards to expand and contract, resulting in a change in the shape of the sub-boards. Therefore, during subsequent lamination of multiple sub-boards, the alignment accuracy between multiple sub-boards may be reduced, and there may even be problems with the unqualified multi-layer PCB circuit board formed after lamination. Summary of the Invention

[0005] This application provides a manufacturing method and processing system for multi-layer circuit boards to solve the above technical problems.

[0006] To solve the above technical problems, a technical solution adopted by this application is: to provide a manufacturing method for multi-layer circuit boards, the manufacturing method for multi-layer circuit boards includes:

[0007] Prepare sub-boards;

[0008] Set at least two detection marks in the edge area of the sub-board;

[0009] Obtain the initial positions of the at least two detection marks, and obtain the actual positions of the at least two detection marks after performing a preset processing on the sub-board, and obtain the expansion and contraction rate of the sub-board according to the initial position and the actual position;

[0010] Select at least two of the sub-boards with matching expansion and contraction rates for lamination and fixation.

[0011] Optionally, the step of obtaining the initial positions of the at least two detection marks, and obtaining the actual positions of the at least two detection marks after performing a preset processing on the sub-board, and obtaining the expansion and contraction rate of the sub-board according to the initial position and the actual position, includes:

[0012] Detect the initial positions of the two detection marks to obtain a first distance between the two detection marks when they are in the initial positions;

[0013] After performing a preset processing on the daughter board, the positions of the actual positions of the two detection marks are further detected to obtain a second distance between the two detection marks;

[0014] According to the difference between the first distance and the second distance and the ratio of the first distance, a shrinkage rate of the daughter board in the direction of the line connecting the two detection marks is obtained, where the direction of the line connecting the two detection marks is the shrinkage direction of the daughter board.

[0015] Optionally, the step of selecting at least two of the daughter boards with matching shrinkage rates for lamination fixing includes:

[0016] Select at least two of the daughter boards with a difference in shrinkage rate within a preset range in at least one shrinkage direction for lamination fixing.

[0017] Optionally, the method for manufacturing the multi-layer circuit board further includes:

[0018] Detect the shrinkage rate of the daughter board in the direction of the line connecting any two of the detection marks on the daughter board;

[0019] Obtain the shrinkage rates of the daughter board in at least two shrinkage directions.

[0020] Optionally, the step of selecting at least two of the daughter boards with matching shrinkage rates for lamination fixing includes:

[0021] Select at least two of the daughter boards, where the difference in the shrinkage rate of at least two of the daughter boards in the first shrinkage direction is within a preset range, and the difference in the shrinkage rate of at least two of the daughter boards in the second shrinkage direction is within a preset range; wherein, the first shrinkage direction is not parallel to the second shrinkage direction;

[0022] Laminating and fixing at least two of the daughter boards.

[0023] Optionally, after the step of obtaining the shrinkage rate of the daughter board and before the step of selecting at least two of the daughter boards with matching shrinkage rates for lamination fixing, it further includes:

[0024] Set an information identification code on the daughter board;

[0025] Associate and correspond the shrinkage rate of the daughter board with the information identification code.

[0026] Optionally, when all the detection marks arranged in the edge area of the daughter board are located at the initial positions, the lines connecting all the detection marks form a preset shape;

[0027] The method for manufacturing the multi-layer circuit board further includes:

[0028] Before the step of laminating and fixing at least two of the sub-boards with matching expansion and contraction rates, detect whether the deviation between the actual shape formed by sequentially connecting all the detection marks and the preset shape is within the preset range;

[0029] If not, determine that the sub-board is unqualified.

[0030] Optionally, the detection mark includes a QR code, and the QR code is formed in the edge area of the sub-board by inkjet printing or laser engraving;

[0031] After the step of obtaining the expansion and contraction rate of the sub-board and before the step of selecting at least two of the sub-boards with matching expansion and contraction rates for laminating and fixing, it further includes:

[0032] Associate and correspond the expansion and contraction rate of the sub-board with the detection mark.

[0033] Optionally, the sub-board includes a substrate and a conductive layer provided on at least one surface of the substrate;

[0034] The preset processing of the sub-board includes:

[0035] Perform patterning on the conductive layer so that the conductive layer forms multiple conductive lines constituting a preset pattern.

[0036] To solve the above technical problems, a technical solution adopted by the present application is: provide a processing system for a multi-layer circuit board, and the processing system includes:

[0037] A detection device for detecting a sub-board and obtaining the expansion and contraction rate of the sub-board according to the initial positions of at least two detection marks and the positions of the at least two detection marks after preset processing of the sub-board;

[0038] A lamination device for selecting at least two of the sub-boards with matching expansion and contraction rates for laminating and fixing.

[0039] The beneficial effect of the present application is: in the above solution of the present application, multiple detection marks are provided at the edge of the sub-board, and the expansion and contraction rates of multiple sub-boards are obtained by detecting the initial positions of the detection marks and the actual positions after preset processing, and at least two sub-boards with matching expansion and contraction rates are selected for laminating and fixing during lamination, so that the sub-boards of each layer of the formed multi-layer circuit board can be accurately aligned, and the problem of low alignment accuracy of the multi-layer circuit board or even unqualified multi-layer circuit board caused by different expansion and contraction rates of different sub-boards can be avoided. Description of the Drawings

[0040] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, where:

[0041] Figure 1 is a schematic flowchart of an embodiment of a method for manufacturing a multi-layer circuit board provided by the present application;

[0042] Figure 2 is a schematic structural diagram of a daughter board provided by the present application. Detailed implementation manners

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0044] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) in the embodiments of the present application, the directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly.

[0045] In addition, if there are descriptions such as "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0046] Please refer to Figure 1 , Figure 1 is a schematic flowchart of an embodiment of a method for manufacturing a multi-layer circuit board provided by the present application.

[0047] The method for manufacturing a multi-layer circuit board specifically includes the following steps.

[0048] S110: Prepare the daughter board.

[0049] In this step, the daughter board may include a substrate and a conductive layer. Among them, the number of conductive layers may be one, and one conductive layer is disposed on one side surface of the substrate; or the number of conductive layers may be two, and the two conductive layers are respectively disposed on the opposite side surfaces of the substrate.

[0050] Among them, the substrate can be made of an insulating material. For example, the substrate can be made of a resin material. Or it can also be made by impregnating a reinforcing material with a resin adhesive and through processes such as drying, cutting, and laminating, so as to improve the strength of the substrate.

[0051] The conductive layer can be formed by fixing a conductive material to the surface of the substrate. Among them, the conductive material can include but is not limited to materials such as copper, aluminum, iron, nickel, gold, silver, platinum group, chromium, magnesium, tungsten, molybdenum, lead, tin, indium, zinc or their alloys.

[0052] S120: Set at least two detection marks in the edge area of the daughter board.

[0053] In this step, at least two detection marks can be set in the edge area of the daughter board for subsequent detection.

[0054] Taking one of the daughter boards as an example. Among them, the detection mark can be a hole opened on the substrate, or it can also be a protrusion provided on the substrate; or the detection mark can also be an identification code provided on the surface of the substrate. For example, it can be a two-dimensional code. When the detection mark is an identification code, the identification code can include information such as the file number, batch number, serial number, production date of the daughter board, and the layer number where the daughter board is located during subsequent lamination work hours.

[0055] In this embodiment, at least two detection marks can be set in the edge area of the daughter board. And the two detection marks can be respectively set at the corner positions of the daughter board.

[0056] Specifically, the overall shape of the daughter board can be rectangular or square.

[0057] Among them, the number of detection marks can be two; when the number of detection marks is two, the two detection marks can be set at the two diagonal positions of the daughter board. At this time, the two detection marks on different daughter boards are both set at the corresponding same positions of the daughter board.

[0058] Among them, the number of detection marks can also be three; and the three detection marks can be respectively set at the three corners of the daughter board. Similarly, the three detection marks on different daughter boards are both set at the corresponding same positions of the daughter board.

[0059] Or, the number of detection marks can also be four; and the four detection marks can be respectively set at the four corners of the daughter board. Similarly, the four detection marks on different daughter boards are both set at the corresponding same positions of the daughter board.

[0060] S130: Obtain the initial positions of at least two detection marks, and obtain the actual positions of at least two detection marks after performing a preset processing on the daughter board, and obtain the expansion and contraction rate of the daughter board according to the initial positions and the actual positions.

[0061] In this step, after completing the step of setting at least two detection marks in the edge area of the daughter board, the initial position of each detection mark for detection can also be obtained according to the set coordinates of each detection mark. At this time, the set coordinates of each detection mark can be the respective corresponding initial positions (that is, each detection mark has an initial position).

[0062] However, since there may be dimensional deviations when setting detection marks on the edge of the daughter board, which may lead to inaccurate expansion and contraction rates obtained subsequently, therefore, the initial position of each detection mark can be detected to obtain the actual coordinates of each detection mark at its initial position.

[0063] Specifically, each detection mark on the edge of the daughter board can be obtained through an image detection device, and the actual coordinates of the initial position of each detection mark can be confirmed. And according to the actual coordinates of each detection mark at the initial position, the initial distance between any two detection marks and the connection direction of the two detection marks can be obtained.

[0064] In other embodiments, the actual coordinates of each detection mark may not be confirmed; specifically, an image detection device can be used to obtain the distribution image of each detection mark on the edge of the daughter board, and then the initial distance between any two detection marks and the connection direction of the two detection marks can be identified according to the distribution image.

[0065] Similarly, after performing a preset processing on the daughter board. And before laminating multiple daughter boards, the same method as above for obtaining the initial position can also be used to further detect the detection marks on the daughter board, so that the actual position of each detection mark after the preset processing can be obtained.

[0066] When the initial position and the actual position after processing of each detection mark are obtained, the expansion and contraction rate of the daughter board can be calculated and obtained according to the initial position and the actual position.

[0067] Among them, the expansion and contraction rate of the daughter board can be calculated and obtained through the initial positions and the actual positions of at least two detection marks.

[0068] For example, the distance between the initial positions of two detection marks is the first distance H, and the distance between the actual positions of the two detection marks after a preset processing of the daughter board is the second distance L. At this time, the shrinkage rate corresponding to the two detection marks is (L - H) / H, and the connection direction between the two detection marks represents the shrinkage direction corresponding to the shrinkage rate. If the connection direction between the two detection marks is the first direction, it means that the shrinkage rate of the daughter board in the first direction is (L - H) / H.

[0069] In this embodiment, the shrinkage rates corresponding to different two detection marks can be detected, so that the shrinkage rates of the daughter board in multiple directions can be obtained.

[0070] In this embodiment, the preset processing may refer to patterning the conductive layer on the surface of the daughter board, so that the conductive layer can form a conductive line layer with specific multiple conductive lines. Among them, the multiple conductive lines in the conductive line layer can form a preset pattern.

[0071] S140: Select at least two daughter boards with matching shrinkage rates for lamination and fixation.

[0072] In the above step S130, the shrinkage rates of multiple daughter boards can be detected.

[0073] And when it is necessary to laminate to form a multi-layer circuit board, at least two daughter boards with matching shrinkage rates can be selected for lamination and fixation.

[0074] Among them, the so-called matching shrinkage rates here can be expressed as laminating and fixing daughter boards with equal shrinkage rates or the difference in shrinkage rates within a preset range.

[0075] Specifically, equal shrinkage rates mean that the shrinkage rate values are equal in at least one shrinkage direction; or the shrinkage rate values are equal in multiple shrinkage directions.

[0076] Similarly, the difference in shrinkage rates within a preset range (the preset range can be set as needed, for example, it can be set within 0.5% or within 1%, etc.) means that the difference in shrinkage rate values is within the preset range in at least one shrinkage direction, or the difference in shrinkage rates can also be within the preset range in multiple shrinkage directions.

[0077] Therefore, the solution of the present application is to set a plurality of detection marks at the edge of the daughter board, and detect the actual position after preset processing through the initial position of the detection mark, so as to obtain the shrinkage rates of a plurality of daughter boards, and select at least two daughter boards with matching shrinkage rates for lamination and fixation during lamination, so that the daughter boards of each layer of the formed multi-layer circuit board can be accurately aligned, and the problem of low alignment accuracy of the multi-layer circuit board or even unqualified multi-layer circuit board caused by different shrinkage rates of different daughter boards can be avoided.

[0078] Further, optionally, please refer to Figure 2 . Figure 2 FIG. is a schematic structural diagram of a daughter board provided by the present application.

[0079] In this embodiment, a detection mark 101 can be set at each of the four corner positions of each daughter board 10, that is, 4 detection marks 101 can be set on each daughter board 10. Among them, the connection line of two detection marks 101 in two adjacent corners can be parallel to the side wall of the daughter board 10 connected by these two corners. In this solution, the outer contour formed by the sequential connection of the 4 detection marks 101 can match the outer contour of the daughter board 10.

[0080] Among them, the connection line of two detection marks 101 in two corners connecting the long side of the daughter board 10 can be set as the first shrinkage direction A, and the first shrinkage direction A is parallel to the long side of the daughter board 10; the connection line of two detection marks 101 in two corners connecting the short side of the daughter board 10 can be set as the second shrinkage direction B, and the second shrinkage direction B is parallel to the short side of the daughter board 10.

[0081] In a more preferred embodiment of this embodiment, at least two daughter boards 10 with equal shrinkage rates or differences within a preset range in the first shrinkage direction A and equal shrinkage rates or differences within a preset range in the second shrinkage direction B can be selected for lamination and fixation.

[0082] Further, for the daughter board 10, since the preset patterns corresponding to the conductive lines provided thereon can be set differently, the shrinkage rates of the daughter board 10 in its different shrinkage directions may be different. Therefore, after the preset processing of the daughter board 10, the daughter board 10 may be deformed.

[0083] In this embodiment, it is also possible to judge whether the daughter board 10 is qualified after preset processing by detecting the detection mark 101 on the daughter board 10.

[0084] Specifically, taking the example of setting four detection marks 101 at the four corners of the daughter board 10.

[0085] For a conventional daughter board 10, its outer shape is usually rectangular or square.

[0086] Among them, the connection line of two detection marks 101 at two corners connecting the long side of the daughter board 10 can be set as the first expansion and contraction direction A, and the first expansion and contraction direction A is parallel to the long side of the daughter board 10; the connection line of two detection marks 101 at two corners connecting the short side of the daughter board 10 can be set as the second expansion and contraction direction B, and the second expansion and contraction direction B is parallel to the short side of the daughter board 10. Moreover, the first expansion and contraction direction A is perpendicular to the second expansion and contraction direction B.

[0087] Among them, the connection lines of the four detection marks 101 can form a rectangle or a square that matches the outer contour of the daughter board 10. At this time, the shape formed by the connection lines of the four detection marks 101 is the preset shape in the initial position.

[0088] Therefore, after performing preset processing on the daughter board 10, the actual shape formed by the connection lines of the corresponding four detection marks 101 on the daughter board 10 can be detected.

[0089] At this time, it can be detected whether the difference between the actual shape and the preset shape is within the preset range; if not, it is determined that the daughter board 10 is unqualified, and the daughter board 10 cannot be subjected to subsequent lamination processing; if so, it is determined that the daughter board 10 is qualified, and the daughter board 10 can be subjected to subsequent lamination processing.

[0090] Among them, to detect whether the difference between the actual shape and the preset shape is within the preset range, it can be judged by detecting whether the connection line of two detection marks 101 corresponding to the long side of the daughter board 10 and the connection line of two detection marks 101 corresponding to the short side of the daughter board 10 are perpendicular.

[0091] If the connection line of two detection marks 101 corresponding to the long side of the daughter board 10 and the connection line of two detection marks 101 corresponding to the short side of the daughter board 10 are perpendicular; it can be judged that the daughter board 10 is qualified.

[0092] If the included angle between the connection line of two detection marks 101 corresponding to the long side of the daughter board 10 and the connection line of two detection marks 101 corresponding to the short side of the daughter board 10 is within the preset range (for example, 88° - 92°, etc.); it can also be judged that the daughter board 10 is qualified.

[0093] If the included angle between the connection line of two detection marks 101 corresponding to the long side of the daughter board 10 and the connection line of two detection marks 101 corresponding to the short side of the daughter board 10 exceeds the preset range; it is judged that the daughter board 10 is unqualified.

[0094] Alternatively, in other embodiments, it is also possible to perform an overall comparison between the preset shape formed by all the detection marks 101 of the daughter board 10 at the initial position and the actual shape formed by all the detection marks 101 after the preset processing of the daughter board 10. When the overall deviation is within the preset range, it can be determined that the daughter board 10 is qualified; otherwise, it is unqualified.

[0095] Further, in an alternative embodiment, the detection mark 101 can be an information identification code such as a QR code. When the daughter board 10 is detected to obtain its expansion and contraction rate, the expansion and contraction rate can be associated with the detection mark 101. That is, the detection mark 101 is identified by an identification device, so that the expansion and contraction rate (including the value of the expansion and contraction rate and its expansion and contraction direction) associated with the daughter board 10 can be extracted.

[0096] Or in other embodiments, other information identification codes different from the detection mark 101 can also be reset on the daughter board 10, and the expansion and contraction rate of the daughter board 10 is associated with the other information identification code.

[0097] Further, the present application also provides a processing system for a multi-layer circuit board. Among them, the processing system can be used to implement the manufacturing method of the multi-layer circuit board as described above.

[0098] Among them, the processing system can include a detection device and a lamination device. The detection device can be used to detect each daughter board, and based on the initial positions of at least two detection marks on the daughter board and the positions of at least two detection marks after the preset processing of the daughter board, the expansion and contraction rate of the daughter board can be obtained. The lamination device can then select at least two daughter boards with matching expansion and contraction rates for lamination and fixation to form a multi-layer circuit board.

[0099] Among them, the lamination device can further include an identification device, a control device, and a lamination mechanism. The identification can identify the information identification mark on the daughter board (specifically refer to the above), so as to obtain the expansion and contraction rate of the daughter board. The control device can select daughter boards with matching expansion and contraction rates, and the control device can control the lamination mechanism to laminate and fix at least two daughter boards with matching expansion and contraction rates.

[0100] In summary, the solution of the present application uses multiple detection marks are arranged on the edge of the daughter board, and the actual positions of the detection marks after the preset processing are detected through the initial positions of the detection marks, so as to obtain the expansion and contraction rates of multiple daughter boards. When laminating, at least two daughter boards with matching expansion and contraction rates are selected for lamination and fixation, so that the daughter boards of each layer of the formed multi-layer circuit board can be accurately aligned, and the problem of low alignment accuracy of the multi-layer circuit board or even unqualified multi-layer circuit board caused by different expansion and contraction rates of different daughter boards can be avoided.

[0101] The above are only the embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be similarly included in the patent protection scope of the present application.

Claims

1. A manufacturing method of a multilayer circuit board, characterized in that, The manufacturing method of the multi-layer circuit board includes: Preparing a daughter board; Setting at least two detection marks in the edge area of the daughter board; the detection marks include two-dimensional codes, and the two-dimensional codes are formed in the edge area of the daughter board by inkjet printing or laser engraving; Obtaining the initial positions of the at least two detection marks, wherein the initial positions of each detection mark are detected to obtain the actual coordinates of each detection mark at its initial position; And obtaining the actual positions of the at least two detection marks after the preset processing of the daughter board, and obtaining the expansion and contraction rate of the daughter board according to the actual coordinates of the initial positions and the actual positions; the preset processing includes patterning the conductive layer on the surface of the daughter board; Associating and corresponding the expansion and contraction rate of the daughter board with the detection marks; Selecting at least two of the daughter boards with matching expansion and contraction rates for lamination and fixation.

2. The manufacturing method of the multilayer circuit board according to claim 1, characterized in that The steps of obtaining the initial positions of the at least two detection marks, and obtaining the actual positions of the at least two detection marks after the preset processing of the daughter board, and obtaining the expansion and contraction rate of the daughter board according to the actual coordinates of the initial positions and the actual positions include: Detecting the initial positions of the two detection marks to obtain the first distance between the two detection marks when they are at the initial positions; After the preset processing of the daughter board, further detecting the actual positions of the two detection marks to obtain the second distance between the two detection marks; Obtaining the expansion and contraction rate of the daughter board in the direction of the connection line of the two detection marks according to the difference between the first distance and the second distance and the ratio of the first distance, wherein the direction of the connection line of the two detection marks is the expansion and contraction direction of the daughter board.

3. The manufacturing method of the multi-layer circuit board according to claim 2, characterized in that The steps of selecting at least two of the daughter boards with matching expansion and contraction rates for lamination and fixation include: Selecting at least two of the daughter boards with the difference in the expansion and contraction rate in at least one expansion and contraction direction within a preset range for lamination and fixation.

4. The manufacturing method of the multilayer circuit board according to claim 2, characterized in that, The manufacturing method of the multi-layer circuit board further includes: Detecting the expansion and contraction rate in the direction of the connection line of any two detection marks on the daughter board; Obtaining the expansion and contraction rates of the daughter board in at least two expansion and contraction directions.

5. The manufacturing method of the multilayer circuit board according to claim 4, characterized in that, The steps of selecting at least two of the daughter boards with matching expansion and contraction rates for lamination and fixation include: Selecting at least two of the daughter boards, wherein the differences in the expansion and contraction rates of the at least two daughter boards in the first expansion and contraction direction A are all within a preset range, and the differences in the expansion and contraction rates of the at least two daughter boards in the second expansion and contraction direction B are all within a preset range; wherein, the first expansion and contraction direction A is not parallel to the second expansion and contraction direction B; Laminating and fixing at least two of the daughter boards.

6. The manufacturing method of the multilayer circuit board according to any one of claims 1-5, characterized in that, After the step of obtaining the expansion and contraction rate of the daughter board, and before the step of selecting at least two of the daughter boards with matching expansion and contraction rates for lamination and fixation, it further includes: Setting an information identification code on the daughter board; Associating and corresponding the expansion and contraction rate of the daughter board with the information identification code.

7. According to the manufacturing method of the multi-layer circuit board according to claim 1, characterized in that, When all the detection marks provided in the edge area of the daughter board are located at the initial positions, the connection lines of all the detection marks form a preset shape; The method for manufacturing the multi-layer circuit board further includes: Before the step of laminating and fixing at least two of the daughter boards with matching expansion and contraction rates, detecting whether the deviation between the actual shape formed by the sequential connection lines of all the detection marks and the preset shape is within a preset range; If not, it is determined that the daughter board is unqualified.

8. The manufacturing method of the multilayer circuit board according to claim 1, characterized in that, The daughter board includes a substrate and a conductive layer provided on at least one surface of the substrate; The preset processing of the daughter board includes: Performing a patterning process on the conductive layer so that the conductive layer forms a plurality of conductive lines constituting a preset pattern.

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