A method and device for controlling queuing delay of DPDK packet processing

Abstract

The application discloses a kind of DPDK data packet processing queuing delay control method and device, method includes: polling the receiving queue of network card, and according to the current quantity of DPDK data packet in receiving queue determines the state of receiving queue;If the state of receiving queue is idle state, then cyclically execute PAUSE instruction, and obtain time slice, when time slice is not used up, the current quantity of DPDK data packet in receiving queue is reacquired;If current quantity exceeds preset threshold, then the state of receiving queue is switched from idle state to busy state, and DPDK data packet is handled.The application can control receiving queue to switch between idle state and busy state, avoid packet queuing delay too long in acceptance queue, and, the application uses PAUSE instruction instead of by adjusting CPU frequency to reduce the power consumption of CPU, the whole process does not introduce interruption, effectively reach the purpose of reducing overall power consumption and improving energy efficiency.

Description

Technical Field

[0001] This invention relates to the field of data packet processing technology, and in particular to a queuing delay control method and apparatus for DPDK data packet processing. Background Technology

[0002] With the booming development of big data and cloud computing, the demand for network bandwidth in data centers and other fields is increasing daily. This demand is forcing modern network interface cards (NICs) to gradually move towards 40Gbps, 100Gbps, and even 200Gbps. Traditional packet sending and receiving methods use hardware interrupts, and packet processing occurs in the device kernel. After processing, the packet needs to be copied from the kernel buffer to the user space buffer. The huge overhead of interrupt mode and device calls makes it difficult for traditional packet sending and receiving methods to fully utilize the high-speed performance of modern NICs.

[0003] Based on this, engineers developed a data plane development kit, DPDK (Data Plane Development Kit), to provide high-performance network packet processing support. To leverage the performance of these high-speed network cards, DPDK bypasses the kernel network protocol stack and uses a polling mechanism instead of hard interrupts to continuously poll the network card's receive queue directly in user space. While using polling instead of interrupts significantly improves CPU packet processing capabilities, the trade-off is that CPU utilization for packet processing remains at 100%. Although this cost is negligible compared to the huge performance improvement when the network is busy, when the network is idle (i.e., when there are no DPDK packets in the network card's receive queue), the DPDK packet processing thread will still continuously poll the empty receive queue, wasting CPU computing resources and energy.

[0004] Therefore, existing technologies still need to be improved and enhanced. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a queuing delay control method and apparatus for DPDK data packet processing, which addresses the above-mentioned deficiencies of the prior art. The aim is to solve the problem that the use of polling mechanism instead of interrupt mechanism to process DPDK data packets in the prior art easily leads to the waste of CPU computing resources and energy.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] In a first aspect, the present invention provides a queuing delay control method for DPDK packet processing, wherein the method includes:

[0008] Poll the network card's receive queue and determine the state of the DPDK packet processing thread based on the current number of DPDK packets in the receive queue;

[0009] If the DPDK packet processing thread is in an idle state, the PAUSE instruction is executed repeatedly and a time slice is acquired. If the time slice is not used up, the current number of DPDK packets in the receive queue is acquired again. The time slice is used to reflect the total number of clock cycles spent in the idle state.

[0010] If the current number of DPDK data packets in the receiving queue exceeds a preset threshold, the state of the DPDK data packet processing thread is switched from the idle state to the busy state, and the DPDK data packets are processed based on the DPDK data packet processing thread.

[0011] In one implementation, determining the state of the DPDK packet processing thread based on the current number of DPDK packets in the receive queue includes:

[0012] If the current number of DPDK packets in the receive queue is empty, then the state of the DPDK packet processing thread is determined to be idle.

[0013] If the current number of DPDK data packets in the receive queue is not empty, the state of the DPDK data packet processing thread is determined to be busy, and the DPDK data packets are processed based on the DPDK data packet processing thread.

[0014] In one implementation, the method further includes:

[0015] If the time slice is used up, the steps of polling the network card's receive queue and determining the state of the DPDK packet processing thread based on the current number of DPDK packets in the receive queue are re-executed.

[0016] In one implementation, the method further includes:

[0017] If the state of the DPDK packet processing thread switches from the idle state to the busy state, the time slice is reduced.

[0018] In one implementation, the method further includes:

[0019] If the current number of DPDK data packets in the receiving queue is less than or equal to the preset threshold, then the queuing delay of the DPDK data packets is obtained;

[0020] The state of the DPDK packet processing thread is switched based on the queuing delay.

[0021] In one implementation, switching the state of the DPDK packet processing thread based on the queuing delay includes:

[0022] The queuing delay is compared with a preset maximum allowable delay time;

[0023] If the queuing delay is greater than the maximum allowed delay time, the state of the DPDK packet processing thread is switched to the busy state.

[0024] If the queuing delay is less than or equal to the maximum allowed delay time, the state of the DPDK packet processing thread is switched to the idle state.

[0025] In one implementation, switching the state of the DPDK packet processing thread based on the queuing delay further includes:

[0026] If the DPDK packet processing thread switches to an idle state, the time slice is increased.

[0027] In one implementation, the receiving queue corresponds one-to-one with the DPDK packet processing thread, and the DPDK packet processing thread is bound to a CPU core.

[0028] Secondly, embodiments of the present invention also provide a queuing delay control device for DPDK packet processing, wherein the device includes:

[0029] The thread state determination module is used to poll the network card's receive queue and determine the state of the DPDK packet processing thread based on the current number of DPDK packets in the receive queue.

[0030] The data packet quantity determination module is used to repeatedly execute the PAUSE instruction and acquire a time slice if the DPDK data packet processing thread is in an idle state. If the time slice is not used up, the module reacquires the current number of DPDK data packets in the receiving queue. The time slice is used to reflect the total number of clock cycles spent in the idle state.

[0031] The thread state switching module is used to switch the state of the DPDK data packet processing thread from the idle state to the busy state if the current number of DPDK data packets in the receiving queue exceeds a preset threshold, and to process the DPDK data packets based on the DPDK data packet processing thread.

[0032] In one implementation, the thread state determination module includes:

[0033] The idle state determination unit is used to determine that the state of the DPDK data packet processing thread is idle if the current number of DPDK data packets in the receive queue is empty.

[0034] The busy state determination unit is used to determine that the state of the DPDK data packet processing thread is busy if the current number of DPDK data packets in the receiving queue is not empty, and to process the DPDK data packets based on the DPDK data packet processing thread.

[0035] In one implementation, the receiving queue corresponds one-to-one with the DPDK packet processing thread, and the DPDK packet processing thread is bound to a CPU core.

[0036] Thirdly, embodiments of the present invention also provide a terminal device, the terminal device including a memory, a processor, and a queuing delay control program for DPDK packet processing stored in the memory and executable on the processor. When the processor executes the queuing delay control program for DPDK packet processing, it implements the steps of the queuing delay control method for DPDK packet processing as described in any of the above schemes.

[0037] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing a queuing delay control program for DPDK packet processing. When the queuing delay control program for DPDK packet processing is executed by a processor, it implements the steps of the queuing delay control method for DPDK packet processing as described in any of the above schemes.

[0038] Beneficial Effects: Compared with existing technologies, this invention provides a queuing delay control method for DPDK packet processing. First, this invention polls the network interface card's (NIC) receive queue and determines the state of the DPDK packet processing thread based on the current number of DPDK packets in the receive queue. Then, if the DPDK packet processing thread is in an idle state, it repeatedly executes the PAUSE instruction and acquires a time slice. If the time slice is not used up, it reacquires the current number of DPDK packets in the receive queue. The time slice reflects the total number of clock cycles spent in the idle state. Finally, if the current number of DPDK packets in the receive queue exceeds a preset threshold, the state of the DPDK packet processing thread is switched from the idle state to the busy state, and the DPDK packets are processed based on the DPDK packet processing thread. This invention can control the receiving queue to switch between idle and busy states, avoiding excessive queuing delays for data packets in the receiving queue, thereby ensuring that the queuing delay of each data packet is controllable. Furthermore, in the idle state, this invention uses the PAUSE instruction instead of adjusting the CPU frequency to reduce CPU power consumption. The entire process does not introduce interrupts, and the cost of switching between states is very small, effectively achieving the goal of reducing overall power consumption and improving energy efficiency. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the DPDK data packet processing procedure.

[0040] Figure 2 A flowchart illustrating a specific implementation of the queuing delay control method for DPDK packet processing provided in this embodiment of the invention.

[0041] Figure 3 This is a flowchart illustrating a specific application of the DPDK packet processing queuing delay control method provided in this embodiment of the invention.

[0042] Figure 4 This is a schematic diagram of the queuing delay control device for DPDK packet processing provided in an embodiment of the present invention.

[0043] Figure 5 A schematic diagram of a terminal device provided in an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0045] This embodiment first describes the processing procedure of DPDK data packets, such as... Figure 1As shown, when the network card receives a network data packet, it automatically fills the Rx Ring (the specific implementation of the network card's receive queue) queue via DMA (Direct Memory Access). If the Rx Ring queue is full, the network card will discard the network data packet. The network card driver polls the Rx Ring frequently. When the Rx Ring is empty, an empty poll will occur. When there is a data packet in the Rx Ring, the network card driver will attempt to retrieve the data packet from the Rx Ring to fill the batch for data packet processing.

[0046] Currently, the commonly used power management technology DVFS (Dynamic Voltage and Frequency Scaling) dynamically adjusts the CPU frequency and voltage based on CPU utilization to regulate CPU power consumption. However, DVFS requires CPU utilization as input. During DPDK packet processing, regardless of network activity, CPU utilization is always maintained at 100%. Therefore, the actual CPU utilization needs to be estimated in user space and passed to the kernel. This necessitates a kernel trap and interrupt trigger, which negatively impacts packet latency and processing performance. This is because the CPU's transition from low to high frequency is not immediate but a gradual process. This can cause packets in the receive queue to not be processed promptly during this period, ultimately leading to higher packet latency or packet loss due to a full receive queue. Furthermore, in high-performance packet processing environments, high-precision clocks may be frequently used. Traditional high-precision clocks are based on HPET (High Precision Event Timer). Obtaining the clock value requires a system call, which wastes a significant number of CPU cycles on clock acquisition, increasing the number of CPU cycles required to process a single packet. Therefore, in high-performance packet capture environments, a cheaper clock implementation—the rdtsc instruction—is often used. However, clocks based on the rdtsc instruction need to ensure the stability of the CPU frequency.

[0047] Another proposed strategy to improve energy efficiency is to proactively relinquish CPU usage and enter a sleep state when the network is idle. However, this strategy has several drawbacks: 1) The switching overhead between sleep and working states is significant, requiring interrupts and kernel traps, resulting in poor performance on network links above 10GbE. 2) When the DPDK packet processing thread enters a sleep state, other threads may preempt the current CPU, causing cache loss when the DPDK packet processing thread resumes from sleep. 3) High-granularity control of sleep duration is difficult to achieve.

[0048] The two energy efficiency improvement strategies mentioned above both introduce interrupts during packet processing to improve energy efficiency, sacrificing some performance, and do not utilize the metadata information of the network interface card's (NIC) receive queue to control the maximum latency of each packet. Therefore, this embodiment provides a queuing latency control method for DPDK packet processing. Specifically, this embodiment first polls the NIC's receive queue and determines the state of the DPDK packet processing thread based on the current number of DPDK packets in the receive queue. Then, if the DPDK packet processing thread is in an idle state, it repeatedly executes the PAUSE instruction and acquires a time slice. If the time slice is not used up, it reacquires the current number of DPDK packets in the receive queue. The time slice reflects the total number of clock cycles spent in the idle state. Finally, if the current number of DPDK packets in the receive queue exceeds a preset threshold, the state of the DPDK packet processing thread is switched from the idle state to the busy state, and the DPDK packets are processed based on the DPDK packet processing thread. This embodiment can control the receiving queue to switch between idle and busy states, avoiding excessive queuing delays for data packets in the receiving queue, thereby ensuring that the queuing delay of each data packet is controllable. Furthermore, in the idle state, this embodiment uses the PAUSE instruction instead of adjusting the CPU frequency to reduce CPU power consumption. The entire process does not introduce interrupts, and the cost of switching between states is very small, effectively achieving the goal of reducing overall power consumption and improving energy efficiency.

[0049] Exemplary methods

[0050] The queuing delay control method for DPDK packet processing in this embodiment can be applied to terminal devices, such as computers, tablets, and other intelligent terminal products. Specifically, as shown... Figure 2 As shown in the figure, the queuing delay control method for DPDK packet processing in this embodiment includes the following steps:

[0051] Step S100: Poll the network card's receive queue and determine the state of the DPDK packet processing thread based on the current number of DPDK packets in the receive queue.

[0052] In practical applications, combined with Figure 3As shown, this embodiment first polls the network card's receive queue, which is used to receive DPDK data packets. Therefore, when the network card's receive queue is polled for the first time, the current number of DPDK data packets in the receive queue can be obtained. At this time, the DPDK data packets in the receive queue are the data packets to be processed. In order to control the queuing delay of DPDK data packets in the receive queue, this embodiment needs to determine the state of the DPDK data packet processing thread at this time, that is, to determine whether the DPDK data packet processing thread is in a busy state or an idle state, so as to take different measures to process the DPDK data packets in the receive queue based on different states.

[0053] In one implementation, this embodiment includes the following steps when determining the state of the receiving queue:

[0054] Step S101: If the current number of DPDK data packets in the receive queue is empty, then determine that the state of the DPDK data packet processing thread is idle.

[0055] Step S102: If the current number of DPDK data packets in the receiving queue is not empty, then the state of the DPDK data packet processing thread is determined to be busy, and the DPDK data packets are processed based on the DPDK data packet processing thread.

[0056] Specifically, in practical applications, each DPDK packet processing thread is either idle or busy, repeatedly switching between these two states. The state of a DPDK packet processing thread is determined by the "tidal effect" of network traffic; that is, the utilization rate of the network transmission link is sometimes very high and lasts for a period of time, and sometimes very low or even zero. The state of the DPDK packet processing thread can be determined based on the utilization rate of the network transmission link. The utilization rate of the network transmission link is closely related to the number of DPDK packets in the receive queue. The current number of DPDK packets in the receive queue reflects the number of DPDK packets that need to be processed at that moment. Therefore, the current number reflects the congestion level of DPDK packets in the receive queue. If the current number of DPDK packets in the receive queue is empty, it means there are no DPDK packets in the receive queue, and thus the state of the DPDK packet processing thread can be determined to be idle. Conversely, if the current number of DPDK packets in the receive queue is not empty, it means there are DPDK packets in the receive queue, and thus the state of the DPDK packet processing thread is determined to be busy.

[0057] Step S200: If the DPDK data packet processing thread is in an idle state, the PAUSE instruction is executed repeatedly and a time slice is obtained. If the time slice is not used up, the current number of DPDK data packets in the receiving queue is obtained again. The time slice is used to reflect the total number of clock cycles spent in the idle state.

[0058] After determining the state of the DPDK packet processing thread based on the current number of DPDK packets in the receive queue, this embodiment can determine that the state of the DPDK packet processing thread is either idle or busy. When the state of the DPDK packet processing thread is determined to be idle, this embodiment can repeatedly execute the PAUSE instruction. The PAUSE instruction was introduced by the Pentium 4 processor, and its main purpose is to improve the performance of the CPU during spin. One of its implicit functions is to reduce CPU power consumption when the CPU is performing spin. Furthermore, the PAUSE instruction is backward compatible with all IA-32 series processors. Therefore, repeatedly executing the PAUSE instruction can effectively reduce CPU power consumption, thereby reducing overall power consumption and improving energy efficiency. In addition, this embodiment also acquires a time slice, which is used to reflect the total number of clock cycles spent in the idle state. Therefore, based on this time slice, it can be determined whether the idle state has ended. If the time slice has expired, it means that the idle state has ended. At this time, the process of polling the network card's receive queue and determining the state of the DPDK packet processing thread based on the current number of DPDK packets in the receive queue can be repeated. In other words, it is necessary to re-determine whether the receive queue is empty in order to determine the state of the DPDK packet processing thread and switch the state of the DPDK packet processing thread.

[0059] If the time slice is not used up, it means that the DPDK packet processing thread is still in an idle state. At this time, the DPDK packets in the receive queue can be monitored to obtain the current number of DPDK packets in the receive queue, and further determine whether the DPDK packets in the receive queue are congested, so as to switch the state of the DPDK packet processing thread in a timely manner.

[0060] Step S300: If the current number of DPDK data packets in the receiving queue exceeds a preset threshold, the state of the DPDK data packet processing thread is switched from the idle state to the busy state, and the DPDK data packets are processed based on the DPDK data packet processing thread.

[0061] Since the time slice in this embodiment reflects the total number of clock cycles spent in the idle state, the current number of DPDK packets in the receive queue is obtained in the idle state. This embodiment compares the current number of DPDK packets in the receive queue with a preset threshold. If the current number of DPDK packets in the receive queue is greater than the preset threshold, it indicates that the DPDK packets in the receive queue are too congested. In this case, the state of the DPDK packet processing thread needs to be switched from the idle state to the busy state, and the DPDK packets are processed based on the DPDK packet processing thread. Specifically, in this embodiment, LR is set to the total length of the Rx Ring, i.e., the maximum number of DPDK packets it can hold. T This is a preset threshold for the number of DPDK packets in the Rx Ring. When the number of DPDK packets in the Rx Ring exceeds this preset threshold, the DPDK packet processing thread immediately enters a busy state. R The return value of the `rte_eth_rx_queue_count` function is the number of data packets currently available. Therefore, in this embodiment, before the time slice is exhausted, the `rte_eth_rx_queue_count` function is called to obtain the current number R of DPDK data packets in the receive queue. R If R R >L T If the current number of DPDK data packets exceeds a preset threshold, the state of the DPDK data packet processing thread is switched to a busy state. Simultaneously, since the DPDK data packet processing thread is already in a busy state, this embodiment also reduces the time slice, decreasing the total number of clock cycles spent in the idle state.

[0062] To avoid performance penalties caused by cache misses, DPDK packets are processed by assigning a dedicated CPU core to each DPDK packet processing thread. Similarly, each receive queue is bound to a unique DPDK packet processing thread. This means that access to each receive queue is single-threaded safe, eliminating cache consistency costs associated with reading and writing DPDK packets within the receive queue. If the receive queue's metadata resides in the L1 cache, monitoring the number of DPDK packets in the receive queue will be very fast, without incurring additional performance losses.

[0063] In another implementation, if the current number of DPDK data packets in the receiving queue is less than or equal to the preset threshold, the queuing delay of the DPDK data packets is obtained. The queuing delay reflects the waiting time for all DPDK data packets in the receiving queue to be processed. Based on the obtained queuing delay, it can be determined whether the state of the DPDK data packet processing thread needs to be switched. Specifically, this embodiment compares the queuing delay with a preset maximum allowable delay time. If the queuing delay is greater than the maximum allowable delay time, it indicates that there are enough DPDK data packets in the receiving queue, making it congested. Therefore, since the queuing delay is greater than the maximum allowable delay time, the state of the DPDK data packet processing thread needs to be switched to a busy state to process the DPDK data packets. If the queuing delay is less than or equal to the maximum allowable delay time, it indicates that there are relatively few DPDK data packets in the receiving queue, and the state of the DPDK data packet processing thread can be switched to an idle state. In specific applications, this embodiment sets C... s The total number of clock cycles spent in the idle state, i.e., the time slice. C m The maximum allowable delay time for DPDK packets. Since the CPU frequency is very stable throughout the process and the threads are configured with CPU affinity, they will not be scheduled between multiple CPUs. Therefore, the maximum allowable delay time for packets can be represented by the number of clock cycles. p The number of clock cycles required to process a single data packet. To achieve finer-grained control over packet queuing latency, this embodiment calculates the total number of clock cycles actually spent in the idle state, i.e., C. p *R R However, if max(C p *R R C s >C m This means that the queuing delay of DPDK packets may exceed the maximum allowed delay time. In this case, the state of the DPDK packet processing thread is switched to the busy state. If max(C p *R R C s )≤C m This means that the queuing delay of DPDK packets will not exceed the maximum allowed delay time, at which point the state of the DPDK packet processing thread switches to the idle state. Simultaneously, since the DPDK packet processing thread has switched to the idle state, this embodiment also increases the time slice, increasing the total number of clock cycles spent in the idle state.

[0064] Therefore, since there is no context switching, the switching cost between states of the DPDK packet processing thread is very low, and there is almost no delay between the waiting and processing of DPDK packets. This means that more granular control can be exercised over the queuing latency of DPDK packets. On the other hand, since there is no significant adjustment to the CPU frequency, when the DPDK packet processing thread transitions from an idle state to a busy state, it can immediately process DPDK packets at full power. Soon, all packets in the receive queue are cleared, and the thread returns to an idle state. Therefore, the queuing latency of DPDK packets is lowest in the busy state.

[0065] In summary, this embodiment first polls the network interface card's (NIC) receive queue and determines the state of the DPDK packet processing thread based on the current number of DPDK packets in the receive queue. Then, if the DPDK packet processing thread is in an idle state, it repeatedly executes the PAUSE instruction and acquires a time slice. If the time slice is not used up, it reacquires the current number of DPDK packets in the receive queue. The time slice reflects the total number of clock cycles spent in the idle state. Finally, if the current number of DPDK packets in the receive queue exceeds a preset threshold, the state of the DPDK packet processing thread is switched from the idle state to the busy state, and the DPDK packets are processed based on the DPDK packet processing thread. This embodiment can control the receive queue to switch between idle and busy states, avoiding excessive queuing delays for packets in the receive queue, thus ensuring controllable queuing delays for each packet. Furthermore, in the idle state, this embodiment uses the PAUSE instruction instead of adjusting the CPU frequency to reduce CPU power consumption. The entire process does not introduce interrupts, and the cost of switching between states is minimal, effectively achieving the goal of reducing overall power consumption and improving energy efficiency.

[0066] Exemplary device

[0067] Based on the above embodiments, the present invention also discloses a queuing delay control device for DPDK packet processing, such as... Figure 4As shown, the device in this embodiment includes: a thread state determination module 10, a data packet quantity determination module 20, and a thread state switching module 30. Specifically, the thread state determination module 10 is used to poll the network card's receive queue and determine the state of the DPDK data packet processing thread based on the current quantity of DPDK data packets in the receive queue. The data packet quantity determination module 20 is used to repeatedly execute the PAUSE instruction and acquire a time slice if the state of the DPDK data packet processing thread is idle. If the time slice is not used up, the current quantity of DPDK data packets in the receive queue is acquired again. The time slice reflects the total number of clock cycles spent in the idle state. The thread state switching module 30 is used to switch the state of the DPDK data packet processing thread from the idle state to the busy state if the current quantity of DPDK data packets in the receive queue exceeds a preset threshold, and process the DPDK data packets based on the DPDK data packet processing thread.

[0068] In one implementation, the thread state determination module includes:

[0069] The idle state determination unit is used to determine that the state of the DPDK data packet processing thread is idle if the current number of DPDK data packets in the receive queue is empty.

[0070] The busy state determination unit is used to determine that the state of the DPDK data packet processing thread is busy if the current number of DPDK data packets in the receiving queue is not empty, and to process the DPDK data packets based on the DPDK data packet processing thread.

[0071] In one implementation, the apparatus further includes:

[0072] The re-polling module is used to re-execute the polling of the network card's receive queue if the time slice is used up, and to determine the state of the DPDK packet processing thread based on the current number of DPDK packets in the receive queue.

[0073] The time slice reduction module is used to reduce the time slice if the state of the DPDK packet processing thread switches from the idle state to the busy state.

[0074] The queuing delay determination module is used to obtain the queuing delay of the DPDK data packets if the current number of DPDK data packets in the receiving queue is less than or equal to the preset threshold.

[0075] The state switching control module is used to switch the state of the DPDK packet processing thread according to the queuing delay.

[0076] In one implementation, the state switching control module includes:

[0077] The comparison unit is used to compare the queuing delay with a preset maximum allowable delay time;

[0078] The first switching unit is used to control the state of the DPDK packet processing thread to switch to a busy state if the queuing delay is greater than the maximum allowed delay time.

[0079] The second switching unit is used to control the state of the DPDK packet processing thread to switch to an idle state if the queuing delay is less than or equal to the maximum allowed delay time.

[0080] The time slice increment unit is used to increment the time slice if the state of the DPDK packet processing thread switches to the idle state.

[0081] In one implementation, the receiving queue corresponds one-to-one with the DPDK packet processing thread, and the DPDK packet processing thread is bound to a CPU core.

[0082] The working principle of each module in the queuing delay control device for DPDK packet processing in this embodiment is the same as that of each step in the above method embodiment, and will not be repeated here.

[0083] Based on the above embodiments, the present invention also provides a terminal device, the schematic diagram of which can be as follows: Figure 5 As shown. The terminal device may include one or more processors 100 ( Figure 5 (Only one is shown in the image), memory 101, and a computer program 102 stored in memory 101 and executable on one or more processors 100, such as a program for queuing delay control of DPDK packet processing. When one or more processors 100 execute computer program 102, they can implement the various steps in the method embodiment for queuing delay control of DPDK packet processing. Alternatively, when one or more processors 100 execute computer program 102, they can implement the functions of various modules / units in the apparatus embodiment for queuing delay control of DPDK packet processing, which are not limited here.

[0084] In one embodiment, the processor 100 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0085] In one embodiment, memory 101 may be an internal storage unit of an electronic device, such as a hard drive or RAM. Memory 101 may also be an external storage device of the electronic device, such as a plug-in hard drive, smart media card (SMC), secure digital (SD) card, flash card, etc. Furthermore, memory 101 may include both internal and external storage units. Memory 101 is used to store computer programs and other programs and data required by the terminal device. Memory 101 can also be used to temporarily store data that has been output or will be output.

[0086] Those skilled in the art will understand that Figure 5 The block diagram shown is merely a partial structural diagram related to the present invention and does not constitute a limitation on the terminal device to which the present invention is applied. The specific terminal device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0087] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the methods described above. Any references to memory, storage, operational databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual operating data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0088] In summary, this invention discloses a queuing delay control method and apparatus for DPDK packet processing. The method includes: polling the receive queue of the network interface card (NIC) and determining the state of the receive queue based on the current number of DPDK packets in the receive queue; if the receive queue is in an idle state, repeatedly executing the PAUSE instruction and acquiring a time slice; if the time slice is not used up, reacquiring the current number of DPDK packets in the receive queue; if the current number exceeds a preset threshold, switching the state of the receive queue from an idle state to a busy state and processing the DPDK packets. This invention can control the receive queue to switch between idle and busy states, avoiding excessive queuing delays for packets in the receive queue. Furthermore, this invention uses the PAUSE instruction instead of adjusting the CPU frequency to reduce CPU power consumption, and the entire process does not introduce interrupts, effectively achieving the goal of reducing overall power consumption and improving energy efficiency.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for controlling queuing delay of DPDK packet processing, characterized in that, The method comprises: polling a receiving queue of a network card and determining a state of a DPDK data packet processing thread according to a current number of DPDK data packets in the receiving queue, wherein each DPDK data packet processing thread is only in an idle state or a busy state and repeatedly switches between the two states; if the state of the DPDK data packet processing thread is the idle state, executing a PAUSE instruction in a loop, obtaining a time slice, and when the time slice is not used up, re-obtaining the current number of DPDK data packets in the receiving queue, wherein the time slice is used to reflect a total number of clock cycles spent in the idle state; if the time slice is used up, re-executing the steps of polling the receiving queue of the network card and determining the state of the DPDK data packet processing thread according to the current number of DPDK data packets in the receiving queue; if the current number of DPDK data packets in the receiving queue exceeds a preset threshold, switching the state of the DPDK data packet processing thread from the idle state to the busy state and processing the DPDK data packets based on the DPDK data packet processing thread; if the current number of DPDK data packets in the receiving queue is less than or equal to the preset threshold, obtaining a queuing delay of the DPDK data packets; switching the state of the DPDK data packet processing thread according to the queuing delay; the step of determining the state of the DPDK data packet processing thread according to the current number of DPDK data packets in the receiving queue comprises: if the current number of DPDK data packets in the receiving queue is empty, determining that the state of the DPDK data packet processing thread is the idle state; if the current number of DPDK data packets in the receiving queue is not empty, determining that the state of the DPDK data packet processing thread is the busy state and processing the DPDK data packets based on the DPDK data packet processing thread.

2. The method of claim 1, wherein, The method further comprises: if the state of the DPDK data packet processing thread is switched from the idle state to the busy state, reducing the time slice.

3. The method of claim 1, wherein the method further comprises: the step of switching the state of the DPDK data packet processing thread according to the queuing delay comprises: comparing the queuing delay with a preset maximum allowed delay time; if the queuing delay is greater than the maximum allowed delay time, controlling the state of the DPDK data packet processing thread to be switched to the busy state; if the queuing delay is less than or equal to the maximum allowed delay time, controlling the state of the DPDK data packet processing thread to be switched to the idle state.

4. The method of claim 3, wherein, the step of switching the state of the DPDK data packet processing thread according to the queuing delay further comprises: if the state of the DPDK data packet processing thread is switched to the idle state, increasing the time slice.

5. The method of claim 1, wherein, The receiving queue and the DPDK data packet processing thread are in one-to-one correspondence, and the DPDK data packet processing thread is bound to one CPU core.

6. A device for controlling queuing delay of DPDK packet processing, characterized in that, The device is applied to implement the steps of the queuing delay control method for DPDK data packet processing according to any one of claims 1-5, and comprises: The thread state determining module is configured to poll a receiving queue of a network card and determine a state of a DPDK data packet processing thread according to a current number of DPDK data packets in the receiving queue. The packet number determining module is configured to, if the state of the DPDK data packet processing thread is an idle state, execute a PAUSE instruction cyclically, acquire a time slice, and, if the time slice is not used up, reacquire the current number of DPDK data packets in the receiving queue, the time slice being used to reflect a total clock cycle number spent by the idle state. The thread state switching module is configured to, if the current number of DPDK data packets in the receiving queue exceeds a preset threshold, switch the state of the DPDK data packet processing thread from the idle state to a busy state and process the DPDK data packets based on the DPDK data packet processing thread.

7. The DPDK packet processing queuing delay control apparatus of claim 6, wherein, The thread state determining module comprises: The idle state determining unit is configured to, if the current number of DPDK data packets in the receiving queue is empty, determine the state of the DPDK data packet processing thread to be an idle state. The busy state determining unit is configured to, if the current number of DPDK data packets in the receiving queue is not empty, determine the state of the DPDK data packet processing thread to be a busy state and process the DPDK data packets based on the DPDK data packet processing thread.

8. The DPDK packet processing queuing delay control apparatus of claim 6, wherein, The receiving queue and the DPDK data packet processing thread correspond to each other, and the DPDK data packet processing thread is bound to one CPU core.

9. A terminal device, comprising: The terminal device comprises a memory, a processor, and a DPDK data packet processing queuing delay control program stored in the memory and executable on the processor. When the processor executes the DPDK data packet processing queuing delay control program, the steps of the DPDK data packet processing queuing delay control method according to any one of claims 1-5 are implemented.

10. A computer-readable storage medium, characterized in that, A DPDK data packet processing queuing delay control program is stored on a computer readable storage medium. When the DPDK data packet processing queuing delay control program is executed by a processor, the steps of the DPDK data packet processing queuing delay control method according to any one of claims 1-5 are implemented.

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